Analog-to-digital conversion circuit, chip and integrated circuit system

Abstract

The invention discloses an analog-to-digital conversion circuit, a chip and an integrated circuit system. The analog-to-digital conversion circuit comprises a first-stage quantization unit, a second-stage quantization unit, a third-stage quantization unit and a data combination unit, and the data combination unit is used for combining quantized digital codes generated by the first-stage quantization unit, the second-stage quantization unit and the third-stage quantization unit into output of the analog-to-digital conversion circuit. The method can be widely applied to the technical field of report and extraction.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to an analog-to-digital conversion circuit, a chip, and an integrated circuit system. Background Technology

[0002] In the next-generation wireless network standard WiFi-7 (802.11be), the bandwidth has been pushed to 320MHz, and quadrature amplitude modulation (QAM) has increased to 4096-QAM. This makes high-sampling-rate (GS / s) and high-precision (12-bit) analog-to-digital converters (ADCs) more valuable. Among various ADC architectures, pipelined ADCs are widely used in high-speed communication systems due to their ability to achieve high-speed, high-precision data conversion and relatively low power consumption. They mainly consist of multiple cascaded sub-stage circuits, each stage including a sample-and-hold circuit, a low-resolution coarse quantizer, a digital-to-analog converter (DAC), a subtractor, and a residual amplifier (RA). The residual amplifier is one of the most critical components, typically constructed from a high-gain operational amplifier connected in a closed-loop negative feedback loop to achieve fast and accurate amplification. However, with the upgrading of integrated circuit technology, the transistor feature size is becoming smaller at advanced process nodes, leading to a decrease in operating voltage and intrinsic gain, thus significantly limiting the design of high-gain operational amplifiers. Gain limitations lead to nonlinearity issues in traditional closed-loop negative feedback residual amplifiers, affecting the accuracy and performance of ADCs. Therefore, there are still technical problems that need to be solved in related technologies. Summary of the Invention

[0003] The purpose of this application is to at least partially solve one of the technical problems existing in the prior art.

[0004] Therefore, one objective of this application is to provide an analog-to-digital conversion circuit, chip, and integrated circuit system that can improve the nonlinearity problem of traditional closed-loop negative feedback residual amplifiers and improve the accuracy of circuit signal conversion.

[0005] To achieve the above-mentioned technical objectives, the technical solution adopted in this application embodiment includes: an analog-to-digital conversion circuit, comprising: a first-level quantization unit, a second-level quantization unit, a third-level quantization unit, and a data combination unit; the data combination unit is used to combine the quantized digital codes generated by the first-level quantization unit, the second-level quantization unit, and the third-level quantization unit into the output of the analog-to-digital conversion circuit; wherein, the first-level quantization unit includes a first sampling switch, a first cutoff switch, a first capacitor digital-to-analog converter, a first voltage-to-time converter, a first time-to-digital converter, a first time residual generator, a first cutoff clock generator, and a first floating inverter-type amplifier; the first sampling switch is disposed between the first capacitor digital-to-analog converter and the input signal, and the first sampling switch is disposed between the first voltage-to-time converter and the input signal; the data combination unit, the first capacitor digital-to-analog converter, the first voltage-to-time converter, and the first time residual generator are connected to the first time-to-digital converter; the first cutoff switch and the first capacitor digital-to-analog converter are connected to the first floating inverter-type amplifier; the first cutoff clock generator is connected to the first cutoff switch.

[0006] In addition, the analog-to-digital conversion circuit according to the above embodiments of the present invention may also have the following additional technical features:

[0007] Furthermore, in this embodiment, the second-stage quantization unit includes a second cutoff switch, a second capacitor digital-to-analog converter, a second voltage-to-time converter, a second time-to-digital converter, and a second floating inverter amplifier; the second capacitor digital-to-analog converter, the second voltage-to-time converter, and the data combination unit are connected to the second time-to-digital converter; the second capacitor digital-to-analog converter and the second voltage-to-time converter are connected to the first cutoff switch; the second cutoff switch and the second capacitor digital-to-analog converter are connected to the second floating inverter amplifier.

[0008] Furthermore, in this embodiment, the third-level quantization unit includes a third-capacitor digital-to-analog converter, a first comparator, a second comparator, and a successive approximation analog-to-digital converter; a second cut-off switch, the first comparator, and the second comparator are connected to the third-capacitor digital-to-analog converter; the first comparator and the second comparator are connected to the successive approximation analog-to-digital converter.

[0009] Furthermore, in this embodiment, the first-level quantization unit is used to generate a 3.5-bit quantized digital code; the second-level quantization unit is used to generate a 4-bit quantized digital code; and the third-level quantization unit is used to generate a 6-bit quantized digital code.

[0010] Furthermore, in this embodiment of the application, the first capacitor digital-to-analog converter is used to generate residual voltage; the first time digital-to-digital converter is used to generate residual time; wherein, the residual voltage and the residual time carry the same residual information.

[0011] Furthermore, in this embodiment, the first-level quantization unit and the third-level quantization unit are connected to the second-level quantization unit; the first-level quantization unit, the third-level quantization unit, and the second-level quantization unit are connected to the data combination unit.

[0012] Furthermore, in this embodiment of the application, the first cutoff clock generator is used to generate a control signal to control the first cutoff switch.

[0013] Furthermore, in this embodiment of the application, the second cut-off switch is controlled by a fixed clock edge.

[0014] In addition, this application also provides a chip, which includes the analog-to-digital conversion circuit as described in any of the preceding claims.

[0015] In addition, this application also provides an integrated circuit system, the system including the analog-to-digital conversion circuit as described in any of the preceding claims.

[0016] The advantages and beneficial effects of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application:

[0017] This application adds a first time residual generator and a first truncation clock generator to the first sampling switch, first cutoff switch, first capacitor digital-to-analog converter, first voltage-to-time converter, first time-to-digital converter, and first floating inverter-type amplifier of the first-stage quantization unit. By generating residual times that carry the same residual information as the residual voltage through the first time residual generator and the first truncation clock generator, the correspondence between the amplifier's input voltage and the amplifier's amplification time can be achieved. This application, through this technology, can compensate for the amplifier's compression nonlinearity in the pure analog domain, improve the linearity of the analog-to-digital conversion circuit during the residual amplification process, and thus improve the accuracy of the circuit signal conversion. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of an analog-to-digital converter circuit in a specific embodiment of the present invention;

[0019] Figure 2 This is a control timing diagram of an analog-to-digital conversion circuit in a specific embodiment of the present invention. Detailed Implementation

[0020] The following detailed description, in conjunction with the accompanying drawings, illustrates the principles and processes of the analog-to-digital conversion circuits, systems, chips, and integrated circuit systems in the embodiments of the present invention.

[0021] In the next-generation wireless network standard WiFi-7 (802.11be), the bandwidth has been pushed to 320MHz, and quadrature amplitude modulation (QAM) has increased to 4096-QAM. This makes high-sampling-rate (GS / s) and high-precision (12-bit) analog-to-digital converters (ADCs) more valuable. Among various ADC architectures, pipelined ADCs are widely used in high-speed communication systems due to their ability to achieve high-speed, high-precision data conversion and relatively low power consumption. They mainly consist of multiple cascaded sub-stage circuits, each stage including a sample-and-hold circuit, a low-resolution coarse quantizer, a digital-to-analog converter (DAC), a subtractor, and a residual amplifier (RA). The residual amplifier is one of the most critical components, typically constructed from a high-gain operational amplifier connected in a closed-loop negative feedback loop to achieve fast and accurate amplification. However, with the upgrading of integrated circuit technology, the transistor feature size is becoming smaller at advanced process nodes, leading to a decrease in operating voltage and intrinsic gain, thus significantly limiting the design of high-gain operational amplifiers. Due to gain limitations, traditional closed-loop negative feedback residual amplifiers suffer from nonlinearity issues, affecting the accuracy and performance of ADCs.

[0022] Figure 1This is a structural diagram of an analog-to-digital converter circuit proposed in this invention. The analog-to-digital converter circuit of this application may include a single-channel three-stage pipelined ADC. The first stage of the single-channel three-stage pipelined ADC consists of a sampling switch, a capacitor digital-to-analog converter (CDAC), a voltage-to-time converter (VTC), a time-to-digital converter (TDC), a time residual generator (TRG), a cut-off clock generator (CCG), and a floating inverter amplifier (FIA). Specifically, the first-stage quantization unit includes a first sampling switch, a first cutoff switch, a first capacitor digital-to-analog converter, a first voltage-to-time converter, a first time-to-digital converter, a first time residual generator, a first cutoff clock generator, and a first floating inverter-type amplifier; the first sampling switch is disposed between the first capacitor digital-to-analog converter and the input signal, and the first sampling switch is disposed between the first voltage-to-time converter and the input signal; the data combination unit, the first capacitor digital-to-analog converter, the first voltage-to-time converter, and the first time residual generator are connected to the first time-to-digital converter; the first cutoff switch and the first capacitor digital-to-analog converter are connected to the first floating inverter-type amplifier; the first cutoff clock generator is connected to the first cutoff switch.

[0023] The timing diagram of the ADC used in this technology is as follows: Figure 2 As shown. The signal processing procedure of the ADC proposed in this embodiment is as follows:

[0024] First, in the sampling phase (CKS), the input signal is sampled by the sampling switch and the voltage is held in CDAC and VTC respectively.

[0025] Secondly, the VTC converts the sampled voltage into time, which is then coarsely quantized by the TDC using 3.5 bits (12 quantization intervals). The quantized digital code is returned to the CDAC for capacitor array switching. After the switching is complete, the voltage retained on the CDAC is the residual voltage, carrying information that has been further refined.

[0026] Furthermore, the residual time is generated from the time signal in the TDC through TRG. The residual time (time domain) generated by TRG and the residual voltage (voltage domain) on the CDAC both carry the same residual information and are processed by the subsequent stage, but are reflected in different domains.

[0027] Finally, the residual time is generated by the CCG with a single-ended cutoff signal (CLKcutoff) corresponding to the clock. This clock signal is the amplification clock of the amplifier and determines the amplification time of the open-loop FIA.

[0028] Therefore, this application enables the correspondence between amplifier input voltage and amplifier amplification time. That is, the larger the amplifier input, the longer the amplifier integration time, and the greater the corresponding gain, and vice versa. This technique can compensate for the amplifier's compression nonlinearity in the pure analog domain, thereby improving the linearity of the residual amplification process.

[0029] Reference Figure 1 The second stage of this ADC uses a 4-bit TDC as a coarse quantizer and is amplified to the third stage by an open-loop FIA. Since the first-stage amplifier FIA1 amplifies the residual signal, the linearity requirement of the second-stage amplifier FIA2 is reduced. Therefore, FIA2 does not require additional linearity compensation, and the cutoff signal CLKcu toff2 is generated by a fixed clock edge. Specifically, the second-stage quantization unit may include a second cutoff switch, a second capacitor digital-to-analog converter, a second voltage-to-time converter, a second time-to-digital converter, and a second floating inverter-type amplifier; the second capacitor digital-to-analog converter, the second voltage-to-time converter, and the data combination unit are connected to the second time-to-digital converter; the second capacitor digital-to-analog converter and the second voltage-to-time converter are connected to the first cutoff switch; the second cutoff switch and the second capacitor digital-to-analog converter are connected to the second floating inverter-type amplifier.

[0030] Reference Figure 1 The third stage of this ADC is a 6-bit successive-approximation (SAR) ADC using a ping-pong comparator. SAR ADCs have a simple structure and offer a good trade-off between accuracy, speed, power consumption, and area. Specifically, the third-stage quantization unit may include a third-capacitor digital-to-analog converter, a first comparator, a second comparator, and a successive-approximation SAR ADC; a second cutoff switch, the first comparator, and the second comparator are connected to the third-capacitor digital-to-analog converter; the first comparator and the second comparator are connected to the successive-approximation SAR ADC.

[0031] In the third-level quantization unit, when the rising edge of the first comparison clock (CKC) arrives, the comparator compares the input values. When the input is greater than 0, the input voltage is reduced by half the reference voltage through capacitor switching; when the input is less than 0, the input voltage is increased by half the reference voltage, and so on.

[0032] After one comparator completes its comparison, it is immediately reset. During the reset process, the other comparator performs its next comparison, and this cycle repeats. Unlike traditional SAR ADCs with a single comparator, using two ping-pong comparators saves comparator reset time and offers high speed. After the SAR ADC completes its 6 comparisons, 6-bit quantization is achieved.

[0033] In summary, this technology employs a purely analog-domain nonlinear compensation method, reusing the information carried by the residual time in the time-domain ADC. By combining the residual time with the residual voltage, the integration time of the integrating open-loop amplifier during amplification can be adaptively adjusted, following changes in the amplifier's input, thereby compensating for the amplifier's nonlinearity. Compared to existing technologies, the technical solution of this application has the following advantages:

[0034] 1. Compared to existing Gm-R amplifiers, the integrating open-loop amplifier used in this technology has advantages such as high speed, low power consumption, and simple implementation. It can improve the ADC's operation at a sampling rate of 1 GS / s, and the amplifier's power consumption is controlled to be less than 1 mW.

[0035] 2. Compared to existing calibration techniques based on storing the inverse function of the open-loop amplifier's nonlinear characteristics using a lookup table (LUT), the analog compensation method proposed in this application is stable and reliable under variations in process technology, voltage, and temperature. Since the residual time and residual voltage within the ADC are inherently correlated, their trends and amplitudes are relatively consistent. Even when the external environment changes, the integration time can still be adaptively adjusted to improve the linearity requirements of the integrating open-loop amplifier.

[0036] 3. This technology requires relatively little additional hardware cost. Since it reuses and processes the time signal from the time-domain ADC, only two modules, TRG and CCG, are needed to achieve nonlinear compensation for the integrating open-loop amplifier. Furthermore, the signal path for processing the residual time is isolated from the main signal path (i.e., the path where the residual voltage is amplified), eliminating crosstalk between signals.

[0037] 4. In this technique, the generation of the truncated clock and the integration process of the open-loop amplifier are performed in parallel. That is, while the residual voltage is amplified, the residual signal of the residual time is extracted and an amplification time corresponding to the residual voltage is generated. This technique does not occupy extra operating time of the ADC, which can improve the high sampling rate of the ADC; at the same time, this technique can significantly improve the linearity of the amplifier and improve the high resolution of the ADC.

[0038] In addition, this application also provides a chip. This chip may include the aforementioned digital-to-analog converter circuit.

[0039] It should be noted that the contents of the above analog-to-digital conversion circuit embodiments are all applicable to this chip embodiment. The specific functions implemented by this chip embodiment are the same as those of the above analog-to-digital conversion circuit embodiments, and the beneficial effects achieved are also the same as those achieved by the above analog-to-digital conversion circuit embodiments.

[0040] Furthermore, this application also provides an integrated circuit system. This integrated circuit system may include the aforementioned digital-to-analog converter circuit.

[0041] It should be noted that the contents of the above analog-to-digital conversion circuit embodiments are all applicable to this integrated circuit system embodiment. The specific functions implemented by this integrated circuit system embodiment are the same as those of the above analog-to-digital conversion circuit embodiments, and the beneficial effects achieved are also the same as those achieved by the above analog-to-digital conversion circuit embodiments.

[0042] Furthermore, although this application is described in the context of functional modules, it should be understood that, unless otherwise stated, one or more of the functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding this application. Rather, given the properties, functions, and internal relationships of the various functional modules in the apparatus disclosed herein, the actual implementation of the module will be understood within the scope of conventional technology for an engineer. Therefore, those skilled in the art can implement the application set forth in the claims using ordinary techniques without excessive experimentation. It is also understood that the specific concepts disclosed are merely illustrative and not intended to limit the scope of this application, which is determined by the full scope of the appended claims and their equivalents.

[0043] In the foregoing description of this specification, the references to terms such as "one embodiment," "another embodiment," or "some embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0044] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

[0045] The above is a detailed description of the preferred embodiments of this application, but this application is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application, and these equivalent modifications or substitutions are all included within the scope defined by the claims of this application.

Claims

1. An analog-to-digital converter circuit, characterized in that, include: The circuit comprises a first-level quantization unit, a second-level quantization unit, a third-level quantization unit, and a data combination unit. The data combination unit combines the quantized digital codes generated by the first-level quantization unit, the second-level quantization unit, and the third-level quantization unit into the output of the analog-to-digital converter. The first-level quantization unit includes a first sampling switch, a first cutoff switch, a first capacitor-to-analog converter, a first voltage-to-time converter, a first time-to-digital converter, a first time residual generator, a first cutoff clock generator, and a first floating inverter-type amplifier. The first sampling switch is located between the first capacitor-to-analog converter and the input signal, and also between the first voltage-to-time converter and the input signal. The data combination unit, the first capacitor-to-analog converter, the first voltage-to-time converter, and the first time residual generator are connected to the first time-to-digital converter. The first cutoff switch and the first capacitor-to-analog converter are connected to the first floating inverter-type amplifier. The first cutoff clock generator is connected to the first cutoff switch.

2. The analog-to-digital converter circuit according to claim 1, characterized in that, The second-stage quantization unit includes a second cutoff switch, a second capacitor digital-to-analog converter, a second voltage-to-time converter, a second time-to-digital converter, and a second floating inverter amplifier; the second capacitor digital-to-analog converter, the second voltage-to-time converter, and the data combination unit are connected to the second time-to-digital converter; the second capacitor digital-to-analog converter and the second voltage-to-time converter are connected to the first cutoff switch; the second cutoff switch and the second capacitor digital-to-analog converter are connected to the second floating inverter amplifier.

3. The analog-to-digital converter circuit according to claim 1, characterized in that, The third-level quantization unit includes a third-capacitor digital-to-analog converter, a first comparator, a second comparator, and a successive approximation analog-to-digital converter; The second cut-off switch, the first comparator, and the second comparator are connected to the third capacitor digital-to-analog converter; the first comparator and the second comparator are connected to the successive approximation analog-to-digital converter.

4. The analog-to-digital converter circuit according to claim 1, characterized in that, The first-level quantization unit is used to generate a 3.5-bit quantized digital code; the second-level quantization unit is used to generate a 4-bit quantized digital code; and the third-level quantization unit is used to generate a 6-bit quantized digital code.

5. The analog-to-digital converter circuit according to claim 1, characterized in that, The first capacitor-to-digital converter is used to generate a residual voltage; the first time-to-digital converter is used to generate a residual time; wherein the residual voltage and the residual time carry the same residual information.

6. The analog-to-digital converter circuit according to claim 1, characterized in that, The first-level quantization unit and the third-level quantization unit are connected to the second-level quantization unit; the first-level quantization unit, the third-level quantization unit, and the second-level quantization unit are connected to the data combination unit.

7. The analog-to-digital converter circuit according to claim 1, characterized in that, The first cutoff clock generator is used to generate a control signal to control the first cutoff switch.

8. The analog-to-digital converter circuit according to claim 2, characterized in that, The second cut-off switch is controlled by a fixed clock edge.

9. A chip comprising the analog-to-digital conversion circuit as described in any one of claims 1-7.

10. An integrated circuit system comprising the analog-to-digital converter circuit as described in any one of claims 1-7.

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