A clock generation circuit for a time-interleaved ADC

Abstract

The application discloses a clock generation circuit for time-interleaved ADC, and belongs to the technical field of integrated circuits. The clock generation circuit comprises a delay circuit Delay, a frequency division module and a pulse width adjustment circuit CLK_sample. The pulse width adjustment circuit CLK_sample is used for generating a sampling clock signal CLKS with adjustable pulse width and inputting the sampling clock signal CLKS to a second AND gate group. The frequency division module divides an external clock signal CLK into multiple paths and inputs the multiple paths into a first AND gate group to obtain multiple intermediate clock signals, and inputs the multiple intermediate clock signals to the second AND gate group. The second AND gate group performs AND operation on the sampling clock signal CLKS and each intermediate clock signal to obtain multiple multi-phase clock sampling signals, and inputs the multiple multi-phase clock sampling signals to each sub-ADC module to perform time-interleaved sampling and analog-digital conversion. Then, after merging and synchronization, a final signal is obtained. The circuit of the application has the advantages of simple structure, smaller area, lower power consumption, extremely small phase deviation between each interleaved sampling clock signal, and the ability to freely adjust the pulse width of the sampling clock signal.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more particularly to a clock generation circuit for a time-interleaved ADC. Background Technology

[0002] To meet the demands of the communications industry for transmitting higher-speed and higher-quality information, the bandwidth of wired and wireless transmission systems is constantly increasing, greatly stimulating the demand for high-speed ADCs with medium resolution, low power consumption, and GHz sampling rates and ultra-high bandwidth. Existing ADC architectures offer advantages such as high precision, low power consumption, and small size, but the conversion speed of a single ADC is difficult to further improve. Higher sampling rate ADCs require time interleaving. When the speed of a single-channel ADC approaches its design bottleneck, achieving ultra-high sampling rates using time interleaving becomes particularly important. The time interleaving circuit, located at the front end of the ADC, is a key component determining the ADC's input bandwidth and sampling rate, and is of great significance for the implementation of high-speed ADCs.

[0003] In existing technologies, the pulse width of the interleaved sampling clock signal is not adjusted; its sampling pulse width is fixed at 50% duty cycle. In high-speed ADC applications, due to the very high sampling clock speed, a sampling time with a 50% pulse width will cause the ADC's maximum sampling rate to decrease. In order to further improve the ADC's sampling rate, a clock signal with a 20% or even 10% duty cycle is usually required. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a clock generation circuit for a time-interleaved ADC.

[0005] The objective of this invention is achieved through the following technical solution: a clock generation circuit for a time-interleaved ADC, comprising a delay circuit Delay, a frequency divider module, and a first D flip-flop, wherein the input terminals of the delay circuit Delay, the frequency divider module, and the first D flip-flop receive an external clock signal CLK;

[0006] The delay circuit Delay is used to generate an external clock signal CLK after adjusting the timing and input it to the pulse width adjustment circuit CLK_sample; the pulse width adjustment circuit CLK_sample is used to generate a sampling clock signal CLKS with adjustable pulse width and input it to the second AND gate group;

[0007] The frequency divider module divides the external clock signal CLK into multiple inputs, which are then combined in pairs by the first AND gate group to obtain multiple intermediate clock signals. The multiple intermediate clock signals are then input into the second AND gate group. The second AND gate group performs an AND operation on the sampled clock signal CLKS and each intermediate clock signal to obtain multiple multi-phase clock sampling signals. These multiple multi-phase clock sampling signals are then input into each sub-ADC module of the time-interleaved ADC for time-interleaved sampling and analog-to-digital conversion.

[0008] Each sub-ADC module outputs a digital signal to the multiplexer MUX circuit, which combines the signals into a single data output signal. The data output signal is then input to the first D flip-flop driven by the external clock signal CLK for synchronization before outputting the final signal.

[0009] Preferably, the frequency division module includes at least one frequency divider; the first AND gate group includes multiple AND gates, and the second AND gate group also includes multiple AND gates.

[0010] Preferably, the duty cycle of the intermediate clock signal is 25%; the duty cycle of the multi-channel frequency division signal output by the frequency division module is 50%.

[0011] Preferably, the multiplexing MUX circuit is driven by an intermediate clock signal.

[0012] Preferably, the frequency divider is a D flip-flop with its inverting output terminal fed back to the D input terminal.

[0013] Preferably, the pulse width modulation circuit CLK_sample includes a second D flip-flop with a reset function. The input of the second D flip-flop is connected to a high potential VDD. The clock port of the second D flip-flop receives an external clock signal CLK after passing through the delay circuit Delay. The output of the second D flip-flop is connected to the input of an inverter and each AND gate in the second AND gate group. The output of the inverter is connected to multiple series-connected delay cells (DELAY cells). The output signal of each delay cell (DELAY cell) is output to the input of a multiplexer (MUX). The multiplexer (MUX) is controlled by a multi-bit control signal PULSE. <n:0>A delay signal is selected and output to the first input of the first AND gate to adjust the pulse width of the sampling clock signal CLKS; the second input of the first AND gate receives the external reset control signal RST, and the output of the first AND gate is connected to the reset control port of the second D flip-flop.

[0014] The beneficial effects of this invention are:

[0015] The circuit structure of this invention is simple, with smaller area, lower power consumption, and minimal phase deviation between each interleaved sampling clock signal. At the same time, the pulse width of the sampling clock signal can be freely adjusted. Attached Figure Description

[0016] Figure 1 The schematic diagram of the clock generation circuit is shown as an example of a four-sampling-time interleaved ADC.

[0017] Figure 2 The circuit schematic of the pulse width modulation circuit CLK_sample;

[0018] Figure 3 This is the schematic diagram of a frequency divider circuit.

[0019] Figure 4 The timing waveform diagram is shown for a clock generation circuit using a four-sampling-time interleaved ADC as an example.

[0020] Figure 5 This is a schematic diagram of a two-channel time-interleaved clock generation circuit based on the present invention. Detailed Implementation

[0021] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] See Figures 1-5 The present invention provides a technical solution: a clock generation circuit for a time-interleaved ADC, comprising a delay circuit Delay, a frequency divider module and a first D flip-flop, wherein the input terminals of the delay circuit Delay, the frequency divider module and the first D flip-flop receive an external clock signal CLK;

[0023] The delay circuit Delay is used to generate an external clock signal CLK after adjusting the timing and input it to the pulse width adjustment circuit CLK_sample; the pulse width adjustment circuit CLK_sample is used to generate a sampling clock signal CLKS with adjustable pulse width and input it to the second AND gate group;

[0024] The frequency divider module divides the external clock signal CLK into multiple inputs, which are then combined in pairs by the first AND gate group to obtain multiple intermediate clock signals. The multiple intermediate clock signals are then input into the second AND gate group. The second AND gate group performs an AND operation on the sampled clock signal CLKS and each intermediate clock signal to obtain multiple multi-phase clock sampling signals. These multiple multi-phase clock sampling signals are then input into each sub-ADC module of the time-interleaved ADC for time-interleaved sampling and analog-to-digital conversion.

[0025] Each sub-ADC module outputs a digital signal to the multiplexer MUX circuit, which combines the signals into a single data output signal. The data output signal is then input to the first D flip-flop driven by the external clock signal CLK for synchronization before outputting the final signal.

[0026] In this embodiment, as Figure 1 As shown, taking a four-sampling time-interleaved ADC as an example, it includes components such as a delay circuit, a pulse width adjustment circuit (CLK_sample), a divider, and an AND gate to generate the multi-phase sampling clock signals CLKS_1, CLKS_2, CLKS_3, and CLKS_4 required by the four-channel time-interleaved ADC.

[0027] The input clock signal CLK is simultaneously input to the delay circuit (Delay), the frequency divider module, and the first D flip-flop. The delay circuit (Delay) is a driving buffer that generates a clock delay and is used to adjust the signal timing to ensure that the rising edge of the CLKS signal is later than the rising edges of the signals CK_1, CK_2, CK_3, and CK_4. This ensures that there is sufficient setup time when the two are used in an AND operation, and that the rising edges of the output clock signals CLKS_1, CLKS_2, CLKS_3, and CLKS_4 are completely consistent with the rising edge of the CLKS signal, thereby reducing the phase deviation between the various sampled clock signals.

[0028] The output of the delay circuit is connected to a pulse width modulation circuit (CLK_sample). The pulse width modulation circuit outputs a sampling clock signal CLKS, which is controlled by the input control signal PULSE. <n:0>The pulse width w1 of the CLKS signal can be freely adjusted. In high-speed time-interleaved ADC applications, the time length of w1 can be appropriately shortened to meet the requirements of high-speed sampling and analog-to-digital conversion.

[0029] The CLK signal is input to the frequency divider module's divider, which outputs two clock signals with opposite phases and 50% duty cycles. These two clock signals are then connected to two identical dividers, each of which outputs two clock signals with opposite phases and 50% duty cycles, namely CLK_1 and CLK_3, and CLK_2 and CLK_4, respectively. The CLK_1, CLK_2, CLK_3, and CLK_4 signals (divided signals) are combined in pairs through the AND gates in the first AND gate group to output intermediate clock signals CK_1, CK_2, CK_3, and CK_4 with 25% duty cycles. Specifically, CLK_1 and CLK_4 generate CK_1 through an AND gate, CLK_1 and CLK_2 generate CK_2 through an AND gate, CLK_2 and CLK_3 generate CK_3 through an AND gate, and CLK_3 and CLK_4 generate CK_4 through an AND gate.

[0030] The signals CK_1, CK_2, CK_3, and CK_4 are ANDed with the CLKS signal output from the pulse width modulation circuit in the respective AND gates of the second AND gate group to output the final multi-phase clock sampling signals CLKS_1, CLKS_2, CLKS_3, and CLKS_4. Therefore, the final output multi-phase clock sampling signals have the exact same pulse width w1 as the CLKS signal, and the rising edge times of all multi-phase sampling clock signals are completely consistent with the CLKS signal, ensuring minimal phase deviation between the sampling clock signals to reduce harmonic distortion in the time-interleaved ADC. Finally, all the multi-phase clock sampling signals are connected to the respective sub-ADC modules (ADC1, ADC2, ADC3, ADC4) of the time-interleaved ADC for time-interleaved sampling and analog-to-digital conversion.

[0031] The digital signals Data_1 converted and output by each sub-ADC module <n:0>、Data_2 <n:0>、Data_3 <n:0>、Data_4 <n:0>After passing through a multi-channel selection MUX circuit, the signals are combined into a single data output signal. Then, after synchronization by a D flip-flop driven by the CLK clock, the output DATAOUT is generated. <n:0>The multiplexer (MUX) circuit is driven by clock signals CK_1, CK_2, CK_3 and CK_4 with a 25% duty cycle, and sequentially selects one of the input signals for output.

[0032] CLKS_1, CLKS_2, CLKS_3, and CLKS_4 have extremely small phase deviations because all multi-phase clock sampling signals are generated from the same CLKS signal, and their clock edges are completely consistent with the CLKS signal. The only possible phase deviation is caused by the delay difference between the multiple AND gates that generate the multi-phase clock sampling signals. The delay deviation between multiple AND gates that are close to each other on the same chip layout is very small. In time-interleaved ADC applications, the phase deviation between multi-phase sampling clock signals will seriously affect the overall harmonic distortion index of the ADC. At the same time, due to the function of the pulse width adjustment circuit (CLK_sample), the technical solution provided by this invention can freely adjust the pulse width of the multi-phase clock sampling signal, thus better adapting to the narrow pulse width requirement of high-speed time-interleaved ADCs for clock sampling signals.

[0033] The timing waveform of the clock generation circuit, taking a four-sampling time-interleaved ADC as an example, is as follows: Figure 4 As shown in the figure, the delay time of the CLKS signal relative to the input CLK signal is d1. The d1 delay time includes the delay of the Delay unit and the total delay of the pulse width adjustment circuit (CLK_sample). The purpose of adding the d1 delay to the CLKS signal is to ensure that the rising edge of the CLKS signal is later than the rising edge of the signals CK_1, CK_2, CK_3, and CK_4, so as to ensure that there is enough setup time when the two are ANDed, so that the rising edge of the output clock signals CLKS_1, CLKS_2, CLKS_3, and CLKS_4 is completely consistent with the rising edge of the CLKS signal, thereby reducing the phase deviation between the various multi-phase clock sampling signals. Figure 4 The high-level pulse width w1 of the CLKS signal is controlled and adjusted by the pulse width adjustment circuit (CLK_sample). In high-speed time-interleaved ADC applications, the time length of w1 can be appropriately shortened to meet the requirements of high-speed sampling and analog-to-digital conversion.

[0034] The technical solution provided by this invention can very easily expand the number of sampling clocks to two (a two-channel time-interleaved clock generation circuit, such as...). Figure 5 Circuit structures with 8, 16, etc. (as shown).

[0035] In some embodiments, the frequency division module includes at least one frequency divider; the first AND gate group includes a plurality of AND gates, and the second AND gate group also includes a plurality of AND gates.

[0036] In some embodiments, the duty cycle of the intermediate clock signal is 25%; the duty cycle of the multi-channel frequency division signal output by the frequency division module is 50%.

[0037] In some embodiments, the multiplexing MUX circuit is driven by an intermediate clock signal.

[0038] In some embodiments, the frequency divider is a D flip-flop with its inverting output terminal fed back to the D input terminal.

[0039] In this embodiment, the circuit structure of the divider can adopt various designs, one of which is a simple divider circuit structure implementation such as... Figure 3 As shown, the inverting output of the D flip-flop is fed back to the D input. Driven by the clock CLK, the frequency divider function is implemented. The frequency divider needs to output the in-phase frequency divider signal DIV_CLKp and the inverting frequency divider signal DIV_CLKn at the same time.

[0040] In some embodiments, the pulse width modulation circuit CLK_sample includes a second D flip-flop with a reset function. The input of the second D flip-flop is connected to a high potential VDD. The clock port of the second D flip-flop receives an external clock signal CLK after passing through the delay circuit Delay. The output of the second D flip-flop is connected to the inputs of an inverter and each AND gate in the second AND gate group. The output of the inverter is connected to multiple series-connected delay cells (DELAY cells). The output signal of each delay cell (DELAY cell) is output to the input of a multiplexer (MUX). The multiplexer (MUX) is controlled by a multi-bit control signal PULSE. <n:0>A delay signal is selected and output to the first input of the first AND gate to adjust the pulse width of the sampling clock signal CLKS; the second input of the first AND gate receives the external reset control signal RST, and the output of the first AND gate is connected to the reset control port of the second D flip-flop.

[0041] In this embodiment, as Figure 2 As shown, its function is to convert the input 50% duty cycle clock signal (CLK) into a sampled signal (CLKS) with freely adjustable pulse width as the output. The pulse width adjustment circuit (CLK_sample) includes a second D flip-flop (DFF) with reset function, an inverter (INV), delay cells (DELAY cells) connected in series, a multiplexer (MUX), and a first AND gate. The input of the second D flip-flop is connected to a high potential VDD, and the clock port is connected to the input clock signal CLK. The output port of the second D flip-flop generates the pulse width-adjusted output signal CLKS, which is also connected to the input of the inverter (INV). The output of the inverter (INV) is connected in series with multiple delay cells (DELAY cells). The output signal of each delay cell is connected to the input of the multiplexer (MUX). The multiplexer adjusts the pulse width based on the input multi-bit control signal PULSE. <n:0>To select one output from the multiple input signals, the output of the multiplexer (MUX) is connected to one of the inputs of the first AND gate, the other input of the first AND gate is connected to the external reset control signal RST, and the output of the first AND gate is connected to the reset control port of the second D flip-flop.

[0042] When the reset control signal RST is 0, the second D flip-flop is in the reset state, and the output CLKS is 0. When the RST signal is high (1), the pulse width adjustment circuit enters the normal operation mode, outputting a high level (1) to the CLKS port at each rising edge of the input clock signal CLK. At the same time, the CLKS signal is invertered to obtain a 0-level signal. This 0-level signal is delayed by a multi-stage delay unit, and then a multiplexer selects one of the delayed signals for output. The output signal of the multiplexer and the RST signal are connected to the reset terminal of the second D flip-flop after passing through the first AND gate to reset the output of the second D flip-flop. After the reset, the second D flip-flop outputs a 0-level signal, that is, the CLKS signal becomes 0, thus obtaining a narrow pulse signal of the CLKS sampling signal. The width of its high-level pulse is controlled by the total delay time of the delay unit. By selecting different delay unit output signals through the multiplexer, the pulse width of the CLKS pulse signal can be freely adjusted.

[0043] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A clock generation circuit for a time-interleaved ADC, characterized by: The delay circuit Delay, the frequency division module and the first D flip-flop, an input end of the delay circuit Delay, the frequency division module and the first D flip-flop receives an external clock signal CLK; The delay circuit Delay is used for generating an external clock signal CLK after timing adjustment and inputting to a pulse width adjustment circuit CLK_sample; the pulse width adjustment circuit CLK_sample is used for generating a sampling clock signal CLKS with adjustable pulse width and inputting to a second AND gate group; The frequency division module divides the external clock signal CLK into multiple input paths to the first AND gate group for two-by-two combination to obtain multiple intermediate clock signals, and inputs the multiple intermediate clock signals to the second AND gate group; the second AND gate group performs AND operation on the sampling clock signal CLKS and each intermediate clock signal to obtain multiple multi-phase clock sampling signals, and inputs the multiple multi-phase clock sampling signals to each sub-ADC module of the time-interleaved ADC for time-interleaved sampling and analog-to-digital conversion; Each sub-ADC module outputs a digital signal to a multiplexer MUX circuit to combine into one data output signal, and inputs the data output signal to a first D flip-flop driven by the external clock signal CLK for synchronization and then outputs a final signal.

2. The clock generation circuit for a time-interleaved ADC of claim 1, wherein: The frequency division module includes at least one frequency divider; the first AND gate group includes multiple AND gates, and the second AND gate group also includes multiple AND gates.

3. The clock generation circuit for a time-interleaved ADC of claim 1, wherein: The duty cycle of the intermediate clock signal is 25%, and the duty cycle of the multiple frequency division signals output by the frequency division module is 50%.

4. The clock generation circuit for a time-interleaved ADC of claim 1, wherein: The multiplexer MUX circuit is driven by the intermediate clock signal.

5. The clock generation circuit for a time-interleaved ADC of claim 2, wherein: The frequency divider is a D flip-flop with an inverting output end feedback connected to a D input end.

6. The clock generation circuit for a time-interleaved ADC of any of claims 1-5, wherein: The pulse width adjusting circuit CLK_sample comprises a second D flip-flop with a reset function, an input end of the second D flip-flop is connected to a high potential VDD, a clock port of the second D flip-flop receives an external clock signal CLK through a delay circuit Delay, an output end of the second D flip-flop is connected to an input end of each AND gate in a second inverter and second AND gate group; an output end of the inverter is connected to a plurality of series-connected delay units DELAY cell; an output signal of each delay unit DELAY cell is output to an input end of a multiplexer MUX; the multiplexer MUX outputs a signal according to a plurality of bit control signals PULSE <n:0>One path of delay signal is selected to be output to the first input end of the first AND gate to adjust the pulse width of the sampling clock signal CLKS; the second input end of the first AND gate receives an external reset control signal RST, and the output end of the first AND gate is connected to the reset control port of the second D flip-flop.< / n:0>

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