Semi-structured interleaver and interleaving method suitable for IRA codes

Abstract

The invention discloses a semi-structured interleaver and an interleaving method suitable for IRA codes, and solves the technical problems that short ring generation is difficult to suppress, the performance is unstable and the flexibility is insufficient. The device comprises a cascaded parameter calculation module and a bit interleaving module, the bit interleaving module comprises a plurality of sub-interleavers, the number of the sub-interleavers is equal to the degree value of a variable node with the lowest degree, and the lengths of the sub-interleavers are approximately equal. The interleaving method comprises the following steps: constructing a semi-structured interleaver suitable for IRA codes; determining the position of the low-degree variable node in each sub-interleaver; equally dividing the height variable node to each sub-interleaver; and determining the specific position of the height variable node in each sub-interleaver. According to the method, a hierarchical optimization mechanism driven by degree characteristics is constructed, differential interleaving is carried out on variable nodes of different degrees, the short ring elimination capability is high, the degree adaptability is better, the performance stability of IRA codes is remarkably improved, and the method is used for all scenes in which the IRA codes are adopted for channel coding.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of communication, and mainly relates to a semi-structured interleaver and an interleaving method, in particular to a semi-structured interleaver and an interleaving method suitable for IRA code. The present application can effectively alleviate the error floor phenomenon in the high signal-to-noise ratio region by optimizing the interleaving method of variable nodes with different degrees, and improve the decoding performance stability, which can be used in the channel coding and decoding module of the digital communication system using IRA code. BACKGROUND

[0002] In the digital communication system, channel coding is one of the core technologies to ensure the reliability of data transmission. Its basic principle is to introduce redundant information, so that the receiver can recover the original data through decoding algorithm when the information is damaged due to channel noise, interference or burst error. IRA code (Irregular Repeat-Accumulate Code) is widely concerned among many channel coding schemes due to its excellent performance of approaching Shannon limit. The core innovation of IRA code lies in its irregular degree distribution design: unlike the traditional RA code (Repeat-Accumulate Code) which uses fixed repetition mode, IRA code repeats the input sequence bits with different degrees according to the preset probability distribution, rearranges the repeated bit stream through interleaver, and generates check bits through linear combiner, finally forms a code word.

[0003] However, the traditional IRA code scheme will appear error floor phenomenon in the high signal-to-noise ratio region: the error rate reduction rate is sharply slowed down, and finally stagnates at a high order of magnitude, which seriously limits its application in the super high speed and low error rate scene. After in-depth analysis, this phenomenon is closely related to the generation of short cycle (Short Cycle) in the interleaver design: the traditional interleaver may introduce short cycle structure when constructing the factor graph of IRA code; during the iterative decoding process, short cycle will cause the message to repeatedly pass in the ring, causing information confusion and error propagation, and finally inhibiting the improvement of decoding performance and leading to error floor. In IRA code, the variable nodes with lower degrees have lower reliability in the decoding process, and their error probability directly affects the overall decoding performance, so selecting a suitable interleaving method to improve the reliability of low-degree nodes is the key to reducing error floor.

[0004] At present, there is no literature or technical patent at home and abroad that specifically optimizes the IRA code interleaver.

[0005] The following two types are mainly used in the existing IRA interleaving scheme:

[0006] 1. Restricted random interleaver: This type of interleaver can suppress the generation of short loops to some extent by imposing constraints when randomly selecting interleaving positions, such as avoiding nodes with close physical positions, ensuring uniform neighbor distribution, and controlling the minimum Hamming distance. However, the constraint checking complexity is extremely high, making it difficult to support long code encoding scenarios. Moreover, the global constraint strategy lacks specificity and cannot optimize the distribution of low-degree nodes, resulting in low-degree nodes still being susceptible to short loops and the error floor problem not being fundamentally solved.

[0007] 2. Block interleaver: Block interleaver divides data into several sub-blocks and exchanges positions within or between blocks, such as Z-shaped interleaving by writing in columns and reading in rows, to disperse long burst errors and reduce the frequency of short loop occurrence. However, conventional block interleavers do not employ differentiated interleaving strategies for nodes of different degrees, nor do they explicitly constrain the position relationship between nodes, leading to low-degree nodes still being susceptible to short loops due to their concentrated distribution after interleaving, and thus unable to effectively improve their decoding reliability.

[0008] In summary, the existing technology has the following core defects in the design of IRA code interleaver: traditional interleavers are difficult to suppress the generation of short loops in the factor graph, leading to error floor in high signal-to-noise ratio regions; there is a lack of differentiated interleaving strategies for nodes of different degrees, especially low-degree nodes, which cannot effectively improve the decoding reliability of low-degree nodes; the constraint checking complexity of interleavers in long code scenarios is high, making it difficult to balance performance and implementation efficiency. SUMMARY

[0009] The purpose of the present application is to address the deficiencies of the existing technology, and to propose a semi-structured interleaver for IRA codes that can effectively suppress the occurrence of short loops and an interleaving method. The present application can effectively alleviate the error floor phenomenon of IRA codes in high signal-to-noise ratio regions and improve signal transmission reliability.

[0010] The present application is a semi-structured interleaver for IRA codes, which includes a parameter calculation module and a bit interleaving module in cascade. The bit interleaving module is composed of multiple sub-interleavers, the number of sub-interleavers is equal to the degree value of the variable node with the lowest degree in the IRA code, and the lengths of each sub-interleaver are approximately equal.

[0011] The present application is also a semi-structured interleaving method for IRA codes, characterized by splitting the total interleaver into multiple sub-interleavers according to the degree value of the variable node with the lowest degree, and strictly constraining the position of the variable node with the lowest degree on each sub-interleaver, including the following steps:

[0012] Step 1, constructing a semi-structured interleaver suitable for IRA code: including a parameter calculation module and a bit interleaving module in cascade, characterized by being composed of a plurality of sub-interleavers, the number of sub-interleavers being equal to the degree value of the variable node with the lowest degree in the IRA code, and the lengths of the sub-interleavers being approximately equal. Based on the IRA code with a degree distribution of {a, b, c; d c}, the total interleaver is split into a sub-interleavers, denoted as I1, I2,..., I a , respectively, and the lengths of the sub-interleavers are approximately equal, wherein a, b, and c are different degree values of the variable nodes, the variable node with degree a being the variable node with the lowest degree, and d c is the degree value of the check node.

[0013] Step 2, determining the position of the low-degree variable node on the first sub-interleaver: on the first sub-interleaver I1, for the variable node with degree a, an index value is first generated by a random algorithm, and then it is checked whether the position corresponding to the index is occupied; if not, the position is directly assigned to the current low-degree variable node; if it is occupied, a new random index is generated, and the occupation condition is checked again, and this is repeated until an unoccupied position is found, which is determined as the position of the current low-degree variable node.

[0014] Step 3, determining the position of the low-degree variable node on the non-first sub-interleaver: on the non-first sub-interleaver I k , for the variable node with degree a, an idle position is found by random trial method, which is adjacent to the variable nodes with degree a in other sub-interleavers and has different adjacent nodes, and the position is determined as the position of the current low-degree variable node, wherein the positions of the adjacent variable nodes are limited to the first d c positions and the last d c positions of the variable nodes with degree a in the sub-interleaver, I k represents the kth sub-interleaver, 1 < k ≤ a.

[0015] Step 4, uniformly distributing high-degree variable nodes to each sub-interleaver: taking the remainder r of the degree value b of the high-degree variable node divided by the degree value a of the low-degree variable node, for the first b-r variable nodes obtained by copying the same variable node with degree b, they are sequentially assigned to each sub-interleaver in a circular order; for the last r variable nodes obtained by copying the same variable node, they are sequentially assigned to the corresponding sub-interleaver according to the current sub-interleaver number indicated by the global polling flag signal, and the flag signal is updated to point to the next sub-interleaver after assigning each node, and if the last sub-interleaver is reached, it returns to the first one, and so on, to uniformly distribute the variable nodes with degree c to each sub-interleaver, achieving uniform distribution of high-degree variable nodes to each sub-interleaver.

[0016] Step 5, determining the specific position of the high-degree variable node on each sub-interleaver: the specific position of the high-degree variable node on each sub-interleaver is determined by a random trial method.

[0017] The present application reduces the number of short loops between low-degree variable nodes and improves the stability of IRA decoding.

[0018] The present application solves the problems of large amount of stored data, unstable performance and insufficient flexibility in the existing interleaver scheme, controls the complexity of the scheme while avoiding the appearance of short loops, effectively improves the error floor phenomenon of IRA decoding, and improves the stability of decoding.

[0019] Compared with the prior art, the present application has the following advantages:

[0020] Systematic improvement of short loop elimination capability: Although the traditional random interleaver can randomly disperse nodes, it cannot systematically avoid short loops. Structured interleavers, such as block interleavers, are prone to form fixed short loop patterns due to their regularity. The present application solves the short loop problem from two aspects of structure design and position allocation through the double-checking mechanism of block constraint and adjacent position. The block constraint splits the total interleaver into a number of sub-interleavers with approximately equal lengths according to the degree a of the low-degree variable node in the IRA code. This block method matching the degree of low-degree nodes physically cuts off the basis of forming short loops across sub-interleavers and limits the connection range of low-degree nodes. In the adjacent position checking mechanism, the first sub-interleaver is checked by random index generation and occupation to ensure that the initial position of the low-degree node has no overlap. The non-first sub-interleaver uses a random trial method to verify the position of the free node and limits the adjacent range to the first d c and the last d c position in the sub-interleaver, and ensures that the adjacent nodes of the same type of nodes in other sub-interleavers are not repeated. The double-checking completely blocks the short loop path between low-degree nodes and realizes the systematic improvement of short loop elimination capability.

[0021] Degree adaptability is better: The traditional interleaver adopts a unified strategy for all nodes and cannot optimize the connection for different degrees. Some semi-structured schemes only support single-degree or fixed-degree distribution. The present application customizes allocation rules for different degree nodes, forces low-degree nodes to be evenly distributed to each sub-interleaver, and realizes spatial dispersion through adjacent constraints; high-degree nodes are allocated by a hybrid of modulo cycle and polling mechanism to ensure uniformity between sub-interleavers.

[0022] Better complexity and performance balance: the existing random interleaver needs to store the complete permutation table, and the generation is time-consuming, the structured interleaver stores simply but the performance loss is serious. The present application splits the total interleaver into a number of sub-interleavers with approximately equal length according to the low-degree variable node degree value a, and only needs to store the sub-interleaver division information and local occupation table. At the same time, by limiting the low-degree node constraint range to the non-overlapping adjacent nodes of the adjacent nodes and the low-degree nodes in other sub-interleavers, and the high-degree nodes only need to be randomly allocated within a single block, the generation time of the interleaving table is greatly reduced, while ensuring the performance of suppressing short loops, the double optimization of storage and calculation complexity is realized.

[0023] Stronger adaptability to channel conditions: the traditional interleaver does not consider the channel characteristics, and is prone to performance degradation in burst error channels. The present application splits the interleaver into a number of sub-interleavers with approximately equal length according to the low-degree variable node degree value a, and adopts the block structure to naturally resist continuous errors, combined with the adjacent position constraint of low-degree nodes, can effectively disperse the burst error into multiple sub-blocks, greatly improve the decoding success rate; at the same time, by flexibly adjusting the sub-block size and adjacent constraint parameters, the bit error rate characteristics of different channels can be adaptively adjusted. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 The structural diagram of the semi-structured interleaver of the present application;

[0025] Figure 2 The flow chart of the semi-structured interleaving method of the present application;

[0026] Figure 3 The IRA code using the semi-structured interleaver and interleaving method of the present application and the IRA bit error rate performance curve using the traditional random interleaving scheme are compared. DETAILED DESCRIPTION

[0027] The present application will be described in detail below in combination with the drawings and examples.

[0028] Example 1

[0029] In the field of channel coding, IRA code is concerned because of its excellent performance in approaching the Shannon limit, but the traditional IRA code will appear error flat phenomenon in high SNR area-the error rate drops rapidly slow down, eventually stagnate in a higher order of magnitude, which seriously limits its application in ultra-high speed, low error rate scene. This phenomenon is closely related to the generation of short loops in the design of interleaver, and the reliability of variable nodes with lower degree is lower, and it is more likely to appear short loop and affect the overall decoding performance of IRA code; The traditional interleaver is difficult to suppress the generation of short loops in the factor graph, lacks differentiated interleaving strategies for variable nodes of different degrees, and the constraint checking complexity of the interleaver is high in the long code scene, which is difficult to balance performance and efficiency. The present application uses problem targeting thinking, hierarchical control thinking and parameter coupling thinking, through repeated simulation and adjustment, a semi-structured interleaver and interleaving method suitable for IRA code are proposed.

[0030] The present application is a semi-structured interleaver suitable for IRA code, which includes cascaded parameter calculation module and bit interleaving module, see Figure 1 , Figure 1 The structure diagram of the semi-structured interleaver of the present application, wherein the parameter calculation module receives coding related parameters, wherein the coding related parameters include IRA code degree distribution, code length, etc., the module generates configuration parameters of sub-interleavers based on the coding parameters operation, such as interleaving mapping rules, grouping strategies, etc., and the generated configuration parameters are distributed to each sub-interleaver; The sub-interleavers in the bit interleaving module synchronously receive IRA code data, coding related parameters and configuration parameters generated by the parameter calculation module, perform bit rearrangement processing according to the configuration, and finally the bit interleaving module collects the results of each sub-interleaver and outputs interleaved data. The bit interleaving module in the present application is composed of multiple sub-interleavers, in other words, the bit interleaving module of the present application includes multiple sub-interleavers split from the total interleaver, wherein the number of sub-interleavers is equal to the degree value of the variable node with the lowest degree in IRA code, and the length of each sub-interleaver is approximately equal.

[0031] The present application aims at the problem that the traditional interleaver cannot differentiate the variable nodes of different degrees, cannot systematically avoid the short loop formed by the low-degree variable nodes, and thus cannot alleviate the error floor phenomenon. The present application adopts a degree value driven modular split thinking, selects the lowest degree value a of the variable node in the IRA code as the quantity reference of the split total interleaver, splits the total interleaver into a number of independent sub-interleavers with approximately equal length. The lowest degree value a is selected as the split reference because the variable node with degree a has the weakest connection constraint in the factor graph and is most likely to cause short loop, and the exclusive sub-interleaver can block the short loop generation path by rearranging the data carried by the variable node. The configuration of the sub-interleavers with approximately equal length is to ensure the balanced processing load of each module and avoid the efficiency loss caused by unbalanced resource allocation. This split mode makes each sub-interleaver become an independent processing unit, provides a basis for subsequent layered optimization, and makes the interleaver adapt to the differentiated processing needs of variable nodes with different degrees. The present application can effectively alleviate the error floor phenomenon of IRA code in the high signal-to-noise ratio region and improve the signal transmission reliability.

[0032] Embodiment 2

[0033] The present application is also a semi-structured interleaving method suitable for IRA code, as shown in Figure 2 , Figure 2 is a flow chart for implementing the semi-structured interleaving method of the present application. The traditional interleaver adopts a unified architecture and a random allocation strategy, does not distinguish the degree difference of the variable nodes, and lacks connection constraints across sub-modules, which finally leads to the prominent error floor phenomenon of IRA code in the high signal-to-noise ratio region. Based on this, the present application takes “suppressing short loop + balancing load + preserving flexibility” as the core improvement idea, splits the total interleaver into a plurality of sub-interleavers according to the degree value of the variable node with the lowest degree, and strictly restricts the position of the variable node with the lowest degree on each sub-interleaver, thereby systematically reducing the number of short loops between the low-degree variable nodes and effectively improving the stability of IRA decoding. The specific steps are as follows:

[0034] Step 1, constructing a semi-structured interleaver suitable for IRA code: including a cascaded parameter calculation module and a bit interleaving module, the bit interleaving module of the present application is composed of a plurality of sub-interleavers, in other words, the bit interleaving module of the present application includes a plurality of sub-interleavers split from the total interleaver, the number of sub-interleavers is equal to the degree value of the variable node with the lowest degree in the IRA code, and the lengths of the sub-interleavers are approximately equal. That is, based on the IRA code with degree distribution {a, b, c; d c}, the total interleaver is split into a number of sub-interleavers I1, I2,..., I a , and the lengths of the sub-interleavers are approximately equal, wherein a, b, and c are different degree values of the variable nodes, and a<b<c, a is the degree value of the variable node with the lowest degree, b and c are the degree values of the high-degree variable nodes, and d is the degree value of the variable node with the highest degree.c is the degree value of the check node. Since the variable node with degree a has the weakest connection and is most likely to trigger short cycles in the factor graph, differential control can be achieved based on this splitting criterion, breaking through the homogenization limitation of the traditional "single interleaver".

[0035] In the present invention, the value of a follows the "low-degree node characteristic adaptation principle", and generally takes the value of 2 or 3. Because too low degree will lead to insufficient connectivity, and too high degree will lose the characteristic of "low-degree nodes being easy to control short cycles"; in the short code scenario, a usually takes 2 to simplify the structure; in the long code scenario, a preferably takes 3 to enhance the short cycle suppression ability; in special high reliability requirement scenarios, such as satellite communication, etc., it can be extended to 4, but the length balance of the sub-interleaver needs to be adjusted synchronously.

[0036] The value of b is generally 3 - 5 times that of a. For example, when a = 2, b takes 6 - 10, and when a = 3, b takes 9 - 15. This not only ensures the degree difference from a to reflect the characteristics of "high-degree nodes", but also avoids the increase in the remainder operation complexity during allocation due to too large a value; in the short code scenario, the lower limit can be taken to simplify the equalization algorithm, and in the long code scenario, the upper limit can be taken to enhance the diversity of node connections.

[0037] The value of c is usually 3 - 6 times that of b. For example, when b = 10, c takes 30 - 60, and it needs to satisfy c ≤ code length / 5 to avoid node connection overlap caused by too high degree; in ultra-high-speed transmission scenarios, such as 5G millimeter wave communication, c can be appropriately increased to 8 times that of b to improve the coding gain. [[ID=十二]]

[0038] d c The value of is generally 2 - 3 times that of a. For example, when a = 3, d c takes 6 - 9, and it needs to be less than b to avoid the short cycle risk caused by the check node connection range covering too many high-degree nodes; in the short code scenario, d c takes the lower limit to reduce the constraint check complexity, and in the long code scenario, it takes the upper limit to enhance the check coverage; in the low signal-to-noise ratio scenario, d c can be increased to 4 times that of a to compensate for the channel loss by strengthening the check constraint.

[0039] In this example, the value of a is 3, the value of b is 10, the value of c is 36, and d c takes the value of 6.

[0040] Step 2, determine the position of low-degree variable nodes on the first sub-interleaver: on the first sub-interleaver I1, for a variable node with degree value a, first generate an index value by random algorithm, then check whether the position corresponding to the index is occupied; if not, directly assign the position to the current low-degree variable node; if occupied, generate a new random index and check the occupation again, repeat until an unoccupied position is found, then determine the position as the position of the current low-degree variable node. The prior art random allocation is prone to position conflicts, forming short loops within the same sub-interleaver, and this step avoids conflicts through loop checking, laying the foundation for subsequent adjacency constraints.

[0041] Step 3, determine the position of the variable node with the lowest degree on the non-first sub-interleaver: on the non-first sub-interleaver I k , for a variable node with degree value a, find a free position by random trial method, and the adjacency nodes of the variable node with degree a in other sub-interleavers are not the same, and determine the position as the position of the current low-degree variable node, wherein the position of the adjacent variable node is limited to the first d c positions and the last d c positions of the variable node with degree a in the sub-interleaver, I k represents the kth sub-interleaver, 1<k≤a. The prior art does not consider adjacency repetition across sub-interleavers, but such repetition is a key cause of the ring structure of the factor graph, and this step blocks the short loop path across modules by comparing the adjacency nodes of the allocated sub-interleavers, and the embedding of parameter d c adapts the constraint logic to the depth of the IRA code check relationship.

[0042] Step 4, uniformly distribute high-degree variable nodes to each sub-interleaver: take the remainder r of the degree value b of the high-degree variable node with respect to the degree value a of the low-degree variable node, and for the first b-r variable nodes obtained by copying the same degree value b variable node, sequentially assign them to each sub-interleaver in the loop order; for the last r variable nodes obtained by copying the same variable node, sequentially assign the variable nodes to the corresponding sub-interleaver according to the current sub-interleaver number indicated by the global polling flag signal, update the flag signal to point to the next sub-interleaver after assigning each node, and if the last sub-interleaver is reached, return to the first one, and so on, to uniformly distribute the variable nodes with degree c to each sub-interleaver, achieving uniform distribution of high-degree variable nodes to each sub-interleaver; this step ensures the minimization of the load difference of each sub-interleaver, avoiding the short loop problem caused by excessive node density in traditional interleavers.

[0043] Step 5, determining the specific position of the high-degree variable node on each sub-interleaver: the specific position of the high-degree variable node on each sub-interleaver is determined by a random trial method. The conventional interleaver usually adopts a fixed position, which can cause structural rigidity and loss of interleaving flexibility. The present step realizes balance through "randomness within constraints", so that the coding strategy is controllable and adaptive.

[0044] The specific idea for achieving the object of the present application is that first, the interleaver is subjected to a block operation, and the number of blocks is determined by the degree of the variable node with a lower degree, then different interleaving methods are adopted for variable nodes with different degrees, the low-degree variable nodes are first evenly distributed to each sub-interleaver, and the position of the node on the sub-interleaver is strictly controlled to ensure that the low-degree variable nodes between the sub-interleavers do not overlap within the first d c front and rear positions, wherein d c is the number of check nodes, and then the high-degree variable nodes are evenly distributed to the idle positions of each sub-interleaver. The present application constructs a "degree-driven hierarchical management system": the low-degree nodes are divided into the first sub-interleaver and the non-first sub-interleaver to realize fine short loop suppression, the high-degree nodes realize load balancing through mathematical rules, and the parameters such as the degree of the check node d c and the degree of the low-degree node a are coupled with the code structure characteristics throughout the process. This design not only solves the contradiction between "short loop suppression and flexibility" in the conventional scheme, but also significantly alleviates the error floor phenomenon of IRA codes in the high signal-to-noise ratio scenario through parameter coupling and closed-loop optimization, providing coding support with performance and engineering feasibility for high-speed communication, storage error correction and other fields.

[0045] The present application is an overall technical solution, which comprises five steps of constructing a semi-structured interleaver suitable for IRA codes, determining the position of the low-degree variable node on the first sub-interleaver, determining the position of the low-degree variable node on the non-first sub-interleaver, evenly distributing the high-degree variable node to each sub-interleaver, and determining the specific position of the high-degree variable node on each sub-interleaver. The present application solves the problems of large storage data, unstable performance and insufficient flexibility in the existing interleaver technology, controls the complexity of the scheme while avoiding the occurrence of short loops, effectively improves the error floor phenomenon of IRA decoding, and improves the stability of decoding.

[0046] Embodiment 3

[0047] The semi-structured interleaver and interleaving method suitable for IRA codes are the same as those in Embodiments 1-2, and the position of the variable node with the lowest degree in the non-first sub-interleaver is determined in Step 3 of the present application. The specific step design is derived from the defect that the traditional interleaver in the prior art lacks adjacency constraints in the allocation of the position of the low-degree node in the non-first sub-interleaver, and only does a simple vacancy check, which leads to repeated low-degree node adjacency of different sub-interleavers, forms a short loop across sub-interleavers, and aggravates the error floor phenomenon. Based on this improvement, the present application divides the step into three stages of "alternative position search-overlapping check-cyclic confirmation", which effectively solves the above problems. The specific steps are as follows:

[0048] Step 3.1, find the unoccupied alternative position: find the unoccupied alternative position through "randomly generated index + occupation check". This design is because randomization can reduce the regularity of position distribution and reduce the inherent short loop risk, and the occupation check avoids position conflicts within the same sub-interleaver and lays the foundation for subsequent adjacency constraints. In terms of parameter selection, the index range is not additionally limited to retain randomness to enhance the interleaving effect. In the non-first sub-interleaver I k , for the variable node with degree a, first randomly generate an index value, then check whether the position corresponding to the index has been occupied, if not, the position is taken as the alternative position; if it has been occupied, a new random index is generated and the occupation condition is checked again, and so on, until an unoccupied position is found, which is taken as the alternative position, wherein I k represents the kth sub-interleaver, 1 < k ≤ a.

[0049] Step 3.2, overlapping check on the alternative position: judge whether the adjacency variable nodes of the alternative position are the same as those of other sub-interleavers I1~I k-1 with low-degree variable nodes, if they are all different, it is determined that the position is the position of the current low-degree variable node; otherwise, return to Step 3.1, and so on, until an unoccupied position that meets the overlapping check is found, which is determined as the position of the current low-degree variable node, wherein the positions of the adjacency variable nodes are limited to the first d c positions and the last d c positions of the variable node with degree a in the sub-interleaver. The present application limits the adjacency range to the first d c positions and the last d c positions in the sub-interleaver, and compares the adjacency nodes of the current alternative position with the adjacency nodes of the low-degree nodes in the allocated sub-interleavers I1~I k-1 , to ensure that there is no repetition, because the adjacency repetition across sub-interleavers is a key cause of the ring structure of the factor graph; if it does not meet the requirement, return to Step 3.1 to search again, forming a closed loop optimization.

[0050] Step 3.3. The non-first sub-interleaver I is completed by cyclically performing the "free position search" of step 3.1 and the "adjacent overlapping check" of step 3.2 k The position of all low-degree variable nodes with the degree value a is determined, and this process achieves the satisfaction of the double constraints of "no position conflict + no adjacent node repetition" of the full-degree low-degree nodes in the cross-sub-interleaver range, completely blocks the short loop paths of the factor graph formed due to improper connection relationship of the low-degree nodes, and solves the defect that the "single check coverage is not complete, and some nodes still have a short loop risk" in the traditional scheme. The closed loop design of the present application is derived from the cognition that "low-degree nodes are the core inducement of error flat layer", and through repeated verification, it is ensured that the position allocation of each node meets the constraint rules adapted to the IRA code structure, and the performance short board caused by missed check is avoided.

[0051] In this example, the value of a is 2, the value of b is 6, the value of c is 18, and the value of d c is 4.

[0052] The present application combines the random trial method with the adjacent node overlapping check mechanism to form a progressive position optimization strategy: on the one hand, the random trial generates free position candidates, retaining the randomness of the interleaving process, which solves the problem of insufficient coding flexibility caused by the rigid position distribution of the traditional fixed structure interleaver, and avoids the potential short loop risk caused by regular arrangement; on the other hand, the adjacent node overlapping check is introduced, which compares the adjacent relationship of the current candidate position with the allocated low-degree nodes, and blocks the short loop generation path across the sub-interleaver from the source, wherein the adjacent range is limited to the first d c and the last d c positions in the sub-interleaver, matching the connection characteristics of the check node degree d c . The synergistic effect of this double mechanism solves the contradiction in the prior art that "random allocation is prone to short loops, and fixed allocation lacks flexibility": random trial ensures the irregularity of position distribution, providing a basis for coding flexibility; the adjacent check realizes the targeting of short loop suppression through deep coupling with the IRA code factor graph structure.

[0053] Embodiment 4

[0054] The semi-structured interleaver and interleaving method suitable for IRA codes are the same as those in embodiments 1-3, and the high-degree variable nodes are uniformly distributed to each sub-interleaver in step 4. The high-degree node distribution in the prior art lacks structured rules, and traditional random distribution is prone to excessive concentration of high-degree nodes in a sub-interleaver, causing local load imbalance and short loop density (high-degree node connection number), and the distribution complexity increases linearly with the code length in the long code scenario. The present application proposes an improved scheme of "mathematical balancing algorithm + dynamic scheduling" to solve the above defects, and the specific steps are as follows:

[0055] In this example, the value of a is 3, the value of b is 12, the value of c is 36, and the value of d c is 6.

[0056] Step 4.1, taking the remainder r of the degree value a of the low-degree node by the degree value b of the high-degree node, where a is the degree value of the variable node with the lowest degree, and b is the degree value of the high-degree node. The remainder operation can decompose b into "an integer multiple of a + remainder r", providing a mathematical basis for subsequent segment allocation, ensuring that the allocation rule adapts to the number of sub-interleavers depth.

[0057] Step 4.2, for the first b-r variable nodes obtained by copying the variable nodes with the same degree value b, they are sequentially allocated to each sub-interleaver in a circular order, thereby ensuring the basic balance of each sub-interleaver, as b-r is an integer multiple of a, unbiased allocation can be achieved.

[0058] Step 4.3, for the last r variable nodes obtained by copying the variable nodes with the same degree value b, the variable nodes are sequentially allocated to the corresponding sub-interleaver according to the current sub-interleaver number indicated by the global polling flag signal, and the flag signal is updated to point to the next sub-interleaver after each node is allocated, and if the last sub-interleaver is reached, it returns to the first sub-interleaver. By dynamically updating the global polling flag signal, i.e. automatically pointing to the next sub-interleaver after allocation, the invention solves the imbalance problem of the remainder part, avoiding the disadvantage of some sub-interleavers carrying r nodes caused by traditional fixed order.

[0059] Step 4.4, by analogy, the high-degree variable nodes with degree value c are uniformly allocated to each sub-interleaver, and the uniform allocation of all high-degree variable nodes is completed, realizing the unified balance strategy of all types of high-degree nodes.

[0060] The invention breaks through the limitation of the traditional "single allocation mode": through the mathematical design of "remainder decomposition + segmented processing", the allocation rule is parameter-coupled with node degree and sub-interleaver number, rather than relying on random probability; the dynamic scheduling mechanism of the global polling flag disperses the allocation error of the remainder r to each sub-interleaver, ensuring that the load difference is always controlled within 1 in the long code scenario. The advantage of using the invention is that the uniformity of high-degree nodes in each sub-interleaver is improved, avoiding the generation of short loops and error propagation caused by local concentration; the ordered update of the polling flag reduces the complexity of the allocation process, adapts to the long code scenario; the mathematical rule ensures that the allocation logic is reproducible and easy to implement in hardware, solving the uncontrollability of traditional random allocation. Ultimately, it provides a balanced load basis for subsequent high-degree node position determination, and cooperates with the short loop suppression strategy of low-degree nodes, further improving the transmission reliability of IRA code in high signal-to-noise ratio scenarios, and is suitable for 5G / 6G wideband communication, space measurement and control, and other fields with strict requirements on coding efficiency and stability.

[0061] The following gives an example of a combined interleaver and interleaving method to further illustrate the present invention.

[0062] Example 5

[0063] The semi-structured interleaver and interleaving method applicable to IRA codes are the same as those in Examples 1-4. The present invention is a semi-structured interleaver and interleaving method applicable to IRA codes, which can be used in all scenarios where IRA codes are used for channel coding, especially in fields with high requirements for transmission reliability, processing rate, and scenario adaptability. Traditional solutions mostly use a fixed number of sub-interleavers for splitting, and only simple idle checks are performed for node position allocation, resulting in dense short cycles of low-degree nodes and unbalanced loads of high-degree nodes, ultimately limiting the application of IRA codes in high-reliability scenarios. Based on the above defects, the present invention proposes a semi-structured interleaver and interleaving method applicable to IRA codes, based on an IRA code with a degree distribution of {a, b, c; d c}, where the variable nodes with degree a are low-degree variable nodes, and d c is the number of check nodes. The implementation method of the present invention is further described, including the following steps:

[0064] In this example, the value of a is 3, the value of b is 9, the value of c is 32, and the value of d c is 8.

[0065] Step 1, split the total interleaver: approximately equally divide the total interleaver I with dimension M×1 into a sub-interleavers, denoted as I1, I2,..., I a , where M represents the total number of connection edges between variable nodes and check nodes. The dimensions of each sub-interleaver are L1×1, L2×1,..., L a ×1 respectively, and satisfy L1 + L2 + … + L a = M. Most prior arts split with a fixed number and cannot adapt to the characteristic of "low-degree nodes being the main cause of short cycles" of IRA codes. The low-degree variable nodes with degree a have the weakest connection constraints in the factor graph. Therefore, the present invention splits the total interleaver based on this, making each sub-interleaver a dedicated processing unit for low-degree nodes, laying an architectural foundation for subsequent hierarchical constraints. This splitting method breaks through the limitation of the traditional "disconnection between architecture and code structure", and through the configuration of approximately equal L1 to L a , the risk of unbalanced load is avoided in advance.

[0066] The application utilizes the modular splitting thought driven by the degree value, and splits the total interleaver into multiple sub-interleavers with approximately equal length according to the degree value of the variable node with the lowest degree in the IRA code, so that each sub-interleaver becomes an independent processing unit, and provides a basis for subsequent hierarchical optimization, so that the interleaver can adapt to the differentiated processing requirements of variable nodes with different degrees, and relieves the error floor phenomenon of IRA code in the high signal-to-noise ratio area.

[0067] Step 2, determining the position of the low-degree variable node on the first sub-interleaver: on the first sub-interleaver I1, for the variable node with the degree value a, first generate an index value by a random algorithm, and then check whether the position corresponding to the index is occupied; if not, directly assign the position to the current low-degree variable node; if it is occupied, generate a new random index and check the occupation again, and repeat until an unoccupied position is found, and the position is determined as the position of the current low-degree variable node.

[0068] Step 3, determining the position of the low-degree node on other sub-interleavers I2,..., Ia. a The prior art random allocation is prone to position conflict, forming a short ring in the same sub-interleaver, and the step ensures the uniqueness of the position through cyclic checking, and the design logic is “first solve the conflict, and then optimize the connection”, which provides a basis for adjacency constraints. The prior art does not consider adjacency repetition across sub-interleavers, and such repetition is a key cause of the ring structure of the factor graph, and the step makes the constraint logic deeply coupled with the IRA code checking relationship through the embedding of the parameter d c , blocks the short ring path across the module, and the specific steps are as follows:

[0069] Step 3.1, finding an unoccupied candidate position: on the non-first sub-interleaver I k , for the variable node with the degree value a, first generate a random index value, then check whether the position corresponding to the index is occupied, if not, take the position as a candidate position; if it is occupied, generate a new random index and check the occupation again, and repeat until an unoccupied position is found, and the position is taken as a candidate position, wherein I k represents the kth sub-interleaver, and 1

[0070] Step 3.2, performing overlap checking on the candidate position: judging whether the adjacency variable node of the candidate position is overlapped with other sub-interleavers I1~I k-1The adjacent variable nodes of the variable node with the moderate degree a are the same, if they are not the same, the position is determined as the position of the current low degree variable node; otherwise, return to step 3.1, and repeat until a position is found which is not occupied and meets the overlap check, and the position of the adjacent variable node is limited to the first d c positions and the last d c positions of the variable node with the degree a in the sub-interleaver.

[0071] Step 3.3, repeat step 3.1 and step 3.2 until the positions of all low degree variable nodes on the non-first sub-interleaver are determined.

[0072] Step 4, evenly distribute the high degree variable nodes to each sub-interleaver, in order to solve the problem of uneven distribution of high degree nodes in the prior art, which leads to the load tilt of the sub-interleaver, the quantization rule of "mod operation + cyclic distribution + global polling" is used in this step:

[0073] Step 4.1, take the remainder r of the degree value b of the high degree node with respect to the degree value a of the low degree node;

[0074] Step 4.2, for the first b-r variable nodes obtained by copying the variable nodes with the same degree value b, they are sequentially distributed to each sub-interleaver in the cyclic order;

[0075] Step 4.3, for the last r variable nodes obtained by copying the variable nodes with the same degree value b, the variable nodes are sequentially distributed to the corresponding sub-interleaver according to the current sub-interleaver number indicated by the global polling flag signal, and the flag signal is updated to point to the next sub-interleaver after each node is distributed, and if the last sub-interleaver is reached, the first sub-interleaver is returned.

[0076] Step 4.4, by analogy, the high degree variable nodes with the degree value c are evenly distributed to each sub-interleaver, and the even distribution of all high degree variable nodes is completed.

[0077] Step 5, determine the specific position of the high degree variable node on each sub-interleaver: first, generate an index value by a random algorithm, then check whether the position corresponding to the index is occupied; if not, directly assign the position to the current low degree variable node; if it is occupied, generate a new random index again and check the occupation condition again, and repeat until an unoccupied position is found, then the position is determined as the position of the current high degree variable node. If the fixed position allocation is used in the prior art, the structure is easy to be rigid, and the flexibility of the interleaver to resist channel interference is lost, and in this step, the uncertainty is preserved within the constraint condition by random exploration, so that the coding strategy can suppress the short loop and not excessively sacrifice the adaptive ability.

[0078] The application discloses a semi-structured interleaver and an interleaving method suitable for IRA codes, and solves the technical problem of difficulty in restraining short ring generation to cause error flat phenomenon of IRA codes. The application comprises a cascaded parameter calculation and bit interleaving module, the bit interleaving module comprises a plurality of sub-interleavers, the number of the sub-interleavers is equal to the degree value of a variable node with the lowest degree in the IRA code, and the lengths of the sub-interleavers are approximately equal. The interleaving method comprises the following steps: constructing a semi-structured interleaver suitable for IRA codes; determining the positions of low-degree variable nodes in each sub-interleaver; equally distributing high-degree variable nodes to each sub-interleaver; and determining the specific positions of the high-degree variable nodes in each sub-interleaver. The application constructs a layered optimization mechanism driven by the degree characteristic, performs differential interleaving on variable nodes with different degrees, has strong short ring elimination capability, is more optimal in degree adaptability, and is better in complexity and performance balance, and can be used in all scenarios of channel coding by using IRA codes.

[0079] The application breaks through the limitation of the traditional interleaver in the single allocation strategy and the homogeneous architecture, constructs a layered optimization mechanism driven by the degree characteristic, realizes the accuracy of short ring suppression by distinguishing the low-degree node position allocation logic of the first sub-interleaver and the non-first sub-interleaver, allocates high-degree nodes by using the mathematical rules of "modulus operation + cyclic allocation + global polling", ensures load balancing by parameter adaptation and dynamic flag updating of "b mod a = r", and embeds the check node degree d c , the low-degree node degree a in the adjacency range definition and the number of sub-interleavers respectively, so that the interleaving strategy is deeply bound with the factor graph connection characteristics of the IRA code, and finally, through the collaborative design of "layered processing-cross-module constraint-code structure coupling", the problems of short ring concentration and load imbalance are systematically solved, and the transmission reliability in a high signal-to-noise ratio area is improved.

[0080] The technical effects of the application are verified by simulation and experimental data.

[0081] Embodiment 6

[0082] Simulation conditions:

[0083] There are two groups of simulation parameters used in the application.

[0084] Parameter 1: the code rate of the IRA code is 0.5, and the degree distribution is {3, 10, 36; 6}. Firstly, the information source sends a random binary information sequence with a length of 8188, and the encoder encodes the information sequence to obtain an encoded sequence with a length of 16374. Then, the encoded sequence is modulated by BPSK to obtain a modulated sequence, and the modulated sequence is sent to the decoder through a Gaussian white noise channel. The decoder recovers the information sent by the information source by using the belief propagation decoding algorithm on the received encoded sequence. The original information sequence includes 5832 variable nodes with a degree of 3, 2046 variable nodes with a degree of 10, and 310 variable nodes with a degree of 36, and the number of check nodes is 8186.

[0085] Parameter 2: the code rate of the IRA code is 0.8, and the degree distribution is {3, 10, 36; 16}. Firstly, the information source sends a random binary information sequence with a length of 13103, and the encoder encodes the information sequence to obtain an encoded sequence with a length of 16378. Then, the encoded sequence is modulated by BPSK to obtain a modulated sequence, and the modulated sequence is sent to the decoder through a Gaussian white noise channel. The decoder recovers the information sent by the information source by using the belief propagation decoding algorithm on the received encoded sequence. The original information sequence includes 11426 variable nodes with a degree of 3, 1625 variable nodes with a degree of 10, and 52 variable nodes with a degree of 36, and the number of check nodes is 3275.

[0086] Simulation content:

[0087] The simulation experiment of the present application has four: the first simulation experiment is the code rate of 0.5 IRA code using the traditional random interleaving scheme in the Gaussian white noise channel under the bit error rate performance simulation experiment; the second simulation experiment is the code rate of 0.5 IRA code using the semi-structured interleaver and interleaving method proposed in the present application in the Gaussian white noise channel under the bit error rate performance simulation experiment; the third simulation experiment is the code rate of 0.8 IRA code using the traditional random interleaving scheme in the Gaussian white noise channel under the bit error rate performance simulation experiment; the fourth simulation experiment is the code rate of 0.8 IRA code using the semi-structured interleaver and interleaving method proposed in the present application in the Gaussian white noise channel under the bit error rate performance simulation experiment; the result curves of the four simulation experiments are shown in Figure 3 Figure 3 The IRA code using the semi-structured interleaver and interleaving method proposed in the present application and the IRA code using the traditional random interleaving scheme are compared in the bit error rate performance curve. Figure 3 The horizontal coordinate in the figure represents the signal-to-noise ratio, and the vertical coordinate represents the bit error rate. The four bit error rate performance curves are shown in Figure 3

[0088] Simulation results and analysis:

[0089] Referring to Figure 3 ,​​Figure 3 The curve marked with a circle is the BER performance curve of an IRA code with a code rate of 0.5 using a random interleaving scheme; the curve marked with a square is the BER performance curve of an IRA code with a code rate of 0.5 using the semi-structured interleaver and interleaving method proposed by the present invention; the curve marked with a triangle is the BER performance curve of an IRA code with a code rate of 0.8 using a random interleaving scheme; the curve marked with a diamond is the BER performance curve of an IRA code with a code rate of 0.8 using the semi-structured interleaver and interleaving method proposed by the present invention.

[0090] From Figure 3 It can be seen that for an IRA code with a code rate of 0.5 using the semi-structured interleaver and interleaving method proposed by the present invention, when the BER is 3×10 -7 , the SNR is approximately 1.15 dB, and compared with an IRA code with a code rate of 0.5 using a traditional random interleaving scheme, there is a gain of 0.63 dB; for an IRA code with a code rate of 0.8 using the semi-structured interleaver and interleaving method proposed by the present invention, when the BER is 3×10 -7 , the SNR is approximately 2.92 dB, and compared with an IRA code with a code rate of 0.5 using a traditional random interleaving scheme, there is a gain of 0.68 dB. And from Figure 3 it can be clearly seen that the overall BER curve of the IRA code using the semi-structured interleaver and interleaving method proposed by the present invention is lower than that of the IRA code using a traditional random interleaving scheme. In summary, compared with the prior art, the present invention can effectively suppress short cycles, alleviate the error floor phenomenon of IRA codes in the high SNR region, and improve the reliability of signal transmission.

[0091] In summary, the present invention is a semi-structured interleaver applicable to IRA codes. In the present invention, the bit interleaving module consists of multiple sub-interleavers, the number of sub-interleavers is equal to the degree value of the variable node with the lowest degree in the IRA code, and the lengths of each sub-interleaver are approximately equal.

[0092] The present invention is also a semi-structured interleaving method applicable to IRA codes, and the implementation includes constructing a semi-structured interleaver applicable to IRA codes; determining the positions of low-degree variable nodes on the first sub-interleaver; determining the positions of low-degree variable nodes on non-first sub-interleavers; evenly distributing high-degree variable nodes to each sub-interleaver; and determining the specific positions of high-degree variable nodes on each sub-interleaver.

[0093] The present invention constructs a degree-driven hierarchical optimization mechanism, divides the total interleaver into multiple sub-interleavers according to the degree value of the variable node with the lowest degree, and strictly restricts the positions of low-degree variable nodes on each sub-interleaver in combination with the degree value of the check node, while ensuring the balance of the number of high-degree variable nodes on each sub-interleaver.

[0094] Compared with the traditional interleaving scheme, the present application has the following advantages: fine position control for low-degree nodes can suppress short loop generation, significantly alleviate the error floor phenomenon of IRA code in the high signal-to-noise ratio area, and improve the signal transmission reliability; the "mathematical balancing algorithm" of high-degree nodes ensures the load balancing of each sub-interleaver, avoids the efficiency loss caused by resource tilt, and improves the overall processing rate; embedding the code structure characteristics such as node degree and check relationship into the interleaving strategy makes the scheme flexible to adapt to IRA codes with different degree distribution, and enhances the scene applicability; the collaborative design of hierarchical processing and cross-module constraints balances between suppressing short loops and ensuring randomness, and takes into account performance optimization and engineering realizability, providing efficient support for the application of IRA code in high-speed communication, storage error correction and other fields.

[0095] The present application is applicable to all scenarios using IRA code for channel coding, and has significant application value in fields with high requirements for transmission reliability, processing rate and scene adaptability: in the field of wideband communication, such as 5G / 6G base station data transmission and optical fiber communication system, the ability of the present application to alleviate error floor in high signal-to-noise ratio area can improve the stability of high-speed data transmission; in the field of storage error correction, the present application enhances the error correction performance of IRA code through optimized interleaving strategy and reduces the error code in the data reading and writing process; in complex channel environments such as satellite communication and Internet of Things long-distance transmission, the load-balanced parallel architecture and flexible degree distribution adaptability can adapt to diversified channel characteristics and code length requirements; in addition, in scenarios that require efficient processing of large frame length IRA code, such as broadcast television signal transmission and industrial control data link, the hierarchical optimization mechanism of the present application can improve the processing efficiency while ensuring performance, providing core interleaving support for various systems relying on IRA code encoding.

Claims

1. A semi-structured interleaver suitable for IRA codes comprising a cascaded parameter computation module and a bit interleaving module, characterized in that, The bit interleaving module is composed of a plurality of sub-interleavers, the number of the sub-interleavers is equal to the degree value of the variable node with the lowest degree in the IRA code, and the lengths of the sub-interleavers are approximately equal.

2. A semi-structured interleaving method suitable for IRA codes, characterized in that, The total interleaver is split into a plurality of sub-interleavers according to the degree value of the variable node with the lowest degree, and the position of the variable node with the lowest degree on each sub-interleaver is strictly restricted, including the following steps. Step 1, constructing a semi-structured interleaver suitable for IRA code: including a parameter calculation module and a bit interleaving module in cascade, characterized in that the bit interleaving module is composed of a plurality of sub-interleavers, the number of sub-interleavers is equal to the degree value of the variable node with the lowest degree in the IRA code, and the lengths of the sub-interleavers are approximately equal; based on the IRA code with the degree distribution {a, b, c; d c}, the total interleaver is split into a sub-interleavers, respectively denoted as I1, I2,..., I a , the lengths of the sub-interleavers are approximately equal, wherein a, b, and c are different degree values of the variable nodes, the variable node with degree a is the variable node with the lowest degree, and d c is the degree value of the check node; Step 2: determining the position of the low-degree variable node on the first sub-interleaver: on the first sub-interleaver I1, for the variable node with the degree value a, a random index value is first generated by a random algorithm, and then it is checked whether the position corresponding to the index has been occupied; if not, the position is directly assigned to the current low-degree variable node; if yes, a new random index is generated, and the occupation checking is performed again, and the process is repeated until an unoccupied position is found, and the position is determined as the position of the current low-degree variable node. Step 3, determining the position of the low-degree variable node on the non-first sub-interleaver: on the non-first sub-interleaver I k Above, for the variable node with degree value a, the position of the current low-degree variable node is determined by finding the position of the idle and adjacent node which is not the same as the adjacent node of the variable node with degree value a in other sub-interleavers through random trial method, wherein the position of the adjacent variable node is limited to the first d c positions and the last d c positions of the variable node with degree a in the sub-interleaver, I k represents the kth sub-interleaver, 1<k≤a. Step 4: uniformly distributing the high-degree variable nodes to each sub-interleaver: the remainder r is obtained by taking the modulus of the degree value b of the high-degree variable node with respect to the degree value a of the low-degree variable node, the first b-r variable nodes obtained by copying the same variable node with the degree value b are sequentially distributed to each sub-interleaver in a cyclic order, the last r variable nodes obtained by copying the same variable node are sequentially distributed to the corresponding sub-interleaver according to the current sub-interleaver number indicated by the global polling flag signal, the flag signal is updated to point to the next sub-interleaver after each node is distributed, and if the last sub-interleaver is reached, the first sub-interleaver is returned, and the process is repeated, so that the variable nodes with the degree value c are uniformly distributed to each sub-interleaver, and the high-degree variable nodes are uniformly distributed to each sub-interleaver. Step 5: determining the specific position of the high-degree variable node on each sub-interleaver: the specific position of the high-degree variable node on each sub-interleaver is determined by a random trial method.

3. The interleaving method for IRA codes according to claim 2, wherein, The specific steps of determining the position of the low-degree variable node on the non-first sub-interleaver in step 3 are as follows: Step 3.1, finding an unoccupied alternative position: in the non-first sub-interleaver I k For a variable node with degree value a, an index value is first randomly generated, then it is checked whether the position corresponding to the index is occupied or not. If not, the position is taken as an alternative position. If yes, a new random index is generated and the occupation checking is performed again. This is repeated until an unoccupied position is found, which is taken as an alternative position, where I k represents the kth sub-interleaver, 1 < k ≤ a. Step 3.2, overlap check for the alternative position: judging whether the adjacent variable nodes of the alternative position are the same as the other sub-interleavers I1~I k-1 the adjacent variable nodes of the variable nodes with degree a are the same, if not, it is determined that the position is the position of the current low-degree variable node; otherwise, return to step 3.1, and repeat until a position that is not occupied and meets the overlap check is found, and the position is determined as the position of the current low-degree variable node, wherein the position of the adjacent variable node is limited to the first d c positions and the last d c positions of the variable nodes with degree a in the sub-interleaver. Step 3.3: repeating step 3.1 and step 3.2 until the positions of all low-degree variable nodes on the non-first sub-interleaver are determined.

4. The interleaving method for IRA codes according to claim 3, wherein, The specific steps of uniformly distributing the high-degree variable nodes to each sub-interleaver in step 4 are as follows: Step 4.1: taking the modulus of the degree value b of the high-degree node with respect to the degree value a of the low-degree node to obtain the remainder r; Step 4.2: for the first b-r variable nodes obtained by copying the same variable node with the degree value b, they are sequentially distributed to each sub-interleaver in a cyclic order; Step 4.3: for the last r variable nodes obtained by copying the same variable node with the degree value b, the variable nodes are sequentially distributed to the corresponding sub-interleaver according to the current sub-interleaver number indicated by the global polling flag signal, the flag signal is updated to point to the next sub-interleaver after each node is distributed, and if the last sub-interleaver is reached, the first sub-interleaver is returned; Step 4.4: the high-degree variable nodes with the degree value c are uniformly distributed to each sub-interleaver, and the uniform distribution of all high-degree variable nodes is completed.

Images