Cross-asynchronous clock domain time correction method and device, equipment and medium
By using a time correction method across asynchronous clock domains and dynamically selecting correction parameters, the problem of synchronization error accumulation caused by RTC time value jitter is solved, improving time accuracy and network timing stability. This method is applicable to 5G base stations, financial transactions, and industrial control systems.
Patent Information
- Application Number
- CN202511240806.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-01
- Publication Date
- 2025-11-18
AI Technical Summary
In existing technologies, jitter or deviation in RTC time values leads to the accumulation of synchronization errors, affecting the stability of network timing, especially causing timing chaos in 5G base stations, financial transactions, and industrial control systems.
By using a cross-asynchronous clock domain time correction method, cross-domain transmission parameters or local timing parameters are dynamically selected to correct the target system time. This includes obtaining the target system time and determining its update status, and using the clock cycle of the target clock domain and local timing parameters for correction, thereby eliminating delay deviations and time discontinuities.
It improves the accuracy of RTC time values, ensures the time accuracy obtained by the timestamp sampling module, is compatible with heterogeneous PTP systems, saves software and hardware costs, and ensures the stability of network timing.
Smart Images
Figure CN120979591A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of communication, in particular to a time correction method and device across asynchronous clock domains, equipment and medium. BACKGROUND
[0002] In the fields of communication network, finance, industrial automation and distributed computing, high-precision time synchronization is the core requirement to guarantee system reliability and real-time function. IEEE 1588v2 Precision Time Protocol (PTP) can realize the precise synchronization of Real-Time Clock (RTC) in networked distributed system, and achieve sub-microsecond time synchronization accuracy through Ethernet, becoming the mainstream scheme of low-cost and high-reliability time synchronization. RTC time value as a hardware-level time reference determines the time stamp sampling accuracy of data frame sending and receiving time. If the RTC time value has jitter or deviation, the synchronization error will be accumulated step by step, and serious time sequence confusion may be caused. In the related technology, the RTC time is sampled by fixed period pulse, and the local system time obtained by the time stamp sampling module in the fixed period is unchanged, which will cause great precision loss. Therefore, how to improve the precision of RTC time value is the current problem to be solved. SUMMARY
[0003] Therefore, the present application provides a time correction method, device, equipment and medium across asynchronous clock domains to solve the problem of inaccurate time.
[0004] In the first aspect, the present application provides a time correction method across asynchronous clock domains, which comprises:
[0005] obtaining target system time;
[0006] judging whether the target system time is updated;
[0007] based on the update result of the target system time, using cross-domain transmission parameters or local time sequence parameters to correct the target system time, wherein the cross-domain transmission parameters at least include the clock period of target clock domain, and the local time sequence parameters at least include the system time corrected at the last time.
[0008] The method for time correction across asynchronous clock domains provided by the embodiment comprises: obtaining target system time; judging whether the target system time is updated; and based on the update result of the target system time, using cross-domain transmission parameters or local timing parameters to correct the target system time, wherein the cross-domain transmission parameters at least include clock periods of a target clock domain, and the local timing parameters at least include system time corrected at a previous time. The method dynamically selects cross-domain transmission parameters or local timing parameters for correction according to the update state of the target system time, can eliminate the time delay deviation of cross-clock transmission or the time continuity when there is no update, and improves the time precision.
[0009] In an optional embodiment, the method for time correction across asynchronous clock domains provided by the embodiment comprises:
[0010] If it is judged that the target system time is updated, the cross-domain transmission parameters are used to correct the target system time.
[0011] In an optional embodiment, the method for time correction across asynchronous clock domains provided by the embodiment comprises:
[0012] If it is judged that the target system time is not updated, the local timing parameters are used to correct the target system time.
[0013] In an optional embodiment, the method for time correction across asynchronous clock domains provided by the embodiment comprises:
[0014] If it is judged that the target system time is updated, the clock period of a source clock domain, the clock period of the target clock domain before correction, and the number of flip-flops are collected.
[0015] The target system time is corrected based on the clock period of the source clock domain, the clock period of the target clock domain, and the number of flip-flops. The corrected target system time is determined according to the following formula:
[0016] Corrected target system time = clock period of source clock domain + (number of flip-flops * clock period of target clock domain before correction) + clock period of target clock domain before correction
[0017] In an optional embodiment, the method for time correction across asynchronous clock domains provided by the embodiment comprises:
[0018] If it is judged that the target system time is not updated, the input of a step correction unit is used as the output of a latch.
[0019] Determine if a correction instruction exists;
[0020] If no correction instruction is available, the corrected target system time is obtained based on the sum of the corrected system time from the previous moment and the first delay.
[0021] In an optional implementation, the step of correcting the target system time using local time series parameters if it is determined that the target system time has not been updated further includes:
[0022] If a correction instruction exists, obtain the preset correction coefficient and the second delay;
[0023] The second delay is corrected based on the preset correction coefficient to obtain the third delay;
[0024] The corrected target system time is obtained by summing the corrected system time from the previous moment and the third delay.
[0025] In a second aspect, the present invention provides a time correction device across asynchronous clock domains, the device comprising:
[0026] The time acquisition module is used to acquire the time of the target system.
[0027] The time determination module is used to determine whether the target system time has been updated;
[0028] The correction module is used to correct the target system time based on the update result of the target system time, using cross-domain transmission parameters or local timing parameters. The cross-domain transmission parameters include at least the clock period of the target clock domain, and the local timing parameters include at least the corrected system time of the previous moment.
[0029] Thirdly, the present invention provides an electronic device comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to perform the time correction method across asynchronous clock domains described in the first aspect or any corresponding embodiment thereof.
[0030] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to perform the time correction method across asynchronous clock domains described in the first aspect or any corresponding embodiment thereof.
[0031] Fifthly, the present invention provides a computer program product, including computer instructions for causing a computer to execute the time correction method across asynchronous clock domains described in the first aspect or any corresponding embodiment thereof. Attached Figure Description
[0032] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0033] Figure 1 This is a flowchart illustrating a time correction method across asynchronous clock domains according to an embodiment of the present invention;
[0034] Figure 2 This is a schematic diagram of a time correction system across asynchronous clock domains according to an embodiment of the present invention;
[0035] Figure 3 This is a schematic diagram of the correction module according to an embodiment of the present invention;
[0036] Figure 4 This is a structural block diagram of a time correction device across asynchronous clock domains according to an embodiment of the present invention;
[0037] Figure 5 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of the present invention. Detailed Implementation
[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0039] As a hardware-level time reference, the RTC time value directly affects the accuracy of timestamp sampling for data frame transmission and reception. In the IEEE 1588v2 protocol, the calculation of parameters such as path delay, frequency deviation, and time deviation between master and slave nodes all rely on accurate timestamp information. If the RTC time value fluctuates or deviates, synchronization errors will accumulate, potentially causing network timing chaos in severe cases. This can affect the normal operation of critical scenarios such as 5G base station air interface alignment, timing consistency in financial transaction systems, and collaborative operation of industrial control systems.
[0040] In related technologies, the RTC module time is typically sampled using fixed-period pulses. Within this fixed period, the local system time acquired by the timestamp sampling module remains unchanged, meaning that the message timestamps within this fixed period are all the same. This leads to a significant loss of accuracy, the specific amount of which depends on the synchronizer's cross-clock delay. Therefore, effectively reducing the accuracy loss caused by the local system time during cross-clocking is a pressing technical problem that needs to be solved.
[0041] According to an embodiment of the present invention, a time correction method embodiment across asynchronous clock domains is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.
[0042] This embodiment provides a time correction method across asynchronous clock domains. Figure 1 This is a flowchart of a time correction method across asynchronous clock domains according to an embodiment of the present invention, as follows: Figure 1 As shown, the process includes the following steps:
[0043] Step S101: Obtain the target system time.
[0044] The target system time is generated by the synchronizer. The synchronizer receives the source system time (systime_src), processes it across clock domains (such as trigger synchronization, handshake protocol, etc.), and converts the time information of the source clock domain into the target system time (systime_dest) that can be recognized by the target clock domain. The synchronizer then passes it to the correction module (CORR module). The correction module includes a delay correction unit and a step correction unit.
[0045] Step S102: Determine whether the target system time has been updated.
[0046] When the synchronizer completes a transmission, it outputs a corresponding hardware trigger signal, such as a pulse or a level transition, which marks the target system time update.
[0047] Step S103: Based on the update result of the target system time, the target system time is corrected using cross-domain transmission parameters or local timing parameters.
[0048] Among them, the cross-domain transmission parameters include at least the clock period of the target clock domain, and the local timing parameters include at least the corrected system time of the previous moment.
[0049] The update result for the target system time includes whether the target system time has been updated or not. Based on the updated or not updated result, the target system time is corrected using cross-domain transmission parameters or local timing parameters. Specifically, when the target system time is updated, the delay between the target system time update time and the source system time calibration time is calculated and compensated using cross-domain transmission parameters containing the target clock domain clock period, thus completing the correction. When the target system time has not been updated, the correction is performed by adding the target clock period or the known actual delay, using local timing parameters containing the corrected system time from the previous moment as a reference.
[0050] The time correction method across asynchronous clock domains provided in this embodiment includes obtaining the target system time; determining whether the target system time has been updated; and correcting the target system time based on the update result using cross-domain transmission parameters or local timing parameters. The cross-domain transmission parameters include at least the clock period of the target clock domain, and the local timing parameters include at least the corrected system time from the previous moment. This method dynamically selects cross-domain transmission parameters or local timing parameters for correction based on the target system time update status, which can eliminate time delay deviations from cross-clock transmissions or time continuity when there is no update, thereby improving time accuracy.
[0051] This embodiment provides a time correction method across asynchronous clock domains, which includes the following steps:
[0052] Step S201: Obtain the target system time. For details, please refer to [link to relevant documentation]. Figure 1 Step S101 of the illustrated embodiment will not be described again here.
[0053] Step S202: Determine whether the target system time has been updated.
[0054] Specifically, step S202 includes:
[0055] Please see details Figure 1 Step S102 of the illustrated embodiment will not be described again here.
[0056] Step S203: Based on the update result of the target system time, the target system time is corrected using cross-domain transmission parameters or local timing parameters.
[0057] Specifically, step S203 includes:
[0058] Step S2031: If it is determined that the target system time has been updated, the cross-domain transmission parameters are used to correct the target system time.
[0059] Specifically, step S2031 includes:
[0060] Step a1: If the target system time is determined to be updated, collect the clock cycle of the source clock domain, the clock cycle of the target clock domain before correction, and the number of triggers.
[0061] The delay correction unit receives the target system time from the synchronizer. If it determines that the target system time has been updated, it collects the clock period of the source clock domain, the clock period of the target clock domain before correction, and the number of flip-flops. The clock period of the source clock domain (T_src) represents the oscillation period of the clock domain where the source system resides, reflecting the reference frequency of the source system time. The clock period of the target clock domain before correction (T_dest) represents the oscillation period of the clock domain where the target system resides, serving as the time reference for the target system itself. The number of flip-flops (SYNC_STAGE) represents the number of flip-flop stages in the synchronizer used for cross-clock domain processing.
[0062] Step a2: Correct the target system time based on the clock period of the source clock domain, the clock period of the target clock domain, and the number of flip-flops.
[0063] The time delay between the target system's time update time and its corresponding source system's time calibration time is corrected by the time delay correction unit. The corrected target system time is determined by the following formula:
[0064] Corrected target system time = Source clock domain clock cycle + (Number of flip-flops * Original target clock domain clock cycle) + Original target clock domain clock cycle
[0065] In some alternative implementations, if a two-way handshake DMUX cross-clock synchronizer is used, the corrected target system time = 1 * clock cycle of the source clock domain + (number of triggers * clock cycle of the target clock domain before correction) + 1 * clock cycle of the target clock domain before correction.
[0066] Step S2032: If it is determined that the target system time has not been updated, the target system time is corrected using local timing parameters.
[0067] Specifically, step S2032 includes:
[0068] In step b1, if it is determined that the target system time has not been updated, the input of the step correction unit is used as the output of the latch.
[0069] If the target system time is determined not to have been updated, the previously corrected system time will be used as the reference for correction. The latch is a hardware storage unit used to save the previously corrected system time. By locking the input of the step correction unit to the output of the latch, the starting point of the current correction can be fixed at the result of the previous correction, avoiding time base confusion due to lack of new data.
[0070] Step b2: Determine if a correction instruction exists.
[0071] Correction indicators are pre-set hardware signals, such as register flags or logic levels, used to identify whether the current situation is an unconventional scenario that requires special handling, such as fluctuations caused by clock gating or periodic anomalies.
[0072] As an example, if a clock gating enable signal is detected to be valid, it is determined that a correction indication exists; if the clock is running normally, the correction indication does not exist.
[0073] Step b3: If there is no correction instruction, the corrected target system time is obtained based on the sum of the corrected system time of the previous moment and the first delay.
[0074] The first delay is a predefined, known actual delay that matches the abnormal scenario. If there is no correction instruction, the corrected target system time = the corrected system time of the previous moment + the first delay. That is, the correction content is the delay (T_dest) between the rising edge of the current clock and the rising edge of the clock of the previous moment systime_corr.
[0075] Step b4: If a correction instruction exists, obtain the preset correction coefficient and the second delay.
[0076] The preset correction factor is used to correct the second delay. If there is a correction indication, such as a known jitter caused by clock gating, then the known delay needs to be corrected, and the preset correction factor is obtained.
[0077] Step b5: Correct the second delay based on the preset correction coefficient to obtain the third delay.
[0078] Step b6: Based on the corrected system time from the previous moment and the sum of the third delay, obtain the corrected target system time.
[0079] The second time delay is corrected using a second preset correction factor. Specifically, the product of the second preset correction factor and the second time delay is calculated to obtain the third time delay. The corrected target system time = the corrected system time at the previous moment + the third time delay.
[0080] The time correction method for cross-asynchronous clock domains provided by this invention is used to correct the time of an RTC system synchronized across clock domains, ensuring that the RTC system time obtained by the timestamp sampling module has good accuracy. This method is not aware of the specific operating location of the timestamp sampling module, thus it can be well-compatible with heterogeneous PTP (Precision Time Protocol) system architectures, achieving high-precision synchronization efficiency for PTP systems while saving software and hardware costs. The time correction system for cross-asynchronous clock domains is as follows: Figure 2As shown, it includes a real-time clock module, a cross-clock synchronizer, a correction module, and a timestamp sampling module. The correction module corrects the target system time. The correction parameters in the correction module are issued by the APB software, and the correction module can complete the known items to be corrected through hardware self-feedback indication signals.
[0081] Figure 3 The diagram shows the correction module, which includes a delay correction unit and a step correction unit. The delay correction unit receives the target system time (systime_dest) from the synchronizer and performs delay correction on it at the update time of the source system time. The correction content is the delay between the rising edge of the target system time update clock and the calibration time of the source system time.
[0082] The 2-to-1 MUX is used to select the source of the final output corrected system time. When the target system time is updated, the output corrected system time comes from the delay correction unit; when the target system time is not updated, the output corrected system time comes from the step correction unit. The step correction unit obtains the corrected system time from the latch at the previous moment and corrects it by subtracting the clock delay between the current clock rising edge and the previous corrected system time.
[0083] This embodiment also provides a time correction device across asynchronous clock domains, which is used to implement the above embodiments and implementation methods; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, hardware implementations, or a combination of software and hardware, are also possible and contemplated.
[0084] This embodiment provides a time correction device across asynchronous clock domains, such as... Figure 4 As shown, it includes:
[0085] The time acquisition module is used to acquire the time of the target system.
[0086] The time determination module is used to determine whether the target system time has been updated;
[0087] The correction module is used to correct the target system time based on the update result of the target system time, using cross-domain transmission parameters or local timing parameters. The cross-domain transmission parameters include at least the clock period of the target clock domain, and the local timing parameters include at least the corrected system time of the previous moment.
[0088] In some alternative implementations, the correction module includes:
[0089] The first correction unit is used to correct the target system time using cross-domain transmission parameters if it is determined that the target system time has been updated.
[0090] In some alternative implementations, the correction module includes:
[0091] The second correction unit is used to correct the target system time using local timing parameters if it is determined that the target system time has not been updated.
[0092] In some optional implementations, the first correction unit includes:
[0093] The first acquisition subunit is used to acquire the clock period of the source clock domain, the clock period of the target clock domain before correction, and the number of triggers if it is determined that the target system time has been updated.
[0094] The first correction subunit is used to correct the target system time based on the clock period of the source clock domain, the clock period of the target clock domain, and the number of flip-flops; the corrected target system time is determined according to the following formula:
[0095] Corrected target system time = Source clock domain clock cycle + (Number of flip-flops * Original target clock domain clock cycle) + Original target clock domain clock cycle
[0096] In some optional implementations, the second correction unit includes:
[0097] The second acquisition subunit is used to take the input of the step correction unit as the output of the latch if it is determined that the target system time has not been updated.
[0098] The indicator judgment subunit is used to determine whether a correction indicator exists;
[0099] The second correction subunit is used to obtain the corrected target system time based on the sum of the corrected system time of the previous moment and the first delay if no correction instruction exists.
[0100] In some optional implementations, the second correction unit includes:
[0101] The third acquisition subunit is used to acquire the preset correction coefficient and the second time delay if a correction indication exists;
[0102] A delay correction subunit is used to correct the second delay based on the preset correction coefficient to obtain a third delay;
[0103] The third correction subunit is used to obtain the corrected target system time based on the system time corrected in the previous moment and the sum of the third delay.
[0104] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.
[0105] In this embodiment, the time correction device across asynchronous clock domains is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above-mentioned functions.
[0106] This invention also provides an electronic device having the above-described features. Figure 4 The time correction device shown is for use across asynchronous clock domains.
[0107] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of an electronic device provided in an optional embodiment of the present invention, such as... Figure 5 As shown, the electronic device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise as required. The processors can process instructions executed within the electronic device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple electronic devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 5 Take a processor 10 as an example.
[0108] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.
[0109] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.
[0110] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the electronic device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the electronic device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.
[0111] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.
[0112] The electronic device also includes a communication interface 30 for communicating with other devices or communication networks.
[0113] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.
[0114] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.
[0115] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and all such modifications and variations fall within the scope defined by the invention.
Claims
1. A time correction method across asynchronous clock domains, characterized in that, The method includes: Obtain the target system time; Determine whether the target system time has been updated; Based on the update result of the target system time, the target system time is corrected using cross-domain transmission parameters or local timing parameters. The cross-domain transmission parameters include at least the clock period of the target clock domain, and the local timing parameters include at least the corrected system time of the previous moment.
2. The time correction method across asynchronous clock domains according to claim 1, characterized in that, The step of correcting the target system time based on the update result of the target system time, using cross-domain transmission parameters or local timing parameters, includes: If it is determined that the target system time has been updated, then the target system time is corrected using cross-domain transmission parameters.
3. The time correction method across asynchronous clock domains according to claim 1, characterized in that, The step of correcting the target system time based on the update result of the target system time, using cross-domain transmission parameters or local timing parameters, includes: If it is determined that the target system time has not been updated, the target system time is corrected using local time series parameters.
4. The time correction method across asynchronous clock domains according to claim 2, characterized in that, If it is determined that the target system time has been updated, then the target system time is corrected using cross-domain transmission parameters, including: If the target system time is determined to be updated, the clock period of the source clock domain, the clock period of the target clock domain before correction, and the number of triggers are collected. Based on the clock period of the source clock domain, the clock period of the target clock domain, and the number of flip-flops, the target system time is corrected; the corrected target system time is determined according to the following formula: The corrected target system time = the clock cycle of the source clock domain + (number of flip-flops * clock cycle of the target clock domain before correction) + clock cycle of the target clock domain before correction.
5. The time correction method across asynchronous clock domains according to claim 3, characterized in that, If it is determined that the target system time has not been updated, then the target system time is corrected using local time series parameters, including: If it is determined that the target system time has not been updated, the input of the step correction unit will be used as the output of the latch. Determine if a correction instruction exists; If no correction instruction is available, the corrected target system time is obtained based on the sum of the corrected system time from the previous moment and the first delay.
6. The time correction method across asynchronous clock domains according to claim 5, characterized in that, The step of correcting the target system time using local time series parameters if it is determined that the target system time has not been updated also includes: If a correction instruction exists, obtain the preset correction coefficient and the second delay; The second delay is corrected based on the preset correction coefficient to obtain the third delay; The corrected target system time is obtained by summing the corrected system time from the previous moment and the third delay.
7. A time correction device across asynchronous clock domains, characterized in that, The device includes: The time acquisition module is used to acquire the time of the target system. The time determination module is used to determine whether the target system time has been updated; The correction module is used to correct the target system time based on the update result of the target system time, using cross-domain transmission parameters or local timing parameters. The cross-domain transmission parameters include at least the clock period of the target clock domain, and the local timing parameters include at least the corrected system time of the previous moment.
8. An electronic device, characterized in that, Includes: A memory and a processor are communicatively connected, the memory storing computer instructions, and the processor executing the computer instructions to perform the time correction method across asynchronous clock domains as described in any one of claims 1 to 6.
9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to perform the time correction method across asynchronous clock domains as described in any one of claims 1 to 6.
10. A computer program product, characterized in that, Includes computer instructions for causing a computer to perform the time correction method across asynchronous clock domains as described in any one of claims 1 to 6.