UDP sending method and system for FPGA multi-board synchronization signals

Abstract

The application relates to the communication technical field and discloses a UDP sending method and system of FPGA multi-board synchronization signals, wherein the method comprises the following steps: encapsulating data of the same subband in a continuous specified number of time slots into a single subband frame, and arranging a sorting timestamp in the frame header of the single subband frame; the sorting timestamp is arranged in the following manner: in response to a synchronization reset signal, the values of the sorting timestamps of all FPGA board cards are synchronously reset; for any FPGA in the reset state, if a first-path first-subband effective signal is detected, the FPGA enters a running state, and the value of the corresponding sorting timestamp is updated to an initial value; in the running state, the value of the sorting timestamp is increased by a specified step length every time a specified number of first-path last-subband effective signals are detected; and if the value of the sorting timestamp reaches a preset maximum value, the value is automatically reset to zero to realize cyclic counting. The method has the beneficial effect of reducing the synchronization output complexity and hardware cost of all FPGAs.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to a UDP sending method and system of FPGA multi-board synchronization signals. BACKGROUND

[0002] With the continuous development of array signal processing technology and processor computing capacity, the data volume demand of real-time processing is also gradually increasing. Due to the limited processing capacity of a single FPGA board card, multiple FPGA board cards often need to work cooperatively. How to send FPGA multi-board synchronization signals out so that the signals received by the next stage of functional modules are still in a synchronous state has become the key to system integration. However, related technologies have limitations in complexity control and the like. SUMMARY

[0003] The present application provides a UDP sending method and system of FPGA multi-board synchronization signals, which solves the technical problem of how to realize FPGA multi-board synchronization transmission at low cost and high reliability, and achieves the technical effect of reducing system complexity.

[0004] In order to achieve the above purpose, the main technical scheme adopted by the present application includes:

[0005] In a first aspect, the present application provides a UDP sending method of FPGA multi-board synchronization signals, which comprises: determining the number of parallel output channels and the number of subbands per channel according to the total number of subbands required by the receiver and the maximum subband capacity of the FPGA single transmission interface; filtering the input channelized signal based on the total number of subbands to obtain valid subbands; distributing the valid subbands based on the number of parallel output channels and the number of subbands per channel to generate rate-matched channelized output signals; for any one of the channelized output signals, encapsulating the data of the same subband in a continuous specified number of time slots into a single subband frame, and setting a sorting timestamp in the frame header of the single subband frame; wherein the sorting timestamp is set in the following manner: in response to a synchronization reset signal, the values of the sorting timestamps of all FPGA board cards are synchronized and reset; for any FPGA in the reset state, if a valid signal of the first subband of the first channel is detected, the FPGA enters a running state and updates the value of the corresponding sorting timestamp to an initialization value; in the running state, every time a valid signal of the last subband of the first channel is detected for a specified number of times, the value of the sorting timestamp is increased by a specified step; if the value of the sorting timestamp reaches a preset maximum value, the value is automatically reset to zero to realize cyclic counting; adding a UDP header to the single subband frame, generating a UDP data packet of a specified length through a padding mechanism; and generating and sending an IP datagram and an Ethernet frame based on the UDP data packet.

[0006] The FPGA multi-board synchronization signal UDP sending method provided by the embodiment of the application is suitable for a direct transmission architecture and a switch forwarding transmission architecture, the number of parallel output channels and the number of subbands per channel are determined according to the total number of subbands required by a receiver and the maximum subband capacity of a single FPGA transmission interface, the input channelized signal is filtered based on the total number of subbands to obtain valid subbands, the valid subbands are distributed based on the number of parallel output channels and the number of subbands per channel to generate a rate-matched channelized output signal, and the data of the same subband in a continuous specified number of time slots in any output channel of the channelized output signal is encapsulated into a single subband frame, and the frame header of the single subband frame is provided with a sorting timestamp, wherein, in response to a synchronization reset signal, the values of the sorting timestamps of the FPGA boards are synchronized, for any FPGA in a reset state, if a first subband effective signal of a first channel is detected, the FPGA enters a running state, and the value of the corresponding sorting timestamp is updated to an initialization value, in the running state, every time a specified number of last subband effective signals of the first channel are detected, the value of the sorting timestamp is increased by a specified step, and if the value of the sorting timestamp reaches a preset maximum value, the value is automatically reset to zero to realize cyclic counting, a UDP header is added to the single subband frame, a UDP data packet of a specified length is generated through a padding mechanism, and an IP datagram and an Ethernet frame are generated and sent based on the UDP data packet, the output synchronization of the FPGA boards is realized through the sorting timestamp, and the FPGA multi-board synchronization transmission is realized at low cost and high reliability without relying on high-precision clock hardware, thereby reducing the complexity and hardware cost of FPGA synchronization output.

[0007] Optionally, determining the number of parallel output channels and the number of subbands per channel according to the total number of subbands required by a receiver and the maximum subband capacity of a single FPGA transmission interface includes: calculating a first ratio of the total number of subbands to the maximum subband capacity of a single FPGA transmission interface, rounding up the first ratio, and taking the result of rounding up as the number of parallel output channels; calculating a second ratio of the total number of subbands to the number of parallel output channels, and in the case that the total number of subbands is divisible by the number of parallel output channels, taking the second ratio as the number of subbands per channel; in the case that the total number of subbands is not divisible by the number of parallel output channels, calculating the remainder of the total number of subbands divided by the number of parallel output channels, and determining the number of subbands per channel based on the second ratio and the remainder.

[0008] Optionally, the determining the number of sub-bands per channel based on the second ratio and the remainder comprises: if the current output channel sequence number is less than or equal to the remainder, performing an upward rounding on the second ratio, and taking the result of the upward rounding as the number of sub-bands of the current output channel; if the current output channel sequence number is greater than the remainder, performing a downward rounding on the second ratio, and taking the result of the downward rounding as the number of sub-bands of the current output channel.

[0009] Optionally, the method further comprises: the sub-band number of the effective sub-band is less than or equal to the total number of sub-bands; and for any time slot, the first data signals of each output channel in the channelized output signal are aligned in the same clock cycle.

[0010] Optionally, the method further comprises: the generation of the channelized output signal and the packaging of the single-sub-band frame share a synchronous reset signal and a channelized clock domain; the generation of the UDP data packet and the generation and transmission of the IP datagram and the Ethernet frame share a transmission reset signal and a transmission clock domain; the clock domain conversion from the channelized clock domain to the transmission clock domain is performed on the single-sub-band frame, and a UDP header is added to the single-sub-band frame after the clock domain conversion.

[0011] Optionally, the method further comprises: the conversion from the channelized clock domain to the transmission clock domain is implemented by an asynchronous FIFO; and the execution of the packaging of the single-sub-band frame is controlled based on the state of the asynchronous FIFO and the value of the current ordering timestamp.

[0012] Optionally, for any output channel in the channelized output signal, the data of the same sub-band in a continuous specified number of time slots is packaged into a single-sub-band frame, comprising: performing a transposition operation on the specified number of time slot data of any output channel, so that the data of the same sub-band in the specified number of time slots is continuously output, and the data of different sub-bands is output with a specified number of clock cycles in between.

[0013] Optionally, the frame header further comprises a display timestamp, a frame number, a sub-band number, and a board card number; and the frame number is used to number each single-sub-band frame in the same ordering timestamp.

[0014] Optionally, the UDP header is added to the single-sub-band frame, and a UDP data packet of a specified length is generated by a padding mechanism, comprising: generating a corresponding UDP header based on the sub-band number of the single-sub-band frame; if the payload length in the single-sub-band frame is less than the specified length, padding the single-sub-band frame data to the specified length, and adding the UDP header to the padded single-sub-band frame to generate the UDP data packet of the specified length.

[0015] In a second aspect, the embodiments of the present application provide a FPGA multi-board synchronization signal UDP sending system, which comprises: a rate matching module, configured to determine the number of parallel output channels and the number of subbands per channel according to the total number of subbands required by a receiver and the maximum subband capacity of a FPGA single transmission interface, filter an input channelized signal based on the total number of subbands to obtain effective subbands, and distribute the effective subbands based on the number of parallel output channels and the number of subbands per channel to generate a rate-matched channelized output signal; a packaging module, configured to package data of the same subband in a continuous specified number of time slots as a single subband frame for any one of the channelized output signals, and set a sorting timestamp in a frame header of the single subband frame; wherein the sorting timestamp is set in the following manner: in response to a synchronization reset signal, the values of the sorting timestamps of all FPGA boards are synchronized and reset; for any FPGA in a reset state, if a first subband effective signal of a first channel is detected, the FPGA enters a running state, and the value of the corresponding sorting timestamp is updated to an initial value; in the running state, the value of the sorting timestamp is increased by a specified step length every time a specified number of last subband effective signals of the first channel are detected; and if the value of the sorting timestamp reaches a preset maximum value, the value of the sorting timestamp is automatically reset to zero to realize cyclic counting; a first generation module, configured to add a UDP header to the single subband frame to generate a UDP data packet of a specified length through a padding mechanism; and a second generation module, configured to generate an IP datagram and an Ethernet frame based on the UDP data packet and send the IP datagram and the Ethernet frame.

[0016] In a third aspect, the embodiments of the present application provide a computer device, which comprises a memory and a processor, the memory and the processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the FPGA multi-board synchronization signal UDP sending method.

[0017] In a fourth aspect, the embodiments of the present application provide a computer readable storage medium, which stores computer instructions, and the computer instructions are used to make a computer perform the FPGA multi-board synchronization signal UDP sending method.

[0018] In a fifth aspect, the embodiments of the present application provide a computer program product, which comprises computer instructions, and the computer instructions are used to make a computer perform the FPGA multi-board synchronization signal UDP sending method. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or prior art description. Obviously, the drawings described below are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0020] Figure 1 The flow chart of the FPGA multi-board synchronization signal UDP sending method provided by the embodiment of the present application;

[0021] Figure 2 The schematic diagram of the input channelized signal provided by the embodiment of the present application;

[0022] Figure 3 The schematic diagram of the channelized output signal provided by the embodiment of the present application;

[0023] Figure 4 The schematic diagram of the frame header format provided by the embodiment of the present application;

[0024] Figure 5 The schematic diagram of the state machine model provided by the embodiment of the present application;

[0025] Figure 6 The schematic diagram of the data storage address provided by the embodiment of the present application;

[0026] Figure 7 The flow chart of the data readout provided by the embodiment of the present application;

[0027] Figure 8 The schematic diagram of the transposed signal waveform provided by the embodiment of the present application;

[0028] Figure 9 The schematic diagram of the FPGA multi-board synchronization signal UDP sending system provided by the embodiment of the present application;

[0029] Figure 10 The structural schematic diagram of a computer device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0031] With the development of array signal processing technology and processor computing capacity, the data volume demand of real-time processing is gradually increasing. Due to the limited processing capacity of a single FPGA board, multiple FPGA boards often need to work cooperatively. For example, in a multi-antenna system, a single FPGA can process the data volume of 8 antenna units, and 160 antenna units need 20 FPGAs to work cooperatively to complete the synchronous acquisition and processing of data, and send the processed synchronous signals to the next functional module for further processing. How to send the FPGA multi-board synchronous signals so that the signals received by the next functional module are still in a synchronous state has become a key problem in system integration.

[0032] In order to realize the sending of FPGA multi-board synchronous signals, one method is that each FPGA board sends data to the receiver in turn, and the receiver recovers the synchronous signals through the arrival order of the data. However, this method is only applicable to the transmission architecture in which multiple FPGAs are directly connected to the receiver, and is not applicable to the transmission link environment with packet loss. For a wideband system, the digital channelization technology divides the wideband signal into multiple sub-band signals, thereby realizing the parallel processing and analysis of signals; in such a system, the channelization signals processed by the FPGA need to be sent to multiple processors, and each processor is responsible for the processing and analysis of part of the sub-band, so the multiple FPGAs need to be connected through a switch, and the switch needs to complete the distribution of the sub-band; for such a transmission architecture, the method of recovering the synchronous signals according to the arrival order of the data cannot be applied. Another method is to add clock stamp information before sending, and the receiver recovers the synchronous signals according to the time sequence. However, this method requires that the time information of multiple FPGAs be completely synchronized, which increases the complexity of system design and implementation; and in order to reduce the complexity of the receiver in recovering the synchronous signals, the FPGA data sending has additional requirements, such as that the data frames sent in each time stamp are integers, which increases the complexity of FPGA data sending. On the other hand, in order to meet the real-time processing demand of large data volume, the working clock frequency of the FPGA is often high, and it is necessary to reduce the fan-out as much as possible in design and implementation to reduce the wiring and timing pressure.

[0033] The embodiment of the present application provides a UDP sending method of FPGA multi-board synchronous signals. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0034] Please refer to Figure 1 , Figure 1 The flowchart of the UDP sending method of FPGA multi-board synchronous signals provided by the embodiment of the present application is as follows:Figure 1 As shown, the flow includes the following steps:

[0035] Step S1, according to the total number of subbands required by the receiver and the maximum subband capacity of the single transmission interface of the FPGA, determine the number of parallel output channels and the number of subbands per channel, filter the input channelized signal based on the total number of subbands to obtain valid subbands, and distribute the valid subbands based on the number of parallel output channels and the number of subbands per channel to generate a rate-matched channelized output signal.

[0036] Wherein, the total number of subbands required by the receiver is not greater than the total number of subbands of the input channelized signal. According to the total number of subbands required by the receiver, the input channelized signal is filtered to obtain valid subbands. Based on the serial number of the valid subbands, the valid subbands are distributed to parallel channels to complete rate matching and generate a channelized output signal arranged in time slot order. In the channelized output signal, for any time slot, the first subband data of each channel appears in the same clock cycle.

[0037] Step S3, for any output channel in the channelized output signal, the data of the same subband in a continuous specified number of time slots is encapsulated into a single subband frame, and the frame header of the single subband frame is provided with a sorting timestamp; wherein, the sorting timestamp is set in the following manner: in response to a synchronization reset signal, the values of the sorting timestamps of each FPGA board are synchronized and reset; for any FPGA in the reset state, if a first subband valid signal is detected, the FPGA enters a running state and the value of the corresponding sorting timestamp is updated to an initialization value; in the running state, every time a specified number of first subband valid signals are detected, the value of the sorting timestamp is increased by a specified step; if the value of the sorting timestamp reaches a preset maximum value, it is automatically reset to zero to realize cyclic counting.

[0038] Wherein, the channelized data of the same subband in a continuous specified number of time slots is encapsulated in the same frame, and the sorting timestamp, display timestamp, frame number, subband number and board number information are added to the frame header to complete single subband framing. The subband number indicates which subband the data payload of the current single subband frame is, the board number indicates which FPGA board the current single subband frame comes from, and the frame number is used to number each single subband frame within the same sorting timestamp. The generation and update rules of the sorting timestamps of each FPGA are consistent, so that the synchronized digital channelized signal still has a synchronized state after being sent. The sorting timestamp is used to realize the output synchronization of each FPGA board, without the need for high-precision clock hardware, thereby reducing the complexity and hardware cost of the synchronized output of each FPGA.

[0039] Step S5, add a UDP header to the single subband frame to generate a UDP data packet of a specified length through a padding mechanism.

[0040] A single sub-band frame consists of a frame header and a data payload, wherein the frame header contains information of sequencing timestamp, display timestamp, frame number, sub-band number, board number, and the data payload is data within a specified number of time slots (i.e. one time slot) of the same sub-band.

[0041] Step S7, generating IP datagram and Ethernet frame based on the UDP data packet and sending.

[0042] Finally, IP datagram and Ethernet frame are generated according to IP protocol and Ethernet frame format, and physical layer sending is completed based on GT core.

[0043] In some embodiments, the number of parallel output paths and the number of sub-bands per path are determined according to the total number of sub-bands required by the receiver and the maximum sub-band capacity of the single transmission interface of the FPGA, including: calculating a first ratio of the total number of sub-bands to the maximum sub-band capacity of the single transmission interface of the FPGA, rounding up the first ratio to obtain the number of parallel output paths; calculating a second ratio of the total number of sub-bands to the number of parallel output paths, and in the case that the total number of sub-bands is divisible by the number of parallel output paths, taking the second ratio as the number of sub-bands per path; in the case that the total number of sub-bands is not divisible by the number of parallel output paths, calculating the remainder of the total number of sub-bands divided by the number of parallel output paths, and determining the number of sub-bands per path based on the second ratio and the remainder.

[0044] In some embodiments, the number of sub-bands per path is determined based on the second ratio and the remainder, including: if the current output path sequence number is less than or equal to the remainder, rounding up the second ratio to obtain the number of sub-bands per path; if the current output path sequence number is greater than the remainder, rounding down the second ratio to obtain the number of sub-bands per path.

[0045] In some embodiments, the sub-band number of the effective sub-band is less than or equal to the total number of sub-bands; and for any time slot, the first data signals of each output path in the channelized output signal are aligned in the same clock cycle.

[0046] In some embodiments, the rate matching process includes:

[0047] First, the total number of sub-bands required by the receiver and the maximum sub-band capacity of the single transmission interface of the FPGA (i.e. the maximum number of sub-bands that can be sent by the single transmission interface are determined to determine the number of parallel output paths and the number of sub-bands per path of UDP sending.

[0048] ​The total number of subbands required by the receiver Maximum number of subbands that can be sent with a single FPGA transmission interface The first ratio, rounded up, is used as the number of parallel output paths sent via UDP. ,Right now: .like It can be If divisible, then evenly distributed, the number of sub-bands in each path. The total number of subbands required by the receiver Number of parallel output paths The second ratio, namely .like It cannot be Divisible by integers, calculate the total number of subbands required by the receiver. Number of parallel output paths The remainder, if the current output path number Less than or equal to the remainder, that is Then the total number of subbands required by the receiver will be... Number of parallel output paths The second ratio, rounded up, is the current output path (numbered as...). Number of subbands ,Right now If the current output path number is... The total number of subbands required by the receiver is greater than the total number of subbands required by the receiver. Number of parallel output paths The remainder, that is Then the total number of subbands required by the receiver will be... Number of parallel output paths The ratio is rounded down to the nearest integer as the current output path (number is...). Number of subbands ,Right now .

[0049] The receiver is a UDP communication receiver, and there can be one or more; the total number of subbands required by the receiver. This represents the sum of the actual needs of all receivers. The FPGA, acting as the sender in UDP communication, can be connected to the receiver either directly or via a switch.

[0050] For each FPGA board, the rate-matched channelized input signal is: Parallel roads, the first The number of routes is The channelized signal has a total number of subbands. The rate-matched channelized output signal is Parallel roads, the first The number of routes is The total number of subbands of the output signal is not greater than the total number of subbands of the input signal, and satisfies the following formula:

[0051]

[0052] The number of subbands of each output signal is not greater than the maximum number of subbands that can be transmitted by the single transmission interface of the FPGA, and needs to satisfy:

[0053]

[0054] In the above formula, is the total number of subbands required by the receiver, is the maximum number of subbands that can be transmitted by the single transmission interface of the FPGA.

[0055] The maximum number of subbands that can be transmitted by the single transmission interface of the FPGA is related to the maximum transmission rate of the single transmission interface , the channelization clock frequency , and the data bit width of a single time slot of a single subband , and satisfies , wherein, is the number of clock cycles occupied by a time slot of the channelized input signal.

[0056] For example, the maximum transmission rate of the single transmission interface is 100 Gbps, the channelization clock frequency is 350 MHz, the data bit width of a single time slot of a single subband is 256 bits, and each time slot occupies no less than 256 clock cycles. Then the maximum number of subbands that can be transmitted by a single transmission interface is If the total number of subbands required by the receiver is 320, then the number of parallel paths of the UDP transmission is , and the number of subbands transmitted by each path is 160.

[0057] Then, the channelized input signal is filtered according to the total number of subbands required by the receiver . The channelized signal with a subband number less than or equal to the total number of subbands required by the receiver and being valid is cached, the signal with a subband number less than or equal to is output to the first path, the signal with a subband number greater than and less than or equal to is output to the th path. .

[0058] The clock domain used by the input channelized signal is the same as the channelization clock domain, and the reset is completed under the control of the synchronization reset signal. After receiving the reset instruction of the synchronization reset signal, the first Lu Mei Each channelized signal is divided into a group, denoted as Group 1, Group 2, Group 3, and so on; then each group contains... The input consists of channelized data, which are signals belonging to different sub-bands within the same time slot. (Time slot) The channelization signal output of different subbands occupies One clock cycle. For different time slots It can be the same fixed value or an indefinite value. The first value in rate matching... Validity of input signal passed Signal representation, if A value of 1 indicates the first... The channelized signal input to the first path is valid; otherwise, it is invalid. Rate matching... The sub-band number of the input signal is obtained through Signal representation, satisfying , .

[0059] The first rate matching The validity of the output signal is verified. Signal representation, if A value of 1 indicates the first... The channelized signal output by the first path is valid; otherwise, it is invalid. Rate matching... The sub-band number of the output signal is obtained through Signal representation, satisfying , Upon receiving the reset command from the synchronous reset signal, the first... Lu Mei Each channelized signal is divided into a group, denoted as Group 1, Group 2, Group 3, and so on; then each group contains... These are channelized data signals belonging to different subbands within the same time slot. For each time slot, the first valid input signal of each channel occurs within the same channelized clock cycle, and the first valid output signal of each channel also occurs within the same channelized clock cycle.

[0060] For example, please refer to Figure 2 , Figure 2 This is a schematic diagram of the input channelized signal provided in an embodiment of this application. The input channelized signal is a dual-channel channelized signal with 200 sub-bands per channel, and its effectiveness... With sub-band number Waveform examples are as follows Figure 2 As shown, time slot N occupies 256 channelized clock cycles, and time slot N+1 also occupies 256 channelized clock cycles. Furthermore, the valid signals of sub-bands 1 and 201 appear in the same channelized clock cycle. Please refer to... Figure 3 ,Figure 3 The schematic diagram of the channelized output signal provided by the embodiment of the present application is shown in FIG. 3. The rate-matched output signal is a signal with two parallel paths and 160 subbands per path, and the waveform of the validity of the subband number is shown in FIG. 3. Time slot N occupies 256 channelized clock cycles, time slot N+1 also occupies 256 channelized clock cycles, and the valid signals of subbands numbered 1 and 161 appear in the same channelized clock cycle. Please refer to FIG. 3. Figure 3 Figure 4 Figure 4 The schematic diagram of the frame header format provided by the embodiment of the present application is shown in FIG. 4. As shown in FIG. 4, the length is 16 bytes; the data payload is the data of a single subband Figure 4 For example, the data bit width of each time slot is 256 bits, and the length of the data payload is 6400 bytes.

[0061] In some embodiments, the generation of the channelized output signal and the packaging of the single-subband frame share the synchronous reset signal and the channelized clock domain; the generation of the UDP data packet and the generation and transmission of the IP datagram and the Ethernet frame share the transmission reset signal and the transmission clock domain; the clock domain conversion of the single-subband frame from the channelized clock domain to the transmission clock domain is performed, and the UDP header is added based on the single-subband frame after the clock domain conversion.

[0062] In the fixed-length UDP data packet generation process, the single-subband frame is taken as the input, and the conversion from the channelized clock domain to the transmission clock domain is first performed. Each single-subband frame is the data payload of the UDP data packet. Through the differentiation of the synchronous reset signal and the transmission reset signal, the fan-out of the reset signal is reduced.

[0063] The pull-up of the transmission reset signal needs to be performed only once, and the number of pull-ups of the synchronous reset signal is determined by the generation strategy of the multi-board synchronization signal. In order to realize the multi-board synchronization of the channelized signal, two or more synchronous reset operations may be required. For example, the first synchronous reset is used for the synchronization of the single-board multi-channel channelized signal, the second synchronous reset is used for the synchronization of the channelized signal between the multi-boards, and the third synchronous reset is used for improving the synchronization performance. For each single-subband frame, the conversion from the channelized clock domain to the transmission clock domain is performed, and the UDP header is added according to the UDP protocol to form the UDP data packet with a specified length.

[0064] In some embodiments, the conversion from the channelized clock domain to the transmission clock domain is realized by using an asynchronous FIFO; based on the state of the asynchronous FIFO and the value of the current sequencing timestamp, the execution of the single-subband frame packaging is controlled.

[0065] In the conversion from the channelized clock domain to the transmission clock domain, the asynchronous FIFO is used, and after the reset is completed, the asynchronous FIFO needs to wait for ​​​​one slow clock cycle. Only when the asynchronous FIFO is ready, the single sub-band framing can be driven.

[0066] In some embodiments, for any one of the channelized output signals, encapsulating data of the same sub-band in a continuous specified number of time slots as a single sub-band frame comprises: performing a transposition operation on the specified number of time slot data of any one of the output signals, so that the data of the same sub-band of the specified number of time slots is output continuously, and the data of different sub-bands is output with a specified number of clock cycles in between.

[0067] In some embodiments, the working process of the single sub-band framing provided by the embodiments of the present application specifically comprises the following steps:

[0068] (1) judging whether the state of the asynchronous FIFO is ready.

[0069] Among them, the conversion from the channelization clock domain to the transmission clock domain is realized based on the asynchronous FIFO. After the reset is completed, the asynchronous FIFO needs to wait one slow clock cycle to be ready, for example .

[0070] Real-time acquisition of the ready state of the asynchronous FIFO, the state value of 1 indicates that it is ready, and the state value of 0 indicates that it is not ready; if the state of the asynchronous FIFO is ready, i.e. the state value is 1, go to step (2); otherwise, execute this step again.

[0071] (2) obtaining the ordering timestamp value of the current clock cycle, if the ordering timestamp value is greater than zero and less than , then taking this value as the timestamp threshold, and then going to step (3); otherwise, executing this step again.

[0072] Among them, the bit width of the ordering timestamp is , which is used to indicate the rough time sequence, and the ordering timestamps of each FPGA board card are synchronized. In order to realize the synchronization of the ordering timestamps of multiple boards, the counting process of the ordering timestamp is as follows: when the synchronization reset signal is pulled high, the ordering timestamp is reset to , wherein is always equal to 0; then waiting for the output signal of rate matching, if the first sub-band valid signal of the first channel (the first channel signal is valid and is the first sub-band of the first channel) is detected, i.e. and , then the ordering timestamp is initialized to , which can be a fixed value, otherwise the ordering timestamp remains unchanged. When each FPGA board card detects the first sub-band valid signal of the first channel, the corresponding timestamp is initialized to This ensures that the starting times of multiple boards are aligned.

[0073] After the sorting timestamp is initialized, for any FPGA, each received The second-to-last sub-band valid signal (the first signal is valid and is the last sub-band of the first channel), i.e. and Then the sort timestamp value is incremented by 1 until... Then, if another one is received Second-rate and Upon receiving the signal, the sort timestamp is updated to 0 to avoid overflow errors. Then, each time a signal is received... Second-rate and If the signal is received, the sorted timestamp value will increase by a specified step until... This process repeats. The specified step size can be 1. , R is a positive integer.

[0074] For example, the bit width of the sorted timestamp is 30. , R is 6400; when the synchronization reset signal goes high, the sorting timestamp is reset to 0; then it waits for the rate matching output signal, and if the first valid signal of the first sub-band is detected for the first time, i.e. and If the sort timestamp is not initialized, it is set to 100; otherwise, it remains at 0. After initialization, the sort timestamp is set to 100 every 1,280,000 valid signals from the first and last sub-bands. and If the sort timestamp value is greater than 1000, then the sort timestamp value is incremented by 1. A timestamp threshold is set, for example, to 1000. Framing only begins when all FPGA boards are at the same timestamp state, i.e., all sort timestamps are greater than 1000, thus ensuring global synchronization. The timestamp threshold defines a safe start boundary for single-subband framing.

[0075] (3) Determine if the current value of the timestamp is valid. If the sorted timestamp of the current clock cycle is greater than the timestamp threshold, it means that the current value of the sorted timestamp is valid, and proceed to step (4); otherwise, execute this step again. For example, if the timestamp threshold is 1000, proceed to the next step only if the sorted timestamp of the current channelized clock cycle is 1001.

[0076] (4) For the first The road, with Each valid data point is grouped together. For the rate-matched output channelized signal and its corresponding sorted timestamp, transpose and buffer operations are performed respectively, ensuring that the same sub-band... Data from each time slot is output within a continuous clock cycle, with at least a time interval between data from different sub-bands on the same path. One clock cycle; while outputting single sub-band data, read the current sub-band from the buffer. The sorting timestamp and display timestamp corresponding to the first timestamp in each timestamp. Then, proceed to step (5).

[0077] Please refer to Figure 5 , Figure 5 This is a schematic diagram of a state machine model provided in an embodiment of this application. Figure 5 As shown, a transpose operation is performed on the rate-matched output channelized signal. State 0 is the initialization state, state 1 is writing to the first data buffer module, state 2 is writing to the second data buffer module and reading out of the first data buffer module, and state 3 is writing to the second data buffer module and reading out of the first data buffer module. For example, the number of sub-bands... The number of time slots is 160. Please refer to the following: Figure 6 , Figure 6 This is a schematic diagram of the data storage address provided in the embodiments of this application. The data storage addresses of the first data buffer module and the second data buffer module are as follows: Figure 6 As shown, the data storage address interval between adjacent sub-bands in the same time slot is 200, and the data storage address interval between adjacent time slots in the same sub-band is 1.

[0078] exist Figure 5 In the state machine model shown, the write count is calculated as follows: the write count in state 0 is always 0; after entering state 1, the count of the first valid data received is 1, and the count is incremented by 1 for each subsequent valid data received until the count reaches 1. Then the count for the next valid data is 1, and the count is incremented by 1 for each subsequent valid data received until the count reaches 1. ; repeat in sequence.

[0079] Please refer to Figure 7 , Figure 7 A flowchart illustrating data reading provided in embodiments of this application. Figure 5 In the state machine model shown, the flowchart for data reading is as follows: Figure 7 As shown, the specific process is as follows:

[0080] a) At the start of state 2 or state 3, read the first data and then proceed to step b). Specifically, set the read enable to 1, the read address to 0, the read slot count to 1, and the read pause count to 0.

[0081] The value of read enable is 0 or 1, and the value 1 indicates reading data from a storage address of the data buffer module, and the storage address is the value of the read address; the value 0 indicates not reading data. The value of read slot count ranges from 1 to , indicating the slot count in a single sub-band frame. The read pause count is used to control the interval of single sub-band frames of two adjacent sub-bands.

[0082] b) judging whether the value of the slot count is less than the number of slots , if yes, entering step c); otherwise, entering step d).

[0083] c) continuously reading data of different slots of the same sub-band. Specifically, setting the read enable to 1, the read address to +1, the read slot count to +1, and the read pause count to 0; then, entering step b).

[0084] d) judging whether the read address is less than , if yes, entering step e); otherwise, entering step h.

[0085] e) judging whether the read pause count is less than the interval of single sub-band frames , if yes, entering step f); otherwise, entering step g).

[0086] f) pausing data reading. Specifically, setting the read enable to 0, the read address to be unchanged, the read slot count to be unchanged, and the read pause count to +1; then, entering step b).

[0087] g) reading the first data of the next sub-band, and then entering step b). Specifically, setting the read enable to 1, the read address to +1, the read slot count to 1, and the read pause count to 0.

[0088] h) completing data reading. Specifically, setting the read enable to 0, the read address to be unchanged, the read slot count to be unchanged, and the read pause count to 0.

[0089] For example, if the channelized output signal is a signal of two parallel paths and each path has 160 sub-bands, each time slot occupies no less than 256 clock cycles, , then , please refer to Figure 8 , Figure 8 for the signal waveform diagram provided by the embodiment of the present application after transposition.

[0090] The to-be-encapsulated sorting time stamp corresponding to the data transposed output signal has the following characteristics: the data read from the same data buffer module has the same to-be-encapsulated sorting time stamp. For example, in the implementation, a FIFO is used to complete the caching and reading of the sorting time stamp; specifically, for the data read from the same data buffer module, the to-be-encapsulated sorting time stamp is the same. Figure 5As shown in the state machine model, the ordering timestamp of the clock cycle is written into the FIFO whenever the write count is 1; the ordering timestamp is read out whenever the read enable is 1, the read-out time slot count is 1, and the read address is 0, and the to-be-encapsulated ordering timestamp is updated to the value.

[0091] The display timestamp is used to identify the real physical time of data collection or generation. The PS (Processing System) issues the UTC time once per second, including the year, month, day, and second information. The bit width of the display timestamp is , wherein , , , are respectively used for the year, month, day, and second information, and are used to inform the receiving party of the acquisition time of the channelized data. When the synchronization reset signal is pulled high, the display timestamp is reset to ; then, the latest UTC time issued by the PS is read, and the value of the display timestamp is updated. The display timestamps of different FPGA boards can be unsynchronized, but do not affect the multi-board FPGA synchronization, and the receiving party can only use the display timestamp of one FPGA. By using the ordering timestamp and the display timestamp, the implementation complexity of time synchronization and the complexity of data transmission are reduced.

[0092] (5) The frame number of each single sub-band frame is obtained in the order, and if the data of multiple single sub-band frames are in the same clock cycle, the smaller has the smaller frame number. Then, the ordering timestamp, the display timestamp, the frame number, the sub-band number, and the board number information are added according to the frame header format, and the single sub-band frame is generated.

[0093] The frame number is used to number the single sub-band frames in the same ordering timestamp, and the ordering timestamp and the frame number together determine the fine time sequence. There are frame numbers for each ordering timestamp value; after the value of the ordering timestamp changes, the frame number is numbered from 0 again; the value range of the frame number is 0 to . For example, for the waveform diagram shown in Figure 8 , the data of 200 time slots of sub-band 1 and sub-band 161 are in the same clock cycle, and the frame number of sub-band 1 is smaller than that of sub-band 161, for example, the frame number of sub-band 1 is 0, and the frame number of sub-band 161 is 1.

[0094] The output of the single sub-band frame is controlled by the synchronization reset signal, and when the synchronization reset signal is pulled high, the single sub-band framing is reset. If the reset operation is not located in the frame interval of the single sub-band frame, the output of the single sub-band frame will have an incomplete phenomenon, that is, the data payload of a certain single sub-band frame is less than time slots.

[0095] All the boards are triggered to update the sequencing timestamp in the same rule, so that the global timestamp can be kept synchronized. The sequencing timestamp provides a global timing reference without the need of high-precision clock hardware. Even if the delay is different after the data is forwarded through the switch, the receiver can still reorganize the timing through the sequencing timestamp. Through the synchronization reset and the unified data-driven sequencing timestamp mechanism, the global timing synchronization of multiple FPGA boards is realized at a low cost.

[0096] In some embodiments, a UDP header is added to the single sub-band frame, and a UDP data packet of a specified length is generated through a padding mechanism, including: generating a corresponding UDP header based on the sub-band number of the single sub-band frame; if the payload length in the single sub-band frame is less than the specified length, padding the single sub-band frame data to the specified length, and adding the UDP header to the padded single sub-band frame to generate the UDP data packet of the specified length.

[0097] Specifically, a UDP header is added according to the UDP protocol to form a UDP data packet of a specified length; wherein the UDP source port number and the UDP destination port number contained in the UDP header are configured according to the sub-band number. When adding the UDP header, for an incomplete single sub-band frame, after the UDP header is added, data padding is performed, so that the output of the UDP data packet always contains the channelized data of a single sub-band (without the data of the remaining sub-bands), and the byte number of the packet length is always , wherein the frame header byte number of the single sub-band frame, the byte number of the single time slot channelized data. For a complete single sub-band frame, after the UDP header is added, the packet length of the UDP data packet is still . For example, , , When the single sub-band frame with the sub-band number 12 is preparing to output the data of the 8th time slot, the synchronization reset signal is pulled high, so that the data payload of the frame only contains the data of 7 time slots, and the frame length is 16+7x32=240 bytes; in the generation process of the fixed-length UDP data packet, the UDP header is added to the single sub-band frame, and zero data is added at the tail of the data frame, so that the length of the UDP data packet is 8+16+200x32=6424 bytes.

[0098] In the generation process of the IP datagram and the Ethernet frame, the input UDP data packet always has a fixed packet length. The UDP source port number and the UDP destination port number contained in the UDP header, the IP source address and the IP destination address contained in the IP datagram, and the source MAC address and the destination MAC address contained in the Ethernet frame are all configured according to the sub-band number.

[0099] Please refer to Figure 9 ,Figure 9 The schematic diagram of the FPGA multi-board synchronization signal UDP sending system provided in the embodiment of the present application is shown in FIG. 1. Figure 9 As shown in FIG. 1, the system comprises: a rate matching module, configured to determine the number of parallel output channels and the number of subbands per channel according to the total number of subbands required by a receiver and the maximum subband capacity of a single FPGA transmission interface, filter the input channelized signal based on the total number of subbands to obtain valid subbands, and distribute the valid subbands based on the number of parallel output channels and the number of subbands per channel to generate a rate-matched channelized output signal; a packaging module, configured to package the data of the same subband within a continuous specified number of time slots in any output channel of the channelized output signal as a single subband frame, and set a sorting timestamp in the frame header of the single subband frame; wherein the sorting timestamp is set in the following manner: in response to a synchronization reset signal, the values of the sorting timestamps of all FPGA boards are reset synchronously; for any FPGA in the reset state, if a first subband valid signal in a first channel is detected, the FPGA enters a running state, and the value of the corresponding sorting timestamp is updated to an initialization value; in the running state, the value of the sorting timestamp is increased by a specified step size every time a specified number of first subband valid signals in the last subband of the first channel are detected; if the value of the sorting timestamp reaches a preset maximum value, the sorting timestamp is automatically reset to zero to realize cyclic counting; a first generation module, configured to add a UDP header to the single subband frame to generate a UDP data packet of a specified length through a padding mechanism; and a second generation module, configured to generate an IP datagram and an Ethernet frame based on the UDP data packet and send the same.

[0100] The rate matching module and the packaging module share the synchronization reset signal and the channelized clock domain; the first generation module and the second generation module share the transmission reset signal and the transmission clock domain.

[0101] The further function descriptions of the above modules and units are the same as those of the corresponding embodiments described above, and will not be described here again.

[0102] The FPGA multi-board synchronization signal UDP sending system in the embodiment is presented in the form of functional units, where the units refer to ASIC (Application Specific Integrated Circuit) circuits, processors and memories executing one or more software or fixed programs, and / or other devices that can provide the above functions.

[0103] Please refer to Figure 10 , Figure 10 FIG. 2 is a structural schematic diagram of a computer device provided in the embodiment of the present application, as shown in FIG. 2. Figure 10As shown, the computer device includes one or more processors 10, memory 20, and interfaces 30 for the various components to communicate with one another. The various components communicate through the use of the various buses, and can be mounted on a common motherboard or in other manners as appropriate. The processor 10 can process instructions for execution within the computer device, including instructions stored in the memory 20 or elsewhere to implement routines for displaying graphical information, such as a GUI on an external input / output device, such as a display device coupled to the interface 30. In some embodiments, multiple processors and / or multiple buses can be employed as appropriate, as will be appreciated by those skilled in the art. Additionally, various components of the computer device can be used for processing instructions according to the embodiments, as will be appreciated. The computer device 100 is further illustrated in terms of a number of functional components and various embodiments include fewer, different and / or additional components not shown in FIG. 1. For example, the computer device 100 can also include one or more communication devices 40, such as a modem or network interface adapter to enable communications with a network. The computer device 100 can also include one or more input / output devices 50, such as a keyboard, mouse, or other input device to allow a user to interact with the computer device 100. Additionally, the computer device 100 can include one or more output devices 60, such as displays or speakers to facilitate output to a user. Figure 10 The processor 10 is used as an example in the embodiments.

[0104] The processor 10 can be a central processing unit, a network processor, or a combination thereof. The processor 10 can further include a hardware chip. The hardware chip can be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device can be a complex programmable logic device, a field programmable logic device, a general array logic, or any combination thereof.

[0105] The memory 20 stores instructions that are executable by the at least one processor 10 to cause the at least one processor 10 to perform the methods illustrated in the embodiments.

[0106] The memory 20 can include a program storage area and a data storage area. The program storage area can store an operating system, application programs, etc. required by at least one function. The data storage area can store data created by the computer device, etc. In addition, the memory 20 can include a high-speed random access memory, and can further include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some alternative embodiments, the memory 20 can optionally include a memory that is remotely located with respect to the processor 10, and these remote memories can be connected to the computer device through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0107] The memory 20 can include a volatile memory, such as a random access memory, and can also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. The memory 20 can also include an array of memories of the same kind or of different kinds.

[0108] The computer device further includes a communication interface 30 for the computer device to communicate with other devices or communication networks.

[0109] The embodiments of the present application further provide a computer readable storage medium, and the method according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or be implemented as computer code stored in a remote storage medium or a non-transitory machine readable storage medium and stored in a local storage medium to be downloaded through a network, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special hardware. The storage medium can be a disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid state disk, etc. Further, the storage medium can also include a combination of the above-mentioned memories. It can be understood that the computer, the processor, the microprocessor controller, or the programmable hardware includes a storage component that can store or receive software or computer code, which, when accessed and executed by the computer, the processor, or the hardware, implements the method shown in the above embodiments.

[0110] The embodiments of the present application provide a computer program product, which includes computer instructions stored in a computer readable storage medium. A processor of a computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to enable the computer device to perform the method of any of the embodiments of the present application.

[0111] The system or module illustrated in the above embodiments can be implemented by a computer chip or entity, or by a product having certain functions. A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0112] For the convenience of description, the above apparatus is described as various units in terms of functions to be described respectively. Of course, functions of the units can be implemented in one or more software and / or hardware in the implementation of the present application.

[0113] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0114] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart or flowsheet block or blocks. Figure 1 one or more flowchart or flowsheet blocks Figure 1 one or more flowchart or flowsheet blocks

[0115] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart or flowsheet block or blocks. Figure 1 one or more flowchart or flowsheet blocks Figure 1 one or more flowchart or flowsheet blocks

[0116] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart or flowsheet block or blocks. Figure 1 one or more flowchart or flowsheet blocks Figure 1 Figure 1 one or more flowchart or flowsheet blocks

[0117] It should be further understood that the terms "comprise", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements in the list, but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0118] Each of the embodiments in the present specification is described in a progressive manner, and the same or similar parts between the embodiments can be mutually referred to. Each of the embodiments mainly explains the difference from other embodiments. In particular, for the system embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiments.

[0119] The above merely provides an example of the present application, but is not intended to limit the present application. The present application can have various modifications and changes for those skilled in the art. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the scope of claims of the present application.

[0120] Although the embodiments of the present application are described with reference to the drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes shall fall within the scope defined by the appended claims.

Claims

1. A method for transmitting UDP synchronization signals across multiple FPGA boards, characterized in that, The method includes: Based on the total number of subbands required by the receiver and the maximum subband capacity of a single FPGA transmission interface, the number of parallel output channels and the number of subbands per channel are determined. The input channelized signal is filtered based on the total number of subbands to obtain effective subbands. The effective subbands are allocated based on the number of parallel output channels and the number of subbands per channel to generate a rate-matched channelized output signal. For any output of the channelized output signal, the data of the same sub-band within a specified number of consecutive time slots is encapsulated into a single sub-band frame, and the frame header of the single sub-band frame is provided with a sorting timestamp; wherein, the sorting timestamp is set as follows: in response to the synchronization reset signal, the value of the sorting timestamp of each FPGA board is synchronously reset; for any FPGA in the reset state, if the first sub-band valid signal is detected, it enters the running state and updates the value of the corresponding sorting timestamp to the initial value; in the running state, every time the first last sub-band valid signal is detected a specified number of times, the value of the sorting timestamp is incremented by a specified step size; if the value of the sorting timestamp reaches the preset maximum value, it is automatically reset to zero to achieve cyclic counting; Add a UDP header to a single subband frame and generate UDP packets of a specified length using a padding mechanism; Based on the UDP data packet, generate IP datagrams and Ethernet frames and send them.

2. The method according to claim 1, characterized in that, Based on the total number of subbands required by the receiver and the maximum subband capacity of a single FPGA transmission interface, determine the number of parallel output channels and the number of subbands per channel, including: Calculate the first ratio of the total number of sub-bands to the maximum sub-band capacity of a single FPGA transmission interface, round the first ratio up, and use the rounded result as the number of parallel output channels; Calculate a second ratio between the total number of sub-bands and the number of parallel output channels. If the total number of sub-bands is divisible by the number of parallel output channels, use the second ratio as the number of sub-bands per channel. If the total number of sub-bands is not divisible by the number of parallel output channels, calculate the remainder when the total number of sub-bands is divided by the number of parallel output channels. Based on the second ratio and the remainder, determine the number of sub-bands per channel.

3. The method according to claim 2, characterized in that, Based on the second ratio and the remainder, the number of sub-bands for each path is determined, including: if the current output path number is less than or equal to the remainder, the second ratio is rounded up, and the result obtained by rounding up is used as the number of sub-bands for the current output path; if the current output path number is greater than the remainder, the second ratio is rounded down, and the result obtained by rounding down is used as the number of sub-bands for the current output path.

4. The method according to claim 1, characterized in that, The method further includes: the sub-band number of the effective sub-band is less than or equal to the total number of sub-bands; for any time slot, the first data signal output from each channel in the channelized output signal is aligned in the same clock cycle.

5. The method according to claim 1, characterized in that, The method further includes: the generation of the channelized output signal and the encapsulation of the single subband frame share a synchronous reset signal and a channelized clock domain; the generation of UDP packets and the generation and transmission of IP datagrams and Ethernet frames share a transmission reset signal and a transmission clock domain; the single subband frame is converted from the channelized clock domain to the transmission clock domain, and a UDP header is added to the single subband frame after the clock domain conversion.

6. The method according to claim 5, characterized in that, The method further includes: implementing the conversion from the channelized clock domain to the transmission clock domain through an asynchronous FIFO; and controlling the execution of single-subband frame encapsulation based on the state of the asynchronous FIFO and the value of the current sorting timestamp.

7. The method according to claim 1, characterized in that, For any output of the channelized output signal, data from the same subband within a specified number of consecutive time slots is encapsulated into a single subband frame, including: Perform a transpose operation on a specified number of time slots of data from any output channel, so that the data of the same sub-band in the specified number of time slots is output continuously, and the data of different sub-bands are output at intervals of a specified number of clock cycles.

8. The method according to claim 1, characterized in that, The frame header also includes a display timestamp, frame number, sub-band number, and board number; wherein, the frame number is used to number each single sub-band frame within the same sorted timestamp.

9. The method according to claim 1, characterized in that, Adding a UDP header to a single subband frame and generating a UDP packet of a specified length through a padding mechanism includes: generating a corresponding UDP header based on the subband number of the single subband frame; if the payload length in the single subband frame is less than the specified length, padding the single subband frame data to the specified length and adding the UDP header to the padded single subband frame to generate a UDP packet of the specified length.

10. A UDP transmission system for FPGA multi-board synchronization signals, employing the UDP transmission method for FPGA multi-board synchronization signals as described in any one of claims 1-9, characterized in that, The system includes: The rate matching module is used to determine the number of parallel output channels and the number of sub-bands per channel based on the total number of sub-bands required by the receiver and the maximum sub-band capacity of a single FPGA transmission interface. Based on the total number of sub-bands, the input channelized signal is filtered to obtain effective sub-bands. Based on the number of parallel output channels and the number of sub-bands per channel, the effective sub-bands are allocated to generate a rate-matched channelized output signal. The encapsulation module is used to encapsulate data from the same subband within a specified number of consecutive time slots into a single subband frame for any output of the channelized output signal. The frame header of the single subband frame has a sorting timestamp. The sorting timestamp is set as follows: in response to a synchronization reset signal, the sorting timestamp values ​​of each FPGA board are synchronously reset; for any FPGA in the reset state, if a valid first subband signal is detected, it enters the running state and updates the corresponding sorting timestamp value to the initial value; in the running state, every time a valid first-to-last subband signal is detected a specified number of times, the sorting timestamp value is incremented by a specified step size; if the sorting timestamp value reaches a preset maximum value, it is automatically reset to zero to achieve cyclic counting. The first generation module is used to add UDP headers to single subband frames and generate UDP packets of a specified length through a padding mechanism. The second generation module is used to generate IP datagrams and Ethernet frames based on the UDP datagrams and send them.

Images