Semiconductor structure, preparation method thereof and electronic equipment

Abstract

The invention relates to a semiconductor structure, a preparation method thereof and electronic equipment. The semiconductor structure comprises a bit line, a common source line and a storage unit. The bit lines and the common source lines are arranged along a first direction and extend along a second direction. The memory cell includes a first transistor and a second transistor. The first transistor is located between the bit line and the common source line in the first direction, and the first channel layer is connected with the bit line in the first direction. The second transistor comprises a second grid electrode, a second gate dielectric layer and a second channel layer. The second grid electrode is located between the first transistor and the common source line and comprises a storage grid, a dielectric layer and a control grid. The dielectric layer surrounds the control gate. The storage gate surrounds the dielectric layer and is connected with the first channel layer in the first direction. The second gate dielectric layer is located between the storage gate and the second channel layer in the second direction. The two sides of the second channel layer in the first direction are connected with the bit line and the common source line respectively. The storage density can be effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a semiconductor structure, a preparation method thereof, and an electronic device. BACKGROUND

[0002] With the development of integrated circuit technology, the critical dimension of devices is increasingly reduced, and the types and quantities of devices contained in a single chip are also increased, so that any slight difference in process production can affect the performance of the devices.

[0003] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs. SUMMARY

[0004] Based on this, the present application provides a semiconductor structure which can effectively improve the storage density, a preparation method thereof, and an electronic device.

[0005] A semiconductor structure, comprising:

[0006] a bit line and a common source line, the bit line and the common source line are arranged along a first direction, and both of them extend along a second direction, the second direction intersects the first direction;

[0007] a storage unit, the storage unit comprises:

[0008] a first transistor, located between the bit line and the common source line in the first direction, comprising a first gate, a first gate dielectric layer, and a first channel layer, the first gate dielectric layer surrounds the first gate, the first channel layer surrounds the first gate dielectric layer, and connects the bit line in the first direction;

[0009] a second transistor, comprising a second gate, a second gate dielectric layer, and a second channel layer; the second gate is located between the first transistor and the common source line in the first direction, and comprises a storage gate, a dielectric layer, and a control gate, the dielectric layer surrounds the control gate, the storage gate surrounds the dielectric layer, and connects the first channel layer in the first direction; the second gate dielectric layer extends along the first direction and is located between the bit line and the common source line, and is located between the storage gate and the second channel layer in the second direction; the second channel layer extends along the first direction and connects the bit line and the common source line on both sides in the first direction.

[0010] In one of the embodiments, the second transistor comprises a junctionless P-type transistor.

[0011] In one of the embodiments, the storage gate is provided with the second gate dielectric layer and the second channel layer connected thereto on both sides thereof in the second direction.

[0012] In one of the embodiments, the second gate dielectric layer is further located between the first channel layer and the second channel layer in the second direction.

[0013] In one of the embodiments, the second channel layer comprises a first doped region, a second doped region and a channel region located therebetween, the first doped region is connected to the bit line, the second doped region is connected to the common source line, and the channel region is located on the surface of the second gate dielectric layer away from the storage gate.

[0014] In one of the embodiments, the same common source line is provided with the storage unit connected thereto on both sides thereof in the first direction.

[0015] In one of the embodiments, the semiconductor structure further comprises:

[0016] a substrate, the substrate is provided with a plurality of layers of the storage unit arranged in an array in the first direction and the second direction, wherein the first direction and the second direction are both parallel to the substrate;

[0017] a first word line, extending from the top layer of the storage unit to the substrate and comprising the first gate of a plurality of the first transistors arranged perpendicularly to the substrate;

[0018] a second word line, extending from the top layer of the storage unit to the substrate and comprising the control gate of a plurality of the second transistors arranged perpendicularly to the substrate;

[0019] the common source line, extending from the top layer of the storage unit to the substrate and connecting the second channel layer of a plurality of the second transistors arranged perpendicularly to the substrate and in the second direction.

[0020] In one of the embodiments, the semiconductor structure further comprises:

[0021] a stack layer, located on the substrate, comprising first dielectric layers and second dielectric layers alternately stacked, the storage unit and the bit line being embedded in the second dielectric layer;

[0022] a first filling layer, located on the side of the second channel layer away from the second gate dielectric layer in the second direction and extending from the top layer of the storage unit to the substrate;

[0023] a second filling layer, located on the side of the bit line away from the storage unit in the first direction and extending from the top layer of the storage unit to the substrate;

[0024] A third filling layer is located between the first channel layer and the first gate dielectric layer and the first dielectric layer, or between the first gate dielectric layer and the first dielectric layer, and insulates and separates the first channel layer and the first word line.

[0025] A method for manufacturing a semiconductor structure, comprising:

[0026] A substrate is provided.

[0027] A second transistor is formed on the substrate, the second transistor comprising a second gate, a second gate dielectric layer and a second channel layer; the second gate comprising a storage gate, a dielectric layer and a control gate, the dielectric layer surrounding the control gate, and the storage gate surrounding the dielectric layer; the second gate dielectric layer extending in a first direction and connected to the storage gate in a second direction; the second channel layer extending in the first direction and located on a side of the second gate dielectric layer away from the storage gate in the second direction; wherein the first direction and the second direction are both parallel to the substrate and intersect with each other.

[0028] A bit line and a common source line are respectively formed on opposite sides of the second gate in the first direction, the bit line and the common source line both extending in the second direction, and the bit line and the common source line being connected to two sides of the second channel layer in the first direction, respectively.

[0029] A first transistor is formed between the bit line and the second gate, the first transistor comprising a first gate, a first gate dielectric layer and a first channel layer, the first gate dielectric layer surrounding the first gate, and the first channel layer surrounding the first gate dielectric layer and being connected to the bit line and the storage gate in the first direction, respectively.

[0030] In one embodiment, forming a second transistor on the substrate comprises:

[0031] A stack material layer is formed on the substrate, the stack material layer comprising first dielectric material layers and second dielectric material layers alternately stacked;

[0032] The stack material layer is etched to form a first opening, the first opening comprising a first through hole and a first lateral hole, the first lateral hole being communicated with the first through hole and formed by laterally etching the second dielectric material layer;

[0033] A second gate dielectric initial layer and a second channel layer are formed in the first lateral hole, and a first filling layer is formed in the remaining space in the first opening, the second gate dielectric initial layer being formed on the surface of the second dielectric material layer exposed by the first lateral hole, and the second channel layer being formed on the surface of the second gate dielectric initial layer.

[0034] forming a second opening by etching the stack of material layers, the second opening including a second via and a second lateral hole, the second lateral hole being in communication with the second via and being formed by etching the second dielectric material layer laterally, the second via having a dimension in the first direction that is smaller than a dimension of the first via in the first direction, and the second via being located on one side of the first via in the second direction;

[0035] forming a second gate in the second opening, the second gate including a storage gate, a dielectric layer, and a second word line, the storage gate being formed in the second lateral hole, the dielectric layer being formed on a surface of the storage gate, a sidewall and a bottom of the second via, and the second word line being formed on a surface of the dielectric layer and filling a remaining space of the second opening, the second word line including a plurality of the control gates of the second transistors arranged perpendicularly to the substrate;

[0036] removing portions of the second gate dielectric initial layer that cover both ends of the second channel layer in the first direction to form a second gate dielectric layer.

[0037] In one embodiment, when the stack of material layers is etched to form the first opening, at least two first openings are formed that are oppositely arranged in the second direction; and when the stack of material layers is etched to form the second opening, the second opening is formed between the two first openings that are oppositely arranged in the second direction.

[0038] In one embodiment, the forming of the second gate dielectric initial layer and the second channel layer in the first lateral hole, and the forming of the first filling layer in the remaining space of the first opening, include:

[0039] sequentially forming a second gate dielectric material layer, a second channel material layer, and an insulating protective material layer on a surface of the structure after the first opening is formed;

[0040] removing the insulating protective material layer that is outside the first lateral hole to form an insulating protective layer;

[0041] based on the insulating protective layer, removing the second channel material layer and the second gate dielectric material layer that are outside the first lateral hole to form the second channel layer and the second gate dielectric initial layer;

[0042] forming a first filling layer in the remaining space of the first opening.

[0043] In one embodiment, the process of forming the bit line includes:

[0044] etching the stack material layer at one side of the first opening in the first direction to form an isolation trench extending in a second direction and a lateral trench, the isolation trench penetrating through the stack material layer, the lateral trench being in communication with the isolation trench and being formed by laterally etching the second dielectric material layer, and the lateral trench exposing the second gate dielectric initial layer;

[0045] etching the second gate dielectric initial layer from the lateral trench to expose the second channel layer;

[0046] forming a bit line in the lateral trench connecting the exposed second channel layer;

[0047] forming a second filling layer in the isolation trench.

[0048] In one embodiment, before the step of forming a bit line in the lateral trench connecting the exposed second channel layer, the method further comprises:

[0049] doping the second channel layer through the lateral trench to form a first doped region;

[0050] forming a first metal silicide on the surface of the first doped region.

[0051] In one embodiment, the forming of the common source line comprises:

[0052] etching the stack material layer at the other side of the first opening in the first direction to form a source line trench, the source line trench exposing the second gate dielectric initial layer;

[0053] etching the second gate dielectric initial layer from the source line trench to expose the second channel layer;

[0054] forming the common source line in the source line trench connecting the exposed second channel layer.

[0055] In one embodiment, when the stack material layer is etched to form a first opening, at least two first openings are formed which are oppositely arranged in the first direction; when the source line trench is formed, the source line trench is formed between the two first openings which are oppositely arranged in the first direction, and the source line trench exposes the second gate dielectric initial layer on both sides thereof.

[0056] In one embodiment, before the step of forming the common source line in the source line trench connecting the exposed second channel layer, the method further comprises:

[0057] doping the second channel layer through the source line trench to form a second doped region;

[0058] forming a second metal silicide on a surface of the second doped region.

[0059] In one of the embodiments, a first transistor is formed between the bit line and the second gate, including:

[0060] etching the stack material layer between the bit line and the storage gate to form a third opening, and the remaining stack material layer forms a stack layer, wherein the remaining first dielectric material layer forms a first dielectric layer, and the remaining second dielectric material layer forms a second dielectric layer, the third opening includes a third via and a third lateral hole, the third lateral hole is communicated with the third via and is formed by laterally etching the second dielectric material layer, and the third opening exposes the bit line and the storage gate;

[0061] sequentially forming a first channel material layer, a first gate dielectric material layer, and a conductive protection material layer on a surface of the structure after forming the third opening, the material of the conductive protection material layer is a conductive material;

[0062] removing the conductive protection material layer outside the third lateral hole to form a conductive protection layer;

[0063] based on the conductive protection layer, removing the first gate dielectric material layer and the first channel material layer outside the third lateral hole to form the first gate dielectric layer and the first channel layer;

[0064] forming a third filling layer in a gap between the first channel layer and the first gate dielectric layer and the first dielectric layer, or in a gap between the first gate dielectric layer and the first dielectric layer;

[0065] forming the first word line in the remaining space of the third opening, the first word line includes multiple layers of the first gate of the first transistor.

[0066] An electronic device includes the semiconductor structure of any of the above embodiments, or a semiconductor structure made according to the method of making a semiconductor structure of any of the above embodiments.

[0067] The aforementioned semiconductor structure and its fabrication method, by incorporating a second gate within the second transistor, allows the control gate to control the memory gate via capacitive coupling. This improves the operating voltage range of the control gate, facilitating the future implementation of multi-bit memory devices. Simultaneously, the memory gate surrounds the control gate, enabling connection to the first channel layer in a first direction and the second gate dielectric layer in a second direction. In this configuration, while the bit lines, first transistor, second gate, and common source line are arranged along the first direction, the second channel layer and second gate can be arranged along the second direction. Therefore, the first and second transistors can share bit lines, effectively reducing the number of bit lines and halving the subsequent step-connection process. Furthermore, the shared bit lines between the first and second transistors allow for a significantly higher memory cell density per unit area. Attached Figure Description

[0068] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0069] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure provided in one embodiment;

[0070] Figures 2 to 19 This is a three-dimensional or cross-sectional schematic diagram of the structure obtained during the fabrication process of the semiconductor structure provided in one embodiment, wherein... Figures 3 to 19 In the figure, (a) is a three-dimensional schematic diagram, and the other figures are schematic diagrams of the longitudinal sections along the section lines marked in (a).

[0071] Figure 20 This is a top view schematic diagram of a semiconductor structure provided in one embodiment;

[0072] Figure 21 This is a three-dimensional schematic diagram of a semiconductor structure provided in another embodiment;

[0073] Explanation of reference numerals in the attached figures:

[0074] 100 - substrate, 110 - semiconductor substrate, 120 - insulating isolation layer, 200 - second transistor, 210 - second gate, 211 - storage gate, 2111 - storage gate material layer, 212 - dielectric layer, 213 - control gate, 213a - second word line, 220 - second gate dielectric layer, 2201 - second gate dielectric material layer, 2202 - second gate dielectric initial layer, 230 - second channel layer, 2301 - second channel material layer, 300 - bit line, 400 - common source line, 500 - first transistor, 510 - first gate, 510a - first word line, 520 - first gate dielectric layer, 530 - first channel layer, 6001 - stack material layer, 6101 - first dielectric material layer, 6201 - second dielectric material layer, 610 - first dielectric layer, 620 - second dielectric layer, 710 - insulating protective layer, 720 - conductive protective layer, 730 - mask material layer, 810 - first fill layer, 820 - second fill layer, 830 - third fill layer, 910 - first doped source, 920 - first metal material, 10 - first opening, 11 - first via, 12 - first lateral hole, 20 - second opening, 21 - second via, 22 - second lateral hole, 30 - third opening, 31 - third via, 32 - third lateral hole, 41 - isolation trench, 42 - lateral trench, 50 - source line trench. DETAILED DESCRIPTION

[0075] For the purposes of this application, reference will be made to the accompanying drawings in which preferred embodiments of the application are illustrated. The application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art.

[0076] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0077] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0078] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction, and the spatially relative terms used herein can be interpreted accordingly.

[0079] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0080] In one embodiment, referring to Figure 1 , a method for fabricating a semiconductor structure is provided, comprising the following steps:

[0081] Step S1, providing a substrate 100.

[0082] Referring toFigure 2 The base 100 can include a semiconductor substrate 110. The semiconductor substrate 110 can include, but is not limited to, a silicon substrate. In addition, the base 100 can further include an insulating isolation layer 120 for insulating and isolating the memory cell from the semiconductor substrate 110, so as to prevent leakage between the semiconductor substrate 110.

[0083] Step S2, please refer to Figure 15 (while referring to Figure 20 ), a second transistor 200 is formed on the base 100, the second transistor 200 includes a second gate 210, a second gate dielectric layer 220 and a second channel layer 230; the second gate 210 includes a storage gate 211, a dielectric layer 212 and a control gate 213, the dielectric layer 212 surrounds the control gate 213, and the storage gate 211 surrounds the dielectric layer 212; the second gate dielectric layer 220 extends at least in the first direction and is connected to the storage gate 211 in the second direction; the second channel layer 230 extends along the first direction and is located on the side of the second gate dielectric layer 220 away from the storage gate 211 in the second direction.

[0084] The second transistor 200 can be a junctionless transistor, and the second channel layer 230 can be a doped semiconductor layer. The material of the second channel layer 230 can include, but is not limited to, polysilicon. For example, the material of the second channel layer 230 can also be a metal oxide material, such as IGZO, etc.

[0085] In the second gate 210, the connection of the storage gate 211 and the first channel layer can be used as a storage node to store data, and the control gate 213 controls the storage gate 211 by capacitive coupling, so as to control the on and off of the second transistor 200.

[0086] The materials of the storage gate 211 and the control gate 213 can be different or the same. For example, the material of the storage gate 211 can include, but is not limited to, a conductive material TiN. The material of the control gate 213 can include, but is not limited to, a conductive material.

[0087] The material of the dielectric layer 212 and / or the second gate dielectric layer 220 can include, but is not limited to, a high dielectric constant material. For example, the material of the second gate dielectric layer 220 can include, but is not limited to, HfOx, HfSiOx, HfOx / SiO2stacked layer material, or Al2O3, STO, etc.

[0088] Step S3, please refer to Figure 16 (while referring to Figure 20The bit line 300 and the common source line 400 are respectively formed on two sides of the second gate 210 in the first direction, and the bit line 300 and the common source line 400 extend along the second direction.

[0089] The bit line 300 can be formed before the common source line 400, or can be formed after the common source line 400. Alternatively, the bit line 300 and the common source line 400 can have an overlapping step. Here, the above are not limited.

[0090] The material of the bit line 300 and the common source line 400 can include, but is not limited to, a conductive material such as TiN. The materials of the bit line 300 and the common source line 400 can be the same or different.

[0091] The bit line 300 and the common source line 400 are respectively connected to two sides of the second channel layer 230 in the first direction, so as to respectively connect the source region and the drain region of the second transistor.

[0092] The bit line 300 and the common source line 400 extend along the second direction, so as to respectively provide a second bit line signal and a source signal (such as a ground signal) for a plurality of second transistors arranged in the second direction.

[0093] Step S4, please refer to Figure 19 (while referring to Figure 20 The first transistor 500 is formed between the bit line 300 and the second gate 210, and the first transistor 500 includes a first gate 510, a first gate dielectric layer 520, and a first channel layer 530. The first gate dielectric layer 520 surrounds the first gate 510, and the first channel layer 530 surrounds the first gate dielectric layer 520. The first channel layer 530 is respectively connected to the bit line 300 and the storage gate 211 in the first direction.

[0094] The material of the first channel layer 530 can be IGZO, so that the first transistor 500 has a lower off-state current. Of course, the material of the first channel layer 530 is not limited to this, for example, it can also be other metal oxide materials.

[0095] The material of the first gate 510 can include, but is not limited to, a conductive material ITO. The material of the first gate dielectric layer 520 can include, but is not limited to, a high dielectric constant material.

[0096] The first channel layer 530 is connected with the bit line 300 and the storage gate 211 on both sides in the first direction, so that the bit line 300 and the storage gate 211 can be connected with the source region and the drain region of the first transistor 500 respectively. At this time, the first transistor 500 can obtain the write bit line signal from the bit line 300, and store data to the storage gate 211 when the first transistor 500 is turned on under the control of the first gate 510.

[0097] The first transistor 500 and the second transistor 200 can form a 2T0C architecture storage unit.

[0098] As an example, a plurality of storage units arranged in an array in the first direction and the second direction can be stacked on the substrate 100, and the first word line 510a and the second word line 213a can be formed. The first word line 510a extends from the top layer of the storage unit to the substrate 100, and includes the first gate 510 of a plurality of first transistors 500 arranged perpendicularly to the substrate. The second word line 213a extends from the top layer of the storage unit to the substrate 100, and includes the control gate 213 of a plurality of second transistors arranged perpendicularly to the substrate.

[0099] As an example, the second transistor 200 can include a P-type transistor (such as a PMOS transistor).

[0100] When writing data, the first transistor 500 can be turned on by applying a turn-on voltage to the first word line 510a. At the same time, a voltage signal corresponding to the data to be written can be applied to the bit line 300 to store data into the storage gate 211. At this time, the second transistor 200 is set to a P-type transistor, so that whether the bit line 300 stores zero voltage or positive voltage into the storage gate 211, the second transistor 200 can be in a cut-off and open state, so as not to affect the data writing. Of course, when the circuit is reasonably designed so that a negative potential can be applied to the bit line 300, the second transistor 200 can also be set to an N-type transistor.

[0101] When the second transistor is a P-type transistor, the first word line 510a, the second word line 213a, the bit line 300 and the common source line 400 can be applied with voltages in the following table during the reading and writing of the storage unit.

[0102]

[0103]

[0104] When writing data, a voltage of 0 / V WL can be applied to the second word line 213a, so that the voltage on the control gate 213 is 0V or V WL , thereby closing the second transistor 200. At this time, the bit line 300 can be used to provide a write bit line signal.

[0105] When writing data "1", zero voltage is applied to the bit line 300, so that zero voltage can be stored in the storage gate 211 as a storage node. When writing data "0", voltage Vw is applied to the bit line 300, so that positive voltage can be stored in the storage gate 211 as a storage node. When positive voltage is stored, the second transistor 200 is more biased to be off because the second transistor 200 is a P-type transistor.

[0106] When reading data, the bit line 300 can be used to provide a read bit line signal, to which voltage V R can be applied. At the same time, -V WL can be applied to the second word line 213a, so that the voltage on the control gate 213 is negative. At this time, the voltage on the control gate 213 generates an electric field, and through the coupling between the control gate 213 and the storage gate 211, the voltage on the storage gate 211 is increased by the negative voltage based on the voltage stored when writing data.

[0107] At this time, the on-off state of the second transistor 200 is affected by the voltage stored on the storage gate 211. The on-off state of the second transistor 200 is different when the voltage stored on the storage gate 211 is different, so the voltage change on the bit line 300 and the current value are different.

[0108] Therefore, data "1" and "0" can be read according to the voltage change on the bit line 300 in the voltage mode, or according to the current value on the bit line 300 in the current mode. When zero voltage is stored on the storage gate 211 (i.e., writing "1"), the second transistor 200 is turned on, the voltage change on the bit line 300 is large, and the current value is large, so that data "1" can be read. When positive voltage is stored on the storage gate 211, the second transistor 200 is turned off due to the mutual offset of positive and negative voltages, so the voltage change on the bit line 300 is small, and the current value is small, so that data "0" can be read.

[0109] In the embodiment, the second gate 210 of the second transistor 200 is arranged such that the control gate 213 controls the storage gate 211 through capacitive coupling, so that the operating range of the operating voltage of the control gate 213 can be improved, and the implementation of a future multi-bit memory device is facilitated. Meanwhile, the storage gate 211 surrounds the control gate 213, so that the first channel layer 530 can be connected in the first direction on the one hand, and the second gate dielectric layer 220 can be connected in the second direction on the other hand. At this time, while the bit line 300, the first transistor 500, the second gate 210 and the common source line 400 are arranged in the first direction, the second channel layer 230 and the second gate 210 can be arranged in the second direction. Therefore, the first transistor 500 and the second transistor 200 can share the bit line 300, so that the number of bit lines can be effectively reduced, and the subsequent process of connecting the bit line step can be reduced by half. Moreover, the first transistor 500 and the second transistor 200 share the bit line 300, so that the storage unit density in a unit area can be effectively increased.

[0110] In one embodiment, in step S2, forming the second transistor 200 on the substrate 100 comprises:

[0111] In step S21, referring to Figure 2 forming a stack material layer 6001 on the substrate 100, the stack material layer 6001 comprising first dielectric material layers 6101 and second dielectric material layers 6201 alternately stacked.

[0112] The first dielectric material layers 6101 and the second dielectric material layers 6201 can be alternately stacked on the substrate 100 through a deposition process. The deposition process can include, but is not limited to, chemical vapor deposition, etc. As an example, the material of the first dielectric material layers 6101 can be the same as that of the insulating isolation layer 120. At this time, the insulating isolation layer 120 can be formed on the semiconductor substrate 110, and then the second dielectric material layers 6201 and the first dielectric material layers 6101 can be periodically stacked on the insulating isolation layer.

[0113] As an example, the material of the first dielectric material layers 6101 can be silicon oxide, and the material of the second dielectric material layers 6201 can be silicon nitride. The first dielectric material layers 6101 can be prepared by, for example, a TEOS sol-gel method, and the second dielectric material layers 6201 can be prepared by, for example, a plasma-enhanced chemical vapor deposition (PECVD) process.

[0114] In step S22, referring to Figure 4 forming a first opening 10 by etching the stack material layer 6001, the first opening 10 comprising a first through hole 11 and a first lateral hole 12, the first lateral hole 12 being communicated with the first through hole 11 and being formed by laterally etching the second dielectric material layers 6201.

[0115] As an example, please refer to Figure 3 The first via hole 11 can be formed by dry etching the stacked material layer 6001. Then, please refer to Figure 4 The second dielectric material layer 6201 is wet etched from the first via hole 11 to form the first lateral hole 12.

[0116] At step S23, please refer to Figure 6 The second gate dielectric initial layer 2202 and the second channel layer 230 are formed in the first lateral hole 12, and the first filling layer 810 is formed in the remaining space in the first opening 10. The second gate dielectric initial layer 2202 is formed on the surface of the second dielectric material layer 6201 exposed by the first lateral hole 12, and the second channel layer 230 is formed on the surface of the second gate dielectric initial layer 2202.

[0117] As an example, step S23 can include:

[0118] At step S231, please refer to Figure 5 The second gate dielectric material layer 2201, the second channel material layer 2301, and the insulating protective material layer are sequentially formed on the surface of the structure after the first opening 10 is formed.

[0119] The second gate dielectric material layer 2201, the second channel material layer 2301, and the insulating protective material layer can be sequentially formed on the surface of the structure after the first opening 10 is formed by deposition processes such as atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0120] At step S232, please refer to Figure 6 The insulating protective material layer is removed outside the first lateral hole 12 to form the insulating protective layer 710.

[0121] As an example, while the insulating protective material layer outside the first lateral hole 12 is removed, the part of the insulating protective material layer in the first lateral hole 12 can also be partially removed to reduce the process difficulty. At this time, the insulating protective layer 710 can not fill the first lateral hole 12.

[0122] At step S233, please continue to refer to Figure 6 Based on the insulating protective layer 710, the second channel material layer 2301 and the second gate dielectric material layer 2201 outside the first lateral hole 12 are removed to form the second channel layer 230 and the second gate dielectric initial layer 2202.

[0123] At this time, the formed second channel layer 230 can be effectively opposite to the storage gate 211 in the second direction.

[0124] In some examples, the second dielectric material layer 2201 outside the first lateral hole 12 can also not be removed.

[0125] Step S234, please continue to refer to Figure 6 The first filling layer 810 is formed in the remaining space in the first opening 10.

[0126] The material of the first filling layer 810 is an insulating material, which can play an insulating isolation role. As an example, the material of the first filling layer 810 can be silicon oxide, which can be formed by a spin-on dielectric (SOD) process or the like.

[0127] Step S24, please refer to Figure 6 The second opening 20 is formed by etching the stacked material layer 6001, the second opening 20 includes a second via hole 21 and a second lateral hole 22, the second lateral hole 22 is communicated with the second via hole 21 and is formed by etching the second dielectric material layer 6201 laterally, the size of the second via hole 21 in the first direction is smaller than the size of the first via hole 11 in the first direction, and the second via hole 21 is located on one side of the first via hole 11 in the second direction, the second direction intersects the first direction.

[0128] As an example, dry etching can be performed on the stacked material layer 6001 first, thereby forming the second via hole 21. Then, wet etching is performed on the second dielectric material layer 6201 from the second via hole 21, thereby forming the second lateral hole 22.

[0129] The size of the second via hole 21 in the first direction is smaller than the size of the first via hole 11 in the first direction, so as to reserve space for the first transistor 500 formed subsequently.

[0130] Step S25, please refer to Figure 9 The second gate 210 is formed in the second opening 20, the second gate 210 includes a storage gate 211, a dielectric layer 212, and a second word line 213a, the storage gate 211 is formed in the second lateral hole 22, the dielectric layer 212 is formed on the surface of the storage gate 211, the sidewall and the bottom of the second via hole 21, and the second word line 213a is formed on the surface of the dielectric layer 212 and fills the remaining space of the second opening 20, the second word line 213a includes a plurality of control gates 213 of the second transistors arranged perpendicularly to the substrate.

[0131] As an example, at least two first openings 10 are formed in the opposite arrangement in the second direction when the stacked material layer 6001 is etched to form the first opening 10 in the previous step S22, and the second opening 20 is formed between the two first openings 10 arranged in the opposite direction in the second direction when the stacked material layer 6001 is etched to form the second opening 20 in step S24.

[0132] At this time, the second channel layer 230 can be formed on both sides of the second gate 210 in the second direction, so as to improve the gate control ability of the transistor.

[0133] Of course, the second channel layer 230 can also be formed on only one side of the second gate 210 in the second direction, which is not limited herein.

[0134] The second gate 210 can be formed by referring to Figure 7 The storage gate material layer 2111 can be first formed on the structure surface after forming the second opening 20 by atomic layer deposition (ALD) or the like. Figure 8 Then, the storage gate material layer 2111 except the second lateral hole 22 is removed, so as to form the storage gate 211.

[0135] After that, the dielectric material layer can be formed on the structure surface after forming the storage gate 211, and then the second word line material layer is formed on the surface of the dielectric material layer to fill the second opening 20.

[0136] After that, by referring to Figure 9 The second word line material layer and the dielectric material layer except the second opening 20 can be removed, so as to form the second word line 213a and the dielectric layer 212. In some embodiments, the dielectric material layer except the second opening 20 can also not be removed.

[0137] The part of the second word line 213a opposite to the second channel layer 230 can be used as the control gate 213 of the second transistor.

[0138] In step S26, the part of the second gate dielectric initial layer 2202 covering both ends of the second channel layer 230 in the first direction is removed, so as to form the second gate dielectric layer 220 (by referring to Figure 20 ).

[0139] After removing the part of the second gate dielectric initial layer 2202, the second gate dielectric layer 220 formed can expose both ends of the second channel layer 230 in the first direction, so that both ends of the second channel layer 230 in the first direction can be connected with the bit line 300 and the common source line 400 formed subsequently, respectively.

[0140] It can be understood that step S26 can be performed after step S23, and there is no strict sequence limitation between step S26 and step S25. For example, step S26 can also be performed before step S24.

[0141] In the embodiment, the channel structure (including the second channel layer 230 and the second gate dielectric layer 220) of the second transistor 200 and the second gate 210 (including the storage gate 211, the dielectric layer 212 and the second word line 213a) are all formed by the process of hole etching, so that the size and the process flow are extremely advantageous.

[0142] In one embodiment, the forming of the bit line 300 in step S3 includes:

[0143] Step S31, referring to Figure 10 , etching the stack material layer 6001 at one side of the first opening 10 in the first direction to form an isolation trench 41 extending along the second direction and a lateral groove 42, the isolation trench 41 penetrates the stack material layer 6001, the lateral groove 42 is communicated with the isolation trench 41 and is formed by laterally etching the second dielectric material layer 6201, and the lateral groove 42 exposes the second gate dielectric initial layer 2202.

[0144] First, the stack material layer 6001 can be dry etched to form the isolation trench 41 extending along the second direction, and then the second dielectric material layer 6201 can be wet etched from the isolation trench 41 to expose the second gate dielectric initial layer 2202, thereby forming the lateral groove 42.

[0145] As an example, after the second word line 213a is formed, a mask material layer 730 can also be formed on the structure surface after the second word line 213a is formed by PECVD or the like. The material of the mask material layer 730 can be, for example, silicon oxide.

[0146] At this time, the mask material layer 730 and the stack material layer 6001 can be dry etched in sequence to form the isolation trench 41. At this time, the mask material layer 730 can not only act as a mask for dry etching the stack material layer 6001, but also cover and protect the second word line 213a when wet etching the second dielectric material layer 6201, so as to prevent the second word line 213a from being damaged.

[0147] Step S32, referring to Figure 11 , etching the second gate dielectric initial layer 2202 from the lateral groove 42 to expose the second channel layer 230.

[0148] At this time, this step can be part of the step S26 (removing the part of the second gate dielectric initial layer 2202 covering the two ends of the second channel layer 230 in the first direction to form the second gate dielectric layer 220).

[0149] Step S34, referring to Figure 14 , forming the bit line 300 connected to the exposed second channel layer 230 in the lateral groove 42.

[0150] At this time, the bit line 300 can be connected to one side of the second channel layer 230 in the first direction.

[0151] Step S35, referring to Figure 15 a second fill layer 820 is formed in the isolation trench 41.

[0152] The material of the second fill layer 820 is an insulating material, which can play an insulating isolation role. As an example, the material of the second fill layer 820 can be silicon oxide, which can be formed by a spin-on dielectric (SOD) process or the like.

[0153] As an example, before step S34, it can also include:

[0154] Step S331, the second channel layer 230 is doped through the lateral trench 42 to form a first doped region (not shown).

[0155] After etching the second gate dielectric initial layer 2202 from the lateral trench 42 to expose the second channel layer 230, referring to Figure 12 a first doped source 910 can be deposited on the surface, and the second channel layer 230 exposed by the lateral trench 42 is subjected to a heavy doping process through the first doped source 910, thereby forming the first doped region. After the first doped region is formed, the first doped source 910 is removed. The first doped source 910 can include, but is not limited to, boron-silicon glass (BSG) or the like.

[0156] The first doped region can effectively reduce the contact resistance between the second channel layer 230 and the bit line 300.

[0157] Step S332, a first metal silicide (not shown) is formed on the surface of the first doped region.

[0158] Referring to Figure 13 The first metal material 920 (such as Ni, Co, Ti, or TiSiN, etc.) can be first deposited on the surface of the structure after the first doped region is formed. Then, a thermal annealing process is performed, so that the first metal material 920 reacts with the first doped region to form the first metal silicide. Then, the unreacted first metal material 920 is removed.

[0159] The first metal silicide can further reduce the contact resistance between the second channel layer 230 and the bit line 300.

[0160] In one embodiment, the forming process of the common source line 400 in step S3 includes:

[0161] Step S36, referring to Figure 15The stack material layer 6001 is etched at the other side of the first opening 10 in the first direction to form a source line trench 50, which exposes the second gate dielectric initial layer 2202.

[0162] The source line trench 50 and the isolation trench 41 are respectively located at opposite sides of the first opening 10 in the first direction.

[0163] Step S37, please continue to refer to Figure 15 The second gate dielectric initial layer 2202 is etched from the source line trench 50 to expose the second channel layer 230.

[0164] At this time, this step can be another part of the step in step S26 (remove the part of the second gate dielectric initial layer 2202 covering the two ends of the second channel layer 230 in the first direction to form the second gate dielectric layer 220).

[0165] Step S39, please refer to Figure 16 The common source line 400 is formed in the source line trench 50 to connect the exposed second channel layer 230.

[0166] The deposition of the source line material layer can be performed first, and then the source line material layer outside the source line trench 50 is removed to form the common source line 400. The material of the common source line 400 can include but is not limited to titanium nitride.

[0167] As an example, at least two first openings 10 are formed in the first direction opposite to each other when the stack material layer 6001 is etched to form the first opening 10 in the previous step S22. And, the source line trench 50 is formed between the two first openings 10 in the first direction opposite to each other in the previous step S36, which exposes the second gate dielectric initial layer 2202 located at the two sides thereof.

[0168] At this time, the same common source line 400 can be symmetrically provided with storage units connected thereto on both sides in the first direction, and thus shared by the storage units on both sides thereof. Of course, only one side of the same common source line 400 can be provided with storage units connected thereto.

[0169] As an example, before step S39, it further includes:

[0170] Step S381, the second channel layer 230 is doped through the source line trench 50 to form a second doping region.

[0171] After the second channel layer 230 is exposed by the source line trench 50, a second doping source can be deposited on the whole surface, and the second channel layer 230 exposed by the lateral trench 42 is subjected to a heavy doping process through the second doping source to form a second doping region. After the second doping region is formed, the second doping source is removed. The second doping source can include but is not limited to boron silicon glass (BSG) and the like.

[0172] The second doped region can effectively reduce the contact resistance between the second channel layer 230 and the common source line 400.

[0173] Step S382, forming a second metal silicide on the surface of the second doped region.

[0174] The second metal material (such as Ni, Co, Ti or TiSiN, etc.) can be first deposited on the surface of the structure after the formation of the second doped region. Then, a thermal annealing process is performed, so that the second metal material reacts with the second doped region to form the second metal silicide. After that, the unreacted second metal material is removed.

[0175] The second metal silicide can further reduce the contact resistance between the second channel layer 230 and the common source line 400.

[0176] It can be understood that when the step S3 simultaneously includes the steps S31 to S39, the steps S31 to S35 can be performed before the steps S36 to S39, so that the bit line 300 is formed before the common source line 400; or the steps S31 to S35 can be performed after the steps S36 to S39, so that the bit line 300 is formed after the common source line 400.

[0177] Of course, the formation of the bit line 300 and the common source line 400 is not limited to this. For example, in other embodiments, the bit line slot including the isolation groove 41 and the lateral groove 42 can be first formed, and then the source line groove 50 is formed. After that, the second gate dielectric initial layer 2202 exposed by the lateral groove 42 and the source line groove 50 is removed to form the second gate dielectric layer 220. The conductive material is filled in the bit line slot and the source line groove 50 at the same time, and then the chemical mechanical grinding is performed on the conductive material above the stack material layer 6001 to remove the conductive material, and the conductive material remaining in the source line groove 50 forms the common source line 400. After that, the bit line 300 located in the lateral groove 42 is formed by removing the conductive material outside the lateral groove 42 through photolithography, etching and other processes, and then the second filling layer 820 is filled.

[0178] In one embodiment, the step S4 includes:

[0179] Step S41, please refer to Figure 16, etching the stack material layer 6001 between the bit line 300 and the storage gate 211 to form a third opening 30, the remaining stack material layer 6001 forms a stack layer, wherein the remaining first dielectric material layer 6101 forms a first dielectric layer 610, and the remaining second dielectric material layer 6201 forms a second dielectric layer 620, the third opening 30 includes a third via hole 31 and a third lateral hole 32, the third lateral hole 32 is communicated with the third via hole 31 and is formed by laterally etching the second dielectric material layer 6201, and the third opening 30 exposes the bit line 300 and the storage gate 211.

[0180] The stack material layer 6001 can be first dry-etched to form the third via hole 31. Then, the second dielectric material layer 6201 is wet-etched from the third via hole 31 to expose the bit line 300 and the storage gate 211 to form the third lateral hole 32.

[0181] After the third opening 30 is etched, the remaining first dielectric material layer 6101 forms the first dielectric layer 610, and the remaining second dielectric material layer 6201 forms the second dielectric layer 620.

[0182] Step S42, sequentially forming a first channel material layer, a first gate dielectric material layer, and a conductive protection material layer on the structure surface after forming the third opening 30.

[0183] The first channel material layer, the first gate dielectric material layer, and the conductive protection material layer can be sequentially formed by deposition process or the like.

[0184] As an example, the material of the first channel material layer can be IGZO, the material of the first gate dielectric material layer can be HfOx, and the material of the conductive protection material layer can be ITO.

[0185] Step S43, please refer to Figure 17 , removing the conductive protection material layer outside the third lateral hole 32 to form a conductive protection layer 720.

[0186] Step S44, please continue to refer to Figure 17 , based on the conductive protection layer 720, removing the first gate dielectric material layer and the first channel material layer outside the third lateral hole 32 to form a first gate dielectric layer 520 and a first channel layer 530.

[0187] The conductive protection layer 720 can be used as an etching stop layer to wet-etch the first gate dielectric material layer and the first channel material layer to form the first gate dielectric layer 520 and the first channel layer 530. At this time, affected by the topography of the conductive protection layer 720, a gap will be generated between the first gate dielectric layer 520 and the first dielectric layer 610 (or between the first gate dielectric layer 520 and the first channel layer 530 and the first dielectric layer 610).

[0188] Step S45, referring to Figure 18 , a third filling layer 830 is formed in the gap between the first channel layer 530 and the first gate dielectric layer 520 and the first dielectric layer 610, or in the gap between the first gate dielectric layer 520 and the first dielectric layer 610.

[0189] The third filling material layer can be first deposited on the surface of the structure after the formation of the first gate dielectric layer 520 and the first channel layer 530. Then the third filling material layer is subjected to wet etching, and the third filling material layer remaining in the gap can be retained, thereby forming the third filling layer 830.

[0190] The material of the third filling layer 830 is an insulating material, which can play an insulating isolation role, thereby isolating the first channel layer 530 and the first word line 510a formed subsequently.

[0191] Step S46, referring to Figure 19 , the first word line 510a is formed in the remaining space of the third opening 30, and the first word line 510a includes the first gate 510 of the plurality of first transistors 500 arranged perpendicularly to the substrate.

[0192] The material of the first word line 510a can be the same as that of the conductive protective layer 720, for example, both are ITO. Of course, the materials of the two can also be different, which can be set according to actual needs.

[0193] In the embodiment, the formation process of the first transistor 500 can be completed by the process of hole etching, which has great advantages in size and process flow.

[0194] It should be understood that, although Figure 1 the steps in the flowchart are shown in order according to the arrows, these steps are not necessarily executed in order according to the arrows. Unless otherwise specified in this article, the execution of these steps has no strict order limitation, and these steps can be executed in other orders. Moreover, Figure 1 at least part of the steps in may include multiple steps or stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or steps or stages in other steps.

[0195] Figure 19 In one embodiment, referring to Figure 20 and Figure 21 , a semiconductor structure is also provided, which includes a bit line 300, a common source line 400 and a storage unit.

[0196] The bit line 300 and the common source line 400 are arranged along a first direction and both extend along a second direction. The second direction intersects the first direction.

[0197] The memory cell includes a first transistor 500 and a second transistor 200.

[0198] The first transistor 500 is located between the bit line 300 and the common source line 400 along the first direction, and includes a first gate 510, a first gate dielectric layer 520, and a first channel layer 530. The first gate dielectric layer 520 surrounds the first gate 510. The first channel layer 530 surrounds the first gate dielectric layer 520 and connects the bit line 300 along the first direction.

[0199] The second transistor 200 includes a second gate 210, a second gate dielectric layer 220, and a second channel layer 230. The second transistor 200 can be a junctionless transistor, and the second channel layer 230 can be a doped semiconductor layer.

[0200] The second gate 210 is located between the first transistor 500 and the common source line 400 along the first direction, and includes a storage gate 211, a dielectric layer 212, and a control gate 213.

[0201] The dielectric layer 212 surrounds the control gate 213. The storage gate 211 surrounds the dielectric layer 212. Thus, the control gate 213 can control the storage gate 211 through capacitive coupling, thereby controlling the on and off of the second transistor 200.

[0202] The storage gate 211 connects the first channel layer 530 along the first direction. Thus, the two sides of the first channel layer 530 along the first direction are connected to the storage gate 211 and the bit line 300 respectively, so that the bit line 300 and the storage gate 211 can be connected to the source region and the drain region of the first transistor 500 respectively. At this time, the first transistor 500 can obtain a write bit line signal from the bit line 300, and store data to the storage gate 211 when the first transistor 500 is turned on under the control of the first gate 510.

[0203] The second gate dielectric layer 220 is located between the bit line 300 and the common source line 400 along the first direction, and is located between the storage gate 211 and the second channel layer 230 along the second direction. The second channel layer 230 is located on the side of the second gate dielectric layer 220 away from the storage gate 211 along the second direction.

[0204] The second channel layer 230 is connected with the bit line 300 and the common source line 400 on both sides in the first direction, so that the bit line 300 and the common source line 400 can be connected with the source region and the drain region of the second transistor 200 respectively. At this time, the second transistor 200 can obtain the read bit line signal from the bit line 300, and obtain the source signal (such as the ground signal) from the common source line 400.

[0205] The materials of the bit line 300, the common source line 400, the first gate 510, the control gate 213 and the storage gate 211 can be selected from conductive materials W, Cu, Al, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Ag, Au, and Co-based alloy, Fe-based alloy, Ni-based alloy, FeNi-based alloy, CoNi-based alloy, FeCo-based alloy, Al-based alloy, Cu-based alloy, Mg-based alloy, Ti-based alloy, low-carbon steel, stainless steel, or conductive metal nitride such as titanium nitride TiN, conductive metal silicide, conductive metal carbide, conductive doped semiconductor such as doped polysilicon, conductive metal oxide semiconductor such as indium tin oxide, and the like.

[0206] The materials of the second gate dielectric layer 220 and the first gate dielectric layer 520 can include but are not limited to High K materials. The High K materials can include but are not limited to HfOx, and can also be HfSiOx, a stacked material of HfOx / SiO2, or other oxide materials (for example, Al2O3, STO, and the like).

[0207] The material of the first channel layer 530 can include but is not limited to IGZO. The material of the second channel layer 230 can include but is not limited to amorphous silicon.

[0208] The read and write processes of the stored cells can refer to the above, and will not be described here again.

[0209] In the embodiment, the second gate 210 is arranged in the second transistor 200, so that the control gate 213 controls the storage gate 211 through capacitive coupling, thereby improving the operating range of the operating voltage of the control gate 213, and facilitating the implementation of a multi-bit memory device in the future. Meanwhile, the storage gate 211 surrounds the control gate 213, so as to connect the first channel layer 530 in the first direction on one hand, and connect the second gate dielectric layer 220 in the second direction on the other hand. At this time, the bit line 300, the first transistor 500, the second gate 210 and the common source line 400 are arranged in the first direction, while the second channel layer 230 and the second gate 210 can be arranged in the second direction. Therefore, the first transistor 500 and the second transistor 200 can share the bit line 300, thereby effectively reducing the number of bit lines, and thus the process of making the step of connecting the bit line can be reduced by half. Moreover, the first transistor 500 and the second transistor 200 share the bit line 300, so as to effectively increase the density of the storage unit in a unit area.

[0210] In one embodiment, the second transistor 200 includes a junctionless P-type transistor (such as a PMOS transistor). When data is written, a turn-on voltage can be applied to the first word line 510a to turn on the first transistor 500. At the same time, a positive voltage signal or a zero voltage signal corresponding to the data to be written can be applied to the bit line 300 to store the data into the storage gate 211. At this time, the second transistor 200 is arranged as a P-type transistor, so that whether the bit line 300 stores zero voltage or positive voltage into the storage gate 211, the second transistor 200 can be in a cut-off state, thereby not affecting the data writing.

[0211] Of course, when the circuit is reasonably designed so that a negative potential can be applied to the bit line 300, the second transistor 200 can also be arranged as an N-type transistor.

[0212] In one embodiment, the storage gate 211 is arranged on both sides of the second direction and connected with the second gate dielectric layer 220 and the second channel layer 230. At this time, a conductive channel can be formed on both sides of the second gate 210, thereby increasing the gate control ability.

[0213] In other embodiments, the second gate dielectric layer 220 and the second channel layer 230 can also be arranged on one side of the second gate 210, which is not limited here.

[0214] In one embodiment, the second gate dielectric layer 220 is also arranged between the first channel layer 530 and the second channel layer 230 in the second direction, so as to insulate and separate the first channel layer 530 and the second channel layer 230.

[0215] In one embodiment, the second channel layer 230 includes a first doped region, a second doped region, and a channel region between the two, the first doped region is connected to the bit line 300, the second doped region is connected to the common source line 400, and the channel region is located on the surface of the second gate dielectric layer 220 away from the storage gate 211.

[0216] The first doped region can reduce the contact resistance between the second channel layer 230 and the bit line 300. The second doped region can reduce the contact resistance between the second channel layer 230 and the common source line 400.

[0217] In one embodiment, the same common source line 400 is symmetrically provided with storage units connected thereto on opposite sides in the first direction. At this time, the common source line 400 can be shared by the storage units on both sides, thereby reducing the number of common source lines 400 and improving storage density.

[0218] In other embodiments, the same common source line 400 can also be provided with storage units connected thereto on only one side, which is not limited here.

[0219] In one embodiment, the semiconductor structure further includes a substrate 100, a first word line 510a, and a second word line 213a. The substrate 100 is stacked with a plurality of layers of storage units arranged in an array in the first direction and the second direction.

[0220] The first word line 510a extends from the top layer of storage units to the substrate 100 and includes a first gate 510 of a plurality of first transistors 500 arranged perpendicular to the substrate. The second word line 213a extends from the top layer of storage units to the substrate 100 and includes a control gate 213 of a plurality of second transistors arranged perpendicular to the substrate. The common source line 400 extends from the top layer of storage units to the substrate 100 and is connected to the second channel layer 230 of a plurality of second transistors arranged perpendicular to the substrate and in the second direction.

[0221] In one embodiment, the semiconductor structure further includes a stack layer, a first filler layer 810, a second filler layer 820, and a third filler layer 830.

[0222] The stack layer is located on the substrate 100 and includes first dielectric layers 610 and second dielectric layers 620 stacked alternately, and the storage units and the bit line 300 are embedded in the second dielectric layers 620.

[0223] The first filler layer 810 is located on the side of the second channel layer 230 away from the second gate dielectric layer 220 in the second direction and extends from the top layer of storage units to the substrate 100.

[0224] The second filler layer 820 is located on the side of the bit line 300 away from the storage unit in the first direction and extends from the top layer of storage units to the substrate 100.

[0225] The third filling layer 830 is located between the first channel layer 530 and the first dielectric layer 610, and insulates and separates the first channel layer 530 and the first word line 510a.

[0226] The material of the first filling layer 810, the second filling layer 820 and the third filling layer 830 can be selected from SiO2, other low K materials, HfOx or other oxides or nitrides.

[0227] In an embodiment, an electronic device is also provided, which includes the semiconductor structure provided by any of the above embodiments or the semiconductor structure manufactured according to the manufacturing method of the semiconductor structure provided by any of the above embodiments. The electronic device can be any electronic product with storage function, such as a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply.

[0228] Any combination of the technical features of the above embodiments can be made. In order to make the description simple, all possible combinations of the technical features of the above embodiments are not described, however, as long as the combination of the technical features does not exist, it should be considered as the scope of the description.

[0229] The above embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent application scope. It should be noted that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A semiconductor structure, characterized by, Comprising: a bit line and a common source line, the bit line and the common source line are arranged along a first direction and both extend along a second direction, the second direction intersects the first direction; a memory cell, the memory cell comprises: a first transistor, located between the bit line and the common source line in the first direction, comprising a first gate, a first gate dielectric layer and a first channel layer, the first gate dielectric layer surrounds the first gate, the first channel layer surrounds the first gate dielectric layer and connects the bit line in the first direction; a second transistor, comprising a second gate, a second gate dielectric layer and a second channel layer; the second gate is located between the first transistor and the common source line in the first direction and comprises a storage gate, a dielectric layer and a control gate, the dielectric layer surrounds the control gate, the storage gate surrounds the dielectric layer and connects the first channel layer in the first direction; the second gate dielectric layer extends along the first direction and is located between the bit line and the common source line in the first direction and between the storage gate and the second channel layer in the second direction; the second channel layer extends along the first direction and connects the bit line and the common source line on both sides in the first direction.

2. The semiconductor structure of claim 1, wherein, The second transistor comprises a junctionless P-type transistor.

3. The semiconductor structure of claim 1, wherein, The storage gate is provided with the second gate dielectric layer and the second channel layer connected on both sides in the second direction.

4. The semiconductor structure of claim 1, wherein, The second gate dielectric layer is also located between the first channel layer and the second channel layer in the second direction.

5. The semiconductor structure of claim 1, wherein, The second channel layer comprises a first doped region, a second doped region and a channel region located therebetween, the first doped region connects the bit line, the second doped region connects the common source line, and the channel region is located on the surface of the second gate dielectric layer away from the storage gate.

6. The semiconductor structure of claim 1, wherein, The same common source line is provided with the memory cell connected on both sides in the first direction.

7. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a substrate, a plurality of memory cells are arranged in an array along the first direction and the second direction and are stacked on the substrate, wherein the first direction and the second direction are both parallel to the substrate; a first word line, extending from the top memory cell to the substrate and comprising the first gate of a plurality of first transistors arranged perpendicular to the substrate; a second word line, extending from the top memory cell to the substrate and comprising the control gate of a plurality of second transistors arranged perpendicular to the substrate; the common source line extends from the top memory cell to the substrate and connects the second channel layer of a plurality of second transistors arranged perpendicular to the substrate and along the second direction.

8. The semiconductor structure of claim 7, wherein, The semiconductor structure further comprises: a stack layer, located on the substrate, comprising first dielectric layers and second dielectric layers stacked alternately, the memory cell and the bit line are embedded in the second dielectric layer; a first filling layer, located on the side of the second channel layer away from the second gate dielectric layer in the second direction and extending from the top memory cell to the substrate; A second filling layer is located on the side of the bit line away from the memory cell in the first direction and extends from the memory cell to the substrate; A third filling layer is located between the first channel layer and the first gate dielectric layer and the first dielectric layer or between the first gate dielectric layer and the first dielectric layer, and insulates and separates the first channel layer and the first word line.

9. A method of fabricating a semiconductor structure, characterized by, The method comprises: providing a substrate; forming a second transistor on the substrate, the second transistor comprising a second gate, a second gate dielectric layer and a second channel layer; the second gate comprising a storage gate, a dielectric layer and a control gate, the dielectric layer surrounding the control gate, and the storage gate surrounding the dielectric layer; the second gate dielectric layer extending at least in a first direction and connecting with the storage gate in a second direction; the second channel layer extending along the first direction and located on the side of the second gate dielectric layer away from the storage gate in the second direction; wherein the first direction and the second direction are both parallel to the substrate and intersect with each other; forming a bit line and a common source line on the opposite sides of the second gate in the first direction, respectively, the bit line and the common source line both extending along the second direction, and the bit line and the common source line connecting the two sides of the second channel layer in the first direction, respectively; forming a first transistor between the bit line and the second gate, the first transistor comprising a first gate, a first gate dielectric layer and a first channel layer, the first gate dielectric layer surrounding the first gate, the first channel layer surrounding the first gate dielectric layer, and connecting the bit line and the storage gate on the two sides in the first direction, respectively.

10. The method of claim 9, wherein the semiconductor structure is prepared by a method comprising: forming a second transistor on the substrate, comprising: forming a stack material layer on the substrate, the stack material layer comprising first dielectric material layers and second dielectric material layers stacked alternately; etching the stack material layer to form a first opening, the first opening comprising a first through hole and a first lateral hole, the first lateral hole being communicated with the first through hole and being formed by laterally etching the second dielectric material layer; forming a second gate dielectric initial layer and a second channel layer in the first lateral hole, and forming a first filling layer in the remaining space in the first opening, the second gate dielectric initial layer being formed on the surface of the second dielectric material layer exposed by the first lateral hole, and the second channel layer being formed on the surface of the second gate dielectric initial layer; etching the stack material layer to form a second opening, the second opening comprising a second through hole and a second lateral hole, the second lateral hole being communicated with the second through hole and being formed by laterally etching the second dielectric material layer, the size of the second through hole in the first direction being smaller than the size of the first through hole in the first direction, and the second through hole being located on one side of the first through hole in the second direction; forming a second gate in the second opening, the second gate comprising a storage gate, a dielectric layer and a second word line, the storage gate being formed in the second lateral opening, the dielectric layer being formed on the surface of the storage gate, the sidewall and the bottom of the second via, the second word line being formed on the surface of the dielectric layer and filling the remaining space of the second opening, the second word line comprising a plurality of the control gates of the second transistors arranged in the second direction; removing a portion of the second gate dielectric initial layer covering both ends of the second channel layer in the first direction to form a second gate dielectric layer.

11. The method of claim 10, wherein the semiconductor structure is prepared by a method comprising: forming at least two first openings arranged oppositely in the second direction when etching the stacked material layer to form the first opening; forming the second opening between the two first openings arranged oppositely in the second direction when etching the stacked material layer to form the second opening.

12. The method of claim 10, wherein the semiconductor structure is prepared by a method comprising: the forming of the second gate dielectric initial layer and the second channel layer in the first lateral opening and the forming of the first filling layer in the remaining space of the first opening comprises: sequentially forming a second gate dielectric material layer, a second channel material layer and an insulating protective material layer on the surface of the structure after forming the first opening; removing the insulating protective material layer outside the first lateral opening to form an insulating protective layer; based on the insulating protective layer, removing the second channel material layer and the second gate dielectric material layer outside the first lateral opening to form the second channel layer and the second gate dielectric initial layer; forming a first filling layer in the remaining space of the first opening.

13. The method of claim 10, wherein the semiconductor structure is prepared by a method comprising: the forming process of the bit line comprises: etching the stacked material layer in the first lateral opening on one side of the first opening to form an isolation trench extending in the second direction and a lateral trench, the isolation trench penetrating through the stacked material layer, the lateral trench being communicated with the isolation trench and being formed by laterally etching the second dielectric material layer, and the lateral trench exposing the second gate dielectric initial layer; etching the second gate dielectric initial layer from the lateral trench to expose the second channel layer; forming a bit line connecting the exposed second channel layer in the lateral trench; forming a second filling layer in the isolation trench.

14. The method of claim 13, wherein the semiconductor structure is prepared by a method comprising: before the forming of the bit line connecting the exposed second channel layer in the lateral trench, the process further comprises: doping the second channel layer through the lateral trench to form a first doped region; forming a first metal silicide on the surface of the first doped region.

15. The method of claim 10, wherein the semiconductor structure is prepared by a method comprising: the forming process of the common source line comprises: etching the stacked material layer in the first lateral opening on the other side of the first opening to form a source line trench, the source line trench exposing the second gate dielectric initial layer; etching the second gate dielectric initial layer from the source line trench to expose the second channel layer; forming the common source line connecting the exposed second channel layer in the source line trench.

16. The method of claim 15, wherein the semiconductor structure is prepared by a method comprising: forming at least two first openings arranged oppositely in the first direction when etching the stacked material layer to form the first opening; The source line trench is formed between two first openings arranged opposite to each other in the first direction, and exposes the second gate dielectric initial layer on both sides of the source line trench.

17. The method of claim 15, wherein the semiconductor structure is prepared by a method comprising: Before forming the common source line connected to the exposed second channel layer in the source line trench, the method further comprises: Doping the second channel layer through the source line trench to form a second doped region; Forming a second metal silicide on the surface of the second doped region.

18. The method of claim 10, wherein: Forming a first transistor between the bit line and the second gate, comprising: Etching the stack material layer between the bit line and the storage gate to form a third opening, and the remaining stack material layer forms a stack layer, wherein the remaining first dielectric material layer forms a first dielectric layer, and the remaining second dielectric material layer forms a second dielectric layer, the third opening comprises a third via hole and a third lateral hole, the third lateral hole is communicated with the third via hole and is formed by laterally etching the second dielectric material layer, and the third opening exposes the bit line and the storage gate; Forming a first channel material layer, a first gate dielectric material layer and a conductive protection material layer on the surface of the structure after forming the third opening, the material of the conductive protection material layer is a conductive material; Removing the conductive protection material layer outside the third lateral hole to form a conductive protection layer; Based on the conductive protection layer, removing the first gate dielectric material layer and the first channel material layer outside the third lateral hole to form the first gate dielectric layer and the first channel layer; Forming a third filling layer in the gap between the first channel layer and the first gate dielectric layer and the first dielectric layer, or in the gap between the first gate dielectric layer and the first dielectric layer; Forming the first word line in the remaining space of the third opening, the first word line comprises multiple layers of the first gate of the first transistor.

19. An electronic device, comprising: The semiconductor structure comprises any one of the semiconductor structures according to claims 1 to 8, or is prepared by the semiconductor structure preparation method according to any one of claims 9 to 18.

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