Memory element with planized fins and method of manufacturing the same

Abstract

The invention discloses a memory element and a manufacturing method of the memory element. The memory element includes a semiconductor substrate defining an active region and including a plurality of fins, where the plurality of fins protrude from the semiconductor substrate and are disposed within the active region, where each of the plurality of fins has a first planar top surface; a first word line extending into the semiconductor substrate and extending between a pair of adjacent fins of the plurality of fins, wherein the first word line includes an oxide layer conforming to surfaces of the pair of adjacent fins of the plurality of fins, a first conductive member surrounded by the oxide layer, and a first nitride layer disposed over the first conductive member and surrounded by the oxide layer; an isolation structure extends into the semiconductor substrate and surrounds the active region.

Description

TECHNICAL FIELD

[0001] This application claims priority to U.S. Patent Application No. 18 / 665,837 (i.e., priority date of “May 16, 2024”), the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a memory element and a method of manufacturing the same, and more particularly, to a memory element having a planarized fin on a substrate and a method of manufacturing the same. BACKGROUND

[0003] Dynamic random access memory (DRAM) is a semiconductor configuration used to store bits of data in individual capacitors within an integrated circuit (IC). Dynamic random access memory is typically formed as a trench capacitor DRAM cell. Advanced methods of fabricating a buried gate electrode involve constructing a gate electrode and word line of a transistor in a trench in an active area (AA) including a shallow trench isolation (STI) structure.

[0004] Over the past several decades, as semiconductor manufacturing technology has continued to improve, the size of electronic devices has correspondingly decreased. As the size of unit transistors is reduced to lengths of a few nanometers, the size of the contact between the unit transistor and the active area can become problematic. Smaller contact areas between the unit transistor and the active area can result in a significant decrease in the performance of the unit transistor. Accordingly, there is a need to develop improvements that address the related manufacturing challenges.

[0005] The discussion of the background art does not constitute an admission that any of the art in the background art section is prior art to the present disclosure. The discussion of the background art in the section serves merely to SUMMARY

[0006] One aspect of the present disclosure provides a memory element. The memory element includes a semiconductor substrate defining an active region and including a plurality of fins, wherein the plurality of fins protrude from the semiconductor substrate and are disposed within the active region, wherein each of the plurality of fins has a first planar top surface; a first word line extending into the semiconductor substrate and extending between a pair of adjacent fins of the plurality of fins, wherein the first word line includes an oxide layer conforming to surfaces of the pair of adjacent fins of the plurality of fins, a first conductive member surrounded by the oxide layer, and a first nitride layer disposed on the first conductive member and surrounded by the oxide layer, wherein the first nitride layer has a second planar top surface, wherein the second planar top surface is substantially coplanar with the first planar top surface of each of the plurality of fins; an isolation structure extending into the semiconductor substrate and surrounding the active region; a second word line disposed within the isolation structure and separated from the first word line by the plurality of fins; a conductive plug disposed on each of the plurality of fins and surrounded by a first insulating layer, wherein the first insulating layer is disposed on the semiconductor substrate and the isolation structure; a capacitive plug disposed in a second insulating layer and on the conductive plug and disposed to protrude from the second insulating layer; and a contact pad disposed on the second insulating layer and on the capacitive plug.

[0007] Another aspect of the present disclosure provides a memory element. The memory element includes a semiconductor substrate defining an active region; a plurality of fins disposed in the active region of the semiconductor substrate and protruding from the semiconductor substrate, wherein each of the plurality of fins has a first planar top surface; a word line structure including a first word line extending into the semiconductor substrate and extending between a pair of adjacent fins of the plurality of fins, wherein the first word line includes an oxide layer conforming to surfaces of the pair of adjacent fins of the plurality of fins, a first conductive member surrounded by the oxide layer, and a first nitride layer disposed on the first conductive member and surrounded by the oxide layer, wherein the first nitride layer has a second planar top surface, wherein the second planar top surface is substantially coplanar with the first planar top surface of each of the plurality of fins; an isolation structure extending into the semiconductor substrate and surrounding the active region; a second word line disposed within the isolation structure and separated from the first word line by the plurality of fins; a conductive plug disposed on each of the plurality of fins and surrounded by a first insulating layer, wherein the first insulating layer is disposed on the semiconductor substrate and the isolation structure; a capacitive plug disposed in a second insulating layer and on the conductive plug and protruding from the second insulating layer; a contact pad disposed on the second insulating layer and on the capacitive plug; a patterned mask disposed on the second insulating layer and surrounding the contact pad; and a metal plug disposed on the contact pad.

[0008] Another aspect of the disclosure provides a method of fabricating a memory device. The method includes providing a first semiconductor structure, wherein the first semiconductor structure includes: a semiconductor substrate defining a plurality of active regions; an isolation structure surrounding each of the plurality of active regions; a plurality of first recesses and a plurality of second recesses in the semiconductor substrate; a plurality of fins protruding from the semiconductor substrate, wherein each of the plurality of fins has a planar top surface; a first dielectric layer conforming to each of the plurality of first recesses and surrounding the plurality of fins, wherein each of the plurality of fins has a first top surface after the first dielectric layer is formed; a first conductive member in each of the plurality of first recesses and surrounded by the first dielectric layer; a second dielectric layer disposed on the first conductive member and surrounded by the first dielectric layer; and a conductive plug disposed on each of the plurality of fins and surrounded by a first insulating layer, wherein the first insulating layer is disposed on the semiconductor substrate and the isolation structure, the conductive plug extends through the first insulating layer, and each of the plurality of fins has a planar top surface. The method also includes forming an insulating layer on the first semiconductor structure, forming a capacitive plug in the insulating layer, forming a barrier layer on sidewalls of the capacitive plug and attached to the sidewalls of the capacitive plug, and forming a contact pad on the second insulating layer and on the capacitive plug.

[0009] In summary, because the top portion of each fin protruding from the substrate is planarized before a contact is formed between the cell capacitor and one of the fins, the contact area between the cell capacitor and the fin is increased, and the curved surface of the top portion becomes a planar surface. Thus, the overall performance of the memory device is improved and the process of fabricating the memory device is improved.

[0010] The foregoing has outlined rather broadly the technical features and advantages of the present disclosure so that the detailed description of the present disclosure that follows can be better understood. Additional technical features and advantages of the present disclosure will be described below. The present disclosure is directed to all such technical features and advantages of the present disclosure. It should be appreciated that the concepts and specific embodiments disclosed can be readily utilized as base structures or procedures for modifying or designing other structures or procedures for carrying out the same purposes of the present disclosure. Those skilled in the art who have the present disclosure before them will appreciate that other equally effective build structures and procedures can be substituted for the disclosed concepts and specific embodiments without departing from the spirit and scope of the present disclosure as set forth in the claims. BRIEF DESCRIPTION OF DRAWINGS

[0011] The disclosure will be more fully understood with reference to the drawings and embodiments. The disclosure should also be understood to be in cooperation with the symbols of the drawings, which represent similar elements throughout the specification. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of clarity of discussion.

[0012] Figure 1 is a perspective view illustrating a memory element of some embodiments of the present disclosure.

[0013] Figure 2 is a top view illustrating an array region of the memory element of Figure 1 .

[0014] Figure 3A , Figure 3B and Figure 3C are cross-sectional views illustrating a portion of the memory element of some embodiments of the present disclosure taken along the cross-sectional line A-A’ in Figure 2 .

[0015] Figure 4 is a flowchart illustrating a method of manufacturing a memory element according to some embodiments of the present disclosure.

[0016] Figures 5-29 is a cross-sectional view illustrating an intermediate stage in the formation of a memory element according to some embodiments of the present disclosure.

[0017] In the drawings, the following reference numerals are used:

[0018] 100: memory element

[0019] 101: semiconductor substrate

[0020] 101a: peripheral region

[0021] 101b: array region

[0022] 101c: first surface

[0023] 101d: second surface

[0024] 101e: fin

[0025] 101f: first top surface

[0026] 101g: top surface

[0027] 102: active region

[0028] 103: isolation structure

[0029] 103a: fourth top surface

[0030] 104: recess

[0031] 104a: first recess

[0032] 104b: second recess

[0033] 105: first word line

[0034] 105a: second dielectric layer

[0035] 105b: first conductive member

[0036] 105b': conductive material

[0037] 105c: third dielectric layer

[0038] 105c': dielectric material

[0039] 105d: second top surface

[0040] 105e: third top surface

[0041] 105f: first interface

[0042] 106: second word line

[0043] 106a: second conductive member

[0044] 106b: fourth dielectric layer

[0045] 106c: fifth top surface

[0046] 106d: second interface

[0047] 107: first insulating layer

[0048] 107': insulating material

[0049] 107a: third recess

[0050] 108: conductive plug

[0051] 108a: interface

[0052] 109: peripheral photoresist

[0053] 120: first mask layer

[0054] 120a: first trench

[0055] 121: second mask layer

[0056] 122a: second trench

[0057] 122: first dielectric layer

[0058] 133: patterned mask

[0059] 133TS: top surface

[0060] 151: fifth dielectric layer

[0061] 153: patterned mask

[0062] 160: opening

[0063] 163: metal plug

[0064] 163S: sidewall

[0065] 183TS: top surface

[0066] 411: capacitive plug

[0067] 411A: protrusion

[0068] 412: barrier layer

[0069] 412A: top portion

[0070] 807: second insulating layer

[0071] 807TS: top surface

[0072] 808: liner

[0073] 808A: first silicide layer

[0074] 808B: second silicide layer

[0075] 810: contact pad

[0076] 810TS: top surface

[0077] H1: height

[0078] H2: height

[0079] H3: height

[0080] H4: height

[0081] P2: portion

[0082] S1: sidewall

[0083] S2: sidewall

[0084] S3: sidewall

[0085] S4: sidewall

[0086] W1: width

[0087] W2: width

[0088] W3: width

[0089] W4: width

[0090] S200: method

[0091] S201: step

[0092] S202: step

[0093] S203: step

[0094] S204: step

[0095] S205: step

[0096] S205: step

[0097] S206: step

[0098] S207: step

[0099] S208: step

[0100] S209: step

[0101] S210: step DETAILED DESCRIPTION

[0102] Embodiments or examples of the present disclosure shown in the drawings are now described using specific language. It is to be understood that the scope of the present disclosure is not intended to be limited by the specific language used herein. Any alterations or modifications of the described embodiments, and any further applications of the principles disclosed herein, are contemplated as being within the scope of those skilled in the art to which the present disclosure pertains. Any alterations or modifications of the described embodiments, and any further applications of the principles disclosed herein, are contemplated as being within the scope of those skilled in the art to which the present disclosure pertains.

[0103] It is to be understood that the terms first, second, third, etc. can be used herein to describe various components, features, regions, layers and / or sections but do not connote any priority or order with respect to one another. In other words, a first component, feature, region, layer or section discussed below could be termed a second component, feature, region, layer or section without departing from the teachings of the present disclosure.

[0104] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the inventive concepts. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be understood that the terms "comprises" and "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, components, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, components, or groups thereof.

[0105] Also for ease of description, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" or the like, can be used herein for describing an orientation of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The elements can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0106] Figure 1 is a perspective view illustrating a memory element 100 of some embodiments of the present disclosure. In some embodiments, the memory element 100 includes a plurality of unit cells arranged in rows and columns.

[0107] Referring to Figure 1 The memory element 100 includes a semiconductor substrate 101. In some embodiments, the semiconductor substrate 101 includes a semiconductor material, such as silicon, germanium, gallium, arsenic, or a combination thereof. In some embodiments, the semiconductor substrate 101 includes a bulk semiconductor material. In some embodiments, the semiconductor substrate 101 is a semiconductor wafer (e.g., a silicon wafer) or a semiconductor-on-insulator (SOI) wafer (e.g., a silicon-on-insulator wafer). In some embodiments, the semiconductor substrate 101 is a silicon substrate. In some embodiments, the semiconductor substrate 101 includes lightly doped single crystalline silicon. In some embodiments, the semiconductor substrate 101 is a p-type substrate.

[0108] In some embodiments, the semiconductor substrate 101 includes a peripheral region 101a and an array region 101b at least partially surrounded by the peripheral region 101a. In some embodiments, the peripheral region 101a is adjacent to a periphery of the semiconductor substrate 101, and the array region 101b is adjacent to a central region of the semiconductor substrate 101. In some embodiments, the array region 101b can be used to fabricate transistors, capacitors, or other similar components.

[0109] In some embodiments, the semiconductor substrate 101 includes a first surface 101c and a second surface 101d opposite to the first surface 101c. In some embodiments, the first surface 101c is a front side of the semiconductor substrate 101, where electronic devices or components are subsequently formed over the first surface 101c and electrically connected to external circuits. In some embodiments, the second surface 101d is a back side of the semiconductor substrate 101, where there are no electronic devices or components.

[0110] Figure 2 is a top view illustrating an array region 101b of the semiconductor substrate 101 of Figure 1 Referring to Figure 2 , the semiconductor substrate 101 includes a plurality of active areas 102. In some embodiments, the active areas 102 are doped regions in the semiconductor substrate 101. In some embodiments, the active areas 102 horizontally extend over or under the first surface 101c of the semiconductor substrate 101. In some embodiments, each active area 102 includes the same type of dopant. In some embodiments, each active area 102 includes a different type of dopant than the type of dopant included in other active areas 102. In some embodiments, each active area 102 has the same conductivity type. In some embodiments, the active areas 102 include n-type dopants.

[0111] In some embodiments, the memory element 100 includes isolation structures 103 extending into the semiconductor substrate 101 and surrounding the active areas 102. In some embodiments, the isolation structures 103 extend from the first surface 101c toward the second surface 101d of the semiconductor substrate 101. In some embodiments, the isolation structures 103 are shallow trench isolation (STI) structures. In some embodiments, the isolation structures 103 define the boundaries of each active area 102. In some embodiments, the isolation structures 103 are formed of insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, other similar materials, or combinations thereof.

[0112] Figure 3A is a cross-sectional view illustrating a portion of the memory element 100 taken along the cross-sectional line A-A’ in Figure 2 Referring to Figure 2 and Figure 3AA plurality of grooves 104 are formed in the array region 101b of the semiconductor substrate 101, spanning the active region 102 and the isolation structure 103. In some embodiments, the grooves 104 include a first groove 104a extending into the semiconductor substrate 101 and a second groove 104b extending into the isolation structure 103. In some embodiments, the first groove 104a extends across more than one active region 102. In some embodiments, the first groove 104a and the second groove 104b have the same depth. In some embodiments, the first groove 104a is shallower than the second groove 104b.

[0113] See Figure 3A A plurality of fins 101e are formed in a semiconductor substrate 101. In some embodiments, the top surface of the fins is coplanar with the first surface 101c of the semiconductor substrate 101. In some embodiments, the fins 101e are alternately arranged with the first groove 104a. In some embodiments, the top of the fins 101e is the active region 102 of the semiconductor substrate 101. In some embodiments, each fin 101e has a first top surface 101f, such as... Figure 3A As shown. In some embodiments, the first top surface 101f of the fin 101e is planar or flat.

[0114] In some embodiments, the memory 100 includes a first word line 105 located within a first recess 104a, such as Figure 3A As shown. A first word line 105 extends into a semiconductor substrate 101. In some embodiments, the first word line 105 is disposed between an adjacent pair of fins 101e. In some embodiments, at least a portion of the first word line 105 is surrounded by an active region 102.

[0115] In some embodiments, the first character line 105 includes a second dielectric layer 105a, a first conductive member 105b, and a third dielectric layer 105c. In some embodiments, the second dielectric layer 105a is disposed conforming to the sidewall of the first recess 104a. In some embodiments, the second dielectric layer 105a is disposed conforming to the surfaces of two adjacent fins 101e. In some embodiments, the second dielectric layer 105a contacts the entire sidewall of the first recess 104a. In some embodiments, the second dielectric layer 105a is formed of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, other similar materials, or combinations thereof. In some embodiments, the second dielectric layer 105a comprises a dielectric material having a low dielectric constant (low k).

[0116] In some embodiments, a first conductive member 105b is disposed within a first groove 104a and surrounded by a second dielectric layer 105a. In some embodiments, the first conductive member 105b is separated from the fin 101e by the second dielectric layer 105a. In some embodiments, the first conductive member 105b comprises a conductive material, such as tungsten (W).

[0117] In some embodiments, a third dielectric layer 105c is disposed within the first groove 104a and above the first conductive member 105b, and is surrounded by the second dielectric layer 105a. In some embodiments, the third dielectric layer 105c is formed of an insulating material, such as silicon nitride, silicon oxynitride, other similar materials, or combinations thereof. In some embodiments, the third dielectric layer 105c has a second top surface 105d that is substantially coplanar with the first top surface 101f of the fin 101e. In some embodiments, the second top surface 105d of the third dielectric layer 105c is planar or flat.

[0118] In some embodiments, the second dielectric layer 105a has a third top surface 105e that is substantially coplanar with the first top surface 101f of the fin 101e and the second top surface 105d of the third dielectric layer 105c. In some embodiments, the third top surface 105e of the second dielectric layer 105a is planar or flat. In some embodiments, the third top surface 105e of the second dielectric layer 105a is coupled to the first top surface 101f of the fin 101e and the second top surface 105d of the third dielectric layer 105c.

[0119] In some embodiments, the isolation structure 103 has a fourth top surface 103a that is substantially coplanar with the first top surface 101f of the fin 101e, the second top surface 105d of the third dielectric layer 105c, and the third top surface 105e of the second dielectric layer 105a. In some embodiments, the fourth top surface 103a is planar or flat.

[0120] In some embodiments, the memory 100 includes a second word line 106 located within a second recess 104b, such as Figure 3A As shown. In some embodiments, the second character line 106 is surrounded by an isolation structure 103. In some embodiments, the second character line 106 is separated from the first character line 105 by a fin 101e. In some embodiments, the height H1 of the first character line 105 is substantially the same as the height H2 of the second character line 106. In some embodiments, the height H1 of the first character line 105 is substantially less than the height H2 of the second character line 106.

[0121] In some embodiments, the second word line 106 includes a second conductive member 106a located within the second recess 104b, and a fourth dielectric layer 106b located over the second conductive member 106a and within the second recess 104b. In some embodiments, the second conductive member 106a includes a conductive material, such as tungsten (W). In some embodiments, the fourth dielectric layer 106b is formed of an insulating material, such as silicon nitride, silicon oxynitride, other similar materials, or combinations thereof.

[0122] In some embodiments, the fourth dielectric layer 106b has a fifth top surface 106c that is substantially coplanar with the first top surface 101f of the fin 101e, the second top surface 105d of the third dielectric layer 105c, the third top surface 105e of the second dielectric layer 105a, and the fourth top surface 103a of the isolation structure 103. In some embodiments, the fifth top surface 106c of the fourth dielectric layer 106b is a planar or flat surface. In some embodiments, the fifth top surface 106c of the fourth dielectric layer 106b is coupled with the fourth top surface 103a of the isolation structure 103.

[0123] Referring to Figure 3A , the memory 100 further includes a first insulating layer 107 located over the semiconductor substrate 101 and the isolation structure 103, and a conductive plug 108 extending through the first insulating layer 107. In some embodiments, the first insulating layer 107 covers the isolation structure 103, the second word line 106, the first word line 105, and at least a portion of the fin 101e. In some embodiments, the first insulating layer 107 is formed of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, other similar materials, or combinations thereof.

[0124] In some embodiments, the conductive plug 108 contacts the first top surface 101f of the fin 101e. In some embodiments, an interface 108a between the conductive plug 108 and the fin 101e is a planar interface. In some embodiments, the interface 108a is disposed between the conductive plug 108 and the first top surface 101f of the fin 101e. In some embodiments, the conductive plug 108 is formed of a conductive material, such as copper, silver, or other similar materials. In some embodiments, the conductive plug 108 is configured to be electrically connected to a capacitor disposed over the first insulating layer 107.

[0125] Figure 3B is a cross-sectional view illustrating a portion of the memory element 100 along the cross-sectional line A-A’ in Figure 2 As shown in Figure 3B , the memory 100 can further include a contact pad 810 disposed on the conductive plug 108.

[0126] Referring toFigure 3B A second insulating layer 807 is formed over the first insulating layer 107, and a capacitor plug 411 is formed in the second insulating layer 807. The second insulating layer 807 can be made of the same material as used to form the first insulating layer 107, but is not limited thereto. The second insulating layer 807 is formed by the same process as used to form the first insulating layer 107. The capacitor plug 411 is formed by a process that includes performing a lithography process to define a location of the capacitor plug 411, performing an etching process, such as a directional dry etching process, to form a capacitor plug opening (not shown) extending through the second insulating layer 807, depositing a conductive material over the second insulating layer 807 and in the capacitor plug opening, performing a metallization process in the capacitor plug opening to form the capacitor plug 411 over the conductive plug 108, and performing a planarization process, such as chemical mechanical polishing, to remove excess deposited material to provide a substantially planar surface for subsequent process steps. In some embodiments, the conductive material includes aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy. In some embodiments, the metallization process is chemical vapor deposition, physical vapor deposition, or sputtering. In some embodiments, a barrier layer 412 is disposed between the capacitor plug 411 and the second insulating layer 807. The barrier layer 412 is disposed on and adheres to sidewalls S1 and S2 of the capacitor plug 411. The barrier layer 412 is made of titanium (Ti), titanium nitride (TiN), or a combination thereof.

[0127] Referring to Figure 3B The protruding portion 411 A of the capacitor plug 411 and the top portion 412A of the barrier layer 412 can protrude from the second insulating layer 807. In some embodiments, an etch-back process is performed to remove a top portion of the second insulating layer 807 to expose the protruding portion 411 A of the capacitor plug 411 and the top portion 412A of the barrier layer 412. In some embodiments, after the etch-back process, a top surface of the capacitor plug 411 is higher than a top surface 807TS of the second insulating layer 807, and sidewalls of the top portion 412A of the barrier layer 412 are exposed.

[0128] Referring to Figure 3Bfirst, a deposition process is performed to form a liner (not shown) covering the top surface 807TS of the second insulating layer 807, the top surface of the protruding portion 411 A, and the sidewall S3 and the sidewall S4 of the top portion 412A. In some embodiments, the liner is a silicon-containing layer, such as a polysilicon layer. Next, a heating process is performed to form the contact pad 810 over the second insulating layer 807. In some embodiments, a silicidation process (the heating process) is performed to form the contact pad 810 over the second insulating layer 807, where the contact pad 810 includes the protruding portion 411 A of the capacitive plug 411, the top portion 412A of the barrier layer 412, a first silicide layer (metallic silicide) 808A over the protruding portion 411 A, and a second silicide layer (metallic silicide) 808B on the sidewall of the protruding portion 411 A. In some embodiments, the heating process transforms a portion of the protruding portion 411 A and the liner into the first silicide layer 808A. In some embodiments, the heating process transforms the top portion 412A of the barrier layer 412 and the liner 808 into the second silicide layer 808B. In other words, the first silicide layer 808A and the second silicide layer 808B are different in material. The contact pad 810 is formed without using lithography techniques, i.e., the contact pad 810 is self-aligned with the capacitive plug 411. In some embodiments, the thickness and shape (not shown in the figures) of the protruding portion 411 A and the top portion 412A can be changed.

[0129] In addition, an etching process, such as an anisotropic dry etching process, can be performed to remove the portion of the liner that is not transformed into metallic silicide by the heating process. In some embodiments, the silicidation process between the top portion 412A and the liner is faster than the silicidation process between the protruding portion 411 A and the liner, and the top end of the second silicide layer 808B is higher than the top end of the first silicide layer 808A. In other words, a step structure is formed between the first silicide layer 808A and the second silicide layer 808B because the height H4 of the second silicide layer 808B is greater than the height H3 of the first silicide layer 808A. In some embodiments, the second silicide layer 808B surrounds the first silicide layer 808A, and the width W4 of the second silicide layer 808B is greater than the width W3 of the first silicide layer 808A.

[0130] Figure 3C is a cross-sectional view illustrating a portion of the memory element 100 taken along the cross-sectional line A-A’ in Figure 2 of FIG. 1. Compared to Figure 3B , Figure 3C The memory element 100 in

[0131] Referring to Figure 3CA patterned mask 133 is disposed on the second insulating layer 807, a fifth dielectric layer 151 is disposed on the patterned mask 133, and a metal plug 163 is disposed in the fifth dielectric layer 151. In some embodiments, the metal plug 163 directly contacts the first silicide layer 808A and the second silicide layer 808B. It should be noted that, according to some embodiments, the second silicide layer 808B partially covers the sidewall 163S of the metal plug 163. In some embodiments, the metal plug 163 is electrically connected to the capacitor plug 411 through the first silicide layer 808A and the second silicide layer 808B. In some embodiments, the metal plug 163 is made of a conductive material, such as tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), a combination thereof, or other suitable metallic material. The formation of the metal plug 163 can include a deposition process and a planarization process. The deposition process can include a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, an organometallic chemical vapor deposition process, a sputtering process, an electroplating process, or other suitable process. The planarization process can include a chemical mechanical polishing process.

[0132] Figure 4 is a flowchart illustrating a method S200 of fabricating a memory element according to some embodiments of the present disclosure, and Figures 5-29 is a cross-sectional view illustrating an intermediate stage in the formation of a memory element 100 according to some embodiments of the present disclosure.

[0133] the stages depicted in Figures 5-29 are also schematically shown in the flowchart of Figure 4 . The fabrication stages depicted in Figures 5-29 describe Figure 4 the process steps shown. The method S200 includes a plurality of operations, and the description and illustration should not be taken as a limitation on the order of these operations. The method S200 includes a plurality of steps (S201, S202, S203, S204, S205, S206, S207, S208, S209, and S210).

[0134] In some embodiments, method S200 includes providing a semiconductor substrate defining a plurality of active regions and including an isolation structure surrounding each of the plurality of active regions (step S201); forming and patterning a first dielectric layer on the semiconductor substrate and the isolation structure (step S202); removing portions of the semiconductor substrate exposed via the first dielectric layer to form a plurality of first grooves extending into the semiconductor substrate, and forming a plurality of fins protruding from the semiconductor substrate (step S203); forming a second dielectric layer conforming to each of the plurality of first grooves and surrounding the plurality of fins, wherein after forming the second dielectric layer, each of the plurality of fins has a first top surface, the first top surface being a rounded surface (step S204); forming a first conductive member within each of the plurality of first grooves and surrounded by the second dielectric layer (step S205); forming a third dielectric member on the first conductive member. The first dielectric layer is surrounded by a second dielectric layer (step S206); a portion of the first dielectric layer, the second dielectric layer, and the first top surface of the plurality of fins are removed to form a second top surface of each of the plurality of fins, wherein the second top surface is a planar surface (step S207); a first insulating layer is formed on the semiconductor substrate, and a conductive plug is formed in the first insulating layer (step S208); a second insulating layer is formed on the first insulating layer, a capacitor plug is formed in the second insulating layer and protrudes from the second insulating layer, a barrier layer is formed on the sidewall of the capacitor plug and attached to the sidewall of the capacitor plug, and a contact pad is formed on the second insulating layer and disposed on the capacitor plug (step S209); a patterned mask is formed on the second insulating layer, a fifth dielectric layer is formed on the patterned mask, and a metal plug is formed in the fifth dielectric layer and on the capacitor plug (step S210).

[0135] See Figure 5 ,according to Figure 4 In step S201, a semiconductor substrate 101 is provided. In some embodiments, the semiconductor substrate 101 includes a semiconductor material, such as silicon, germanium, gallium, arsenic, or a combination thereof. In some embodiments, the semiconductor substrate 101 includes a host semiconductor material. In some embodiments, the semiconductor substrate 101 is a semiconductor wafer (e.g., a silicon wafer) or a semiconductor-on-insulator (SOI) wafer (e.g., a silicon-on-insulator wafer). In some embodiments, the semiconductor substrate 101 is a silicon substrate.

[0136] In some embodiments, the semiconductor substrate 101 includes a peripheral region 101a and an array region 101b at least partially surrounded by the peripheral region 101a. In some embodiments, the peripheral region 101a is adjacent to a periphery of the semiconductor substrate 101, and the array region 101b is adjacent to a central region of the semiconductor substrate 101. In some embodiments, the array region 101b can be used to fabricate transistors, capacitors, or other similar components.

[0137] Figure 6 is a top view of the semiconductor substrate 101 of Figure 5 In some embodiments, the peripheral region 101a is covered by a peripheral photoresist 109, as shown in Figure 6 In some embodiments, the peripheral photoresist 109 is used to protect components located in the peripheral region 101a. In some embodiments, the array region 101b is exposed via the peripheral photoresist 109, as shown in Figure 6

[0138] Figure 7 is a cross-sectional view illustrating a portion of the array region 101b taken along the cross-sectional line B-B’ in Figure 6 In some embodiments, the semiconductor substrate 101 includes a plurality of active regions 102. In some embodiments, the active region 102 is a doped region in the semiconductor substrate 101. In some embodiments, each active region 102 includes the same type of dopant. In some embodiments, each active region 102 includes a different type of dopant than the type of dopant included in other active regions 102. In some embodiments, each active region 102 has the same conductivity type.

[0139] In some embodiments, the isolation structure 103 extends into the semiconductor substrate 101 and surrounds the active region 102. In some embodiments, the isolation structure 103 is a shallow trench isolation structure (STI). In some embodiments, the isolation structure 103 defines a boundary of one of the active regions 102. In some embodiments, the isolation structure 103 is formed of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, other similar materials, or combinations thereof.

[0140] In some embodiments, a first dielectric layer 122 is disposed on the semiconductor substrate 101 and the isolation structure 103 according to step S202 in Figure 4 In some embodiments, the first dielectric layer 122 is disposed by deposition, chemical vapor deposition (CVD), or any other suitable process. Next, in some embodiments, the first dielectric layer 122 is covered by a plurality of mask layers, as shown in Figure 7 ​As shown. In some embodiments, the mask layer includes a second mask layer 121 located above the first dielectric layer 122 and a first mask layer 120 located above the second mask layer 121. In some embodiments, the first mask layer 120 includes an insulating material, such as an oxide or other similar material. In some embodiments, the first mask layer 120 includes silicon dioxide. In some embodiments, the first mask layer 120 includes a plurality of first trenches 120a that cut through the first mask layer 120 and extend over the semiconductor substrate 101 and the isolation structure 103. In some embodiments, the second mask layer 121 is at least partially exposed via the first mask layer 120. In some embodiments, the second mask layer 121 includes carbon or other similar materials.

[0141] Next, as Figure 8 and Figure 9 As shown, the first dielectric layer 122 is patterned. In some embodiments, portions of the first dielectric layer 122 exposed via the first mask layer 120 and portions of the second mask layer 121 exposed via the first mask layer 120 are removed to form a plurality of second trenches 122a, as shown. Figure 8 and Figure 9 As shown. Figure 8 This is a top view, illustrating the peripheral region 101a and array region 101b after the formation of the second trench 122a, and Figure 9 It is along Figure 8 A cross-sectional view drawn along line C-C' in the diagram. In some embodiments, the isolation structure 103 and the active region 102 are at least partially exposed through the second trench 122a. After the second trench 122a is formed, the first mask layer 120 is removed, as shown in the diagram. Figure 10 As shown.

[0142] See Figure 11 ,according to Figure 4 In step S203, a portion of the semiconductor substrate 101 exposed via the first dielectric layer 122 and the second mask layer 121 is removed to form a plurality of first grooves 104a. In some embodiments, the portion of the semiconductor substrate 101 is removed by dry etching or any other suitable process. In some embodiments, the first grooves 104a extend into the semiconductor substrate 101, forming a plurality of fins 101e protruding from the semiconductor substrate 101. In some embodiments, the fins 101e are alternately arranged with the first grooves 104a.

[0143] In some embodiments, portions of the isolation structure 103 exposed via the first dielectric layer 122 and the second mask layer 121 are removed to form a plurality of second grooves 104b, such as Figure 11As shown. In some embodiments, the second groove 104b extends into the isolation structure 103. In some embodiments, a portion of the isolation structure 103 is removed by dry etching or any other suitable process. In some embodiments, the first groove 104a and the second groove 104b are alternately arranged. In some embodiments, the height H1 of the first groove 104a is substantially the same as the height H2 of the second groove 104b. In some embodiments, the height H1 of the first groove 104a is substantially less than the height H2 of the second groove 104b. In some embodiments, the first groove 104a and the second groove 104b are formed simultaneously or sequentially.

[0144] In some embodiments, after the first groove 104a is formed, the second mask layer 121 is removed, such as... Figure 12 As shown. In some embodiments, after the second groove 104b is formed, the second mask layer 121 is removed. In some embodiments, the second mask layer 121 is removed by etching or any other suitable process.

[0145] See Figure 13 ,according to Figure 4 In step S204, a second dielectric layer 105a is formed. In some embodiments, the second dielectric layer 105a conforms to the first groove 104a and surrounds the fin 101e. In some embodiments, the second dielectric layer 105a is formed on the bottom and sidewalls of the first groove 104a. In some embodiments, the second dielectric layer 105a is formed by thermal oxidation or any other suitable process. In some embodiments, the formation of the second dielectric layer 105a includes consuming the surface of the fin 101e exposed via the first groove 104a. In some embodiments, the width W1 of the fin 101e (e.g., ...) is... Figure 12 (As shown) This is reduced after the formation of the second dielectric layer 105a. In some embodiments, the second dielectric layer 105a is an oxide layer. In some embodiments, the second dielectric layer 105a is a silicon dioxide layer.

[0146] In some embodiments, after forming the second dielectric layer 105a, a rounded top surface 101g of the fin 101e is formed, such as Figure 14 As shown. Figure 14 This is a magnified image, for example. Figure 13In some embodiments, the rounded top surface 101g is a convex surface. In some embodiments, a portion of the second dielectric layer 105a is disposed between the first dielectric layer 122 and the rounded top surface 101g of the fin 101e. In some embodiments, the second dielectric layer 105a contacts the portion of the fin 101e exposed via the first recess 104a. In some embodiments, the portion of the rounded top surface 101g that contacts the first dielectric layer 122 has a width W2 that is substantially less than the width Wl of the fin 101e.

[0147] Referring to Figure 15 and Figure 16 , according to step S205 in Figure 4 , the first conductive member 105b is formed. In some embodiments, the first conductive member 105b is surrounded by the second dielectric layer 105a. In some embodiments, the formation of the first conductive member 105b includes disposing a conductive material 105b' in the first recess 104a and over the first dielectric layer 122 and the second dielectric layer 105a, as shown in Figure 15 , followed by removing portions of the conductive material 105b' that are over the first dielectric layer 122 and within the first recess 104a, as shown in Figure 16 . In some embodiments, after the portions of the conductive material 105b' are removed, at least a small amount of the second dielectric layer 105a is exposed above the conductive material 105b'. In some embodiments, after the portions of the conductive material 105b' are removed, at least a small amount of the conductive material 105b' is surrounded by the active region 102. In some embodiments, the conductive material 105b' includes tungsten or other similar materials. In some embodiments, the conductive material 105b' is disposed by deposition or any other suitable process. In some embodiments, the portions of the conductive material 105b' are removed by etch-back or any other suitable process.

[0148] In some embodiments, the second conductive member 106a is formed, as shown in Figure 16 . In some embodiments, the second conductive member 106a is formed within the second recess 104b and surrounded by the isolation structure 103. In some embodiments, the formation of the second conductive member 106a includes disposing a conductive material 105b' in the second recess 104b and over the first dielectric layer 122, as shown in Figure 15 , followed by removing portions of the conductive material 105b' that are over the first dielectric layer 122 and portions of the conductive material 105b' within the first recess 104a, as shown in Figure 16 . In some embodiments, the first conductive member 105b and the second conductive member 106a are formed simultaneously or separately.

[0149] Referring to Figure 17 andFigure 18 ,according to Figure 4 In step S206, a third dielectric layer 105c is formed on the first conductive member 105b, and the third dielectric layer 105c is surrounded by the second dielectric layer 105a. In some embodiments, the third dielectric layer 105c is formed on the first conductive member 105b and at least partially formed within the first groove 104a. In some embodiments, the third dielectric layer 105c is a nitride layer. In some embodiments, the formation of the third dielectric layer 105c includes disposing a dielectric material 105c' within the first groove 104a and on the first dielectric layer 122 and the first conductive member 105b, such as... Figure 17 As shown, the portion of dielectric material 105c' located outside the first groove 104a is then removed, as follows. Figure 18 As shown. In some embodiments, the dielectric material 105c' is formed by deposition or any other suitable process. In some embodiments, portions of the dielectric material 105c' are removed by planarization, chemical mechanical polishing (CMP), or any other suitable process.

[0150] In some embodiments, a fourth dielectric layer 106b is formed over the second conductive member 106a and at least partially within the second groove 104b. In some embodiments, the fourth dielectric layer 106b is a nitride layer. In some embodiments, the formation of the fourth dielectric layer 106b includes depositing a dielectric material 105c' within the second groove 104b and over the first dielectric layer 122 and the second conductive member 106a, such as... Figure 17 Then, remove the portion of dielectric material 105c' located outside the second groove 104b, as follows: Figure 18 As shown. In some embodiments, the third dielectric layer 105c and the fourth dielectric layer 106b are formed simultaneously.

[0151] See Figure 18 and Figure 19 ,according to Figure 4 In step S207, a portion of the rounded top surface 101g of the second dielectric layer 105a, the first dielectric layer 122, and the fin 101e is removed. In some embodiments, after removing the rounded top surface 101g of the fin, a flat first top surface 101f of the fin 101e is formed, as shown below. Figure 19 As shown. In some embodiments, the flat first top surface 101f of the fin 101e is substantially lower than the rounded top surface 101g of the fin 101e. In some embodiments, the height H1 of the fin 101e is reduced after the rounded top surface 101g of the fin 101e is removed. In some embodiments, the length of the rounded top surface 101g is greater than the length of the flat first top surface 101f.

[0152] In some embodiments, the rounded top surface 101g and the portion of the dielectric material 105c' (such as...) Figure 17 The first top surface 101f and the third dielectric layer 105c are simultaneously removed, so that the flat first top surface 101f and the third dielectric layer 105c are formed simultaneously. In some embodiments, the removal of the first dielectric layer 122, a portion of the second dielectric layer 105a and the rounded top surface 101g of the fin 101e includes planarization or CMP.

[0153] In some embodiments, a second top surface 105d is also formed after the third dielectric layer 105c is formed. In some embodiments, the second top surface 105d is planar and substantially coplanar with the flat first top surface 101f of the fin 101e. In some embodiments, a third top surface 105e is formed after a portion of the second dielectric layer 105a is removed. In some embodiments, the third top surface 105e is planar and substantially coplanar with the flat first top surface 101f and the second top surface 105d of the fin 101e.

[0154] In some embodiments, a portion of the isolation structure 103 is also removed to form a fourth top surface 103a, such as Figure 18 As shown. In some embodiments, the removal of a portion of the isolation structure 103 and the removal of the rounded top surface 101g are performed simultaneously. In some embodiments, the fourth top surface 103a is planar and substantially coplanar with the flat first top surface 101f, second top surface 105d and third top surface 105e of the fin 101e.

[0155] In some embodiments, a fifth top surface 106c is formed after the fourth dielectric layer 106b is formed. In some embodiments, the removal of a portion of the isolation structure 103 and the formation of the fourth dielectric layer 106b are performed simultaneously. In some embodiments, the fifth top surface 106c is planar and substantially coplanar with the flat first top surface 101f, second top surface 105d, third top surface 105e, and fourth top surface 103a of the fin 101e. In some embodiments, the first interface 105f between the first conductive member 105b and the third dielectric layer 105c is substantially coplanar with the second interface 106d between the second conductive member 106a and the fourth dielectric layer 106b.

[0156] See Figure 20 , Figure 21 and Figure 22 ,according to Figure 4In some embodiments, after forming the planar first top surface 101f, a first insulating layer 107 is formed over the semiconductor substrate 101, and a conductive plug 108 is formed in the first insulating layer 107. In some embodiments, the conductive plug 108 extends through the first insulating layer 107. In some embodiments, the first insulating layer 107 is formed by disposing an insulating material 107' over the fin 101e, the isolation structure 103, the second dielectric layer 105a, the third dielectric layer 105c, and the fourth dielectric layer 106b, as shown in Figure 20 , and then removing portions of the insulating material 107' to form a plurality of third recesses 107a extending through the first insulating layer 107, as shown in Figure 21 . In some embodiments, at least a portion of the planar first top surface 101f of the fin 101e is exposed via the first insulating layer 107. In some embodiments, the insulating material 107' comprises an insulating material, such as an oxide, a nitride, or other similar material.

[0157] Referring to Figure 22 , the conductive plug 108 is formed after forming the first insulating layer 107. In some embodiments, the conductive plug 108 extends through the first insulating layer 107 and contacts the planar first top surface 101f of the fin 101e. In some embodiments, the conductive plug 108 is formed by disposing a conductive material into the third recesses 107a. In some embodiments, the conductive material comprises copper, silver, or other similar material. In some embodiments, the conductive material is disposed by deposition, electroplating, or any other suitable process. In some embodiments, a planar interface 108a is formed between the conductive plug 108 and the planar first top surface 101f of the fin 101e. In this way, the memory element 100 including the array region 101b can be formed, as shown in Figure 1 . In some embodiments, a cell capacitor is disposed over and electrically connected to the conductive plug 108. Figure 3A

[0158] Referring to Figure 4 and Figures 23-26 , according to some embodiments of the present disclosure, in step S209, the formation of the memory 100 can further include forming a second insulating layer 807, a capacitor plug 411, a barrier layer 412, and a contact pad 810. In this way, the memory element 100 including the array region 101b can be formed, as shown in Figure 3A . In some embodiments, a cell capacitor is disposed over and electrically connected to the contact pad 810.

[0159] Referring to Figure 23 ​A second insulating layer 807 is formed over the first insulating layer 107. In some embodiments, the second insulating layer 807 can be made of the same material as used to form the first insulating layer 107, but is not limited thereto. In some embodiments, the second insulating layer 807 is formed by the same process as used to form the first insulating layer 107.

[0160] Referring to Figure 23 A capacitor plug 411 is formed in the second insulating layer 807 and over the conductive plug 108. In some embodiments, the capacitor plug 411 is formed by a process including performing a lithography process to define a location of the capacitor plug 411, performing an etching process, such as a directional dry etching process, to form a capacitor plug opening (not shown) extending through the second insulating layer 807, depositing a conductive material over the second insulating layer 807 and in the capacitor plug opening, performing a metallization process in the capacitor plug opening to form the capacitor plug 411 over the conductive plug 108, and performing a planarization process, such as chemical mechanical polishing, to remove excess deposited material and provide a substantially planar surface for subsequent process steps. In some embodiments, the conductive material includes aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy. In some embodiments, the metallization process is chemical vapor deposition, physical vapor deposition, or sputtering.

[0161] Referring to Figure 23 A barrier layer 412 is disposed between the capacitor plug 411 and the second insulating layer 807. The barrier layer 412 is disposed on and adheres to sidewalls S1 and S2 of the capacitor plug 411. In some embodiments, the barrier layer 412 is made of titanium (Ti), titanium nitride (TiN), or a combination thereof.

[0162] Referring to Figure 24 An etching process is performed to remove a portion of the second insulating layer 807 to expose a protruding portion 411A of the capacitor plug 411. In some embodiments, an etch-back process is performed to remove a top portion of the second insulating layer 807 to expose the protruding portion 411A of the capacitor plug 411 and a top portion 412A of the barrier layer 412. In some embodiments, after the etch-back process, a top surface of the capacitor plug 411 is higher than a top surface of the second insulating layer 807, and sidewalls of the top portion 412A are exposed.

[0163] Referring to Figure 25 A deposition process is performed to form a liner layer 808 covering a top surface 807TS of the second insulating layer 807, a top surface of the protruding portion 411A, and sidewalls S3 and S4 of the top portion 412A. In some embodiments, the liner layer 808 is a silicon-containing layer, such as a polysilicon layer.

[0164] Referring toFigure 26 A heating process is performed to form contact pads 810 over the second insulating layer 807. In some embodiments, a silicidation process (a heating process) is performed to form the contact pads 810 over the second insulating layer 807, where the contact pads 810 include the protruding portion 411A of the capacitor plug 411, the top portion 412A of the barrier layer 412, a first silicide layer (metallic silicide) 808A over the protruding portion 411A, and a second silicide layer (metallic silicide) 808B on sidewalls of the protruding portion 411A. In some embodiments, the heating process transforms a portion of the protruding portion 411A and the liner 808 into the first silicide layer 808A. In some embodiments, the heating process transforms the top portion 412A of the barrier layer 412 and the liner 808 into the second silicide layer 808B. In other words, the contact pads 810 are formed without using lithography techniques, i.e., the contact pads 810 are self-aligned with the capacitor plug 411. In some embodiments, the thickness and shape (not shown in the figures) of the protruding portion 411A and the top portion 412A can be changed.

[0165] In addition, an etching process, such as an anisotropic dry etching process, is performed to remove a portion P2 of the liner 808 that is not transformed into a metallic silicide by the heating process. In some embodiments, the silicidation process between the top portion 412A and the liner 808 is faster than the silicidation process between the protruding portion 411A and the liner 808, and the top end of the second silicide layer 808B is higher than the top end of the first silicide layer 808A. In other words, a step structure is formed between the first silicide layer 808A and the second silicide layer 808B because the height H4 of the second silicide layer 808B is greater than the height H3 of the first silicide layer 808A. In some embodiments, the second silicide layer 808B surrounds the first silicide layer 808A, and the width W4 of the second silicide layer 808B is greater than the width W3 of the first silicide layer 808A.

[0166] Referring to Figure 4 and Figures 27-29 According to some embodiments of the present disclosure, in step S210, the forming of the memory 100 can further include disposing a patterned mask 133 over the second insulating layer 807, forming a fifth dielectric layer 151 over the patterned mask 133, and forming a metallic plug 163 in the fifth dielectric layer 151 and over the capacitor plug 411. In this way, the memory element 100 including the array region 101b can be formed, as shown in Figure 3C In some embodiments, a unit capacitor is disposed over and electrically connected to the metallic plug 163.

[0167] Referring to Figure 27A patterned mask 133 is disposed over the second insulating layer 807, and a contact pad 810 is formed in the patterned mask 133. In some embodiments, a planarization process, such as a chemical mechanical polishing or etching process, is performed to remove portions of the patterned mask 133 to provide a substantially planar surface for subsequent process steps. The planarization process is performed until the second silicide layer 808B is exposed. In some embodiments, a top surface 810TS of the contact pad 810 (or a top surface of the second silicide layer 808B) is substantially coplanar with a top surface 133TS of the patterned mask 133.

[0168] Referring to Figure 28 A fifth dielectric layer 151 is formed over the patterned mask 133, and another patterned mask 153 is formed over the fifth dielectric layer 151. In some embodiments, the fifth dielectric layer 151 is etched using the patterned mask 153 as a mask to form openings 160 through the fifth dielectric layer 151.

[0169] In some embodiments, portions of the patterned mask 133 over the first silicide layer 808A are removed so that a top surface 183TS of the first silicide layer 808A is exposed through the openings 160. Also, during the etching process to form the openings 160, the second silicide layer 808B can be slightly etched. The openings 160 can be formed by a wet etching process, a dry etching process, or a combination thereof. After the openings 160 are formed, the patterned mask 153 can be removed.

[0170] Referring to Figure 29 A metal plug 163 is formed in the openings 160 (see Figure 28 ) to directly contact the second silicide layer 808B and the first silicide layer 808A. In some embodiments, the metal plug 163 is made of tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), a combination thereof, or other suitable metal material. The formation of the metal plug 163 can include a deposition process and a planarization process. The deposition process can include a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, an organometallic chemical vapor deposition process, a sputtering process, an electroplating process, or other suitable process. The planarization process can include a chemical mechanical polishing process.

[0171] One aspect of the present disclosure provides a memory element. The memory element includes a semiconductor substrate defining an active region and including a plurality of fins, wherein the plurality of fins protrude from the semiconductor substrate and are disposed within the active region, wherein each of the plurality of fins has a first planar top surface; a first word line extending into the semiconductor substrate and extending between a pair of adjacent fins of the plurality of fins, wherein the first word line includes an oxide layer conforming to surfaces of the pair of adjacent fins of the plurality of fins, a first conductive member surrounded by the oxide layer, and a first nitride layer disposed on the first conductive member and surrounded by the oxide layer, wherein the first nitride layer has a second planar top surface, wherein the second planar top surface is substantially coplanar with the first planar top surface of each of the plurality of fins; an isolation structure extending into the semiconductor substrate and surrounding the active region; a second word line disposed within the isolation structure and separated from the first word line by the plurality of fins; a conductive plug disposed on each of the plurality of fins and surrounded by a first insulating layer, wherein the first insulating layer is disposed on the semiconductor substrate and the isolation structure; a capacitive plug disposed in a second insulating layer and on the conductive plug and arranged to protrude from the second insulating layer; and a contact pad disposed on the second insulating layer and on the capacitive plug.

[0172] Another aspect of the present disclosure provides a memory element. The memory element includes a semiconductor substrate defining an active region; a plurality of fins disposed in the active region of the semiconductor substrate and protruding from the semiconductor substrate, wherein each of the plurality of fins has a first planar top surface; a word line structure including a first word line extending into the semiconductor substrate and extending between a pair of adjacent fins of the plurality of fins, wherein the first word line includes an oxide layer conforming to surfaces of the pair of adjacent fins of the plurality of fins, a first conductive member surrounded by the oxide layer, and a first nitride layer disposed on the first conductive member and surrounded by the oxide layer, wherein the first nitride layer has a second planar top surface, wherein the second planar top surface is substantially coplanar with the first planar top surface of each of the plurality of fins; an isolation structure extending into the semiconductor substrate and surrounding the active region; a second word line disposed within the isolation structure and separated from the first word line by the plurality of fins; a conductive plug disposed on each of the plurality of fins and surrounded by a first insulating layer, wherein the first insulating layer is disposed on the semiconductor substrate and the isolation structure; a capacitive plug disposed in a second insulating layer and on the conductive plug and arranged to protrude from the second insulating layer; a contact pad disposed on the second insulating layer and on the capacitive plug; a patterned mask disposed on the second insulating layer and surrounding the contact pad; and a metal plug disposed on the contact pad.

[0173] Another aspect of the present disclosure provides a method of fabricating a memory device. The method includes providing a first semiconductor structure, wherein the first semiconductor structure includes: a semiconductor substrate defining a plurality of active regions; an isolation structure surrounding each of the plurality of active regions; a plurality of first recesses and a plurality of second recesses in the semiconductor substrate; a plurality of fins protruding from the semiconductor substrate, wherein each of the plurality of fins has a planar top portion; a first dielectric layer conforming to each of the plurality of first recesses and surrounding the plurality of fins, wherein each of the plurality of fins has a first top surface after the first dielectric layer is formed; a first conductive member in each of the plurality of first recesses and surrounded by the first dielectric layer; a second dielectric layer disposed on the first conductive member and surrounded by the first dielectric layer; and a conductive plug disposed on each of the plurality of fins and surrounded by a first insulating layer, wherein the first insulating layer is disposed on the semiconductor substrate and the isolation structure, the conductive plug extends through the first insulating layer, and each of the plurality of fins has a planar top surface; forming an insulating layer on the first semiconductor structure; forming a capacitor plug in the insulating layer; forming a barrier layer on sidewalls of the capacitor plug and attached to the sidewalls of the capacitor plug; and forming a contact pad on the second insulating layer and on the capacitor plug.

[0174] In summary, since the top portion of each fin protruding from the substrate is planarized before a contact between a cell capacitor and one of the fins is formed, the contact area between the cell capacitor and the fin is increased by the planarization of the top portion, which changes a curved surface of the top portion into a planar surface. Therefore, the overall performance of the memory device is improved and the process of fabricating the memory device is improved.

[0175] While the disclosure and the best mode thereof have been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above can be implemented differently, and many others are possible, with the described steps being implemented in other orders or in other ways, or with additional or fewer steps.

[0176] Moreover, the scope of the application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Accordingly, the disclosure of the present application is intended to be illustrative, but not limiting, of the scope of the application, which is set forth in the following claims. Accordingly, the disclosure of the present application is intended to be illustrative, but not limiting, of the scope of the application, which is set forth in the following claims.

Claims

1. A memory element comprising: a semiconductor substrate defining an active region and including a plurality of fins, wherein the plurality of fins protrude from the semiconductor substrate and are disposed within the active region, wherein each of the plurality of fins has a first planar top surface; a first word line extending into the semiconductor substrate and between a pair of adjacent fins of the plurality of fins, wherein the first word line includes an oxide layer conforming to surfaces of the pair of adjacent fins of the plurality of fins, a first conductive member surrounded by the oxide layer, and a first nitride layer disposed on the first conductive member and surrounded by the oxide layer; an isolation structure extending into the semiconductor substrate and surrounding the active region, wherein the first nitride layer has a second planar top surface, wherein the second planar top surface is substantially coplanar with the first planar top surface of each of the plurality of fins; a second word line disposed within the isolation structure and separated from the first word line by the plurality of fins; a conductive plug disposed on each of the plurality of fins and surrounded by a first insulating layer, wherein the first insulating layer is disposed on the semiconductor substrate and the isolation structure; a capacitive plug disposed in a second insulating layer and on the conductive plug and configured to protrude from the second insulating layer; and a contact pad disposed on the second insulating layer and on the capacitive plug.

2. The memory element of claim 1, wherein the oxide layer has a third planar top surface, wherein the third planar top surface is substantially coplanar with the first planar top surface of each of the plurality of fins and the second planar top surface of the first nitride layer.

3. The memory element of claim 2, wherein the third planar top surface of the oxide layer is coupled to the first planar top surface of one of the plurality of fins and the second planar top surface of the first nitride layer.

4. The memory element of claim 3, wherein the isolation structure has a fourth planar top surface, wherein the fourth planar top surface is substantially coplanar with the first planar top surface of each of the plurality of fins.

5. The memory element of claim 1, wherein the conductive member includes tungsten.

6. The memory element of claim 1, wherein a height of the second word line is substantially greater than a height of the first word line.

7. The memory element of claim 1, wherein the conductive plug extends through the first insulating layer.

8. The memory element of claim 7, wherein the conductive plug is formed of copper, silver, or other similar material.

9. The memory element of claim 8, wherein the conductive plug is configured to be electrically connected to a capacitive plug, wherein the capacitive plug is disposed above the first insulating layer.

10. The memory element of claim 9, wherein the first insulating layer is formed of silicon oxide, silicon nitride, silicon oxynitride, other similar material, or combination thereof.

11. The memory element of claim 1, wherein the capacitive plug includes a protruding portion, wherein the protruding portion protrudes from the second insulating layer. ​ 12. The memory element of claim 11, wherein the capacitor plug is made of aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy.

13. The memory element of claim 12, wherein the second insulating layer is formed of a same material as a material of the first insulating layer.

14. The memory element of claim 13, further comprising a barrier layer disposed between the capacitor plug and the second insulating layer and disposed on and adhered to sidewalls of the capacitor plug.

15. The memory element of claim 14, wherein the barrier layer is made of titanium (Ti), titanium nitride (TiN), or a combination thereof.

16. The memory element of claim 15, wherein the barrier layer includes a top portion, wherein the top portion protrudes from the second insulating layer.

17. The memory element of claim 16, wherein the contact pad includes the protruding portion of the capacitor plug, the top portion of the barrier layer, a first silicide layer on the protruding portion, and a second silicide layer on sidewalls of the top portion of the barrier layer.

18. The memory element of claim 17, wherein a heating process is performed to form the contact pad.

19. The memory element of claim 18, wherein the first silicide layer and the second silicide layer are of different materials.

Images