Semiconductor memory device

Abstract

A semiconductor memory device includes: a bit line disposed on a substrate and extending in a first direction; a channel structure disposed on the bit line and extending in a second direction perpendicular to the first direction, where the channel structure includes a first vertical portion and a second vertical portion spaced apart from the first vertical portion in the first direction; a word line disposed between the first vertical portion and the second vertical portion and extending in the second direction; a gate insulating film disposed between the first vertical portion and the word line and between the second vertical portion and the word line; a molding pattern disposed on at least one side of the channel structure; and a blocking pattern disposed between the molding pattern and the channel structure.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0064772, filed on May 17, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor storage device. Background Technology

[0004] Semiconductor devices are core components used in electronic devices, and various types of semiconductor devices can be manufactured. For example, memory devices are primarily used for storing and retrieving data, while non-memory devices are used for controlling or amplifying electrical signals. Semiconductor devices are core components of electronic devices and play a vital role in various fields, including computers, communication equipment, and consumer electronics.

[0005] With industrial development, the performance and functional requirements of electronic devices are becoming increasingly demanding. Therefore, there is a fundamental requirement for high-performance semiconductor devices, and the integration density of semiconductor devices is constantly improving to meet these requirements. Consequently, transistors with vertical channels have been proposed to enhance the integration density of semiconductor devices. Summary of the Invention

[0006] To address one or more problems (e.g., the problems described above and / or other problems not explicitly described herein), this disclosure provides a semiconductor memory device with improved electrical characteristics and reliability.

[0007] According to some embodiments of this disclosure, by placing a barrier pattern between the molded pattern and the channel structure, hydrogen ions can be prevented from diffusing from the molded pattern to the channel structure. Therefore, the reliability of semiconductor memory devices can be improved.

[0008] According to some embodiments of this disclosure, by placing a barrier pattern between the molded pattern and the bonding pads, hydrogen ions can be prevented from diffusing from the molded pattern to the bonding pads. Therefore, the electrical characteristics of the semiconductor memory device can be improved.

[0009] According to some embodiments of this disclosure, a semiconductor memory device includes: a bit line disposed on a substrate and extending in a first direction; a channel structure disposed on the bit line and extending in a second direction perpendicular to the first direction, wherein the channel structure includes a first vertical portion and a second vertical portion spaced apart from the first vertical portion in the first direction; a word line disposed between the first vertical portion and the second vertical portion and extending in the second direction; a gate insulating film disposed between the first vertical portion and the word line and between the second vertical portion and the word line; a molded pattern disposed on at least one side of the channel structure; and a blocking pattern disposed between the molded pattern and the channel structure.

[0010] According to some embodiments of the present disclosure, a semiconductor memory device includes: bit lines disposed on a substrate and extending in a first direction; molded patterns aligned on the bit lines and spaced apart from each other in the first direction, and extending in a second direction perpendicular to the first direction; blocking patterns disposed on a side surface of each of the molded patterns; a channel trench defined by an upper surface of the bit lines and the blocking patterns; a channel structure disposed in the channel trench; a word line disposed on the channel structure and extending in the second direction; and a gate insulating film disposed between the channel structure and the word line.

[0011] According to some embodiments of this disclosure, a semiconductor memory device includes: a bit line disposed on a substrate and extending in a first direction; a channel structure disposed on the bit line and extending in a second direction perpendicular to the first direction, wherein the channel structure includes a first vertical portion and a second vertical portion spaced apart from the first vertical portion in the first direction; a word line disposed between the first vertical portion and the second vertical portion and extending in the second direction; a gate insulating film disposed between the first vertical portion and the word line and between the second vertical portion and the word line; a molded pattern disposed on at least one side of the channel structure; a blocking pattern disposed between the molded pattern and the channel structure and extending along a side surface of the molded pattern; a bonding pad disposed on each of the first vertical portion and the second vertical portion; and a capacitor structure disposed on the bonding pad, wherein the distance from the upper surface of the bit line to the upper surface of the blocking pattern is equal to or greater than the distance from the upper surface of the bit line to the upper surface of the second vertical portion. Attached Figure Description

[0012] The above and other aspects and features of this disclosure will become clearer from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0013] Figure 1 This is a plan view illustrating a semiconductor memory device according to an exemplary embodiment of the present disclosure;

[0014] Figure 2 It is along Figure 1 A cross-sectional view taken from line AA;

[0015] Figure 3 It is used for explanation Figure 2 A magnified view of region Q1;

[0016] Figure 4 It is along Figure 1 A cross-sectional view of line BB;

[0017] Figure 5 It is along Figure 1 A cross-sectional view taken from line CC;

[0018] Figure 6 It is along Figure 1 A cross-sectional view of line DD;

[0019] Figure 7 This is a diagram illustrating a semiconductor memory device according to an exemplary embodiment of the present disclosure;

[0020] Figure 8 This is a diagram illustrating a semiconductor memory device according to an exemplary embodiment of the present disclosure;

[0021] Figure 9 This is a diagram illustrating a semiconductor memory device according to an exemplary embodiment of the present disclosure;

[0022] Figure 10 A diagram illustrating a semiconductor memory device according to an exemplary embodiment of the present disclosure; and

[0023] Figures 11 to 19 This is a diagram showing an intermediate stage and used to illustrate a method for manufacturing a semiconductor memory device according to an example embodiment of the present disclosure. Detailed Implementation

[0024] In this disclosure, the terms "upper," "lower," "upper surface," and "lower surface" are used for convenience of description, but are not limited thereto. The terms "upper," "lower," "upper surface," and "lower surface" can be described based on the illustrations in the accompanying drawings, and terms referring to vertical relationships can change with vertical rotation of the drawings.

[0025] When referring to orientation, layout, location, shape, size, quantity, or other measure, terms such as “same,” “equal,” “plane,” or “coplanar” as used herein do not necessarily mean exactly the same orientation, layout, location, shape, size, quantity, or other measure, but are intended to include, for example, substantially the same orientation, layout, location, shape, size, quantity, or other measure within acceptable variations that may occur due to manufacturing processes. Unless the context or other statement otherwise indicates, the term “substantially” may be used herein to emphasize that meaning.

[0026] It will be understood that when referring to an element as "connected" or "coupled" to another element or "on" another element, the element may be directly connected or coupled to that other element or directly on that other element, or there may be an intermediate element. In contrast, when referring to an element as "directly connected" or "directly coupled" to another element or "in contact" with another element (or in any form that uses the word "in contact"), there is no intermediate element at the point of contact.

[0027] In the following, a semiconductor memory device and a method for manufacturing the semiconductor memory device according to some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Similar reference numerals always denote similar elements.

[0028] Figure 1 This is a plan view illustrating a semiconductor memory device according to an exemplary embodiment of the present disclosure. Figure 2 It is along Figure 1 The cross-sectional view taken from line AA. Figure 3 It is used for explanation Figure 2 A magnified view of region Q1. Figure 4 It is along Figure 1 The cross-sectional view of line BB. Figure 5 It is along Figure 1 The cross-sectional view taken from line CC. Figure 6 It is along Figure 1 A cross-sectional view taken from line DD. For reference. Figure 1 The dielectric film 224 and the upper electrode 226 of the capacitor structure CAP are omitted and not shown.

[0029] Semiconductor memory devices according to some embodiments of the present disclosure may include memory cells including vertical channel transistors (VCTs). A vertical channel transistor may refer to a transistor whose channel length extends in a direction perpendicular to the upper surface of the semiconductor substrate.

[0030] refer to Figures 1 to 6 According to some embodiments, a semiconductor memory device may include a substrate 100, a wiring insulating film 110, a bit line BL, a channel structure CH, a word line WL, a bit line insulating film 125, a molded pattern 130, a barrier pattern 150, a gate insulating film 160, a gate separation structure 170, a bonding pad 180, an interlayer insulating film 190, and a capacitor structure CAP.

[0031] The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may be formed of or include silicon (Si), silicon germanium (SiGe), indium antimonide (InSb), lead telluride (PbTe), indium arsenide (InAs), indium phosphide (INP), gallium arsenide (GaAs), gallium antimonide (GaSb), etc. However, the aspects are not limited to the above.

[0032] In some embodiments, a plurality of transistors connected to the bit line BL may be disposed in the substrate 100. For example, sensing transistors, transmission transistors, driving transistors, etc., may be disposed in the substrate 100. The type of transistor may vary depending on the layout design of the semiconductor memory device. The region in the substrate 100 in which a plurality of transistors are disposed may be referred to as the peripheral circuit region.

[0033] A wiring insulating film 110 may be disposed on the substrate 100. In some embodiments, a wiring structure may be disposed within the wiring insulating film 110. The wiring structure may electrically connect the substrate 100 and the bit line BL. For example, a plurality of transistors disposed in the substrate 100 may be electrically connected to the bit line BL via the wiring structure.

[0034] Bit lines BL can be disposed on the wiring insulating film 110. Bit lines BL can extend longitudinally along a first direction D1 on the wiring insulating film 110. Adjacent bit lines BL in a plurality of bit lines BL can be spaced apart from each other in a second direction D2. The second direction D2 can be a direction perpendicular to the first direction D1. In some embodiments, the upper surface of the bit line BL and the upper surface of the bit line insulating film 125 can be disposed on the same plane as each other.

[0035] Bit line BL may include a conductive layer 124 and a contact layer 122. The contact layer 122 may be disposed on the conductive layer 124. For example, the lower surface of the contact layer 122 may contact the upper surface of the conductive layer 124. In an example embodiment, the conductive layer 124 may include at least one of the following: doped polysilicon, metal (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co), conductive metal nitride (e.g., TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, RuTiN), conductive metal silicide, or conductive metal oxide (e.g., PtO, RuO2, IrO2, SrRuO3 (SRO), (Ba,Sr)RuO3 (BSRO), CaRuO3 (CRO), LSCo), but is not limited thereto.

[0036] For example, the contact layer 122 may include at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and two-dimensional (2D) materials.

[0037] In some embodiments, the contact layer 122 and the conductive layer 124 may comprise 2D semiconductor materials. For example, the 2D material may comprise 2D allotropes or 2D compounds, and may include at least one of, for example, graphene, carbon nanotubes, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), and tungsten disulfide (WS2), but is not limited thereto. That is, the above-described 2D materials are merely a list of examples, and the 2D materials that may be included in the semiconductor memory devices of this disclosure are not limited to those described above.

[0038] The molded pattern 130 can be disposed on the upper surface of the bit line BL and the upper surface of the bit line insulating film 125. The molded pattern 130 can extend longitudinally in the second direction D2. The molded patterns 130 can be aligned and spaced apart from each other in the first direction D1.

[0039] The molded pattern 130 may be formed of or comprise an insulating material. For example, the molded pattern 130 may comprise at least one of silicon oxide, silicon nitride, silicon oxynitride, and low-k insulating materials.

[0040] The blocking pattern 150 can be disposed on the upper surface of the bit line BL, the upper surface of the bit line insulating film 125, and the side surface 130_SS of the molded pattern 130. The blocking pattern 150 can extend along the side surface 130_SS of the molded pattern 130 in the second direction D2. The blocking pattern 150 can overlap with the molded pattern 130 in the first direction D1. The blocking pattern 150 can not overlap with the molded pattern 130 in the third direction D3. The third direction D3 can be a direction perpendicular to the upper surface of the bit line BL. The third direction D3 can be perpendicular to each of the first direction D1 and the second direction D2.

[0041] A blocking pattern 150 may be disposed between the molded pattern 130 and the channel structure CH. A first side surface 150_SS1 of the blocking pattern 150 may contact a side surface 130_SS of the molded pattern 130. A second side surface 150_SS2 of the blocking pattern 150 may contact the channel structure CH. The first side surface 150_SS1 of the blocking pattern 150 may be opposite to the second side surface 150_SS2 in a first direction D1.

[0042] For example, the blocking pattern 150 may be formed from or include any one of aluminum oxide, hafnium oxide, zirconium oxide and silicon nitride.

[0043] A trench CH_T can be disposed on the upper surface of the bit line BL. The bottom surface of the trench CH_T can be defined as the upper surface of the bit line BL and the upper surface of the bit line insulating film 125. The two side surfaces of the trench CH_T can be defined by two blocking patterns 150 facing each other in a first direction D1. The trench CH_T can extend longitudinally in a second direction D2. The trench CH_T can be spaced apart from each other in the first direction D1 and the second direction D2. The trench CH_T can expose the upper surface of the bit line BL.

[0044] The channel structure CH can be disposed on the upper surface of the bit line BL. The channel structure CH can be connected to the bit line BL. The channel structures CH disposed on a bit line BL can be spaced apart from each other in the first direction D1.

[0045] The channel structure CH can be set in the channel groove CH_T. The channel structure CH can extend along the sidewalls and bottom surface of the channel groove CH_T. From the perspective of cross-section, the channel structure CH can have an approximately "U" shape.

[0046] The channel structure CH may include a first vertical portion CH_V1, a second vertical portion CH_V2, and a horizontal portion CH_H.

[0047] Each of the first vertical portion CH_V1 and the second vertical portion CH_V2 may be disposed on the second side surface 150_SS2 of the blocking pattern 150. Each of the first vertical portion CH_V1 and the second vertical portion CH_V2 may contact the second side surface 150_SS2 of the blocking pattern 150. Each of the first vertical portion CH_V1 and the second vertical portion CH_V2 may extend in a third direction D3. The first vertical portion CH_V1 may extend from one end of the horizontal portion CH_H in the third direction D3, and the second vertical portion CH_V2 may extend from the other end of the horizontal portion CH_H in the third direction D3. The first vertical portion CH_V1 and the second vertical portion CH_V2 may be spaced apart from each other in a first direction D1.

[0048] The horizontal portion CH_H can be disposed along the upper surface of the bit line BL. The horizontal portion CH_H can connect to the first vertical portion CH_V1 and the second vertical portion CH_V2. However, it is not limited to this. Unlike the illustration, the horizontal portion CH_H can be divided into two parts. For example, one separate portion of the horizontal portion CH_H can be connected to the first vertical portion CH_V1, and the other separate portion of the horizontal portion CH_H can be connected to the second vertical portion CH_V2. The gate separation structure 170 can be disposed between the separated horizontal portions CH_H.

[0049] The channel structure CH can include oxide semiconductors. For example, oxide semiconductors can include In... x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O、Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O, Al x Zn y Sn z O、Yb x Ga y Zn z O and In x Ga y The channel structure CH may include at least one of the following, but is not limited thereto. For example, the channel structure CH may include indium gallium zinc oxide (IGZO). The channel structure CH may include a single-layer or multi-layer oxide semiconductor. The channel structure CH may include amorphous, crystalline, or polycrystalline oxide semiconductors.

[0050] In some embodiments, the band gap energy of the channel structure CH can be greater than that of silicon. For example, the channel structure CH can have a band gap energy of about 1.5 eV to 5.6 eV. For example, the channel structure CH can have optimal channel performance when it has a band gap energy of about 2.0 eV to 4.0 eV. For example, the channel structure CH can be polycrystalline or amorphous, but is not limited thereto.

[0051] In some embodiments, the channel structure CH may include a 2D semiconductor material. For example, the 2D semiconductor material may include graphene, carbon nanotubes, or a combination thereof.

[0052] In some embodiments, the distance H1 from the upper surface of the bit line BL to the upper surface of the molded pattern 130 can be equal to the distance H4 from the upper surface of the bit line BL to the upper surface of the blocking pattern 150. In other words, the upper surfaces of the molded pattern 130 and the blocking pattern 150 can be disposed on the same plane. For example, the upper surfaces of the molded pattern 130 and the blocking pattern 150 can be coplanar, and the lower surfaces of the molded pattern 130 and the blocking pattern 150 can be coplanar. The first side surface 150_SS1 of the blocking pattern 150 can completely cover the side surface 130_SS of the molded pattern 130. Therefore, the blocking pattern 150 can block hydrogen ions from diffusing from the side surface 130_SS of the molded pattern 130.

[0053] In some embodiments, the uppermost part of the channel structure CH can be set below the upper surface of the molded pattern 130. For example, the distance H2 from the upper surface of the bit line BL to the upper surface of the second vertical portion CH_V2 can be less than the distance H1 from the upper surface of the bit line BL to the upper surface of the molded pattern 130.

[0054] In some embodiments, the upper surface of the blocking pattern 150 may be configured to be higher than the upper surfaces of the first vertical portion CH_V1 and the second vertical portion CH_V2. For example, the distance H4 from the upper surface of the bit line BL to the upper surface of the blocking pattern 150 may be greater than the distance H2 from the upper surface of the bit line BL to the second vertical portion CH_V2.

[0055] The barrier pattern 150 can completely cover one side surface of the first vertical portion CH_V1 and one side surface of the second vertical portion CH_V2. Using the barrier pattern 150 with this configuration, hydrogen ions can be prevented from diffusing from the molded pattern 130 into the channel structure CH. In other words, the barrier pattern 150 can prevent the electrical characteristics of the channel structure CH from deteriorating. Therefore, the electrical characteristics and reliability of the semiconductor memory device can be improved.

[0056] Word lines WL can be disposed on the channel structure CH. Word lines WL can intersect with bit lines BL. Word lines WL can extend in the second direction D2. Word lines WL can be spaced apart from each other in the first direction D1. Word lines WL can include a first word line WL1 and a second word line WL2.

[0057] Each of the first character line WL1 and the second character line WL2 can be disposed on the channel structure CH. Each of the first character line WL1 and the second character line WL2 can be disposed between the first vertical portion CH_V1 and the second vertical portion CH_V2. The first character line WL1 can be disposed on one side of the horizontal portion CH_H and the first vertical portion CH_V1. The second character line WL2 can be disposed on one side of the horizontal portion CH_H and the second vertical portion CH_V2. The first character line WL1 and the second character line WL2 can be spaced apart from each other in the first direction D1.

[0058] The width of the first character line WL1 in the first direction D1 may not be constant. For example, the portion of the first character line WL1 disposed on the channel structure CH may have a smaller width in the first direction D1 than the portion of the first character line WL1 not disposed on the channel structure CH. For example, the portion of the first character line WL1 disposed between the channel structures CH may have a smaller width in the first direction D1 than the portion of the first character line WL1 not disposed between the channel structures CH. The second character line WL2 may be configured to have the same or similar width as the first character line WL1 in the first direction D1.

[0059] For example, the word line WL may include at least one of the following: doped polycrystalline silicon, metals (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co), conductive metal nitrides (e.g., TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, RuTiN), conductive metal silicides, or conductive metal oxides (e.g., PtO, RuO2, IrO2, SrRuO3 (SRO), (Ba,Sr)RuO3 (BSRO), CaRuO3 (CRO), LSCo), but is not limited thereto. The word line WL may include a single layer of each of the above materials or multiple layers of said materials.

[0060] In some embodiments, the word line WL may include a 2D semiconductor material. For example, the 2D semiconductor material may include graphene, carbon nanotubes, or a combination thereof.

[0061] In some embodiments, the upper surface of the first word line WL1 may be configured to be higher than the upper surface of the first vertical portion CH_V1. The upper surface of the second word line WL2 may be configured to be higher than the upper surface of the second vertical portion CH_V2. For example, the distance H3 from the upper surface of the bit line BL to the upper surface of the second word line WL2 may be greater than the distance H2 from the upper surface of the bit line BL to the upper surface of the second vertical portion CH_V2.

[0062] A gate insulating film 160 can be disposed between the word line WL and the channel structure CH. For example, the gate insulating film 160 can be disposed between the first word line WL1 and the first vertical portion CH_V1, and between the second word line WL2 and the second vertical portion CH_V2, respectively. The gate insulating film 160 can extend parallel to the first word line WL1 and the second word line WL2 in the second direction D2. Due to the presence of the gate insulating film 160, the first word line WL1 and the second word line WL2 can be non-contact with the channel structure CH. For example, the first word line WL1 and the second word line WL2 can be electrically separated from the channel structure CH through the gate insulating film 160.

[0063] A portion of the gate insulating film 160 may protrude further on the third-direction D3 than the upper surface of the first word line WL1 and the upper surface of the second word line WL2. For example, the uppermost part of the gate insulating film 160 may be configured to be higher than the upper surface of the first word line WL1 and the upper surface of the second word line WL2.

[0064] The distance from the upper surface of the bit line BL to the uppermost part of the gate insulating film 160 can be greater than the distance H2 from the upper surface of the bit line BL to the upper surface of the second vertical portion CH_V2 of the channel structure CH. The distance from the upper surface of the bit line BL to the uppermost part of the gate insulating film 160 can be greater than the distance H3 from the upper surface of the bit line BL to the upper surface of the second word line WL2.

[0065] The gate insulating film 160 may include at least one of silicon oxide, silicon oxynitride, and a high-k material with a dielectric constant higher than that of silicon oxide. The high-k material may include a metal oxide or a metal oxynitride. For example, the high-k material that can be used as the gate insulating film 160 may include at least one of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, and Al2O3, but is not limited thereto.

[0066] A gate separation structure 170 may be disposed on the bit line BL and the bit line insulating film 125. The gate separation structure 170 may be disposed in the channel trench CH_T. The gate separation structure 170 may be disposed on the channel structure CH. In a semiconductor memory device according to some embodiments, the gate separation structure 170 may contact the channel structure CH. The gate separation structure 170 may contact the horizontal portion CH_H. The gate separation structure 170 may be spaced apart from the bit line BL on a third-direction D3.

[0067] A gate separation structure 170 may be disposed in a first direction D1 between a first word line WL1 and a second word line WL2 to separate the first word line WL1 and the second word line WL2. The gate separation structure 170 may extend along a second direction D2 between the first word line WL1 and the second word line WL2. The gate separation structure 170 may contact the first word line WL1, the second word line WL2, and the gate insulating film 160.

[0068] The first word line WL1 can be disposed between the gate separation structure 170 and the first vertical portion CH_V1. The second word line WL2 can be disposed between the gate separation structure 170 and the second vertical portion CH_V2.

[0069] The gate separation structure 170 may include a horizontal portion and a protruding portion. The protruding portion of the gate separation structure 170 may protrude from the horizontal portion of the gate separation structure 170 along a third direction D3 toward the bit line BL. The protruding portion of the gate separation structure 170 may be closer to the bit line BL than the horizontal portion of the gate separation structure 170. The horizontal portion of the gate separation structure 170 may be disposed on the upper surface of the first word line WL1 and the second word line WL2. From a cross-sectional perspective, the gate separation structure 170 may have a "T" shape.

[0070] The gate separation structure 170 may include a gate separation pad film 172, a gate separation fill film 174, and a gate separation capping film 176. The gate separation pad film 172 may extend along the upper and outer surfaces of the first word line WL1 and the second word line WL2. The gate separation pad film 172 may extend along the horizontal portion CH_H of the channel structure CH. The gate separation pad film 172 may contact the horizontal portion CH_H. The gate separation pad film 172 may extend along a gate insulating film 160 that protrudes further than the upper surfaces of the first word line WL1 and the second word line WL2. Contrary to the illustration, the gate separation pad film 172 may not extend along the gate insulating film 160 that protrudes further than the upper surfaces of the first word line WL1 and the second word line WL2.

[0071] A gate separation filler film 174 may be disposed on a gate separation pad film 172. For example, the gate separation filler film 174 may contact the side surface and the top surface of the gate separation pad film 172. A gate separation capping film 176 may be disposed on a gate separation filler film 174. For example, the gate separation capping film 176 may contact the top surface of the gate separation filler film 174 and the top surface and side surface of the gate separation pad film 172. The top surfaces of the gate separation capping film 176 and the gate separation pad film 172 may be coplanar. The uppermost surface of the gate separation filler film 174 may be at a vertical level lower than the uppermost surfaces of the gate separation capping film 176 and the gate separation pad film 172. Each of the gate separation pad film 172, the gate separation filler film 174, and the gate separation capping film 176 may be formed of an insulating material. Unlike the illustration, the gate separation structure 170 may be a single layer.

[0072] In some embodiments, the upper surface of the gate separation structure 170 may be disposed on the same plane as the upper surface of the molding pattern 130. For example, the distance from the upper surface of the bit line BL to the upper surface of the gate separation structure 170 may be equal to the distance H1 from the upper surface of the bit line BL to the upper surface of the molding pattern 130. However, the aspects are not limited thereto.

[0073] The bonding pad 180 can be disposed on the barrier pattern 150, the channel structure CH, and the gate separation structure 170. The bonding pad 180 can contact the barrier pattern 150 and the channel structure CH. The bonding pad 180 can be electrically connected to the channel structure CH.

[0074] The bonding pad 180 may include a pad portion 182 and a protrusion portion 184. The pad portion 182 may be disposed on the gate separation structure 170. When viewed in a plan view, the pad portion 182 may have various shapes, such as circular, elliptical, rectangular, square, rhomboid, and hexagonal. When viewed in a plan view, the pad portion 182 may be arranged in various forms along a first direction D1 and a second direction D2, such as matrix, zigzag, and honeycomb. The upper surface of the pad portion 182 may be flush with the upper surface of the interlayer insulating film 190, but is not limited thereto.

[0075] An interlayer insulating film 190 may be disposed on the molded pattern 130 and the gate separation structure 170. The interlayer insulating film 190 may be disposed between adjacent pad portions 182 and may contact the side surfaces of adjacent pad portions 182. The interlayer insulating film 190 may overlap with the pad portions 182 in a first direction D1. The upper surface of the interlayer insulating film 190 and the upper surface of the pad portions 182 may be disposed on the same plane as each other. The interlayer insulating film 190 may include an insulating material.

[0076] The protrusion 184 may protrude from the pad portion 182 toward the bit line BL in a third direction D3. The protrusion 184 may contact the channel structure CH. For example, the protrusion 184 may contact each of the first vertical portion CH_V1 and the second vertical portion CH_V2. A portion of the protrusion 184 may overlap with each of the first word line WL1 and the second word line WL2 in the first direction D1.

[0077] In some embodiments, the protrusion 184 may be disposed between the barrier pattern 150 and the gate insulating film 160. For example, the protrusion 184 may be disposed between the barrier pattern 150 and the gate insulating film 160 disposed on the upper part of the channel structure CH. The protrusion 184 may contact the side surfaces of the barrier pattern 150 and the gate insulating film 160. The barrier pattern 150 may be disposed between the molded pattern 130 and the protrusion 184.

[0078] The bonding pad 180 can be spaced apart from the molded pattern 130 by a barrier pattern 150. The bonding pad 180 can be in no contact with the molded pattern 130. The barrier pattern 150 can prevent hydrogen ions from diffusing from the molded pattern 130 to the bonding pad 180. Therefore, the reliability of the bonding pad 180 can be improved.

[0079] The bonding pad 180 can be made of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x RuO x Or a combination thereof, but not limited to these aspects.

[0080] An etch stop film 210 may be disposed on the bonding pad 180 and the interlayer insulating film 190. The etch stop film 210 may expose the bonding pad 180.

[0081] A capacitor structure CAP can be disposed on the bonding pad 180 and the interlayer insulating film 190. The capacitor structure CAP can store signals received from transistors in the peripheral circuitry of the semiconductor memory device (e.g., row and column decoders, sense amplifiers, etc.). The capacitor structure CAP can be used as a data storage element electrically connected to a transistor. For example, the capacitor structure CAP can store charge under the control of a transistor.

[0082] The capacitor structure CAP may include a lower electrode 222, a dielectric film 224, and an upper electrode 226.

[0083] The lower electrode 222 may be disposed on the bonding pad 180. The lower electrode 222 may be electrically connected to the bonding pad 180. A portion of the lower electrode 222 may be disposed in the etch stop film 210. For example, the lower electrode 222 may extend through the etch stop film 210 and be connected to the bonding pad 180. For example, the lower electrode 222 may extend through the etch stop film 210.

[0084] For example, the lower electrode 222 may include at least one of the following: conductive metal materials (cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), etc.), metal nitrides (titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), etc.), noble metal materials (platinum (Pt), ruthenium (Ru), iridium (Ir), etc.), conductive oxide films (PtO, RuO2, IrO2, SrRuO3 (SRO), (Ba,Sr)RuO3 (BSRO), CaRuO3 (CRO), LSCO, etc.), and metal silicide films. However, the aspects are not limited thereto.

[0085] Although not shown, in some embodiments, at least one support member may be disposed between the lower electrodes 222. The support member may support the lower electrodes 222.

[0086] A dielectric film 224 may be disposed on the lower electrode 222. The dielectric film 224 may extend along the contour of the lower electrode 222. The dielectric film 224 may contact the upper and side surfaces of the lower electrode 222 and the upper surface of the etch stop film 210. For example, the dielectric film 224 may comprise a high dielectric constant material, including silicon oxide, silicon nitride, silicon oxynitride, and metals. Although the dielectric film 224 is shown as a single layer, this is for ease of description only, and the aspects are not limited thereto. Contrary to the illustration, the dielectric film 224 may comprise a multilayer film.

[0087] The upper electrode 226 may be disposed on the dielectric film 224. The upper electrode 226 may contact the dielectric film 224. The upper electrode 226 may fill the empty space between the lower electrodes 222. For example, the upper electrode 226 may include at least one of an elemental semiconductor material film and a compound semiconductor material film. The upper electrode 226 may include doped n-type or p-type impurities.

[0088] Figure 7 This is a diagram illustrating a semiconductor memory device according to an exemplary embodiment of the present disclosure. For reference, Figure 7 It can correspond to Figure 2 A magnified view of region Q1. For ease of description, the main description will be related to... Figures 1 to 6 The configurations described in the text are different.

[0089] refer to Figure 7In a semiconductor memory device according to some embodiments, the upper surface of the blocking pattern 150 may be configured to be lower than the upper surface of the molded pattern 130. For example, the distance H4 from the upper surface of the bit line BL to the upper surface of the blocking pattern 150 may be less than the distance H1 from the upper surface of the bit line BL to the upper surface of the molded pattern 130.

[0090] The upper surface of the blocking pattern 150 can be configured to be higher than the uppermost part of the channel structure CH. For example, the distance H4 from the upper surface of the bit line BL to the upper surface of the blocking pattern 150 can be greater than the distance H2 from the upper surface of the bit line BL to the upper surface of the second vertical portion CH_V2. The outer surface of each of the first vertical portion CH_V1 and the second vertical portion CH_V2 can contact the second side surface 150_SS2 of the blocking pattern 150. The blocking pattern 150 can completely cover the outer surface of each of the first vertical portion CH_V1 and the second vertical portion CH_V2. For example, the blocking pattern 150 can contact the entire outer surface of each of the first vertical portion CH_V1 and the second vertical portion CH_V2. The blocking pattern 150 can block hydrogen ions from diffusing into the first vertical portion CH_V1 and the second vertical portion CH_V2.

[0091] The bonding pad 180 may include a pad portion 182 and a protrusion portion 184. The pad portion 182 may be disposed on the gate separation structure 170. The protrusion portion 184 may protrude from the pad portion 182 toward the bit line BL on a third direction D3. The protrusion portion 184 may be disposed between the molded pattern 130 and the gate insulating film 160 and between the barrier pattern 150 and the gate insulating film 160. From a cross-sectional view, the protrusion portion 184 may have a stepped portion on the barrier pattern 150. The protrusion portion 184 may contact the side surface 130_SS of the molded pattern 130 and the second side surface 150_SS2 of the barrier pattern 150. The protrusion portion 184 may contact the upper surface of the barrier pattern 150 and the side surface of the gate insulating film 160.

[0092] Figure 8 This is a diagram illustrating a semiconductor memory device according to an exemplary embodiment of the present disclosure. For reference, Figure 8 It can correspond to Figure 2 A magnified view of region Q1. For ease of description, the main description will be related to... Figures 1 to 6 The configurations described in the text are different.

[0093] refer to Figure 8In a semiconductor memory device according to some embodiments, the upper surface of the barrier pattern 150 may be disposed on the same plane as the upper surface of the channel structure CH. The upper surface of the channel structure CH may refer to the upper surfaces of the first vertical portion CH_V1 and the second vertical portion CH_V2. For example, the distance H4 from the upper surface of the bit line BL to the upper surface of the barrier pattern 150 may be equal to the distance H2 from the upper surface of the bit line BL to the upper surface of the second vertical portion CH_V2. The barrier pattern 150 may completely cover the outer surface of each of the first vertical portion CH_V1 and the second vertical portion CH_V2. The barrier pattern 150 may prevent hydrogen ions from diffusing into the first vertical portion CH_V1 and the second vertical portion CH_V2.

[0094] The upper surface of the blocking pattern 150 can be set to be lower than the upper surface of the molded pattern 130. For example, the distance H4 from the upper surface of the bit line BL to the upper surface of the blocking pattern 150 can be less than the distance H1 from the upper surface of the bit line BL to the upper surface of the molded pattern 130.

[0095] The bonding pad 180 may include a pad portion 182 and a protrusion portion 184. The pad portion 182 may be disposed on the gate separation structure 170. The protrusion portion 184 may protrude from the pad portion 182 toward the bit line BL on a third direction D3. The protrusion portion 184 may be disposed between the molded pattern 130 and the gate insulating film 160. The protrusion portion 184 may contact the upper surface of the channel structure CH and the upper surface of the barrier pattern 150.

[0096] Figure 9 This is a diagram illustrating a semiconductor memory device according to an exemplary embodiment of the present disclosure. For reference, Figure 9 It can correspond to Figure 2 A magnified view of region Q1. For ease of description, the main description will be related to... Figures 1 to 6 The configurations described in the text are different.

[0097] refer to Figure 9 In a semiconductor memory device according to some embodiments, a gate insulating film 160 may be disposed between the channel structure CH and the first word line WL1 and between the channel structure CH and the second word line WL2.

[0098] Specifically, the gate insulating film 160 may extend along the inner surface of the first vertical portion CH_V1, the upper surface of the horizontal portion CH_H, and the inner surface of the second vertical portion CH_V2. The inner surface of the first vertical portion CH_V1 may be the surface facing the first word line WL1, and the inner surface of the second vertical portion CH_V2 may be the surface facing the second word line WL2. The gate insulating film 160 disposed on the inner surface of the first vertical portion CH_V1 and the gate insulating film 160 disposed on the inner surface of the second vertical portion CH_V2 may be connected to the upper surface of the horizontal portion CH_H. For example, the gate insulating film 160 may contact the upper surface of the horizontal portion CH_H.

[0099] A gate separation structure 170 may be disposed on the first word line WL1, the second word line WL2, and the gate insulating film 160. The gate separation structure 170 may include a gate separation pad film 172, a gate separation fill film 174, and a gate separation capping film 176. The gate separation pad film 172 may be in contact with the gate insulating film 160.

[0100] Figure 10 This is a diagram illustrating a semiconductor memory device according to an exemplary embodiment of the present disclosure. For reference, Figure 10 It can correspond to along Figure 1 The cross-sectional view taken from line AA. For ease of description, the main description will be related to... Figures 1 to 6 The configurations described in the text are different.

[0101] refer to Figure 10 In a semiconductor memory device according to some embodiments, the blocking pattern 150 may include a bottom portion 150_BP disposed between the upper surface of the bit line BL and the molded pattern 130.

[0102] The blocking pattern 150 can be disposed on the upper surface of the bit line BL, the upper surface of the bit line insulating film 125, and the side surfaces 130_SS and lower surface of the molded pattern 130. For example, the bottom portion 150_BP of the blocking pattern 150 can be disposed between the lower surface of the molded pattern 130 and the upper surface of the bit line BL. The bottom portion 150_BP of the blocking pattern 150 can contact the lower surface of the molded pattern 130 and the upper surface of the bit line BL. The blocking patterns 150 disposed on the two side surfaces of the molded pattern 130 can connect to the bottom portion 150_BP. From a cross-sectional perspective, the blocking pattern 150 can have an approximately "U" shape.

[0103] Because of the presence of the bottom portion 150_BP of the blocking pattern 150, the molded pattern 130 can be kept out of contact with the bit line BL. The molded pattern 130 can be spaced apart from the bit line BL on the third direction D3. The bottom portion 150_BP of the blocking pattern 150 can prevent hydrogen ions from diffusing from the molded pattern 130 to the bit line BL.

[0104] Figures 11 to 19 This is a diagram illustrating intermediate stages and used to explain a method for manufacturing a semiconductor memory device according to an exemplary embodiment of this disclosure. For reference, Figure 11 This is a plan view used to illustrate a method for manufacturing semiconductor memory devices. Figures 12 to 19 It can correspond to along Figure 11 The cross-sectional view taken from line AA.

[0105] refer to Figure 11 and Figure 12 Wiring insulating film 110, bit line BL and bit line insulating film 125 can be formed on substrate 100.

[0106] The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may include silicon (Si), silicon germanium (SiGe), indium antimonide (InSb), lead telluride (PbTe), indium arsenide (InAs), indium phosphide (INP), gallium arsenide (GaAs), gallium antimonide (GaSb), etc. However, it is not limited to these aspects.

[0107] In some embodiments, a plurality of transistors connected to the bit line BL may be disposed in the substrate 100. For example, sensing transistors, transmission transistors, driving transistors, etc., may be disposed in the substrate 100. The type of transistor may vary depending on the layout design of the semiconductor memory device. The region in the substrate 100 in which a plurality of transistors are disposed may be referred to as the peripheral circuit region.

[0108] A wiring insulating film 110 can be formed on a substrate 100. Bit lines BL and bit line insulating films 125 can be formed on the wiring insulating film 110. Bit lines BL can extend longitudinally along a first direction D1 on the wiring insulating film 110. Adjacent bit lines BL can be spaced apart from each other in a second direction D2. Bit line insulating films 125 can be disposed between adjacent bit lines BL.

[0109] A pre-molded insulating film 130_P can be formed on the upper surface of the bit line BL and the upper surface of the bit line insulating film 125. The pre-molded insulating film 130_P can cover the bit line BL and the bit line insulating film 125.

[0110] refer to Figure 12 and Figure 13 The pre-molded insulating film 130_P can be etched to form the molded pattern 130.

[0111] Specifically, a hard mask pattern can be formed on a pre-molded insulating film 130_P. The hard mask pattern can expose a portion of the pre-molded insulating film 130_P. The pre-molded insulating film 130_P exposed to the hard mask pattern can be etched to form the molding pattern 130. The molding pattern 130 can extend in a second direction D2. The molding patterns 130 can be configured to be spaced apart from each other in a first direction D1.

[0112] refer to Figure 13 and Figure 14 The pre-blocking pattern 150_P can be formed on the bit line BL, the bit line insulating film, and the molded pattern 130.

[0113] The pre-blocking pattern 150_P can be formed along the side surface 130_SS and top surface of the molded pattern 130, the top surface of the bit line BL, and the top surface of the bit line insulating film (e.g., bit line insulating film 125). The pre-blocking pattern 150_P can cover the top surface of the bit line BL and the top surface of the bit line insulating film (e.g., bit line insulating film 125).

[0114] For example, the pre-blocking pattern 150_P can be formed by any of physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). However, the aspects are not limited to this.

[0115] For example, the pre-blocking pattern 150_P can be formed from or include any one of aluminum oxide, hafnium oxide, zirconium oxide and silicon nitride.

[0116] refer to Figure 14 and Figure 15 A portion of the pre-blocking pattern 150_P can be removed to form the blocking pattern 150.

[0117] Specifically, an anisotropic etching process can be used to remove a portion of the pre-block pattern 150_P. A portion of the pre-block pattern 150_P can be removed to expose the upper surface of the bit line BL and the upper surface of the molded pattern 130. The block pattern 150 can be disposed on the side surface 130_SS of the molded pattern 130. The block pattern 150 can extend along the side surface 130_SS of the molded pattern 130. The block pattern 150 can overlap with the molded pattern 130 in a first direction D1. The block pattern 150 can not overlap with the molded pattern 130 in a third direction D3.

[0118] The blocking pattern 150 can be formed to define a channel trench CH_T. The bottom surface of the channel trench CH_T can be defined as the upper surface of the bit line BL and the upper surface of the bit line insulating film 125. The two side surfaces of the channel trench CH_T can be defined by two blocking patterns 150 facing each other in the first direction D1.

[0119] refer to Figure 15 and Figure 16 The channel structure CH can be formed in the channel groove CH_T. The channel structure CH can be formed along the two sidewalls and the bottom surface of the channel groove CH_T.

[0120] The channel structure CH may include a first vertical portion CH_V1, a second vertical portion CH_V2, and a horizontal portion CH_H. The first vertical portion CH_V1 and the second vertical portion CH_V2 may be formed on the side surface of the molded pattern 130. The horizontal portion CH_H may be formed on the upper surface of the bit line BL.

[0121] A blocking pattern 150 may be disposed between the molded pattern 130 and the channel structure CH. One side surface of the blocking pattern 150 may contact the side surface of the molded pattern 130, and the other side surface of the blocking pattern 150 may contact the vertical portions CH_V1 and CH_V2 of the channel structure CH.

[0122] In some embodiments, the distance from the upper surface of the bit line BL to the upper surface of the blocking pattern 150 may be equal to the distance from the upper surface of the bit line BL to the upper surfaces of the vertical portions CH_V1 and CH_V2.

[0123] refer to Figure 17 The gate insulating film 160 and word line WL can be formed on the channel structure CH.

[0124] The character line WL can extend in the second direction D2. The character line WL can include a first character line WL1 and a second character line WL2. The first character line WL1 can be disposed on a side surface of the first vertical portion CH_V1. The second character line WL2 can be disposed on a side surface of the second vertical portion CH_V2. The first character line WL1 and the second character line WL2 can be spaced apart from each other in the first direction D1.

[0125] The gate insulating film 160 may be disposed between the first word line WL1 and the first vertical portion CH_V1, and between the second word line WL2 and the second vertical portion CH_V2. The gate insulating film 160 may extend along a portion of the inner surface of the first vertical portion CH_V1, the inner surface of the second vertical portion CH_V2, and the upper surface of the horizontal portion CH_H.

[0126] Unlike the illustration, in some embodiments, the gate insulating film 160 may extend along the upper surface of the horizontal portion CH_H. The gate insulating film 160 disposed between the first word line WL1 and the first vertical portion CH_V1 and the gate insulating film 160 disposed between the second word line WL2 and the second vertical portion CH_V2 may be connected to each other.

[0127] Unlike the illustration, in some embodiments, the channel structure CH can be divided into two parts. For example, the horizontal portion CH_H can be divided into two parts. One separate portion of the horizontal portion CH_H can be connected to the first vertical portion CH_V1, and the other separate portion of the horizontal portion CH_H can be connected to the second vertical portion CH_V2. The upper surface of the bit line BL can be exposed between the separate horizontal portions CH_H.

[0128] refer to Figure 18 The gate separation structure 170 can be formed on the channel structure CH, and a portion of the channel structure CH can be removed.

[0129] Specifically, a gate separation structure 170 can be formed on the channel structure CH and word lines WL1 and WL2. The gate separation structure 170 can be disposed in the first direction D1 between the first word line WL1 and the second word line WL2 to separate the first word line WL1 and the second word line WL2. The gate separation structure 170 may include a gate separation pad film 172, a gate separation fill film 174, and a gate separation capping film 176.

[0130] A portion of the first vertical portion CH_V1 and the second vertical portion CH_V2 disposed between the barrier pattern 150 and the gate insulating film 160 can be removed. Therefore, the heights of the first vertical portion CH_V1 and the second vertical portion CH_V2 can be reduced. Height can refer to the length in the third direction D3. The height of the first vertical portion CH_V1 can be equal to the height of the second vertical portion CH_V2. The height of the first vertical portion CH_V1 can be less than the height of the molded pattern 130 and the height of the barrier pattern 150.

[0131] In some embodiments, the uppermost part of the first vertical portion CH_V1 may be set to be lower than the uppermost part of the first word line WL1. In other words, the distance from the upper surface of the bit line BL to the upper surface of the first vertical portion CH_V1 may be less than the distance from the upper surface of the bit line BL to the upper surface of the first word line WL1. However, the aspects are not limited to this.

[0132] Unlike the illustration, in some embodiments, a portion of the channel structure CH may not need to be removed. For example, a portion of the first vertical portion CH_V1 and a portion of the second vertical portion CH_V2 may not need to be removed. The upper surfaces of the blocking pattern 150, the first vertical portion CH_V1, and the second vertical portion CH_V2 may be disposed on the same plane as each other.

[0133] refer to Figure 19 The bonding pad 180 can be formed on the channel structure CH, the barrier pattern 150 and the gate separation structure 170.

[0134] Each bonding pad 180 may include a pad portion 182 and a protrusion portion 184. The pad portion 182 may be formed on the gate separation structure 170. When viewed in a plan view, the pad portion 182 may have various shapes, such as circular, elliptical, rectangular, square, rhomboid, and hexagonal. When viewed in a plan view, multiple pad portions 182 may be arranged in various forms along a first direction D1 and a second direction D2, such as in a matrix, zigzag, or honeycomb pattern.

[0135] An interlayer insulating film 190 may be formed between adjacent pad portions 182. The upper surface of the interlayer insulating film 190 and the upper surface of the pad portion 182 may be disposed on the same plane as each other. The interlayer insulating film 190 may include an insulating material.

[0136] The protrusion 184 may protrude from the pad portion 182 toward the bit line BL in a third direction D3. The protrusion 184 may contact the channel structure CH. For example, the protrusion 184 may contact each of the first vertical portion CH_V1 and the second vertical portion CH_V2. A portion of the protrusion 184 may overlap with each of the first word line WL1 and the second word line WL2 in the first direction D1.

[0137] The protrusion 184 can be disposed between the barrier pattern 150 and the gate insulating film 160 disposed on the upper part of the channel structure CH. The barrier pattern 150 can be disposed between the molded pattern 130 and the protrusion 184. The bonding pad 180 can be spaced apart from the molded pattern 130 by the barrier pattern 150. The bonding pad 180 can be non-contact with the molded pattern 130.

[0138] refer to Figure 2 This can form an etch stop film 210 and a capacitor structure CAP.

[0139] An etch stop film 210 may be disposed on the bonding pad 180 and the interlayer insulating film 190. The etch stop film 210 may expose the bonding pad 180.

[0140] A capacitor structure CAP can be formed on bonding pads 180 and interlayer insulating film 190. The capacitor structure CAP may include a lower electrode 222, a dielectric film 224, and an upper electrode 226. A description of the capacitor structure CAP can be found in the reference... Figures 1 to 6 The descriptions are the same.

[0141] Although certain aspects of this disclosure have been described with reference to the accompanying drawings, those skilled in the art will understand that this disclosure can be implemented in other specific forms without altering its technical concept or essential characteristics. Therefore, it should be understood that the above embodiments are illustrative and non-limiting in all respects.

Claims

1. A semiconductor memory device, comprising: Bit lines are disposed on the substrate and extend in a first direction; A channel structure is disposed on the bit line and extends in a second direction perpendicular to the first direction, wherein the channel structure includes a first vertical portion and a second vertical portion spaced apart from the first vertical portion in the first direction; The character line is positioned between the first vertical portion and the second vertical portion, and extends in the second direction; A gate insulating film is disposed between the first vertical portion and the word line, and between the second vertical portion and the word line; A molded pattern is provided on at least one side of the channel structure; and A blocking pattern is disposed between the molded pattern and the channel structure.

2. The semiconductor memory device according to claim 1, in, The first side surface of the blocking pattern contacts the side surface of the molded pattern, and The second side surface of the blocking pattern, which is opposite to the first side surface, is in contact with the channel structure.

3. The semiconductor memory device according to claim 1, wherein, The distance from the upper surface of the bit line to the upper surface of the molded pattern is equal to the distance from the upper surface of the bit line to the upper surface of the blocking pattern.

4. The semiconductor memory device according to claim 1, wherein, The distance from the upper surface of the bit line to the upper surface of the blocking pattern is equal to or greater than the distance from the upper surface of the bit line to the upper surface of the second vertical portion.

5. The semiconductor memory device according to claim 1, wherein, The molded pattern and the channel structure do not contact each other.

6. The semiconductor memory device according to claim 1, in, The molded pattern extends along the bit line in the second direction, and The blocking pattern covers the side surface of the molded pattern.

7. The semiconductor memory device according to claim 1, further comprising: The bonding pads are located on the first vertical portion. A portion of the bonding pad is in contact with the blocking pattern.

8. The semiconductor memory device according to claim 7, further comprising: A capacitor structure is disposed on the bonding pad and electrically connected to the first vertical portion.

9. The semiconductor memory device according to claim 1, in, The channel structure also includes a horizontal portion connecting the first vertical portion and the second vertical portion, and The horizontal portion extends along the upper surface of the bit line.

10. The semiconductor memory device according to claim 1, in, The character lines include a first character line disposed on one side surface of the first vertical portion and a second character line disposed on one side surface of the second vertical portion, and The semiconductor memory device further includes a gate separation structure disposed between the first word line and the second word line.

11. The semiconductor memory device according to claim 1, wherein, The blocking pattern includes a bottom portion disposed between the molded pattern and the bit line.

12. A semiconductor memory device, comprising: Bit lines are disposed on the substrate and extend in a first direction; The molded pattern is aligned on the bit lines and spaced apart from each other in the first direction, and extends in a second direction perpendicular to the first direction; A blocking pattern is provided on the side surface of each of the molded patterns; The channel groove is defined by the upper surface of the bit line and the blocking pattern; A channel structure is provided in the channel groove; The character line is disposed on the channel structure and extends in the second direction; as well as A gate insulating film is disposed between the channel structure and the word line.

13. The semiconductor memory device according to claim 12, wherein, The upper surface of each of the molded patterns is disposed on the same plane as the upper surface of the blocking pattern.

14. The semiconductor memory device according to claim 12, wherein, The blocking pattern includes any one of aluminum oxide, zirconium oxide, hafnium oxide, or silicon nitride.

15. The semiconductor memory device according to claim 12, in, The channel structure includes a first vertical portion, a second vertical portion spaced apart from the first vertical portion in the first direction, and a horizontal portion connecting the first vertical portion and the second vertical portion. The first vertical portion is in contact with the blocking pattern.

16. The semiconductor memory device according to claim 12, wherein, The blocking pattern and the molding pattern do not overlap each other in a third direction perpendicular to the upper surface of the bit line.

17. The semiconductor memory device according to claim 15, wherein, The distance from the upper surface of the bit line to the upper surface of the second vertical portion is less than the distance from the upper surface of the bit line to the upper surface of the blocking pattern.

18. The semiconductor memory device of claim 12, further comprising: The bonding pads are electrically connected to the channel structure. The bonding pad includes a pad portion and a protrusion portion protruding from the pad portion into the channel structure. The protruding portion is in contact with the blocking pattern and the channel structure.

19. The semiconductor memory device according to claim 18, wherein, The protrusion is disposed between the blocking pattern and the gate insulating film.

20. A semiconductor memory device, comprising: Bit lines are disposed on the substrate and extend in a first direction; A channel structure is disposed on the bit line and extends in a second direction perpendicular to the first direction, wherein the channel structure includes a first vertical portion and a second vertical portion spaced apart from the first vertical portion in the first direction; The character line is positioned between the first vertical portion and the second vertical portion, and extends in the second direction; A gate insulating film is disposed between the first vertical portion and the word line, and between the second vertical portion and the word line; A molded pattern is provided on at least one side of the channel structure; A blocking pattern is disposed between the molded pattern and the channel structure and extends along the side surface of the molded pattern; The bonding pads are disposed on each of the first vertical portion and the second vertical portion; and The capacitor structure is disposed on the bonding pad. Wherein, the distance from the upper surface of the bit line to the upper surface of the blocking pattern is equal to or greater than the distance from the upper surface of the bit line to the upper surface of the second vertical portion.

Images