Semiconductor memory device

Abstract

A semiconductor memory device is disclosed. The semiconductor memory device includes: a bit line on a substrate, where the bit line extends in a first direction, the first direction being parallel to an upper surface of the substrate; a channel structure on the bit line, where the channel structure extends in a second direction, the second direction being parallel to the upper surface of the substrate, and where the channel structure includes a vertical portion extending in a third direction, the third direction being perpendicular to the upper surface of the substrate; a word line on the channel structure; a pad contact layer on the vertical portion of the channel structure; a bonding pad on the pad contact layer; and a capacitor structure electrically connected to the bonding pad, in which the pad contact layer includes a bottom portion on a lower surface of the bonding pad.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0064570, filed on May 17, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor devices. More specifically, this disclosure relates to semiconductor memory devices. Background Technology

[0003] Semiconductor devices are essential components used to control or amplify electrical signals in electronic devices, and various types of semiconductor devices are manufactured. For example, semiconductor memory devices are primarily used for storing and retrieving data, while non-memory semiconductor devices can be used to control or amplify electrical signals. Semiconductor devices play a vital role in a wide range of fields, including computers, communication equipment, and consumer electronics.

[0004] With industrial development, the demands on the performance and functionality of electronic devices are increasing. Therefore, high-performance characteristics of semiconductor devices are required, and to meet these needs, the integration density of semiconductor devices is increasing. Consequently, to improve the integration density of semiconductor devices, transistors with vertical channels have been proposed. Summary of the Invention

[0005] This disclosure provides a semiconductor memory device with improved electrical characteristics and reliability.

[0006] According to some embodiments of this disclosure, by arranging the pad contact layer between the channel structure and the bonding pad, the contact resistance between the pad contact layer and the channel structure, as well as between the pad contact layer and the bonding pad, can be reduced. Therefore, the electrical characteristics and reliability of the semiconductor memory device can be improved.

[0007] According to some embodiments of this disclosure, a semiconductor memory device includes: a substrate; a bit line on the substrate, wherein the bit line extends in a first direction parallel to an upper surface of the substrate; a channel structure on the bit line, wherein the channel structure extends in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction, and wherein the channel structure includes a vertical portion extending upward in a third direction perpendicular to the upper surface of the substrate; a word line on the channel structure; a pad contact layer on the vertical portion of the channel structure; a bonding pad on the pad contact layer; and a capacitor structure electrically connected to the bonding pad, wherein the pad contact layer includes a bottom portion on a lower surface of the bonding pad.

[0008] According to some embodiments of this disclosure, a semiconductor memory device includes: a substrate; a bit line on the substrate, wherein the bit line extends in a first direction parallel to an upper surface of the substrate; a channel structure on the bit line, wherein the channel structure extends in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction, and wherein the channel structure includes a first vertical portion extending upward in a third direction perpendicular to the upper surface of the substrate, and wherein the channel structure further includes a second vertical portion spaced apart from the first vertical portion in the first direction; the first A word line extends on the side surface of the first vertical portion and in a second direction; a second word line extends on the side surface of the second vertical portion and in a second direction; a gate separation structure is located between the first word line and the second word line in a first direction; an interlayer insulating film is located on the gate separation structure; a contact trench is located in the interlayer insulating film, wherein the contact trench is stacked in a third direction with a portion of the channel structure and a portion of the gate separation structure; a pad contact layer is located in the contact trench, wherein the pad contact layer contacts the channel structure; a bonding pad is located on the pad contact layer; and a capacitor structure is electrically connected to the bonding pad.

[0009] According to some embodiments of this disclosure, a semiconductor memory device includes: a substrate; a bit line on the substrate, wherein the bit line extends in a first direction parallel to an upper surface of the substrate; a channel structure on the bit line, wherein the channel structure extends in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction, and wherein the channel structure includes a first vertical portion extending upward in a third direction perpendicular to the upper surface of the substrate, and wherein the channel structure further includes a second vertical portion spaced apart from the first vertical portion in the first direction; and a first word line in the first vertical portion. The second word line extends on the side surface of the second vertical portion and in the second direction; the second word line extends on the side surface of the second vertical portion and in the second direction; the gate separation structure extends between the first word line and the second word line in the first direction; the pad contact layer extends on the upper surface of the first vertical portion; the bonding pad extends on the pad contact layer; and the capacitor structure is electrically connected to the bonding pad, wherein the pad contact layer extends between the bonding pad and the first vertical portion and between the bonding pad and the gate separation structure, wherein the bonding pad includes a first element at a first concentration, wherein the pad contact layer includes a first element at a second concentration, and wherein the second concentration is greater than the first concentration. Attached Figure Description

[0010] The above and other aspects and features of this disclosure will become clearer from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0011] Figure 1 This provides a plan view illustrating a semiconductor memory device according to some embodiments of the present disclosure.

[0012] Figure 2 It is along Figure 1 A cross-sectional view taken from line A-A'.

[0013] Figure 3 It is provided for explanation Figure 2 A magnified view of region Q1.

[0014] Figure 4 It is schematically shown along Figure 3 A diagram showing the concentrations of the first and second elements in line 1.

[0015] Figure 5 It is along Figure 1 The cross-sectional view taken by line B-B'.

[0016] Figure 6 It is along Figure 1 A cross-sectional view taken from line C-C'.

[0017] Figure 7 It is along Figure 1 A cross-sectional view taken from line D-D'.

[0018] Figure 8 This is a diagram illustrating a semiconductor memory device according to some embodiments of the present disclosure.

[0019] Figure 9 This is a diagram illustrating a semiconductor memory device according to some embodiments of the present disclosure.

[0020] Figure 10 This is a diagram illustrating a semiconductor memory device according to some embodiments of the present disclosure.

[0021] Figure 11 This is a diagram illustrating a semiconductor memory device according to some embodiments of the present disclosure.

[0022] Figure 12 This is a diagram illustrating a semiconductor memory device according to some embodiments of the present disclosure.

[0023] Figures 13 to 19 This is a diagram illustrating an intermediate stage of a method for manufacturing a semiconductor memory device according to some embodiments of the present disclosure.

[0024] Figure 20 and Figure 21 This is a diagram illustrating intermediate stages of a method for manufacturing a semiconductor memory device according to some embodiments of the present disclosure.

[0025] Figure 22 and Figure 23This is a diagram illustrating an intermediate stage of a method for manufacturing a semiconductor memory device according to some embodiments of the present disclosure. Detailed Implementation

[0026] In this disclosure, for ease of explanation, spatial relative terms such as “below,” “under,” “lower,” “below,” “above,” and “upper” are used to describe the relationship between one element or feature as shown in the figures and another element or feature. It will be understood that these spatial relative terms are intended to encompass different orientations of the device in use or operation other than those shown in the figures. For example, when the device in the figures can be flipped, an element described as “below,” “below,” or “under other elements” will be oriented “above” the other elements or features. Thus, the example terms “below” and “below” can encompass both “above” and “below” orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly.

[0027] In the following, a semiconductor memory device and a method of manufacturing the same according to some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0028] Figure 1 This provides a plan view illustrating a semiconductor memory device according to some embodiments of the present disclosure. Figure 2 It is along Figure 1 A cross-sectional view taken from line A-A'. Figure 3 It is provided for explanation Figure 2 A magnified view of region Q1. Figure 4 It is a schematic representation of the path along Figure 3 A diagram showing the concentrations of the first and second elements in line 1. Figure 5 It is along Figure 1 The cross-sectional view taken by line B-B'. Figure 6 It is along Figure 1 A cross-sectional view taken from the C-C' line. Figure 7 It is along Figure 1 A cross-sectional view taken from line D-D'. Figure 8 This is a diagram illustrating a semiconductor memory device according to some embodiments of the present disclosure. For reference, the dielectric film 224 and the upper electrode 226 of the capacitor structure CAP are omitted and not shown. Figure 1 As shown in the image.

[0029] Semiconductor memory devices according to some embodiments of this disclosure may include memory cells comprising vertical channel transistors (VCTs). A vertical channel transistor may be defined as a transistor whose channel length extends in a direction perpendicular to the upper surface of the semiconductor substrate (e.g., third direction D3).

[0030] Reference Figures 1 to 8 According to some embodiments, a semiconductor memory device may include: a substrate 100, a wiring insulating film 110, a bit line BL, a channel structure CH, a word line WL, a bit line insulating film 125, a molded pattern 130, a pad (or solder pad) contact layer 140, a gate insulating film 160, a gate separation structure 170, a landing pad (or bonding pad, bonding pad, or bonding pad) 180, an interlayer insulating film 190, and a capacitor structure CAP.

[0031] The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may include: silicon (Si), silicon germanium (SiGe), indium antimonide (InSb), lead telluride (PbTe), indium arsenide (InAs), indium phosphide (InP), gallium arsenide (GaAs), gallium antimonide (GaSb), etc. However, the disclosed aspects are not limited to the above.

[0032] In some embodiments, a plurality of transistors electrically connected to bit line BL may be disposed in substrate 100. For example, sensing transistors, transmission transistors, driving transistors, etc., may be disposed in substrate 100. The type of transistor may vary depending on the layout design of the semiconductor memory device. The region in substrate 100 in which the plurality of transistors are disposed may be referred to as the peripheral circuit region.

[0033] A wiring insulating film 110 may be disposed on the substrate 100. In some embodiments, a wiring structure may be disposed in the wiring insulating film 110. The wiring structure may connect the substrate 100 and the bit line BL (electrically). For example, a plurality of transistors disposed in the substrate 100 may be connected to the bit line BL (electrically) via the wiring structure.

[0034] Bit lines BL can be disposed on the wiring insulating film 110. Bit lines BL can extend on the wiring insulating film 110 in a first direction D1. Adjacent bit lines BL in a plurality of bit lines BL can be spaced apart from each other in a second direction D2. The second direction D2 can be a direction intersecting (i.e., perpendicular to) the first direction D1. In some embodiments, the first direction D1 and the second direction D2 can be parallel to the upper surface of the substrate 100. In some embodiments, the upper surface of the bit line BL and the upper surface of the bit line insulating film 125 can be disposed on the same plane as each other. For example, the upper surface of the bit line BL and the upper surface of the bit line insulating film 125 can be coplanar with each other.

[0035] Bit line BL may include a conductive layer 124 and a contact barrier layer 122. The contact barrier layer 122 may be disposed on the conductive layer 124. For example, the conductive layer 124 may include: doped polysilicon, metals (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, and / or Co), conductive metal nitrides (e.g., TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, and / or RuTiN), conductive metal silicides, and / or conductive metal oxides (e.g., PtO, RuO2, IrO2, SrRuO3 (SRO), (Ba, Sr)RuO3 (BSRO), CoRuO3 (CRO), and / or LaSrCoO (LSCO)), but the disclosed aspects are not limited thereto.

[0036] For example, the contact barrier layer 122 may include: tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and / or two-dimensional (2D) materials.

[0037] In some embodiments, the contact barrier layer 122 and the conductive layer 124 may comprise 2D (semiconductor) materials. For example, the 2D material may comprise a 2D allotrope or a 2D compound, and may include graphene, carbon nanotubes, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), and / or tungsten disulfide (WS2), but the disclosure is not limited thereto. That is, the 2D materials described above are merely examples, and the 2D materials that may be included in the semiconductor memory devices of this disclosure are not limited to those mentioned above.

[0038] The molded pattern 130 can be disposed on the upper surface of the bit line BL and the upper surface of the bit line insulating film 125. The molded pattern 130 can extend in the second direction D2. The molded patterns 130 can be aligned with each other and spaced apart in the first direction D1.

[0039] The molded pattern 130 may include an insulating material. For example, the molded pattern 130 may include silicon oxide, silicon nitride, silicon oxynitride, and / or a low dielectric constant insulating material.

[0040] A channel groove CH_T may be disposed on the upper surface of the bit line BL. The lower surface (e.g., bottom surface) of the channel groove CH_T may be defined as the upper surface of the bit line BL and the upper surface of the bit line insulating film 125. The two side surfaces (opposite side surfaces) of the channel groove CH_T may be defined by side surfaces of the molding pattern 130 that face each other (in the first direction D1 or the second direction D2). The channel groove CH_T may extend in the second direction D2. The channel groove CH_T may be spaced apart from each other in the first direction D1 and / or the second direction D2. The channel groove CH_T may expose the upper surface (a portion of the upper surface) of the bit line BL (and / or a portion of the upper surface of the bit line insulating film 125).

[0041] The channel structure CH can be disposed on the upper surface of the bit line BL. The channel structure CH can be (electrically) connected to the bit line BL. The channel structures CH disposed on a bit line BL can be spaced apart from each other in the first direction D1.

[0042] The channel structure CH can be disposed in the channel groove CH_T. The channel structure CH can be on the side surface and the bottom surface (e.g., the bottom surface) of the channel groove CH_T (extending along the side surface and the bottom surface). Viewed from a cross-sectional perspective, the channel structure CH can have an (approximately) "U" shape.

[0043] The channel structure CH may include: a first vertical section CH_V1, a second vertical section CH_V2, and a horizontal section CH_H.

[0044] Each of the first vertical portion CH_V1 and the second vertical portion CH_V2 may be disposed on a side surface of the molded pattern 130. Each of the first vertical portion CH_V1 and the second vertical portion CH_V2 may extend in a third direction D3. In some embodiments, the third direction D3 may be perpendicular to the upper surface of the substrate 100. For example, the first vertical portion CH_V1 may extend from one end of the horizontal portion CH_H in the third direction D3, and the second vertical portion CH_V2 may extend from the other end of the horizontal portion CH_H in the third direction D3. The first vertical portion CH_V1 and the second vertical portion CH_V2 may be spaced apart from each other in a first direction D1.

[0045] A horizontal portion CH_H may be disposed on the upper surface of the bit line BL (along the upper surface of the bit line BL). The horizontal portion CH_H may connect to the first vertical portion CH_V1 and the second vertical portion CH_V2. In some embodiments, the horizontal portion CH_H, the first vertical portion CH_V1, and the second vertical portion CH_V2 may be connected to each other to form a unitary structure. The unitary structure (e.g., a channel structure CH) may refer to a structure (e.g., a continuum) without visible boundaries between its substructures (e.g., the horizontal portion CH_H, the first vertical portion CH_V1, and the second vertical portion CH_V2). However, the disclosed aspects are not limited to the above. Unlike the example, for example, the horizontal portion CH_H may be separated into two portions. For example, one separated portion of the horizontal portion CH_H may be connected to the first vertical portion CH_V1, and the other separated portion of the horizontal portion CH_H may be connected to the second vertical portion CH_V2. A gate separation structure 170 may be disposed between the separated horizontal portions CH_H.

[0046] The channel structure CH may include, for example, an oxide semiconductor. For example, the oxide semiconductor may include: In x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, Zn x O, Zn x Sn y O, Zn x N y O、Zr x Zn y Sn z O、Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O, Al x Zn y Sn z O、Yb x Ga y Zn z O and / or In x Ga yHowever, the disclosed aspects are not limited thereto. For example, the channel structure CH may include indium gallium zinc oxide (IGZO). The channel structure CH may include a single layer or multiple layers of oxide semiconductors (or multiple oxide semiconductors). The channel structure CH may include amorphous, crystalline, and / or polycrystalline oxide semiconductors.

[0047] In some embodiments, the channel structure CH may have a band gap energy greater than that of silicon. For example, the channel structure CH may have a band gap energy of (approximately) 1.5 eV to 5.6 eV. For example, the channel structure CH may have optimal channel performance when it has a band gap energy of (approximately) 2.0 eV to 4.0 eV. For example, the channel structure CH may be polycrystalline or amorphous, but the disclosed aspects are not limited thereto.

[0048] In some embodiments, the channel structure CH may include a 2D (semiconductor) material. For example, a 2D (semiconductor) material may include graphene, carbon nanotubes, or a combination thereof.

[0049] In some embodiments, the upper surface of the molded pattern 130 and the upper surface of the channel structure CH may be disposed on the same plane as each other. For example, the upper surface of the molded pattern 130 and the upper surface of the channel structure CH may be coplanar with each other. The upper surface of the channel structure CH may represent either the upper surface of the first vertical portion CH_V1 or the upper surface of the second vertical portion CH_V2. In other words, the distance H1 from the upper surface of the bit line BL to the upper surface of the molded pattern 130 may be equal to the distance H2 from the upper surface of the bit line BL to the upper surface of the second vertical portion CH_V2 (or to the upper surface of the first vertical portion CH_V1). However, the disclosed aspects are not limited to the above. For example, the upper surface of the channel structure CH may be set to be lower or higher than the upper surface of the molded pattern 130. Relative vertical and horizontal terms (such as higher and lower) may be relative positions (e.g., distances) from the lower surface of the substrate 100 in a third direction D3. For example, a greater distance from the lower surface of the base 100 can be a higher vertical level. A greater distance from the lower surface of the base 100 can be a lower vertical level.

[0050] Word lines WL may be disposed on the channel structure CH. Word lines WL may intersect with bit lines BL (e.g., overlaying bit lines BL on a third direction D3). Word lines WL may extend in a second direction D2. Word lines WL (a pair of adjacent word lines WL) may include a first word line WL1 and a second word line WL2.

[0051] Each of the first character line WL1 and the second character line WL2 may be disposed on the channel structure CH. Each of the first character line WL1 and the second character line WL2 may be disposed (in the first direction D1) between the first vertical portion CH_V1 and the second vertical portion CH_V2. The first character line WL1 may be disposed on one side of the horizontal portion CH_H and the first vertical portion CH_V1. The second character line WL2 may be disposed on one side of the horizontal portion CH_H and the second vertical portion CH_V2 (for example, on the side of the horizontal portion CH_H in the first direction D1 opposite to the side of the horizontal portion CH_H where the first character line WL1 is disposed). The first character line WL1 and the second character line WL2 may be spaced apart from each other in the first direction D1.

[0052] The width of the first character line WL1 may not be constant in the first direction D1. For example, the portion of the first character line WL1 disposed on the channel structure CH (e.g., the portion of the first character line WL1 overlapping the channel structure CH in the first direction D1) may have a smaller width in the first direction D1 than the portion of the first character line WL1 not disposed on the channel structure CH (e.g., the portion of the first character line WL1 not overlapping the channel structure CH in the first direction D1). That is, a portion of the first character line WL1 disposed between the channel structures CH in the first direction D1 may have a smaller width in the first direction D1 than another portion of the first character line WL1 not disposed between the channel structures CH in the first direction D1. The second character line WL2 may be configured with the same or similar width as the first character line WL1 in the first direction D1. For example, the first character line WL1 and the second character line WL2 may have symmetrical shapes in the first direction D1.

[0053] For example, the word line WL may include: doped polycrystalline silicon, metals (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni and / or Co), conductive metal nitrides (e.g., TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN and / or RuTiN), conductive metal silicides and / or conductive metal oxides (e.g., PtO, RuO2, IrO2, SrRuO3 (SRO), (Ba, Sr)RuO3 (BSRO), CoRuO3 (CRO) and / or LaSrCoO (LSCO)), but the disclosed aspects are not limited thereto. The word line WL may include a single layer of each of the above materials or multiple layers of the above materials.

[0054] In some embodiments, the word line WL may include a 2D semiconductor material. For example, the 2D semiconductor material may include graphene, carbon nanotubes, and / or combinations thereof.

[0055] In some embodiments, the upper surface of the first word line WL1 may be set to be lower than the upper surface of the first vertical portion CH_V1. The upper surface of the second word line WL2 may be set to be lower than the upper surface of the second vertical portion CH_V2. For example, the distance H3 from the upper surface of the bit line BL to the upper surface of the second word line WL2 (or the upper surface of the first word line WL1) may be less than the distance H2 from the upper surface of the bit line BL to the upper surface of the second vertical portion CH_V2 (or the upper surface of the first vertical portion CH_V1).

[0056] A gate insulating film 160 may be disposed between the word line WL and the channel structure CH. For example, the gate insulating film 160 may be disposed between the first word line WL1 and the first vertical portion CH_V1 and between the second word line WL2 and the second vertical portion CH_V2. In some embodiments, the gate insulating film 160 may be disposed on the outer and lower surfaces of the first word line WL1 and the outer and lower surfaces of the second word line WL2. The gate insulating film 160 may be disposed on the horizontal portion CH_H (e.g., in contact with the horizontal portion CH_H). The gate insulating film 160 may extend parallel to the first word line WL1 and the second word line WL2 in a second direction D2. The first word line WL1 and the second word line WL2 may not be in contact with the channel structure CH due to the presence of the gate insulating film 160. For example, the word lines WL (e.g., the first word line WL1 and the second word line WL2) may be spaced apart from the channel structure CH by the gate insulating film 160.

[0057] The gate insulating film 160 may include, for example, silicon oxide, silicon oxynitride, and / or a high dielectric constant material with a dielectric constant higher than that of silicon oxide. The high dielectric constant material may include, for example, metal oxides and / or metal oxynitrides. For example, high dielectric constant materials that can be used as the gate insulating film 160 may include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, and / or Al2O3, but the disclosed aspects are not limited thereto.

[0058] A gate separation structure 170 may be disposed on the bit line BL and the bit line insulating film 125. The gate separation structure 170 may be disposed in the channel trench CH_T. The gate separation structure 170 may be disposed on the channel structure CH. In a semiconductor memory device according to some embodiments, the gate separation structure 170 may contact the channel structure CH. The gate separation structure 170 may be on the horizontal portion CH_H (e.g., may contact the horizontal portion CH_H). The gate separation structure 170 may be spaced apart from the bit line BL on a third-direction D3 (through the channel structure CH).

[0059] A gate separation structure 170 may be disposed between the first word line WL1 and the second word line WL2 to separate the first word line WL1 and the second word line WL2 in a first direction D1. The gate separation structure 170 may extend between the first word line WL1 and the second word line WL2 in a second direction D2.

[0060] The first word line WL1 may be disposed (in the first direction D1) between the gate separation structure 170 and the first vertical portion CH_V1. The second word line WL2 may be disposed (in the first direction D1) between the gate separation structure 170 and the second vertical portion CH_V2.

[0061] The gate separation structure 170 may include a horizontal portion and a protrusion. The horizontal portion of the gate separation structure 170 may extend in a first direction D1. The protrusion of the gate separation structure 170 may protrude from the horizontal portion of the gate separation structure 170 toward the bit line BL in a third direction D3. The protrusion of the gate separation structure 170 may be closer to the bit line BL than the horizontal portion of the gate separation structure 170. The horizontal portion of the gate separation structure 170 may be disposed on the upper surface of the first word line WL1 and the upper surface of the second word line WL2. In some embodiments, the protrusion of the gate separation structure 170 may be between the first word line WL1 and the second word line WL2 in the first direction D1. For example, the horizontal portion of the gate separation structure 170 may be on the protrusion of the gate separation structure 170 and the first word line WL1 and the second word line WL2 (e.g., it may be superimposed on the protrusion of the gate separation structure 170 and the first word line WL1 and the second word line WL2 in the third direction D3). For example, when viewed from a cross-sectional perspective, the gate separation structure 170 may have an (approximately) "T" shape.

[0062] The gate separation structure 170 may include a gate separation pad film 172, a gate separation fill film 174, and a gate separation cap film 176. In some embodiments, the protrusions of the gate separation structure 170 may include the gate separation fill film 174, and the horizontal portion of the gate separation structure 170 may include the gate separation cap film 176. The gate separation pad film 172 may extend along the upper and inner surfaces of the first word line WL1 and the upper and inner surfaces of the second word line WL2. For example, the gate separation pad film 172 may be on the lower and side surfaces of the gate separation fill film 174 and the lower and side surfaces of the gate separation cap film 176. The gate separation pad film 172 may extend along the horizontal portion CH_H of the channel structure CH. The gate separation pad film 172 may be on (e.g., in contact with) the horizontal portion CH_H. The gate separation pad film 172 may extend along the gate insulating film 160, which protrudes further than the upper surface of the first word line WL1 and the upper surface of the second word line WL2 (and is further away from the substrate 100 in the third direction D3). Unlike the example, the gate separation pad film 172 may not extend along the gate insulating film 160, which protrudes further than the upper surface of the first word line WL1 and the upper surface of the second word line WL2 (and is further away from the substrate 100 in the third direction D3).

[0063] A gate separation fill film 174 may be disposed on a gate separation pad film 172. A gate separation cap film 176 may be disposed on a gate separation fill film 174. In some embodiments, the gate separation pad film 172 is disposed on the lower and side surfaces of the gate separation cap film 176 and on the lower and side surfaces of the gate separation fill film 174. The gate separation pad film 172 may be disposed on the upper and inner surfaces of the word line WL. For example, viewed from a cross-sectional perspective, the first word line WL1 and the second word line WL2 may be surrounded by the gate separation pad film 172 and the gate insulating film 160. Each of the gate separation pad film 172, the gate separation fill film 174, and the gate separation cap film 176 may include an insulating material (e.g., may be formed of an insulating material). Unlike the example, the gate separation structure 170 may be a single layer. For example, the gate separation pad film 172, the gate separation fill film 174, and the gate separation cap film 176 may form an integral structure (gate separation structure 170). The horizontal portion and the protruding portion of the gate separation structure 170 can form an integral structure.

[0064] In some embodiments, the upper surface of the gate separation structure 170 may be disposed on the same plane as the upper surface of the molded pattern 130. The upper surface of the gate separation structure 170 may be coplanar with the upper surface of the molded pattern 130. For example, the distance from the upper surface of the bit line BL to the upper surface of the gate separation structure 170 may be equal to the distance from the upper surface of the bit line BL to the upper surface of the molded pattern 130. However, the disclosed aspects are not limited to the above.

[0065] Contact trench 140_T may be disposed on the channel structure CH and the gate separation structure 170. Contact trench 140_T may be disposed on the gate insulating film 160 and the molding pattern 130. Contact trench 140_T may be disposed in the interlayer insulating film 190 (on the channel structure CH, the gate insulating film 160, the gate separation structure 170, and / or the molding pattern 130). The side surface of contact trench 140_T may be defined by the interlayer insulating film 190. The lower surface of contact trench 140_T may expose a portion of the channel structure CH, the gate insulating film 160, and the gate separation structure 170. For example, the lower surface of contact trench 140_T may expose the upper surface of the first vertical portion CH_V1 and the upper surface of the second vertical portion CH_V2. In some embodiments, the lower surface of contact trench 140_T may expose a portion of the molding pattern 130. In some embodiments, the contact trench 140_T may be superimposed on a portion of the channel structure CH and a portion of the gate separation structure 170 on the third-party direction D3.

[0066] A pad contact layer 140 may be disposed in a contact trench 140_T. The pad contact layer 140 may be disposed on the side surface and the lower surface of the contact trench 140_T. The pad contact layer 140 may include a bottom 140_BP and a sidewall 140_SW. The bottom 140_BP of the pad contact layer 140 may be disposed on the lower surface of the contact trench 140_T. For example, the bottom 140_BP may be on the upper surface of the channel structure CH (e.g., the upper surface of the first vertical portion CH_V1 and the upper surface of the second vertical portion CH_V2), the upper surface of the gate insulating film 160, the upper surface of the gate separation structure 170, and / or the upper surface of the molded pattern 130. The sidewall 140_SW of the pad contact layer 140 may be disposed on the side surface of the contact trench 140_T. For example, the sidewall 140_SW may be on the interlayer insulating film 190.

[0067] In some embodiments, the pad contact layer 140 may be conformally disposed. For example, the thickness of the sidewall 140_SW of the pad contact layer 140 in the first direction D1 and the thickness of the bottom 140_BP of the pad contact layer 140 in the third direction D3 may be equal to each other. In some embodiments, the sidewall 140_SW and the bottom 140_BP may form an integral structure. For example, in a cross-sectional view, the pad contact layer 140 may have an (approximately) "U" shape. However, the disclosed aspects are not limited to the above.

[0068] A bonding pad 180 may be disposed on the pad contact layer 140. The bonding pad 180 may contact the pad contact layer 140. The pad contact layer 140 (e.g., bottom 140_BP) may be located on the third direction D3 between the bonding pad 180 and the channel structure CH (e.g., first vertical portion CH_V1 and / or second vertical portion CH_V2). The bonding pad 180 may be electrically connected to the channel structure CH through the pad contact layer 140. The bonding pad 180 may be spaced apart from the gate separation structure 170 on the third direction D3.

[0069] When viewed in a plan view, the bonding pad 180 may have various shapes (e.g., circular, elliptical, rectangular, square, rhomboid, hexagonal, etc.). When viewed in a plan view, the bonding pad 180 may be arranged in various shapes (e.g., matrix shape, sawtooth shape, honeycomb shape, etc.) along the first direction D1 and the second direction D2. The upper surface of the bonding pad 180 may be coplanar with the upper surface of the interlayer insulating film 190, but the disclosed aspects are not limited thereto. The upper surfaces of the bonding pad 180 and the upper surfaces of the interlayer insulating film 190 may be coplanar with each other.

[0070] The sidewall 140_SW of the pad contact layer 140 may be disposed (in the first direction D1) between the bonding pad 180 and the interlayer insulating film 190. The sidewall 140_SW of the pad contact layer 140 may overlap with the interlayer insulating film 190 in the first direction D1. In some embodiments, the sidewall 140_SW of the pad contact layer 140 may surround at least a portion of the side surface 180_SS of the bonding pad 180. For example, as Figure 3 As shown, the sidewalls 140_SW of the pad contact layer 140 can completely surround the side surface 180_SS of the engagement pad 180. As another example, such as... Figure 8 As shown, the sidewall 140_SW of the pad contact layer 140 may surround a portion of the side surface 180_SS of the engagement pad 180. Figure 3 Unlike the diagram shown, a portion of the side surface 180_SS of the bonding pad 180 can contact the interlayer insulating film 190.

[0071] The bottom 140_BP of the pad contact layer 140 may be disposed on the lower surface 180_BS of the mating pad 180. The bottom 140_BP of the pad contact layer 140 may be disposed along the lower surface 180_BS of the mating pad 180. The bottom 140_BP of the pad contact layer 140 may cover the lower surface 180_BS of the mating pad 180 (or overlap with the lower surface 180_BS of the mating pad 180 on a third direction D3). The length of the bottom 140_BP of the pad contact layer 140 in the first direction D1 may be greater than the length of the mating pad 180 in the first direction D1. The length of the bottom 140_BP of the pad contact layer 140 in the first direction D1 may be greater than the length of each of the first vertical portion CH_V1 and the second vertical portion CH_V2 in the first direction D1 (or the width of each of the first vertical portion CH_V1 and the second vertical portion CH_V2).

[0072] A portion of the bottom 140_BP of the pad contact layer 140 may be disposed (on the third direction D3) between the bonding pad 180 and the channel structure CH. The bottom 140_BP of the pad contact layer 140 may contact the channel structure CH. For example, the bottom 140_BP of the pad contact layer 140 may contact the upper surface of the first vertical portion CH_V1 and the upper surface of the second vertical portion CH_V2, respectively.

[0073] A portion of the bottom 140_BP of the pad contact layer 140 may be disposed (on the third direction D3) between the bonding pad 180 and the gate insulating film 160, and (on the third direction D3) between the bonding pad 180 and the gate separation structure 170. In some embodiments, the bottom 140_BP of the pad contact layer 140 may contact the upper surface of the gate insulating film 160 and the upper surface of the molding pattern 130, respectively.

[0074] The bottom 140_BP of the pad contact layer 140 may be superimposed on word lines WL1 and WL2 in the third direction D3. In other words, at least a portion of the bottom 140_BP of the pad contact layer 140 may be disposed (in the third direction D3) between the bonding pad 180 and word lines WL1 and WL2.

[0075] An interlayer insulating film 190 may be disposed on the molded pattern 130 and the gate separation structure 170. The interlayer insulating film 190 may fill the space between adjacent pad contact layers 140 of a plurality of pad contact layers 140. The interlayer insulating film 190 may include an insulating material.

[0076] The pad contact layer 140 may include an oxide semiconductor. For example, the pad contact layer 140 may include indium oxide (InO). In some embodiments, the interface between the pad contact layer 140 and the channel structure CH may not be visible.

[0077] If the bonding pad 180 and the channel structure CH are in direct contact with each other, the contact resistance between the bonding pad 180 and the channel structure CH can increase. However, in a semiconductor memory device according to some embodiments of the present disclosure, a pad contact layer 140 may be disposed between the channel structure CH and the bonding pad 180. Because the pad contact layer 140 contacts each of the channel structure CH and the bonding pad 180, the contact resistance between the pad contact layer 140 and the channel structure CH, and between the pad contact layer 140 and the bonding pad 180, can be reduced. Therefore, the electrical characteristics and reliability of the semiconductor memory device can be improved.

[0078] Bonding pad 180 may include: doped polycrystalline silicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x RuO x And / or combinations thereof (e.g., that may be formed from them), but the disclosed aspects are not limited thereto.

[0079] Reference Figure 4 The concentrations of the first element A1 and the second element A2 included in the bonding pad 180, the pad contact layer 140, and the channel structure CH will be described below. The first element A1 and the second element A2 can be any material other than oxygen.

[0080] The pad contact layer 140 and the channel structure CH may include a first element A1. The bonding pad 180 may not include any amount of the first element A1 or may include a small (insignificant) amount of the first element A1. Although the first element A1 is shown to be included adjacent to the boundary between the bonding pad 180 and the pad contact layer 140 in the bonding pad 180, it should be understood that a small (insignificant) amount of the first element A1 diffuses from the pad contact layer 140 to the bonding pad 180. The concentration of the first element A1 in the pad contact layer 140 may be greater than the concentration of the first element A1 in the channel structure CH. For example, the first element A1 may be indium (In). The term concentration herein may refer to mass concentration, molar concentration, number concentration, volume concentration, atomic concentration, etc.

[0081] The channel structure CH may include a second element A2. The pad contact layer 140 (and the bonding pad 180) may not include any amount of the second element A2 or may include a small (insignificant) amount of the second element A2. Although it is shown that the second element A2 is included in the pad contact layer 140 adjacent to the boundary between the pad contact layer 140 and the channel structure CH, it should be understood that a small (insignificant) amount of the second element A2 diffuses from the channel structure CH into the pad contact layer 140. For example, the second element A2 may include gallium (Ga), zinc (Zn), etc. However, the disclosed aspects are not limited to the above. For example, the second element A2 may also include materials other than indium (In), which is a constituent material of the aforementioned channel structure CH.

[0082] exist Figure 4 The diagram shows that the concentration of the second element A2 in the channel structure CH is greater than the concentration of the first element A1, but this should be understood as an example. The concentrations of the first element A1 and the second element A2 in the channel structure CH can vary depending on the composition ratio of the materials included in the channel structure CH. For example, the concentration of the first element A1 in the channel structure CH can be greater than or equal to the concentration of the second element A2.

[0083] Return to reference Figures 1 to 8 An etch stop film 210 may be disposed on the bonding pad 180 and the interlayer insulating film 190. In some embodiments, the etch stop film 210 may be on the pad contact layer 140. The etch stop film 210 may expose the bonding pad 180 (at least a portion of the bonding pad 180).

[0084] A capacitor structure CAP may be disposed on the bonding pad 180 and the interlayer insulating film 190. In some embodiments, the capacitor structure CAP may be on the pad contact layer 140. The capacitor structure CAP may store signals received from transistors in the peripheral circuitry of a semiconductor memory device (e.g., row decoders and column decoders, sense amplifiers, etc.). The capacitor structure CAP may serve as a data storage element electrically connected to a transistor. For example, the capacitor structure CAP may store charge under the control of a transistor.

[0085] The capacitor structure CAP may include a lower electrode 222, a dielectric film 224, and an upper electrode 226.

[0086] The lower electrode 222 may be disposed on the bonding pad 180. The lower electrode 222 may be electrically connected to the bonding pad 180. A portion of the lower electrode 222 may be disposed in the etch stop film 210. For example, the lower electrode 222 may extend through the etch stop film 210 and be connected to the bonding pad 180.

[0087] For example, the lower electrode 222 may include: a conductive metal material (e.g., cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), etc.), a metal nitride (e.g., titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), etc.), a noble metal material (e.g., platinum (Pt), ruthenium (Ru), iridium (Ir), etc.), a conductive oxide film (e.g., PtO, RuO2, IrO2, SrRuO3 (SRO), (Ba,Sr)RuO3 (BSRO), CoRuO3 (CRO), LaSrCoO (LSCO), etc.), and / or a metal silicide film. However, the disclosed aspects are not limited to the above.

[0088] Although not shown, in some embodiments, at least one support member may be disposed between the lower electrodes 222. The support member may support the lower electrodes 222.

[0089] A dielectric film 224 may be disposed on the lower electrode 222. The dielectric film 224 may extend along the contour of the lower electrode 222. For example, the dielectric film 224 may comprise a high dielectric constant material comprising silicon oxide, silicon nitride, silicon oxynitride, and / or metals. Although the dielectric film 224 is shown as a single film, this is for ease of description only, and the disclosed aspects are not limited thereto. Unlike the example, the dielectric film 224 may comprise multiple films.

[0090] The upper electrode 226 may be disposed on the dielectric film 224. The upper electrode 226 may fill the empty space between the lower electrodes 222. For example, the upper electrode 226 may comprise an elemental semiconductor material film and / or a compound semiconductor material film. The upper electrode 226 may comprise, for example, doped n-type or p-type impurities.

[0091] Figure 9 This is a diagram provided to illustrate a semiconductor memory device according to some embodiments of the present disclosure. For reference, Figure 9 Can be with Figure 2 The enlarged view corresponds to region Q1. For ease of description, the main description will be based on the above references. Figures 1 to 8 The configurations described are different.

[0092] Reference Figure 9 In a semiconductor memory device according to some embodiments, the pad contact layer 140 may include a bottom 140_BP, but may not include... Figure 3 The sidewall 140_SW.

[0093] A pad contact layer 140 may be disposed in a contact groove 140_T. The pad contact layer 140 may be disposed on the lower surface of the contact groove 140_T. The bottom 140_BP of the pad contact layer 140 may be disposed along the lower surface of the contact groove 140_T. A description of the bottom 140_BP of the pad contact layer 140 is provided above. Figures 1 to 8 The descriptions are the same.

[0094] A bonding pad 180 may be disposed on the pad contact layer 140. The lower surface 180_BS of the bonding pad 180 may contact the bottom surface 140_BP of the pad contact layer 140. The length of the bonding pad 180 in the first direction D1 may be the same as (equal to) the length of the pad contact layer 140 in the first direction D1. The side surface 180_SS of the bonding pad 180 may contact the interlayer insulating film 190.

[0095] Figure 10 This is a diagram illustrating a semiconductor memory device according to some embodiments of the present disclosure. Figure 11 This is a diagram provided to illustrate a semiconductor memory device according to some embodiments of the present disclosure. For reference, Figure 10 and Figure 11 Each of them can be combined with Figure 2 The enlarged view corresponds to region Q1. For ease of description, the main description will be related to... Figures 1 to 8 The configurations described in the text are different.

[0096] Reference Figure 10 and Figure 11 In a semiconductor memory device according to some embodiments, the pad contact layer 140 may further include a protrusion 140_PP. For example, as Figure 10 As shown, the pad contact layer 140 may include sidewalls 140_SW, a bottom 140_BP, and protrusions 140_PP. As another example, Figure 11 As shown, the pad contact layer 140 may include a bottom 140_BP and a protrusion 140_PP, but may not include the sidewall 140_SW.

[0097] A protrusion 140_PP of the pad contact layer 140 may protrude from the bottom 140_BP of the pad contact layer 140 toward the channel structure CH in a third direction D3. The protrusion 140_PP may be disposed (in the first direction D1) between the molded pattern 130 and the gate insulating film 160. For example, the protrusion 140_PP may be disposed between the molded pattern 130 and the gate insulating film 160 disposed in the upper part of the channel structure CH.

[0098] The protrusion 140_PP may contact the channel structure CH. For example, the protrusion 140_PP may contact each of the upper surface of the first vertical portion CH_V1 and the upper surface of the second vertical portion CH_V2. A portion of the protrusion 140_PP may overlap with each of the first word line WL1 and the second word line WL2 in the first direction D1.

[0099] The uppermost part of the channel structure CH can be set to be lower than the upper surface of the molded pattern 130. For example, the distance H2 from the upper surface of the bit line BL to the upper surface of the second vertical part CH_V2 (or the upper surface of the first vertical part CH_V1) can be less than the distance H1 from the upper surface of the bit line BL to the upper surface of the molded pattern 130.

[0100] The upper surface of the first word line WL1 can be set to be higher than the upper surface of the first vertical part CH_V1. The upper surface of the second word line WL2 can be set to be higher than the upper surface of the second vertical part CH_V2. For example, the distance H3 from the upper surface of the bit line BL to the upper surface of the second word line WL2 (or the upper surface of the first word line W1) can be greater than the distance H2 from the upper surface of the bit line BL to the upper surface of the second vertical part CH_V2 (or the upper surface of the first vertical part CH_V1).

[0101] A portion of the gate insulating film 160 may protrude more than the upper surface of the first word line WL1 and the upper surface of the second word line WL2 on the third direction D3 (farther from the upper surface of the bit line BL on the third direction D3). For example, the uppermost part of the gate insulating film 160 may be configured to be higher than the upper surface of the first word line WL1 and the upper surface of the second word line WL2.

[0102] Figure 12 This is a diagram provided to illustrate a semiconductor memory device according to some embodiments of the present disclosure. For reference, Figure 12 Can be along Figure 1 The cross-sectional view corresponding to line A-A'. For ease of description, the main description will be... Figures 1 to 8 The configurations described in the text are different.

[0103] Reference Figure 12 The semiconductor memory device according to some embodiments may also include a bit line contact layer 145.

[0104] The bit line contact layer 145 may be disposed on the upper surface of the bit line BL. The bit line contact layer 145 may be disposed between the channel structure CH and the bit line BL. For example, the bit line contact layer 145 may be disposed between the horizontal portion CH_H of the channel structure CH and the contact blocking layer 122 of the bit line BL.

[0105] In some embodiments, bit line contact layer 145 may comprise the same material as pad contact layer 140. For example, bit line contact layer 145 may comprise indium oxide (InO).

[0106] The bit line contact layer 145 can contact the channel structure CH to reduce the contact resistance between the bit line BL and the channel structure CH. Therefore, the electrical characteristics of the semiconductor memory device can be improved.

[0107] Figures 13 to 19 These are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor memory device according to some embodiments of the present disclosure. For reference, Figure 13 It provides a plan view for illustrating the manufacturing method of a semiconductor memory device. Figures 14 to 19 Can be along Figure 13 The cross-sectional view corresponding to line A-A'.

[0108] Reference Figure 13 and Figure 14 Wiring insulating film 110, bit line BL and bit line insulating film 125 can be formed on substrate 100.

[0109] The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may include: silicon (Si), silicon germanium (SiGe), indium antimonide (InSb), lead telluride (PbTe), indium arsenide (InAs), indium phosphide (InP), gallium arsenide (GaAs), gallium antimonide (GaSb), etc. However, the disclosed aspects are not limited to the above.

[0110] In some embodiments, a plurality of transistors electrically connected to bit line BL may be disposed in substrate 100. For example, sensing transistors, transmission transistors, driving transistors, etc., may be disposed in substrate 100. The type of transistor may vary depending on the layout design of the semiconductor memory device. The region in substrate 100 in which a plurality of transistors are disposed may be referred to as the peripheral circuit region.

[0111] A wiring insulating film 110 may be formed on the substrate 100. Bit lines BL and bit line insulating films 125 may be formed on the wiring insulating film 110. The bit lines BL may extend on the wiring insulating film 110 in a first direction D1. Adjacent bit lines BL may be spaced apart from each other in a second direction D2. The bit line insulating films 125 may be disposed between adjacent bit lines BL.

[0112] A pre-molded insulating film 130_P can be formed on the upper surface of bit line BL and bit line insulating film 125. The pre-molded insulating film 130_P can cover bit line BL and bit line insulating film 125 (or be superimposed on bit line BL and bit line insulating film 125 on a third direction D3).

[0113] Reference Figure 14 and Figure 15 A pre-molded insulating film 130_P can be etched to form a molded pattern 130.

[0114] Specifically, a hard mask pattern can be formed on the pre-molded insulating film 130_P. The hard mask pattern can expose a portion of the pre-molded insulating film 130_P. The pre-molded insulating film 130_P exposed from the hard mask pattern can be etched to form the molding pattern 130. The molding pattern 130 can extend in a second direction D2. The molding patterns 130 can be arranged to be spaced apart from each other in a first direction D1.

[0115] A channel or groove CH_T may be formed on the bit line BL. The lower surface of the channel or groove CH_T may be defined as the upper surface of the bit line BL (a portion of the upper surface of the bit line BL) and the upper surface of the bit line insulating film 125 (a portion of the upper surface of the bit line insulating film 125). The two side surfaces of the channel or groove CH_T (e.g., opposing side surfaces in the first direction D1) may be defined by the side surfaces of the molded pattern 130 facing each other in the first direction D1. The channel or groove CH_T may be spaced apart from each other in the first direction D1 and the second direction D2.

[0116] Reference Figure 16 A channel structure CH can be formed in the channel trench CH_T, and a gate insulating film 160 and a word line WL can be formed on the channel structure CH.

[0117] Specifically, the channel structure CH can be formed along the two side surfaces (e.g., opposing side surfaces in the first direction D1) and the lower surface of the channel groove CH_T. The channel structure CH may include a first vertical portion CH_V1, a second vertical portion CH_V2, and a horizontal portion CH_H. The first vertical portion CH_V1 and the second vertical portion CH_V2 can be formed on the side surfaces of the molding pattern 130. The horizontal portion CH_H can be formed on the upper surface of the bit line BL.

[0118] The gate insulating film 160 and word line WL can be formed on the channel structure CH.

[0119] The character line WL may extend in the second direction D2. The character line WL may include a first character line WL1 and a second character line WL2. The first character line WL1 may be disposed on a side surface (inner surface) of the first vertical portion CH_V1. The second character line WL2 may be disposed on a side surface (inner surface) of the second vertical portion CH_V2. The first character line WL1 and the second character line WL2 may be spaced apart from each other in the first direction D1. For example, the inner surfaces of the first vertical portion CH_V1 and the inner surfaces of the second vertical portion CH_V2 may be opposite each other in the first direction D1.

[0120] A gate insulating film 160 may be provided between the first word line WL1 and the first vertical portion CH_V1, and between the second word line WL2 and the second vertical portion CH_V2. The gate insulating film 160 may extend along a portion of the inner surface of the first vertical portion CH_V1, the inner surface of the second vertical portion CH_V2, and the upper surface of the horizontal portion CH_H.

[0121] Unlike the example, in some embodiments, the gate insulating film 160 may extend along the entire upper surface of the horizontal portion CH_H. The gate insulating film 160 disposed between the first word line WL1 and the first vertical portion CH_V1, and the gate insulating film 160 disposed between the second word line WL2 and the second vertical portion CH_V2 may be connected to each other.

[0122] Unlike the example, in some embodiments, the channel structure CH can be separated into two parts. For example, the horizontal portion CH_H can be separated into two parts. One separated portion of the horizontal portion CH_H can be connected to the first vertical portion CH_V1, and the other separated portion of the horizontal portion CH_H can be connected to the second vertical portion CH_V2. The upper surface of the bit line BL can be exposed between the separated horizontal portions CH_H.

[0123] Reference Figure 17 A gate separation structure 170 can be formed on the channel structure CH.

[0124] Specifically, a gate separation structure 170 can be formed on the channel structure CH and word lines WL1 and WL2. The gate separation structure 170 can be disposed between the first word line WL1 and the second word line WL2 to separate the first word line WL1 and the second word line WL2 in the first direction D1. The gate separation structure 170 may include a gate separation pad film 172, a gate separation fill film 174, and a gate separation capping film 176.

[0125] The upper surface of the gate separation structure 170 and the upper surface of the channel structure CH can be disposed on the same plane. The upper surface of the gate separation structure 170 and the upper surface of the channel structure CH can be coplanar. The upper surface of the channel structure CH may include the upper surface of the first vertical portion CH_V1 and the upper surface of the second vertical portion CH_V2.

[0126] Reference Figure 18 An interlayer insulating film 190 may be formed on the molded pattern 130 and the gate separation structure 170, and a first pre-contact layer 140_P1 may be formed (on the interlayer insulating film 190, the gate separation structure 170, the channel structure CH, the molded pattern 130 and / or the gate insulating film 160).

[0127] Specifically, an insulating layer may be formed on the molded pattern 130 and the gate separation structure 170. The insulating layer may cover the molded pattern 130 and the gate separation structure 170 (or be stacked on a third-direction D3 with the molded pattern 130 and the gate separation structure 170). A mask pattern may be formed on the insulating layer. The mask pattern may expose a portion of the insulating layer. The mask pattern may be used as a mask to pattern the insulating layer, and an interlayer insulating film 190 may be formed.

[0128] Contact trenches 140_T may be formed in the interlayer insulating film 190. The contact trenches 140_T may be part of an insulating layer removed by patterning. Side surfaces of the contact trenches 140_T may define the interlayer insulating film 190. The lower surface of the contact trenches 140_T may expose a portion of the channel structure CH, the gate insulating film 160, and the gate separation structure 170. In some embodiments, the lower surface of the contact trenches 140_T may expose a portion of a molded pattern 130.

[0129] A first pre-contact layer 140_P1 may be formed on the interlayer insulating film 190 and the contact trench 140_T. The first pre-contact layer 140_P1 may be formed along the upper surface of the interlayer insulating film 190 and the side and lower surfaces of the contact trench 140_T. In some embodiments, the first pre-contact layer 140_P1 may be formed conformally.

[0130] For example, the first pre-contact layer 140_P1 can be formed by any of physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). However, the disclosed aspects are not limited to the above.

[0131] Reference Figure 18 and Figure 19 A pad contact layer 140 and a bonding pad 180 can be formed in the contact groove 140_T.

[0132] Specifically, the bonding pad 180 may be formed on the first pre-contact layer 140_P1. The upper surface of the bonding pad 180 and a portion of the first pre-contact layer 140_P1 may be removed. For example, a portion of the first pre-contact layer 140_P1 may be removed by a chemical mechanical polishing (CMP) process. However, the disclosed aspects are not limited to the above. In some embodiments, the upper surface of the bonding pad 180 and the upper surface of the interlayer insulating film 190 may be disposed on the same plane as each other. For example, the upper surface of the bonding pad 180 and the upper surface of the interlayer insulating film 190 may be coplanar.

[0133] The pad contact layer 140 may include sidewalls and a bottom. The description of the pad contact layer 140 is consistent with the above reference. Figures 1 to 8 The descriptions are the same.

[0134] Reference Figure 2This can form an etch stop film 210 and a capacitor structure CAP.

[0135] An etch stop film 210 may be provided on the bonding pad 180 and the interlayer insulating film 190. The etch stop film 210 may expose the bonding pad 180 (a portion of the bonding pad 180). In some embodiments, the etch stop film 210 may be on the pad contact layer 140.

[0136] A capacitor structure CAP can be formed on the bonding pad 180 and the interlayer insulating film 190. In some embodiments, the capacitor structure CAP may be on the pad contact layer 140. The capacitor structure CAP may include a lower electrode 222, a dielectric film 224, and an upper electrode 226. A description of the capacitor structure CAP can be found in the above references. Figures 1 to 8 The description of the capacitor structure CAP is the same.

[0137] Figure 20 and Figure 21 These are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor memory device according to some embodiments of the present disclosure. For reference, Figure 20 The method shown above can be referenced. Figures 13 to 17 The manufacturing method that is executed after the described manufacturing method.

[0138] Reference Figure 17 and Figure 20 The second pre-contact layer 140_P2 and the pre-bonding pad 180_P can be sequentially formed on the molded pattern 130, the channel structure CH, and the gate separation structure 170. In some embodiments, the second pre-contact layer 140_P2 and the pre-bonding pad 180_P can be formed on the gate insulating film 160.

[0139] The second pre-contact layer 140_P2 may cover the upper surface of the molded pattern 130, the upper surface of the channel structure CH, and the upper surface of the gate separation structure 170 (or be stacked on the third-direction D3 with the upper surface of the molded pattern 130, the upper surface of the channel structure CH, and the upper surface of the gate separation structure 170). The pre-bonding pad 180_P may cover the upper surface of the second pre-contact layer 140_P2 (or be stacked on the third-direction D3 with the upper surface of the second pre-contact layer 140_P2).

[0140] Reference Figure 20 and Figure 21 The second pre-contact layer 140_P2 and the pre-bonding pad 180_P can be patterned, and an interlayer insulating film 190 can be formed.

[0141] Specifically, a hard mask pattern can be formed on the free bonding pad 180_P. The hard mask pattern can expose a portion of the free bonding pad 180_P. The hard mask pattern can be used as a mask to pattern the pre-bonding pad 180_P and the second pre-contact layer 140_P2. The patterned pre-bonding pad 180_P and the second pre-contact layer 140_P2 can expose the molded pattern 130 (a portion of the molded pattern 130) and the gate separation structure 170 (a portion of the gate separation structure 170).

[0142] An interlayer insulating film 190 may be formed on the (exposed) molded pattern 130 and the gate separation structure 170. The descriptions of the bonding pad 180 and the pad contact layer 140 are consistent with the above references. Figure 9 The descriptions are the same.

[0143] Reference Figure 2 This can form an etch stop film 210 and a capacitor structure CAP.

[0144] Figure 22 and Figure 23 These are diagrams illustrating intermediate stages in a method for manufacturing a semiconductor memory device according to some embodiments of the present disclosure. For reference, Figure 22 The method shown above can be referenced. Figures 13 to 17 The manufacturing method that is executed after the described manufacturing method.

[0145] Reference Figure 17 and Figure 22 This allows for the removal of a portion of the channel structure CH.

[0146] Specifically, a portion of the first vertical portion CH_V1 and the second vertical portion CH_V2 disposed between the molded pattern 130 and the gate insulating film 160 can be removed. Therefore, the heights of the first vertical portion CH_V1 and the second vertical portion CH_V2 can be reduced. The height of the element can represent the length of the element in the third direction D3. The (reduced) height of the first vertical portion CH_V1 can be equal to the (reduced) height of the second vertical portion CH_V2. The height of the first vertical portion CH_V1 (and the height of the second vertical portion CH_V2) can be less than the height of the molded pattern 130.

[0147] In some embodiments, the uppermost part of the first vertical portion CH_V1 (or the second vertical portion CH_V2) may be set lower than the uppermost part of the first word line WL1 (or the uppermost part of the second word line WL2). In other words, the distance from the upper surface of the bit line BL to the upper surface of the first vertical portion CH_V1 (or the second vertical portion CH_V2) may be less than the distance from the upper surface of the bit line BL to the upper surface of the first word line WL1 (or the upper surface of the second word line WL2). However, the disclosed aspects are not limited to the above.

[0148] Reference Figure 22 and Figure 23 An interlayer insulating film 190 can be formed on the molded pattern 130 and the gate separation structure 170, and a third pre-contact layer 140_P3 can be formed (on the interlayer insulating film 190).

[0149] Specifically, an insulating layer may be formed on the molded pattern 130 and the gate separation structure 170. The insulating layer may cover the molded pattern 130 and the gate separation structure 170 (or be stacked on a third-direction D3 with the molded pattern 130 and the gate separation structure 170). A mask pattern may be formed on the insulating layer. The mask pattern may expose a portion of the insulating layer. The mask pattern may be used as a mask to pattern the insulating layer, and an interlayer insulating film 190 may be formed.

[0150] A third pre-contact layer 140_P3 may be formed on the upper surface of the interlayer insulating film 190 and on the portions exposed between the interlayer insulating films 190. The third pre-contact layer 140_P3 may include a protrusion 140_PP. The protrusion 140_PP may be disposed between the molded pattern 130 disposed in the upper part of the channel structure CH and the gate insulating film 160.

[0151] The bonding pad 180 may be formed on the third pre-contact layer 140_P3, and a portion of the third pre-contact layer 140_P3 may be removed to form the pad contact layer 140.

[0152] Reference Figure 2 and Figure 10 This can form an etch stop film 210 and a capacitor structure CAP.

[0153] Although specific aspects of this disclosure have been described with reference to the accompanying drawings, those skilled in the art will understand that this disclosure may be implemented in other specific forms without altering the technical concept or essential features thereof. Therefore, it should be understood that the above embodiments are exemplary in all respects and not restrictive.

Claims

1. A semiconductor memory device, comprising: Base; Bit lines, on a substrate, wherein the bit lines extend in a first direction parallel to the upper surface of the substrate; A channel structure, on the in-situ line, wherein the channel structure extends in a second direction, the second direction being parallel to the upper surface of the substrate and perpendicular to a first direction, and wherein the channel structure includes a vertical portion extending upward in a third direction, the third direction being perpendicular to the upper surface of the substrate. The letter line is on the channel structure; The padding contact layer is located on the vertical part of the channel structure; The mating pad, on the pad contact layer; and The capacitor structure is electrically connected to the bonding pad. The pad contact layer is located at the bottom of the lower surface of the bonding pad.

2. The semiconductor memory device of claim 1, wherein, The length of the bottom of the pad contact layer in the first direction is equal to or greater than the length of the bonding pad in the first direction.

3. The semiconductor memory device of claim 1, wherein, The pad contact layer also includes a sidewall connected to the bottom of the pad contact layer, and The sidewalls of the pad contact layer are on the side surface of the bonding pad.

4. The semiconductor memory device of claim 1, wherein, At least a portion of the bottom of the pad contact layer is in the third direction between the bonding pad and the letter line.

5. The semiconductor memory device of claim 1, wherein, At least a portion of the pad contact layer is stacked with the bonding pad in a first direction.

6. The semiconductor memory device of claim 1, wherein, The pad contact layer also includes a protrusion that extends from the bottom of the pad contact layer into the channel structure.

7. The semiconductor memory device of claim 6, wherein, The protrusion of the pad contact layer overlaps with the letter line in the first direction.

8. The semiconductor memory device of claim 1, wherein, The vertical portion of the channel structure includes: a first vertical portion and a second vertical portion, wherein the second vertical portion is spaced apart from the first vertical portion in a first direction. The character lines include: a first character line and a second character line, wherein the first character line is on the side surface of the first vertical part, and the second character line is on the side surface of the second vertical part. The semiconductor memory device further includes a gate separation structure located between the first word line and the second word line in a first direction.

9. The semiconductor memory device of claim 8, wherein, At least a portion of the bottom of the pad contact layer is in the third-order orientation between the bonding pad and the gate isolation structure.

10. The semiconductor memory device of claim 1, wherein, The bonding pad comprises a first element at a first concentration, the pad contact layer comprises a first element at a second concentration, and the channel structure comprises a first element at a third concentration. The third concentration is greater than the first concentration but less than the second concentration.

11. A semiconductor memory device, comprising: Base; Bit lines, on a substrate, wherein the bit lines extend in a first direction parallel to the upper surface of the substrate; A channel structure, on the in-situ line, wherein the channel structure extends in a second direction, the second direction being parallel to the upper surface of the substrate and perpendicular to a first direction, wherein the channel structure includes a first vertical portion extending upward in a third direction, the third direction being perpendicular to the upper surface of the substrate, and wherein the channel structure also includes a second vertical portion, the second vertical portion being spaced apart from the first vertical portion in the first direction. The first character line extends on the side surface of the first vertical part and in the second direction; The second line extends on the side surface of the second vertical part and in the second direction; A gate separation structure is located between the first word line and the second word line in a first direction; Interlayer insulating film on the gate separation structure; Contact trenches, in an interlayer insulating film, wherein the contact trenches are stacked in a third-order direction with a portion of the channel structure and a portion of the gate separation structure; A pad contact layer is provided in a contact groove, wherein the pad contact layer is in contact with the groove structure. The mating pad, the pad contact layer; and The capacitor structure is electrically connected to the bonding pad.

12. The semiconductor memory device of claim 11, wherein, The length of the pad contact layer in the first direction is greater than the length of the first vertical part of the channel structure in the first direction.

13. The semiconductor memory device of claim 11, wherein, The pad contact layer surrounds at least a portion of the side surface of the bonding pad.

14. The semiconductor memory device of claim 11, wherein, The bottom of the pad contact layer overlaps the lower surface of the bonding pad in a third-sided upward direction.

15. The semiconductor memory device of claim 11, wherein, The bonding pads are spaced apart from the gate separation structure on the third-side upward.

16. The semiconductor memory device of claim 11, wherein, The uppermost part of the pad contact layer is further away from the upper surface of the gate separation structure than the uppermost part of the positioning line in the third direction.

17. The semiconductor memory device of claim 11, wherein, The upper surface of the pad contact layer and the upper surface of the bonding pad are coplanar.

18. The semiconductor memory device of claim 11, further comprising: A gate insulating film is located in a first direction between a first vertical portion of the channel structure and a first word line, wherein a pad contact layer is located on the upper surface of the gate insulating film.

19. The semiconductor memory device of claim 11, wherein, The channel structure also includes: a horizontal section that connects the first vertical section and the second vertical section, and The horizontal portion extends along the upper surface of the bit line.

20. A semiconductor memory device, comprising: Base; Bit lines, on a substrate, wherein the bit lines extend in a first direction parallel to the upper surface of the substrate; A channel structure, on the in-situ line, wherein the channel structure extends in a second direction, the second direction being parallel to the upper surface of the substrate and perpendicular to a first direction, wherein the channel structure includes a first vertical portion extending upward in a third direction, the third direction being perpendicular to the upper surface of the substrate, and wherein the channel structure also includes a second vertical portion, the second vertical portion being spaced apart from the first vertical portion in the first direction. The first character line extends on the side surface of the first vertical part and in the second direction; The second line extends on the side surface of the second vertical part and in the second direction; A gate separation structure is located between the first word line and the second word line in a first direction; A pad contact layer is located on the upper surface of the first vertical section; The mating pad, on the pad contact layer; and The capacitor structure is electrically connected to the bonding pad. The pad contact layer is located between the bonding pad and the first vertical portion, and also between the bonding pad and the gate separation structure. The bonding pad includes a first element at a first concentration. The pad contact layer includes the first element at a second concentration, and The second concentration is greater than the first concentration.

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