Zener diode

Abstract

A Zener diode includes: a PN junction formed in a semiconductor material; and one or more stress initiation regions configured to apply a compressive stress in the PN junction along a current flow direction of the PN junction.

Description

Technical Field

[0001] This disclosure relates to a Zener diode and a method of manufacturing a Zener diode. Background Technology

[0002] A Zener diode is a type of diode designed to reliably allow current to flow "backward" when a certain set reverse voltage (called the Zener voltage) is reached.

[0003] Zener diodes are typically made of two differently doped layers of semiconductor material forming a PN junction. The P-type material has an excess of positive charge carriers (holes), and the N-type material has an excess of electrons. Zener diodes can be fabricated by heavily doping both N-type and P-type semiconductors. Overdoping reduces the depletion width, resulting in a weaker barrier and a lower breakdown voltage.

[0004] Zener diodes can be used to provide a reference voltage for a circuit. Other applications include generating a stable low-power supply rail from a higher voltage and preventing circuit overvoltages, especially electrostatic discharge. Summary of the Invention

[0005] According to a first aspect of this disclosure, a Zener diode is provided, comprising:

[0006] A PN junction, which is formed in a semiconductor material; and

[0007] One or more stress-initiating regions are configured to apply compressive stress in the PN junction along the direction of current flow in the PN junction.

[0008] In one or more embodiments, the PN junction may include an N-type region in contact with the P-type region. The current flow direction may be perpendicular to the interface between the N-type and P-type regions.

[0009] In one or more embodiments, the PN junction may include an N-type region in contact with the P-type region. The one or more stress-inducing regions may include one or more of the following:

[0010] The first stress-initiating region in contact with the P-type region; and

[0011] The second stress-initiating region in contact with the N-type region.

[0012] In one or more embodiments, one or more dimensions of the one or more stress-initiating regions can be selected to control the value of the compressive stress in the PN junction along the current flow direction of the PN junction.

[0013] In one or more embodiments, the Zener diode may include a layered structure, the layered structure comprising:

[0014] The first layer is formed in a semiconductor material;

[0015] The second layer is formed in the semiconductor material between the first layer and the surface of the semiconductor material; and

[0016] A stress-initiating layer is positioned on the surface of the semiconductor material to form one of the one or more stress-initiating regions.

[0017] The first layer and the second layer each include one of the P-type region and the N-type region to form the PN junction.

[0018] In one or more embodiments, the first layer may include a P-type region, and the second layer may include an N-type region. The current flow direction may be perpendicular to the interface between the first and second layers.

[0019] In one or more embodiments, the stress-initiating layer may include a tensile stress layer configured to apply tensile stress to the second layer on one or more axes parallel to the plane of the second layer. The stress-initiating layer may include a tensile stress layer configured to apply tensile stress to the second layer on one or more axes parallel to the plane of the second layer, such that compressive stress is applied along the direction of current flow on an axis perpendicular to the plane of the second layer.

[0020] In one or more embodiments, the stress-initiating layer may include a biaxial tensile stress layer.

[0021] In one or more embodiments, the stress-initiating layer may be indirectly positioned on the surface of the semiconductor material. An oxide layer may be located between the surface of the semiconductor material and the stress-initiating layer.

[0022] In one or more embodiments, the PN junction may be formed between the first stress-initiating region and the second stress-initiating region.

[0023] In one or more embodiments, the PN junction may include an N-type region located adjacent to the P-type region, wherein the interface between the N-type and P-type regions is perpendicular to the top surface of the semiconductor material. The one or more stress-inducing regions may include one or more of the following:

[0024] The first stress-initiating region is adjacent to the P-type region on the side opposite to the N-type region; and

[0025] The second stress-initiating region is adjacent to the N-type region on the side opposite to the P-type region.

[0026] In one or more embodiments, the one or more stress-inducing regions may each include a shallow trench isolation feature.

[0027] In one or more embodiments, the one or more stress-initiating regions may include:

[0028] The first stress-initiating region is adjacent to the P-type region on the side opposite to the N-type region; and

[0029] The second stress-initiating region is adjacent to the N-type region on the side opposite to the P-type region.

[0030] The interval between the first stress-initiating region and the second stress-initiating region is selected to control the value of the compressive stress in the PN junction in the direction of current flow.

[0031] In one or more embodiments, a Zener diode may include:

[0032] The first region, which is formed in the semiconductor material; and

[0033] A second region, formed in the semiconductor material and surrounding the first region, forms a PN junction in the junction plane, wherein the first region and the second region each comprise a different one of a P-type region and an N-type region to form the PN junction.

[0034] The one or more stress-initiating regions include the stress-initiating region surrounding the second region.

[0035] In one or more embodiments, the stress-inducing region may include a shallow trench isolation feature.

[0036] In one or more embodiments, the semiconductor material may include silicon.

[0037] In one or more embodiments, the value of the compressive stress can be between 150 MPa and 200 MPa.

[0038] According to a second aspect of this disclosure, an integrated circuit is provided that includes any of the Zener diodes disclosed herein.

[0039] According to a third aspect of this disclosure, a voltage reference circuit is provided, which includes any Zener diode or integrated circuit disclosed herein.

[0040] According to a fourth aspect of this disclosure, a method for manufacturing a Zener diode is provided, comprising the following steps:

[0041] Provide semiconductor materials;

[0042] Forming a PN junction in a semiconductor material; and

[0043] One or more stress-initiating regions are formed in or on a semiconductor material, wherein the one or more stress-initiating regions are configured to apply compressive stress in the PN junction along the current flow direction of the PN junction.

[0044] While this disclosure allows for various modifications and alternatives, details thereof have been shown by way of example in the drawings and will be described in detail. However, it should be understood that other embodiments besides the specific embodiments described are also possible. All modifications, equivalents, and alternative embodiments falling within the spirit and scope of the appended claims are also covered.

[0045] The above discussion is not intended to represent every example embodiment or every implementation within the scope of the current or future set of technical solutions. The drawings and the following detailed description also illustrate various example embodiments. A more comprehensive understanding of the various example embodiments can be achieved by considering the following detailed description in conjunction with the accompanying drawings. Attached Figure Description

[0046] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, in which:

[0047] Figure 1A An example Zener diode is shown according to an embodiment of the present disclosure;

[0048] Figure 1B A second example Zener diode according to an embodiment of the present disclosure is shown;

[0049] Figure 1C A third example Zener diode according to an embodiment of the present disclosure is shown;

[0050] Figures 2A to 2E An embodiment of the present disclosure is shown for manufacturing Figure 1A The process technology of Zener diodes;

[0051] Figures 3A to 3D An embodiment of the present disclosure is shown for manufacturing Figure 1B The process technology of Zener diodes;

[0052] Figure 4 A method for manufacturing a Zener diode according to an embodiment of the present disclosure is shown;

[0053] Figure 5A The diagram shows the change in breakdown voltage measured in response to compressive stress applied along the current flow direction of the PN junction of a Zener diode.

[0054] Figure 5B The diagram shows the change in breakdown voltage measured in response to tensile stress applied along the current flow direction of the PN junction of a Zener diode; and

[0055] Figure 6 The simulation shows that the Zener breakdown voltage depends on the change in stress along the direction of current flow. Detailed Implementation

[0056] Precision analog circuit systems may require accurate voltage reference circuits. Zener diodes can be a critical component in the operation of Zener reference circuits. Integrated circuit (IC) chips can undergo multiple thermal cycles during verification, altering package stress. The resulting stress accumulation can affect the Zener diode's Zener breakdown voltage and consequently the accuracy of the analog circuit system. One such application of Zener reference circuits is in battery management systems (BMS). BMS may require a cell voltage measurement accuracy of + / -1mV (+ / -0.02%) on a 5V battery cell. However, drift in Zener breakdown voltage due to packaging and aging can be on the order of 0.1%.

[0057] Therefore, a Zener diode design that is unaffected by stress is needed.

[0058] This disclosure provides a Zener diode with built-in compressive stress along the current flow direction, thereby providing sensitivity of the Zener breakdown voltage to reductions in package stress or external stress.

[0059] Figures 1A to 1C An example Zener diode 100 according to a corresponding embodiment of the present disclosure is shown. The figure shows a cross-section of the Zener diode 100. Figure 1C A plan view of the corresponding Zener diode is also shown.

[0060] The Zener diode 100 includes a PN junction 102 formed in a semiconductor material 104, and one or more stress-initiating regions 106-1, 106-2, which are configured to apply compressive stress (indicated by arrow 107) in the PN junction 102 along the current flow direction 108 of the PN junction 102.

[0061] PN junction 102 may include an N-type region 110 in contact with the P-type region 112. Current flow direction 108 is perpendicular to the interface 114 between the N-type region 110 and the P-type region 112 (i.e., PN junction 102). In other words, current flow direction 108 is perpendicular to PN junction 102. Current flow direction 108 is shown as flowing from the P-type region 112 to the N-type region 110 and vice versa, because current flow direction 108 will vary depending on whether PN junction 102 is forward-biased or reverse-biased.

[0062] The one or more stress initiating regions 106-1, 106-2 may include any one or two of the following: (i) a first stress initiating region 106-1 in contact with the P-type region 112; and (ii) a second stress initiating region 106-2 in contact with the N-type region 114. For example, Figure 1A The Zener diode can reverse the positions of the N-type region 110 and the P-type region 112, so that the N-type region 110 comes into contact with the stress-inducing region.

[0063] Semiconductor material 104 may include a semiconductor substrate, such as a semiconductor epitaxial layer.

[0064] Specifically, turn to Figure 1A In a first example, the Zener diode 100 may include a layered structure. In this example, the N-type region 110 includes a first layer formed in the semiconductor material 104, and the P-type region 112 includes a second layer formed in the semiconductor material 104 between the first layer and the surface of the semiconductor material 104. As mentioned herein, the surface of the semiconductor material 104 may refer to the top surface or contact surface of the semiconductor material 104, i.e., as... Figure 1A-1C The top surface shown in each of 2A-2E and 3A-3D. In other examples, N-type region 110 may form a second layer, and P-type region 112 may form a first layer.

[0065] Both the first and second layers extend along orthogonal axes (X, Z) of a plane parallel to the surface of the semiconductor material 104. In other words, the first and second layers extend in a plane parallel to the surface of the semiconductor material 104. The first and second layers form a PN junction 102. Therefore, the current flow direction 108 is on an axis (Y) perpendicular to the interface 114 of the PN junction (the interface between the first and second layers), that is, on an axis (Y) perpendicular to the plane (XZ) of the semiconductor material 104.

[0066] In this example, the one or more stress-initiating regions 106-1, 106-2 include a stress-initiating layer 106-1 located on the surface of the semiconductor material 104. In some examples, the stress-initiating layer 106-1 may be directly located on the surface of the semiconductor material 104 (as shown). In other examples, the stress-initiating layer 106-1 may be indirectly located on the surface of the semiconductor material 104, wherein one or more intervening layers are located between the semiconductor surface and the stress-initiating layer 106-1. In this example, the surface of the second layer forms the surface of the semiconductor material 104, such that the stress-initiating layer 106-1 is located on the second layer.

[0067] The stress-initiating layer 106-1 may include a tensile stress layer 106-1 that applies tensile stress on one or more axes parallel to the (XZ) plane of the second layer / surface of the semiconductor material 104 (as shown by arrow 111 in the figure). In other words, the tensile stress layer 106-1 laterally stretches the PN junction 102 along one or more axes parallel to the (XZ) plane of the second layer / surface (i.e., perpendicular to the current flow direction 108). By stretching the PN junction 102 perpendicular to the current flow direction 108, the tensile stress layer applies compressive stress to the PN junction 102 along the current flow direction 108.

[0068] In this example, the tensile stress layer 106-1 comprises a biaxial tensile stress layer that applies tensile stress along two axes, both parallel to the surface of the semiconductor material 104. The biaxial tensile stress layer may include a silicon nitride layer. The silicon nitride layer subjected to tensile stress can be deposited, for example, by low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition, using reactants comprising dichlorosilane and ammonia. The deposition conditions, reactants, and reactant streams can be adjusted to the desired stress value. In other examples, the tensile stress layer 106-1 may include a uniaxial tensile stress layer that applies tensile stress along a single axis, parallel to the surface of the semiconductor material 104.

[0069] As shown in the figure, a PN junction 102 is formed on the top surface of a semiconductor material 104, wherein an N-type layer 110 is formed in the semiconductor material 104, and a P-type layer 112 is formed on top of the N-type layer 110, wherein the top surface of the P-type layer 112 forms the top surface of the semiconductor material 104. A stress-initiating layer 116-1 is formed / deposited on top of the P-type layer 112 / on the top surface of the semiconductor material 104.

[0070] In some examples, one or more dimensions (thickness / depth, area, width, length, etc.) of the stress-initiating layer / region 106-1 can be selected to control the value of the compressive stress in the PN junction 102 along the current direction 108.

[0071] Figures 2A to 2E It shows the method for forming Figure 1A An example process for Zener diodes. Also exists... Figure 1A-1C In Figures 2A to 2E The characteristics have already been given with the corresponding numbers in the 200 series, and will not need to be described again here.

[0072] exist Figure 2A In the first stage shown, a first N-type region NW 210 and a second N-type region NW2 are formed in semiconductor material 204. In this example, semiconductor material 204 comprises a P-type silicon epitaxial substrate P-epi. The first N-type region 210 corresponds to the N-type region of a PN junction and, in this example, includes an N-well region formed by heavy N-type implantation / doping (e.g., phosphorus implantation). The second N-type region NW2 comprises a lightly doped N-type region for cathode coupling. Different first and second N-type regions can be formed using appropriate known masking and implantation steps.

[0073] exist Figure 2B In the second stage shown, semiconductor material 204 is implanted with a P-type material to form a P-type region PW 212 of a PN junction. In this example, the P-type region includes a P-well region formed by heavy P-type implantation / doping (e.g., boron implantation). As in the first stage, known masking and implantation steps can be used to perform the formation of the P-type region.

[0074] The doping levels of the P-type region 212, the first N-type region 212, and the second N-type region can each include 10. 19 -10 20 cm -3 10 18 -10 19 cm -3 and 10 17 -10 18 cm -3 .

[0075] exist Figure 2C In the third stage shown, a stress-initiating layer 206 is deposited on the surface of semiconductor material 204. In some examples, the stress-initiating layer 206 may be deposited directly on the surface of semiconductor material 204. In other examples, similar to the example shown, the stress-initiating layer 206 may be deposited indirectly on the surface of semiconductor material 204, wherein an intervening layer is positioned between the stress-initiating layer 206 and the top surface of semiconductor material 204. In this example, a silicon oxide layer 216 is deposited on the surface of semiconductor material 204 prior to the deposition of the stress-initiating layer 206. The oxide layer 216 provides a dielectric barrier on top of the doped semiconductor material 204. In this example, the stress-initiating layer 206 comprises a biaxial tensile stress layer, specifically a nitride layer, such as silicon nitride. The stress-initiating layer 206 may comprise a thickness of 10 nm or greater.

[0076] exist Figure 2D In the fourth stage shown, a heavily doped P-type contact region P+ is formed in the P-type region 212, and a heavily doped N-type contact region N+ is formed in the second N-type region NW2. Windows are etched in the silicon oxide layer 216 before implanting the corresponding dopant materials to form the heavily doped contact regions N+ and P+. Known masking and implantation techniques can be used to form the heavily doped contact regions N+ and P+.

[0077] exist Figure 2E In the fifth stage shown, an insulating layer 218 is deposited over semiconductor material 204. In this example, the insulating layer comprises tetraethyl orthosilicate (TEOS). An opening is etched in the TEOS, aligned with the heavily doped contact regions N+ and P+ and extending downwards to its surface. The opening is filled with a metal (e.g., copper, gold, etc.) to form a contact 220 for a Zener diode. In this example, the Zener diode has structural symmetry about an axis along the current flow direction, such that the heavily doped N-type contact region N+, the heavily doped P-type region P+, and the corresponding metal contact 220 form corresponding ring regions and contacts. In other words, there is an anode ring contact coupled to the heavily doped P-type region P+ of the ring structure, and a cathode ring contact coupled to the heavily doped N-type region N+ of the ring structure.

[0078] Return to Figure 1B The image shows a second example Zener diode 100 according to an embodiment of the present disclosure.

[0079] In this example, the PN junction 102 is formed laterally in the semiconductor material 104. The N-type region 110 and the P-type region 112 (in the same layer) are positioned adjacent to each other, and the interface 114 of the PN junction 102 is perpendicular to the top surface of the semiconductor material 104. Therefore, the current flow direction 108 is parallel to the (XZ) plane of the top surface of the semiconductor material 104.

[0080] The one or more stress initiation regions 106-1, 106-2 may include any one or two of the following: a first stress initiation region 106-1 adjacent to the P-type region 112 (and on the opposite side of the N-type region 110); and (ii) a second stress initiation region 106-2 adjacent to the N-type region 110 (and on the opposite side of the P-type region 112). In the example shown, a PN junction 102 is formed between the first stress initiation region 106-1 and the second stress initiation region 106-2.

[0081] In this example, the one or more stress-initiating regions 106-1, 106-2 include shallow trench isolation (STI) features. STIs are features used in ICs to prevent current leakage between adjacent semiconductor device components. They are typically formed by etching trenches in semiconductor material 104 and depositing a dielectric, such as silicon dioxide, into the trenches. Due to the different mechanical properties of oxides and silicon, compressive stress can develop laterally along the current flow direction 108. STI features can exhibit residual thermal stress after the manufacturing process (attributed to the difference in the coefficients of thermal expansion between semiconductor material 104 and the dielectric material). STI features can apply residual thermal stress in a transverse (X-axis) direction parallel to the (XZ) plane of the semiconductor material 104. In this way, STI features can act as stress-initiating regions 106-1, 106-2 and apply compressive stress to the PN junction 102 in the current flow direction 108.

[0082] In some examples, the spacing between the first stress-initiating region 106-1 and the second stress-initiating region 106-2 can be selected to control the value of the compressive stress in the PN junction 102 along the current direction 108. In some examples, one or more dimensions (thickness / depth, area, width, length, etc.) of the one or more stress-initiating regions 106-1, 106-2 can be selected to control the value of the compressive stress in the PN junction 102 along the current direction 108.

[0083] Figure 1C Another example Zener diode 100 according to an embodiment of the present disclosure is shown. The Zener diode has a similar... Figure 1BIt has a transverse structure; however, the structure also has circular symmetry about the vertical (Y) axis, as shown in the plan view in the lower half of the figure.

[0084] The PN junction 102 includes a P-type region 112 surrounded by an N-type region 110 within a junction layer of semiconductor material 104. The junction layer extends in an XZ plane parallel to the top surface of semiconductor material 104. An interface 114 between the P-type region 112 and the N-type region 110 is perpendicular to the surface of semiconductor material 104 and extends circumferentially around the P-type region 112. A current flow direction 108 is perpendicular to the interface 114 and extends radially from the center of the P-type region 112.

[0085] The PN junction 102 is surrounded by a stress-initiating region 106-1. In other words, the N-type region 110 is surrounded by the stress-initiating region 106-1. The stress-initiating region 106-1 applies compressive stress to compress the PN junction 102 radially toward the center of the P-type region 112. In this way, the stress-initiating region 106-1 applies compressive stress in the current flow direction 108.

[0086] In this example, the P-type region 112 is surrounded by the N-type region 110; however, in other examples, the N-type region 110 may be surrounded by the P-type region 112. In some examples, the diode 100 may include a lower level of rotational symmetry than circular symmetry, such as 8th, 6th, 4th, or 2nd order rotational symmetry. For example, when viewed from above, the P-type region 112, the N-type region 110, and the stress-inducing region 106-1 may have a rectangular structure.

[0087] In some examples, one or more of the radius of the P-type region 112, the radius of the N-type region 110, and the radius of the stress-initiating region 106-1 can be selected to control the value of the compressive stress in the current flow direction 108 within the PN junction 102. In some examples, the depth or width of the stress-initiating region 106-1 can be selected to control the value of the compressive stress in the current flow direction 108 within the PN junction 102.

[0088] Figures 3A to 3D Showing the formation Figure 1B and 1C An example process for Zener diodes. Also exists... Figure 1A-1C and Figures 2A-2E In Figures 3A to 3D The characteristics have already been given in the corresponding numbers in the 300 series, and will not need to be described again here.

[0089] exist Figure 3AIn the first stage shown, an N-type region N- is formed in semiconductor material 304. In this example, semiconductor material 304 includes a P-type silicon epitaxial substrate P-epi. A portion of the N-type region N- will form the N-type region 310 of PN junction 302, and in this example includes an N-well region formed by heavy N-type implantation / doping (e.g., phosphorus implantation). The N-type region N- can be formed through suitable known masking and implantation steps.

[0090] exist Figure 2B In the second stage shown, one or more stress-initiating regions 306-1, 306-2 are formed in the semiconductor material 204. In this example, the stress-initiating regions 306-1, 306-2 are formed as STI features by etching trenches in the semiconductor material 304 and depositing a dielectric material such as silicon dioxide in the trenches. The portion of the N-type region between the first stress-initiating region 306-1 and the second stress-initiating region 306-2 forms the N-type region 310 of the PN junction 302.

[0091] exist Figure 3C In the third stage shown, a silicon oxide layer 316 is deposited on the surface of the semiconductor material 304. The oxide layer 316 provides a dielectric barrier on top of the doped semiconductor material 304. After depositing the oxide layer 316, a mask layer 322 is deposited on the oxide layer, such that the portion of the N-type region 310 between the STI regions 306-1 and 306-2 is partially exposed. In this example, the mask layer 322 comprises a nitride layer.

[0092] exist Figure 3D In the fourth stage shown, heavily doped P-type contact regions P+ and N-type contact regions N+ are formed in the N-type region N-. Windows can be etched in the silicon oxide layer 316 before implanting the corresponding dopant materials to form the heavily doped contact regions N+ and P+. Known masking and implantation techniques can be used to form the heavily doped contact regions N+ and P+. The P-type contact region P+ is formed by implanting a P-type dopant between the first STI region 306-1 and the second STI region 306-2 in the N-type region N-. In this manner, a PN junction 302 is formed between the first stress-initiating region 306-1 and the second stress-initiating region 306-2, and the stress-initiating regions apply compressive stress to the PN junction 302 in the current flow direction. A TEOS layer 318 is deposited over the semiconductor material 304, and a metal contact 320 is formed, as described above.

[0093] Figure 4 A method 430 for manufacturing a Zener diode according to an embodiment of the present disclosure is shown.

[0094] The first step 432 includes providing a semiconductor material. The second step 434 includes forming a PN junction in the semiconductor material. The third step 436 includes forming one or more stress-initiating regions in or on the semiconductor material, wherein the one or more stress-initiating regions are configured to apply compressive stress in the PN junction along the current flow direction of the PN junction.

[0095] The theory underlying the improvement in Zener diode performance caused by compressive stress in the direction of current flow is now described.

[0096] Figure 5A and 5B The effects of tensile and compressive stresses on the performance of PN junctions are shown.

[0097] Figure 5A This illustrates the change in breakdown voltage 546 in response to compressive stress applied along the current flow direction 508 of the PN junction 502. The PN junction 502 is formed at the top surface of the semiconductor material 504. A force is then applied to bend the semiconductor material into... This results in tensile stress on the PN junction 502 in the lateral direction (i.e., parallel to the XZ plane of the top surface) (indicated by arrow 511). The tensile lateral stress 511 results in compressive stress 507 in the current flow direction 508 of the PN junction 502.

[0098] The curve shows the increase in measured breakdown voltage 544 caused by this increase in compressive stress 507 along the current flow direction 508.

[0099] Figure 5B This illustrates the change in breakdown voltage 544 in response to tensile stress applied along the current flow direction 508 of the PN junction 502. The PN junction 502 is formed on the top surface of a semiconductor material 504. A force is then applied to bend the semiconductor material into a U-shape. This results in compressive stress on the PN junction in the lateral direction (i.e., the plane parallel to the top surface) (indicated by arrow 540). The compressive lateral stress 540 results in tensile stress 542 in the current flow direction 508 of the PN junction.

[0100] The curve shows the decrease in the measured breakdown voltage 546 caused by this increase in tensile stress along the current flow direction 508.

[0101] Figure 6 This simulation shows that the Zener breakdown voltage depends on the stress variation along the current flow direction. Positive stress values ​​correspond to tensile strain, and negative values ​​correspond to compressive strain.

[0102] The nominal stress-free region 646 of the curve has a relatively steep gradient, which indicates that the nominal stress-free Zener diode experiences a relatively high change in breakdown voltage when subjected to stress along the current flow direction of the PN junction.

[0103] Under a specific compressive stress, the curve reaches a peak region 648 and exhibits lower sensitivity to stress variations caused by external or package stress. The disclosed Zener diode includes one or more stress-inducing regions for applying compressive stress along the current flow direction of the PN junction to move the Zener diode to this region 648 where breakdown voltage sensitivity is reduced. Therefore, the disclosed Zener diode advantageously exhibits reduced breakdown voltage sensitivity to both external and package stresses.

[0104] Figure 6 The shape of the curve can be explained as follows. The breakdown voltage is inversely proportional to the electron tunneling velocity Θ, which can be described by the following equation:

[0105]

[0106] Here, q is the electron charge. ε is the reduced Planck constant, and E is the band gap of the semiconductor material. g The correction factor is given by m*, where m* is the electron tunneling mass. The tunneling rate Θ increases with increasing tunneling mass m* and band gap E. g The mass of the tunnel increases with the increase of the electron mass at the bottom of the conduction band. c Due to the anisotropy in the silicon conduction band, when compressive stress is applied along the direction of current flow, the conduction mass m c Increase, while band gap E g This decreases. This results in a crossover point / peak value of 648 in the curve (at lower compressive stress values, the transfer mass m...). c The increase of E is dominant, and at higher values, the band gap energy E g The reduction is dominant). For tensile stress applied along the direction of current flow, the conduction mass m c and band gap E g Both decrease, thus increasing the tunneling rate and reducing the breakdown voltage.

[0107] In view of the above, the one or more stress-inducing regions of the disclosed Zener diode can be subjected to compressive stress along the current flow direction of the PN junction, such that the breakdown voltage of the Zener diode has reduced sensitivity to stress changes along the current flow direction (relative to the stress-free state). In other words, the value of the compressive stress is selected to reduce the derivative of the breakdown voltage with respect to the compressive stress. In some examples, the compressive stress can be between 150 MPa and 200 MPa.

[0108] This disclosure provides an example Zener diode with built-in compressive stress along the current flow direction, thereby providing reduced sensitivity of the Zener breakdown voltage to package stress or external stress. This contrasts with conventional Zener diode designs, in which stress within the diode and PN junction is typically minimized.

[0109] Unless a specific order is explicitly stated, the instructions and / or flowchart steps in the above diagrams may be performed in any order. Furthermore, those skilled in the art will recognize that while an example set of instructions / methods has been discussed, the material in this specification can be combined in various ways to produce other examples, and should be understood within the context of the detailed description provided herein.

[0110] In some example embodiments, the instruction set / method steps described above are implemented as functional and software instructions embodied in an executable instruction set implemented on a computer or a machine programmed and controlled with said executable instructions. Such instructions are loaded to execute on a processor (e.g., one or more CPUs). The term processor includes a microprocessor, microcontroller, processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing device. A processor may refer to a single component or multiple components.

[0111] In other examples, the instruction sets / methods illustrated herein, along with their associated data and instructions, are stored in appropriate storage devices, which are implemented as one or more non-transient machine- or computer-readable or computer-usable storage media. Such computer-readable or computer-usable storage media are considered part of an article (or article of manufacture). An article or article of manufacture may refer to any single or multiple components manufactured. Non-transient machine- or computer-usable media as defined herein do not include signals, but such media may be capable of receiving and processing information from signals and / or other transient media.

[0112] Example embodiments of the materials discussed in this specification may be implemented, wholly or in part, via a network, computer, or data-based device and / or service. These may include cloud, Internet, intranet, mobile device, desktop computer, processor, lookup table, microcontroller, consumer device, infrastructure, or other enabling devices and services. As may be used herein and in the claims, the following non-exclusive definitions are provided.

[0113] In one example, one or more instructions or steps discussed in this article are automated. The terms automation or automaticity (and similar variations) mean the use of computers and / or mechanical / electrical devices to control the operation of equipment, systems, and / or processes without human intervention, observation, effort, and / or decision-making.

[0114] It should be understood that any components that are alleged to be coupled may be directly or indirectly coupled or connected. In the case of indirect coupling, another component may be positioned between the two components that are alleged to be coupled.

[0115] In this specification, exemplary embodiments have been presented with respect to a selected set of details. However, those skilled in the art will understand that many other exemplary embodiments, including different selected sets of these details, can be practiced. It is intended that the appended claims cover all possible exemplary embodiments.

Claims

1. A Zener diode, characterized in that, include: A PN junction is formed in a semiconductor material; as well as One or more stress-inducing regions are configured to apply compressive stress in the PN junction along the direction of current flow in the PN junction.

2. The Zener diode according to claim 1, characterized in that, The PN junction includes an N-type region in contact with the P-type region, and the one or more stress-initiating regions include one or more of the following: The first stress-initiating region in contact with the P-type region; and The second stress-initiating region that is in contact with the N-type region.

3. The Zener diode according to claim 1 or claim 2, characterized in that, One or more dimensions of the stress initiation regions are selected to control the value of the compressive stress in the PN junction along the direction of current flow in the PN junction.

4. The Zener diode according to any one of the preceding claims, characterized in that, The Zener diode includes a layered structure, the layered structure comprising: The first layer is formed in the semiconductor material; A second layer is formed in the semiconductor material between the first layer and the surface of the semiconductor material; and A stress-initiating layer is positioned on the surface of the semiconductor material to form one of the one or more stress-initiating regions. The first layer and the second layer each include one of the P-type region and the N-type region to form the PN junction.

5. The Zener diode according to claim 4, characterized in that, The stress-initiating layer includes a tensile stress layer configured to apply tensile stress to the second layer on one or more axes parallel to the plane of the second layer.

6. The Zener diode according to claim 5, characterized in that, The stress initiation layer includes a biaxial tensile stress layer.

7. The Zener diode according to any one of claims 4 to 6, characterized in that, The stress-initiating layer is indirectly located on the surface of the semiconductor material, and the oxide layer is located between the surface of the semiconductor material and the stress-initiating layer.

8. The Zener diode according to any one of claims 1 to 3, characterized in that, The PN junction includes an N-type region located adjacent to the P-type region, wherein the interface between the N-type region and the P-type region is perpendicular to the top surface of the semiconductor material, and wherein the one or more stress-initiating regions include one or more of the following: A first stress-initiating region, which is adjacent to the P-type region on the side opposite to the N-type region; and The second stress-initiating region is adjacent to the N-type region on the side opposite to the P-type region.

9. An integrated circuit, characterized in that, Including the Zener diode as described in any of the preceding claims.

10. A method for manufacturing a Zener diode, characterized in that, Includes the following steps: Provide semiconductor materials; A PN junction is formed in the semiconductor material; as well as One or more stress-inducing regions are formed in or on the semiconductor material, wherein the one or more stress-inducing regions are configured to apply compressive stress to the PN junction along the current flow direction of the PN junction.

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