IGBT (Insulated Gate Bipolar Translator) device with split gate structure and preparation method

Abstract

The invention discloses an IGBT device with a split gate structure and a preparation method. Relates to the technical field of semiconductors. A grid electrode and an emitting electrode which are vertically arranged at an interval are arranged in a dielectric layer; the cross section width of the grid is smaller than that of the emitter; a split gate structure is realized by dividing a gate oxide layer in a trench into an upper half gate and a lower half emitter. The structure reduces the gate-oxide electric field and improves the reliability; the emitter is equivalent to an electric field shielding layer formed at the lower half part of the groove, so that the stress of a gate oxide layer is effectively reduced, and gate-oxide breakdown is avoided. When no split gate exists, an electric field at the bottom of the groove may induce a bottom MOS channel, and electric leakage or failure is caused. The split gate structure isolates the bottom of the groove, is no longer controlled by gate voltage, only allows the side wall to form a channel, and improves the off-state electric leakage control capability. And the shield gate also reduces the coupling capacitance (Miller capacitance Crss) of the gate-collector, so that the controllability of dv / dt is improved. As the Miller capacitance is reduced, the grid charge Qg in the switching process is reduced, the loss is reduced, and the EMI is lower.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an IGBT device with a split-gate structure and its fabrication method. Background Technology

[0002] An Insulated Gate Bipolar Transistor (IGBT) is a device composed of a MOS transistor and a bipolar transistor. Its input electrode is a MOS transistor, and its output electrode is a PNP transistor. It combines the advantages of both devices, possessing the low drive power and fast switching speed of MOS transistors, and the low saturation voltage and large capacitance of bipolar transistors. It has been increasingly widely used in modern power electronics technology, especially in high-frequency, high-power transistor applications.

[0003] Currently, trench IGBTs replace the traditional planar structure by embedding the gate inside the silicon wafer to form a vertical channel. Their main characteristics include: Vertical channel: The gate is embedded in the silicon wafer to form a vertical conductive channel.

[0004] High cell density: The trench structure increases cell density and reduces on-resistance.

[0005] Optimized electric field distribution: Improved electric field distribution and enhanced breakdown voltage.

[0006] To reduce the on-state voltage of IGBT devices, trench structures generally require deeper trenches and shorter trench spacing. Trench etching and gate oxidation demand extremely high process precision, inevitably increasing manufacturing complexity. Furthermore, further reducing the trench spacing (to less than 1 micrometer) presents significant challenges in both process technology and device reliability. For example, photolithography and etching require high precision, resulting in high costs and a sharp increase in process complexity; the uniformity of oxide layer growth on the trench sidewalls is difficult to control; short-circuit withstand capability (SCSOA) decreases; gate reliability degrades, and the time-to-delay gate oxide breakdown (TDDB) lifetime is shortened under high electric fields. These process and reliability challenges represent the current bottleneck for achieving nanometer-scale (<1 μm) trench spacing in trench-type IGBTs. Summary of the Invention

[0007] To address the above problems, this invention provides an IGBT device with a split-gate structure and its fabrication method that achieves nanoscale trench spacing (<1μm), reduces on-state voltage drop Vce(sat), and enhances short-circuit withstand capability (SCSOA).

[0008] The technical solution of this invention is: An IGBT device with a split gate structure includes, from bottom to top, a collector metal layer, a P-region one, an N-type buffer zone, an N-type drift region, a P-region two, multiple N+ regions, and multiple dielectric layers; The dielectric layer contains a gate layer extending to the N-type drift region; the gate layer has a narrow top and wide bottom structure, and an arc-shaped bottom structure. The second P region is provided with multiple downwardly extending P+ regions; there is a gap between the bottom surface of the P+ region and the bottom surface of the second P region, and the top corner is connected to the corresponding N+ region; The dielectric layer has an emitter metal layer connected to the P+ region at the top and a P-shield at the bottom.

[0009] Specifically, the dielectric layer includes a first dielectric layer and a silicon dioxide layer; The silicon dioxide layer is wrapped around the gate layer.

[0010] A method for fabricating an IGBT device with a split-gate structure includes the following steps: Step 1: Provide an N-type drift zone; Step 2: Etch the trench structure of the IGBT using an etching process; Step 3: Using a polysilicon deposition process, polysilicon, photoresist, or organic materials are implanted into the trenches and surfaces at high temperatures; Step 4: Etch the polysilicon, photoresist, or organic material within the trench using an etching process; Step 5: Grow a layer of silicon dioxide on the trench; Step 6: Completely etch the remaining polysilicon in the trench using an etching process; Step 7: Using an etching process, etch the sidewalls and bottom of the trench without an oxide layer, designing the trench as a narrow-at-the-top and wide-at-the-bottom structure, dividing the trench into an upper trench and a lower trench; Step 8: Ion implantation is performed at the bottom of the trench to form a P-type doped region; Step 9: Grow silica in the trench; Step 10: Inject polycrystalline silicon into the trench. Step 11: Etch the polysilicon at the trench opening; Step 12: Grow silicon dioxide on the polycrystalline silicon within the trench; Step 13: Deposit polycrystalline silicon in the trench; Step Fourteen: Form P-regions and multiple N+ regions through an injection process; Step 15: Deposit medium layer; Step 16: Photolithography defines the location of the vias. After dry etching through the ILD, silicon is etched and P+ ion implantation is performed at the openings. Step 17: Deposit a metal layer on the front side; perform thinning, N-type buffer doping, P-region formation, and collector metal fabrication processes on the back side.

[0011] Specifically, in step two, a trench with a depth of 2-5 micrometers is etched using an etching process.

[0012] Specifically, in step four, the trenches and surface polysilicon are etched to a depth of 2-3 micrometers using an etching process.

[0013] Specifically, in step five, a gate oxide layer with a thickness of 10-50 nanometers is grown on the trench.

[0014] Specifically, in step seven, the cross-sectional width of the lower trench is 1.2 micrometers to 1.5 micrometers.

[0015] Specifically, in step sixteen, the silicon is etched again to a depth of 0.2-0.4 micrometers.

[0016] Specifically, in step seventeen, a 4-5 μm AlCu metal layer is deposited on the front side.

[0017] Specifically, in step seventeen, the current collector metal includes Ti / TiN, Al / AlSiCu, or Ni / Ag / Au.

[0018] This invention features a gate and emitter spaced vertically within the dielectric layer; the gate cross-sectional width is smaller than the emitter cross-sectional width; a split-gate structure is achieved by dividing the gate oxide layer in the trench into an upper gate and a lower emitter. This structure reduces the gate oxide electric field and improves reliability; the emitter effectively forms an electric field shielding layer in the lower half of the trench, effectively reducing gate oxide stress and preventing gate oxide breakdown. Without a split gate, the electric field at the bottom of the trench may induce a "bottom MOS channel," leading to leakage or failure. The split-gate structure isolates the bottom of the trench, no longer subject to gate voltage control, allowing only the sidewalls to form channels, thus improving off-state leakage control capability. The shielded gate also reduces the gate-collector coupling capacitance (Miller capacitance Crss), thereby improving dv / dt controllability. Because the Miller capacitance is reduced, the gate charge Qg decreases during switching, increasing switching speed, reducing losses, and lowering EMI. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the cross-sectional structure of the N-type silicon substrate of the present invention. Figure 2 This is a schematic diagram of the cross-sectional structure in step two; Figure 3 This is a schematic diagram of the cross-sectional structure of polycrystalline silicon with trench and surface-implanted n-type doped silicon. Figure 4 This is a schematic diagram of the cross-sectional structure of the polysilicon section after etching within the trench; Figure 5 This is a schematic diagram of the cross-sectional structure of the gate oxide layer grown on the sidewall of the trench; Figure 6 This is a schematic diagram of the cross-sectional structure of the remaining polysilicon after etching within the trench; Figure 7 This is a schematic diagram of the cross-sectional structure after etching the bottom of the trench; Figure 8 This is a schematic diagram of the cross-sectional structure of the P-shield; Figure 9 This is a schematic diagram of the cross-sectional structure of the second silica growth. Figure 10 This is a schematic diagram of the cross-sectional structure of the second polycrystalline silicon deposition. Figure 11 This is a schematic diagram of the cross-sectional structure after polysilicon etching in step eleven; Figure 12 This is a schematic diagram of the cross-sectional structure after silicon dioxide growth in step twelve; Figure 13 This is a schematic diagram of the cross-sectional structure after polycrystalline silicon deposition in step thirteen; Figure 14 This is a schematic diagram of the cross-sectional structure of the P-region and N+ region formed by injection in step fourteen; Figure 15 This is a schematic diagram of the cross-sectional structure of the dielectric layer deposited on the wafer surface; Figure 16 This is a schematic diagram of the cross-sectional structure after ion implantation of P+ in step sixteen. Figure 17 This is a schematic diagram of the cross-sectional structure after the deposition of the ALCu metal layer; Figure 18 This is a schematic diagram of the cross-sectional structure after the back-side fabrication process; Figure 19 This is a graph showing the relationship between different mesa spacings and IGBT conduction losses; In the diagram, 1 represents the collector metal layer, 200 represents P-region 1, 300 represents the N-type buffer zone, 400 represents the N-type drift region, 500 represents P-region 2, 600 represents the N+ region, 700 represents the dielectric layer, 710 represents the silicon dioxide layer, 810 represents the emitter, 820 represents the gate, 900 represents the P+ region, A00 represents the emitter metal layer, and B00 represents the P-shield. Detailed Implementation

[0020] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0021] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0022] The following is for reference. Figure 1-19 Describe the present invention; The IGBT device of this invention includes a gate trench that is narrow at the top and wide at the bottom located within an n-drift semiconductor layer; the mesa region between the trenches achieves the opposite structure, i.e., a design that is wide at the top and narrow at the bottom. Existing process flows are utilized for trench etching and gate oxidation to achieve nanometer-level ultra-fine mesa region process precision.

[0023] A method for fabricating an IGBT device with a split-gate structure includes the following steps: Step 1: As Figure 1 As shown, an N-type drift region is provided; select an appropriate resistivity. Step Two: As Figure 2 As shown, the trench structure of the IGBT is etched using an etching process, with a depth of 2-5 micrometers; Step 3: As Figure 3 As shown, polysilicon, photoresist, or organic materials are injected into trenches and surfaces at high temperatures through a deposition process.

[0024] Step Four: As Figure 4 As shown, polysilicon, photoresist or organic matter on the trench is etched by an etching process. For example, if polysilicon is deposited, the depth of polysilicon in the trench after etching is 2-3 micrometers. Organic materials include polymer-type fillers, specifically as follows: 1. Spin-on materials (SOG / SOD for short); 2. SOG (Spin-On Glass); 3. SOD (Spin-On Dielectric); 4. Polyimide; 5. BCB (Benzocyclobutene); Step 5: As Figure 5 As shown, a gate oxide layer with a thickness of 10-50 nanometers is grown on the trench, also known as the first silicon dioxide layer; Step Six: As Figure 6 As shown, the remaining polysilicon, photoresist, or organic matter in the trench is completely etched away using an etching process; Step Seven: As Figure 7 As shown, the sidewalls and bottom of the trench without an oxide layer are etched using an etching process. The trench is designed with a narrow top and wide bottom structure, i.e., an upper trench and a lower trench. The lateral cross-sectional width of the lower trench is greater than that of the upper trench. The bottom of the lower trench adopts an arc-shaped structure design to alleviate the problem of excessive electric field concentration at the bottom (right angles are more prone to breakdown), thereby improving device reliability and reducing gate oxide stress. The mesa region between adjacent trenches is designed to be wider at the top and narrower at the bottom. By reducing the mesa region (the area between trenches), the trench density is increased, carrier control is strengthened, thereby reducing the on-state voltage drop and increasing the current density.

[0025] Specifically, the cross-sectional width of the upper trench is typically 1 micrometer, while the cross-sectional width of the lower trench is between 1.2 and 1.5 micrometers. Widening the lower trench can reduce the mesa region, increase carrier control, and lower the IGBT's on-state voltage.

[0026] The height of the upper trench needs to meet the design length of the trench, generally not less than 1 micrometer; the total trench height is 4-6 micrometers, and the lower trench height is equal to the total height minus the upper trench height. During the etching process, SF6, O2, and / or Ar gases are introduced.

[0027] Step 8: As Figure 8 As shown, ion implantation is performed at the bottom of the trench to form a P-type doped region (P-shield) B00; Step Nine: As Figure 9 As shown, a second silicon dioxide layer with a thickness adapted to the threshold voltage is grown using the SACVD process. Step 10: As Figure 10 As shown, the second polysilicon deposition involves high-temperature implantation of n-type doped polysilicon into the trench and on the surface of the N-type drift region, followed by CMP polishing of the polysilicon to remove excess polysilicon and planarize the surface; the high temperature is 520-560 degrees Celsius. Step 11: Etch the polysilicon at the trench using an etching process, such as... Figure 11 As shown; Step 12: As Figure 12 As shown, a third silicon dioxide layer is grown on polycrystalline silicon using the SACVD process; Step Thirteen: Third polycrystalline silicon deposition, such as Figure 13 As shown, n-type doped polysilicon is implanted at high temperature in the trench and on the surface of the N-type drift region; after implantation, excess silicon dioxide and polysilicon on the device surface are removed. Step Fourteen: A P-region (Pbase) is formed on the N-type drift region through injection, and multiple N+ regions are formed above the P-region through injection, such as... Figure 14 As shown; Step Fifteen: As Figure 15 As shown, a dielectric layer is deposited on the wafer surface (the material of the ILD can be an insulating material such as TEOS or BPSG), and then the surface is planarized by chemical mechanical polishing (CMP) or BPSG reflow. Step Sixteen: Photolithography defines the location of the vias. After dry etching through the ILD, silicon is etched (0.2µm to 0.5µm), and P+ ion implantation is performed at the openings, such as... Figure 16 As shown; Step 17: Deposit fill and etch back to form ohmic contact holes; deposit an ALCu metal layer on the front side, such as... Figure 17 As shown; Step 18: Backside thinning, N-type buffer doping, P-region formation, and collector metal fabrication processes are performed, such as... Figure 18 As shown.

[0028] Specifically, the P-region (P-collector) is formed by back-side implantation; after laser annealing, the back-side collector metal of the IGBT is formed. The metal material (Ti / TiN, Al / AlSiCu, Ni / Ag / Au can be a combination of various types, where " / " indicates a relationship between them) is used.

[0029] Based on the existing mature 1.6-micron process platform, this invention optimizes several key process steps to achieve a device structure with submicron (<1 μm) trench spacing without adding new layout design or relying on more precise photolithography and etching equipment.

[0030] Etching process optimization: By controlling the difference in etching rates between polysilicon and silicon dioxide, the etching rate ratio of silicon dioxide to polysilicon in this case is greater than 1:30, thereby achieving controllable adjustment of the trench morphology.

[0031] Double oxidation process: The process employs two silica growth processes, one for interface passivation and the other for structure control, which significantly improves the morphological accuracy and uniformity of the trench processing.

[0032] Fine etching at the bottom of the trench: By precisely controlling the silicon etching time, the trench depth and bottom profile can be effectively adjusted to avoid structural defects caused by over-etching or under-etching.

[0033] The above steps, through synergistic optimization, enable nanometer-level precision control of trench linewidth and spacing, achieving mass production feasibility for submicron trench spacing without relying on advanced photolithography. Based on the working principle of IGBTs, the electric field distribution at the bottom of the trench is significantly enhanced due to the reduction in geometric scale, thereby triggering the Injection Enhancement Effect (IE). This effect manifests as enhanced hole injection capability in the adjacent region of the trench, resulting in a higher minority carrier concentration in the drift region, reducing the equivalent resistance, and significantly reducing the on-state voltage drop Vce(sat). The optimized device exhibits significant improvement in conduction loss across the rated current range (approximately 0.5–3.0 times the rated current). On the other hand, the structural design of this invention maintains consistency with the conventional 1.6-micron process in the upper half of the trench, with no changes to the threshold voltage, P-Base junction depth, and doping concentration, thus avoiding negative issues such as channel length modulation (CIBL) effect and decreased short-circuit capability that are easily caused in conventional nanoscale trench designs. Conversely, the new process and structure improve the short-circuit withstand capability (SCSOA) of the device, significantly enhancing overall performance and reliability. The process optimization method proposed in this invention is particularly suitable for high-voltage, high-power-density IGBT devices, and can effectively promote the development of new energy power generation, electric vehicles, and high-efficiency power modules.

[0034] Figure 19 This diagram illustrates the relationship between different mesa spacings and IGBT conduction losses. The horizontal axis represents the mesa spacing, and the vertical axis represents the IGBT on-state voltage drop. Figure 19 It can be seen that reducing the mesa spacing can reduce the on-state voltage drop. They are linearly related.

[0035] The design of this invention takes into account electric field uniformity, process manufacturability, parasitic capacitance optimization and current distribution balance, thereby improving device reliability, yield and switching performance; the electric field distribution of IGBT is more uniform, reducing the risk of breakdown, improving current distribution and enhancing short circuit and avalanche capability.

[0036] An IGBT device with a split gate structure includes, from bottom to top, a collector metal layer 100, a P-region 200, an N-type buffer zone 300, an N-type drift region 400, a P-region 500, multiple N+ regions 600, and multiple dielectric layers 700. The dielectric layer 700 is provided with a gate 820 and an emitter 810 arranged at an upper and lower interval; the cross-sectional width of the gate 820 is smaller than the cross-sectional width of the emitter 810. This device effectively reduces the stringent requirements for process precision by optimizing the gate layer structure design. The gate layer (including gate 820 and emitter 810) adopts a "narrow top and wide bottom structure with an arc-shaped bottom." This structure achieves excellent performance without relying on extreme nanoscale trench spacing reduction. On the one hand, it reduces the difficulty of controlling minute dimensions during photolithography and etching, and reduces the scrap rate caused by pursuing high precision. On the other hand, the arc-shaped bottom design avoids the edge damage and uneven etching problems that are prone to occur during etching in traditional right-angle bottom structures. It also reduces the difficulty of controlling the uniformity of the oxide layer growth on the trench sidewalls during gate oxidation, reduces process debugging costs and production cycle, and enables stable production of the device with lower process complexity, breaking through the process bottleneck of nanoscale trench spacing.

[0037] Meanwhile, the narrow-at-the-top and wide-at-the-bottom structure of the gate layer disperses the electric field intensity in the gate region, avoiding the local electric field concentration phenomenon that easily occurs in traditional equal-width gates with narrow pitch. The bottom arc structure further eliminates the superposition effect of electric field at right-angle corners, reducing the impact of high electric field on the gate oxide layer. Through the optimization of electric field distribution, the damage accumulation of the gate oxide layer during long-term operation can be significantly reduced, the occurrence of time-delayed gate oxide breakdown (TDDB) can be delayed, the gate life can be greatly extended, and the long-term reliability of the device under high voltage and high power conditions can be improved, solving the core pain point of poor gate reliability of narrow-pitch trench IGBTs.

[0038] The P-area 2 500 is provided with a plurality of downwardly extending P+areas 900; there is a gap between the bottom surface of the P+area 900 and the bottom surface of the P-area 2 500, and the top corner is connected to the corresponding N+area 600. The P+ region 900 structure design optimizes the current distribution and carrier transport path within the device: On the one hand, the connection method between the P+ region and the N+ region can quickly conduct the large current generated during short circuit faults, and avoid the device overheating and damage caused by excessive current concentration in local areas; On the other hand, the design of extending the P+ region downwards and maintaining a distance from the P+ region can adjust the balance between the on-state voltage drop and the short-circuit current of the device. While ensuring a low on-state voltage drop, it can improve the device's tolerance to short-circuit current, reduce the risk of device failure due to short-circuit faults, and enable the device to operate safely and stably under complex operating conditions.

[0039] The dielectric layer 700 has an emitter metal layer A00 at the top connected to the P+ region 900, and a P-shieldB00 at the bottom.

[0040] The bottom of the P-shield B00 in this case is flat, with rounded corners that connect to the silicon dioxide layer 710.

[0041] The electric field of trench IGBTs is often strongest at the bottom corner of the trench, which can easily lead to local breakdown or excessive stress in the gate oxide layer. Adding p-type doping can create a local depletion region and electric field shielding effect during reverse bias, reducing the electric field spike at the bottom of the trench. Simultaneously, by adjusting the channel current distribution and carrier injection, the p-shield region can alter the potential distribution, allowing more current to be distributed on the trench sidewalls, improving channel controllability and reducing channel resistance fluctuations. Especially during high-speed switching, p-shield helps reduce the electric field and prevent phenomena such as dynamic avalanche.

[0042] Existing technologies often require higher temperatures and longer periods of high-temperature annealing, and the control of doping distribution is more difficult. This invention, by combining with a wider gate bottom structure, allows for more precise control of diffusion distribution. The modulation of the p-shield-type doped region affects carrier storage.

[0043] The dielectric layer 700 includes a first dielectric layer and a silicon dioxide layer 710; The silicon dioxide layer 710 is wrapped around the gate layer 800, and the first dielectric layer has a rectangular cross-section.

[0044] The silicon dioxide layer 710 is connected to the N+ region 600, the P-region 500, and the N-type drift region 400, respectively, and includes an upper silicon dioxide region and a lower silicon dioxide region from top to bottom (the lower silicon dioxide region is an arc-shaped structure region with upper and lower corners); in this case, the cross-section of the silicon dioxide layer 710 and the gate layer 800 has a narrow upper and wide lower structure, and the aforementioned lower silicon dioxide region is the widened region. The cross-sectional thickness of the upper silicon dioxide region is smaller than that of the lower silicon dioxide region.

[0045] The plurality of N+ regions 600 are located on the side of the silicon dioxide layer 710, and their bottoms are connected to the corresponding P+ regions 900.

[0046] In this case, the emitter 810 has arc-shaped top and bottom corners; by dividing the gate oxide layer in the trench into an upper half of the gate and a lower half of the emitter, a split gate structure is achieved. The beneficial effects of this structure are: A. Reduce the gate oxide electric field and improve reliability.

[0047] B. The emitter is equivalent to forming an electric field shielding layer in the lower half of the trench, which effectively reduces the stress of the gate oxide layer and avoids gate oxide breakdown.

[0048] C. Without a split gate, the electric field at the bottom of the trench may induce a "bottom MOS channel," leading to leakage or failure. The split gate structure isolates the bottom of the trench, no longer subject to gate voltage control, and only allows the sidewalls to form channels, improving the off-state leakage control capability.

[0049] D. The shielded gate also reduces the gate-collector coupling capacitance (Miller capacitance Crss), thereby improving dv / dt controllability. Because the Miller capacitance is reduced, the gate charge Qg during switching is reduced, resulting in increased switching speed, decreased losses, and lower EMI.

[0050] Regarding the information disclosed in this case, the following points need to be clarified: (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design. (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments; The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. An IGBT device with a split-gate structure, characterized in that, It includes, from bottom to top, a collector metal layer (100), a P-region one (200), an N-type buffer zone (300), an N-type drift region (400), a P-region two (500), multiple N+ regions (600), and multiple dielectric layers (700). The dielectric layer (700) has a gate layer (800) extending to the N-type drift region (400); the gate layer (800) has a narrow top and wide bottom structure and an arc-shaped bottom structure. The second P region (500) is provided with a plurality of downwardly extending P+ regions (900); there is a gap between the bottom surface of the P+ region (900) and the bottom surface of the second P region (500), and the top corner is connected to the corresponding N+ region (600); The dielectric layer (700) has an emitter metal layer (A00) connected to the P+ region (900) at the top and a P-shield (B00) at the bottom.

2. The IGBT device with a split-gate structure according to claim 1, characterized in that, The dielectric layer (700) includes a first dielectric layer and a silicon dioxide layer (710); The silicon dioxide layer (710) is wrapped around the gate layer (800).

3. A method for fabricating an IGBT device with a split-gate structure, relating to the IGBT device with a split-gate structure as described in claim 1, characterized in that, Includes the following steps: Step 1: Provide an N-type drift zone; Step 2: Etch the trench structure of the IGBT using an etching process; Step 3: Using a polysilicon deposition process, polysilicon, photoresist, or organic materials are implanted into the trenches and surfaces at high temperatures; Step 4: Etch the polysilicon, photoresist, or organic material within the trench using an etching process; Step 5: Grow a layer of silicon dioxide on the trench; Step 6: Completely etch the remaining polysilicon in the trench using an etching process; Step 7: Using an etching process, etch the sidewalls and bottom of the trench without an oxide layer, designing the trench as a narrow-at-the-top and wide-at-the-bottom structure, dividing the trench into an upper trench and a lower trench; Step 8: Ion implantation is performed at the bottom of the trench to form a P-type doped region; Step 9: Grow silica in the trench; Step 10: Inject polycrystalline silicon into the trench. Step 11: Etch the polysilicon at the trench opening; Step 12: Grow silicon dioxide on the polycrystalline silicon within the trench; Step 13: Deposit polycrystalline silicon in the trench; Step Fourteen: Form P-regions and multiple N+ regions through an injection process; Step 15: Deposit medium layer; Step 16: Photolithography defines the location of the vias. After dry etching through the ILD, silicon is etched and P+ ion implantation is performed at the openings. Step 17: Deposit a metal layer on the front side; The back side undergoes thinning, N-type buffer doping, P-region formation, and collector metal fabrication processes.

4. The method for fabricating an IGBT device with a split-gate structure according to claim 3, characterized in that, In step two, a trench with a depth of 2-5 micrometers is etched using an etching process.

5. The method for fabricating an IGBT device with a split-gate structure according to claim 3, characterized in that, In step four, the trenches and surface polysilicon are etched to a depth of 2-3 micrometers using an etching process.

6. The method for fabricating an IGBT device with a split-gate structure according to claim 3, characterized in that, In step five, a gate oxide layer with a thickness of 10-50 nanometers is grown on the trench.

7. The method for fabricating an IGBT device with a split-gate structure according to claim 3, characterized in that, In step seven, the width of the lower trench cross-section is 1.2 micrometers to 1.5 micrometers.

8. The method for fabricating an IGBT device with a split-gate structure according to claim 3, characterized in that, In step sixteen, the silicon is etched again to a depth of 0.2-0.4 micrometers.

9. The method for fabricating an IGBT device with a split-gate structure according to claim 3, characterized in that, In step seventeen, a 4-5 μm AlCu metal layer is deposited on the front side.

10. The method for fabricating an IGBT device with a split-gate structure according to claim 3, characterized in that, In step seventeen, the collector metal includes Ti / TiN, Al / AlSiCu, or Ni / Ag / Au.

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