Semiconductor device and manufacturing method thereof
By removing the irregular area at the bottom of the photoresist layer after patterning, and then treating it with oxygen-containing gas and transferring it to a hard mask layer, the vertical contour problem caused by photoresist residue was solved, and efficient manufacturing of trench semiconductor devices was achieved.
Patent Information
- Application Number
- CN202510969233.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-11
- Publication Date
- 2025-11-18
AI Technical Summary
In the manufacturing process of trench semiconductor devices, the photoresist residue at the bottom prevents the formation of an ideal vertical profile during the etching of the hard mask layer, affecting the electrical performance and yield of the device.
After the photoresist layer is patterned, an oxygen-containing gas is used to remove the irregular area at the bottom of the photoresist layer pattern. By precisely controlling the radio frequency power and gas flow rate, the vertical state of the photoresist layer is ensured, and then it is transferred to the hard mask layer to form a vertical hard mask layer pattern outline.
Precise control of the trench profile was achieved, improving device performance and manufacturing yield, ensuring that the trench angle reaches a vertical angle of 88 to 90 degrees, and enhancing the electrical performance and reliability of the device.
Smart Images
Figure CN120980902A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor device technology, and more specifically, to a semiconductor device and a method for manufacturing the same. Background Technology
[0002] In the fabrication of trench semiconductor devices, such as silicon carbide MOSFETs, trench etching profile formation is a critical step, as it affects the device's electrical performance and reliability. To ensure device performance and reliability, the trench profile angle needs precise control, requiring it to remain perpendicular. However, in actual manufacturing, issues such as photoresist (PR) residue and scum buildup during patterning prevent the formation of an ideal vertical profile during hard mask etching. These problems not only affect the final trench shape but can also lead to degraded device electrical performance and reduced yield.
[0003] Therefore, an effective method is needed to control and improve the pattern profile of hard masks to ensure that precise vertical profiles can be formed during trench etching. Summary of the Invention
[0004] In view of the above problems, this disclosure adds a step to remove the bottom residue of the photolithographic pattern during the manufacturing process of semiconductor devices, thereby optimizing the etching profile of the hard mask layer pattern and the trench etching profile.
[0005] According to one aspect of the embodiments of this disclosure, a method for manufacturing a semiconductor device is provided, comprising:
[0006] A hard mask layer is formed on the semiconductor layer;
[0007] A photoresist layer is formed on the hard mask layer;
[0008] Pattern the photoresist layer;
[0009] The irregular areas at the bottom of the pattern in the photoresist layer are removed using oxygen-containing gas; and
[0010] The hard mask layer is etched to transfer the pattern of the photoresist layer to the hard mask layer, forming an etched outline of the vertical hard mask layer pattern.
[0011] Optionally, the oxygen-containing gas is a mixture of CF4 / O2 / Ar.
[0012] Optionally, the gas flow rate of CF4 is 10~300 sccm; the gas flow rate of O2 is 5~100 sccm; and the gas flow rate of Ar is 10~500 sccm.
[0013] Optionally, the gas flow rate of CF4 is 70~95 sccm; the gas flow rate of O2 is 15~30 sccm; and the gas flow rate of Ar is 150~175 sccm.
[0014] Optionally, in the step of removing the irregular area, the pressure in the process chamber is 10~200mT; the radio frequency power is 200~3000W; and the temperature of the electrostatic chuck in the process chamber is 10~80℃.
[0015] Optionally, the pressure in the process chamber is 30~50mT; the radio frequency power is 1350W~1650W; and the temperature of the electrostatic chuck is 50~65℃.
[0016] Optionally, in the etching step, a fluorine-containing gas is used to etch the hard mask layer.
[0017] Optionally, the fluorine-containing gas includes CF4, or the fluorine-containing gas includes CF4 and CHF3, or the fluorine-containing gas is a mixture of CF4 / CHF3 / O2.
[0018] Optionally, it also includes:
[0019] Photoresist ashing and removal;
[0020] Forming trench-type semiconductor devices.
[0021] According to another aspect of the present disclosure, a semiconductor device is provided, which is manufactured using the manufacturing method described above.
[0022] One of the above technical solutions has the following beneficial effects:
[0023] By using oxygen-containing gas to remove irregular areas (bottom residue, scum) at the bottom of the photoresist layer pattern, the pattern outline of the photoresist layer is kept vertical. This verticality is then copied into the pattern outline of the hard mask layer during the etching process, which helps to maintain the verticality of the trench outline when the semiconductor layer is etched to form trenches.
[0024] In practical applications, to ensure that the top and sidewalls of the photoresist layer are unaffected by the oxygen-containing gas removal process, this invention achieves this by precisely controlling the radio frequency (RF) power and gas flow rate in the process chamber. Specifically, by adjusting the RF power and gas flow rate, the activity of the oxygen-containing gas plasma can be controlled, thereby reducing the bombardment and chemical reaction of the oxygen-containing gas on the top and sidewalls of the photoresist layer and avoiding excessive wear of the photoresist layer. For example, the RF power can be set between 200 and 3000 W, and the oxygen-containing gas flow rate can be set between 5 and 100 sccm. Simultaneously, CF4 and CHF3 gases are used to optimize the etching selectivity and byproduct control of the hard mask layer. Furthermore, by adjusting the chamber pressure and the electrostatic chuck (ESC) temperature, the removal effect of the photoresist layer and the etching quality of the hard mask layer can be further optimized, ensuring that the final trench profile achieves the required vertical angle of 88 to 90 degrees. This achieves precise control of the trench profile, improving device performance and manufacturing yield.
[0025] It should be noted that the above general description and the following detailed description are exemplary and explanatory only and do not limit this disclosure. Attached Figure Description
[0026] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only involve some embodiments of this disclosure, and are not intended to limit this disclosure.
[0027] Figure 1 A flowchart illustrating the manufacturing process of a semiconductor device according to an embodiment of this disclosure is shown.
[0028] Figure 2 This diagram illustrates the structure of a semiconductor device according to an embodiment of the present disclosure after the photoresist layer has been patterned during manufacturing.
[0029] Figure 3 This diagram illustrates the structure of a semiconductor device according to an embodiment of the present disclosure after removing irregular areas at the bottom of the photoresist layer pattern during manufacturing.
[0030] Figure 4 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present disclosure after etching of a hard mask layer during manufacturing is shown.
[0031] Figure 5 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present disclosure after the photoresist layer has been removed during manufacturing is shown.
[0032] Figure 6 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present disclosure after trenches are formed during manufacturing is shown.
[0033] Figure 7The image shows a partial SEM image of a semiconductor device during the manufacturing process without processing the bottom of the photolithographic pattern.
[0034] Figure 8 This image shows a partial SEM image of a semiconductor device with the bottom of a photolithographic pattern processed during the manufacturing process. Detailed Implementation
[0035] The present disclosure will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, a semiconductor structure obtained after several steps can be depicted in a single figure.
[0036] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that there are other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.
[0037] To describe a situation where it is directly above another layer or another area, this article will use expressions such as "directly above" or "above and adjacent to".
[0038] Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without following these specific details.
[0039] Figure 1 A flowchart illustrating the manufacturing process of a semiconductor device according to an embodiment of this disclosure is shown. Figures 2 to 6 A schematic diagram of a portion of the stages in a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown.
[0040] See Figure 1 and Figure 2 In step S1, a hard mask layer 102 is formed on the semiconductor layer 101.
[0041] The semiconductor layer 101 may include a substrate and an epitaxial layer, or only a substrate. The material of the semiconductor layer 101 may be silicon carbide (SiC), silicon (Si), GaN, and other semiconductor materials. A hard mask is a protective layer material used in photolithography and etching processes, typically made of hard materials such as silicon dioxide, silicon nitride, and silicon carbide. Compared to photoresist (soft mask), hard masks have higher chemical and physical stability and can withstand more complex etching processes.
[0042] See further Figure 1 and Figure 2 In step S2, a photoresist layer 103 is formed on the hard mask layer 102.
[0043] The photoresist layer (PR) 103 can be formed on the hard mask layer 102 by spin coating in preparation for patterning. The thickness and uniformity of the photoresist layer 103 are crucial for subsequent etching steps, so parameters such as spin coating speed, time and temperature need to be strictly controlled to ensure that the photoresist layer 103 can meet the requirements of subsequent processes.
[0044] See further Figure 1 and Figure 2 In step S3, the photoresist layer 103 is patterned.
[0045] After spin coating, the photoresist layer 103 forms the desired pattern through exposure and development steps. This pattern will serve as a mask for subsequent etching of the hard mask layer 102. In this embodiment, the pattern in the photoresist layer 103 is an opening 103a.
[0046] like Figure 2 As shown, after the photoresist layer 103 is patterned, due to the potential scum problem during the photolithography process, the bottom of the pattern of the photoresist layer 103 may form an irregular tail contour, which will directly affect the etching effect of the hard mask layer 102.
[0047] See further Figure 1 and Figure 3 In step S4, an oxygen-containing gas is used to remove the irregular area at the bottom of the pattern of the photoresist layer.
[0048] In this embodiment, before etching the hard mask layer 102, irregular areas at the bottom of the photoresist layer 103 pattern are removed by introducing oxygen-containing gas, such as... Figure 3 As shown.
[0049] Specifically, photoresist (PR) is composed of organic materials (C) X H Y O ZThe composition is oxygen-containing gas that generates oxygen free radicals (O•) under the action of radio frequency (RF) power. These oxygen free radicals react chemically with carbon elements (C) in the photoresist layer 103 to generate volatile products such as CO, CO2 and H2O, thereby effectively removing the residues at the bottom.
[0050] CxHyOz + O• → CO, CO2, H2O
[0051] To ensure that the top and sidewalls of the photoresist layer 103 are not damaged, this invention avoids excessive loss of the photoresist layer 103 by precisely controlling the radio frequency power and gas flow rate to regulate the activity of the oxygen plasma. For example, the radio frequency power can be set between 200 and 3000 W, and the oxygen gas flow rate can be set between 5 and 100 sccm.
[0052] In some specific embodiments, the oxygen-containing gas used to remove the irregular areas at the bottom of the photoresist layer 103 pattern is a mixture of CF4 / O2 / Ar.
[0053] In some alternative embodiments, the gas flow rate of CF4 is 10~300 sccm; the gas flow rate of O2 is 5~100 sccm; and the gas flow rate of Ar is 10~500 sccm.
[0054] In some preferred embodiments, the gas flow rate of CF4 is 70~95 sccm; the gas flow rate of O2 is 15~30 sccm; and the gas flow rate of Ar is 150~175 sccm.
[0055] In some alternative embodiments, the pressure in the process chamber during this step is 10~200mT; the radio frequency power is 200~3000W; and the temperature of the electrostatic chuck (ESC) in the process chamber is 10~80°C.
[0056] In some preferred embodiments, the pressure in the process chamber is 30~50mT; the radio frequency power is 1350W~1650W; and the temperature of the electrostatic chuck (ESC) is 50~65°C.
[0057] See further Figure 1 and Figure 4 In step S5, the hard mask layer 102 is etched to transfer the pattern of the photoresist layer 103 to the hard mask layer 102, forming an etched outline of the pattern of the hard mask layer 102 vertically.
[0058] In this embodiment, the etched outline of the pattern of the vertical hard mask layer 102 is an opening 102a, as shown in the figure. Figure 4 As shown.
[0059] In this step, the etching gas used is a fluorine-containing gas, including CF4, or a combination of CF4 and CHF3, with CF4 being the primary etching gas. This is used to optimize the etching selectivity and byproduct control of the hard mask layer 102. Furthermore, by adjusting the chamber pressure and ESC temperature, the removal effect of the photoresist layer 103 and the etching quality of the hard mask layer 102 can be further optimized.
[0060] In some specific embodiments, the fluorine-containing gas is a mixture of CF4 / CHF3 / O2, wherein the gas flow rate of CF4 is preferably 65~100 sccm; the gas flow rate of CHF3 is preferably 25~40 sccm; and the gas flow rate of O2 is 3~5 sccm.
[0061] In some specific embodiments, the fluorine-containing gas may also include Ar as a carrier gas, with an Ar gas flow rate of 10~500 sccm.
[0062] In some alternative embodiments, the removal of irregular areas of the photolithographic pattern and the etching of the hard mask layer can be performed in the same process chamber. This not only simplifies the process flow and reduces the transfer time between process steps, but also improves the stability and repeatability of the process. By performing these two steps consecutively in the same process chamber, contamination and damage to the photoresist layer or hard mask layer caused by environmental changes during the transfer process can be effectively avoided, ensuring precise control of the etching profile.
[0063] See further Figure 1 and Figure 5 In step S6, the photoresist is ashed and removed.
[0064] After etching the mask layer 102, the photoresist layer 103 is removed using an ashing process, such as... Figure 5 As shown. The gas used in the ashing process is O2, with a preferred flow rate of 250-300 sccm, and the preferred pressure in the process chamber during this step is 160-250 mT.
[0065] See further Figure 1 and Figure 6 In step S7, a trench semiconductor device is formed.
[0066] In this embodiment, trenches 110 are formed by etching the semiconductor layer 101 according to the pattern of the hard mask layer 102, such as... Figure 6As shown. During the etching process of the hard mask layer 102, the irregular area at the bottom of the photoresist layer 103 has been effectively removed through the PR processing step, ensuring that the pattern outline of the hard mask layer 102 remains vertical. Therefore, during the subsequent etching process of the semiconductor layer 101, this vertical hard mask layer pattern outline can be accurately replicated into the semiconductor layer 101, ensuring that the angle α between the bottom of the trench 110 and the sidewall reaches 88 to 90 degrees, thereby meeting the requirements of device performance and reliability.
[0067] After forming the trench 110, a gate can be formed within the trench 110, and doping can be performed in the semiconductor layer 101 to form body regions, source or emitter regions, drain or collector regions, etc. Of course, the doping process and the formation sequence of the trench 110 can be adjusted as needed to ultimately form the desired semiconductor device. For example, the semiconductor device can be a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), or other types of trench-type semiconductor devices.
[0068] Figure 7 The diagram shows SEM images of a semiconductor device at certain stages of its manufacturing process without processing the bottom of the photolithographic pattern. Specifically, the SEM image within dashed frame 11 shows an irregular tail contour formed at the bottom of the photoresist layer 103 after patterning; the SEM image within dashed frame 12 shows the irregular tail contour of the photoresist layer 103 being copied into the hard mask layer 102 through etching; and the SEM image within dashed frame 13 shows the effect after removing the photoresist layer 103 using an ashing process.
[0069] Figure 8 The diagram shows SEM images of a semiconductor device at certain stages of its manufacturing process, where the bottom of the photolithographic pattern has been processed. Specifically, the SEM image within dashed frame 21 shows an irregular tail contour formed at the bottom of the pattern after the photoresist layer 103 is patterned; the SEM image within dashed frame 22 shows the removal of the irregular area at the bottom of the photoresist layer 103 using oxygen-containing gas to form a vertical contour, which is then copied into the hard mask layer 102 by etching; and the SEM image within dashed frame 23 shows the effect after removing the photoresist layer 103 using an ashing process.
[0070] By comparison Figure 7 and Figure 8It is known that by using oxygen-containing gas to remove the irregular areas (bottom residue, scum) at the bottom of the photoresist layer pattern, the pattern outline of the photoresist layer is kept vertical. Then, during the etching of the hard mask layer, this vertical state is copied into the pattern outline of the hard mask layer, which is beneficial to maintain the vertical state of the trench outline when etching the semiconductor layer to form trenches in the future.
[0071] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.
Claims
1. A method for manufacturing a semiconductor device, comprising: A hard mask layer is formed on the semiconductor layer; A photoresist layer is formed on the hard mask layer; Pattern the photoresist layer; Oxygen-containing gas is used to remove the irregular areas at the bottom of the pattern of the photoresist layer; as well as The hard mask layer is etched to transfer the pattern of the photoresist layer to the hard mask layer, forming an etched outline of the vertical hard mask layer pattern.
2. The manufacturing method according to claim 1, wherein, The oxygen-containing gas is a mixture of CF4 / O2 / Ar.
3. The manufacturing method according to claim 2, wherein, The gas flow rate of CF4 is 10~300 sccm; the gas flow rate of O2 is 5~100 sccm; and the gas flow rate of Ar is 10~500 sccm.
4. The manufacturing method according to claim 3, wherein, The gas flow rate of CF4 is 70~95 sccm; the gas flow rate of O2 is 15~30 sccm; and the gas flow rate of Ar is 150~175 sccm.
5. The manufacturing method according to any one of claims 1 to 4, wherein, In the step of removing the irregular area, the pressure in the process chamber is 10~200mT; the radio frequency power is 200~3000W; and the temperature of the electrostatic chuck in the process chamber is 10~80℃.
6. The manufacturing method according to claim 5, wherein, The pressure in the process chamber is 30~50mT; the radio frequency power is 1350W~1650W; and the temperature of the electrostatic chuck is 50~65℃.
7. The manufacturing method according to any one of claims 1 to 4, wherein, In the etching step, the hard mask layer is etched using a fluorine-containing gas.
8. The manufacturing method according to claim 7, wherein, The fluorine-containing gas includes CF4, or the fluorine-containing gas includes CF4 and CHF3, or the fluorine-containing gas is a mixture of CF4 / CHF3 / O2.
9. The manufacturing method according to claim 1, further comprising: Photoresist ashing and removal; Forming trench-type semiconductor devices.
10. A semiconductor device, wherein, It is manufactured using the manufacturing method described in any one of claims 1 to 9.