Semiconductor device with trench gate structure and manufacturing method thereof

Abstract

The invention provides a semiconductor device with a trench gate structure and a manufacturing method thereof, and the semiconductor device comprises a silicon carbide body which is provided with a first surface; a trench gate structure extending from the first surface into the silicon carbide body; the drift region is positioned in the silicon carbide body and is adjacent to the side wall of the trench gate structure; the source electrode region is located in the silicon carbide body, the source electrode region is located below the trench gate structure, and the source electrode region comprises a first part adjacent to the bottom of the trench gate structure and a second part adjacent to the side wall of the trench gate structure; the first doped region has a doping type different from that of the source region, and the first doped region is arranged around the source region and is in contact with the side wall of the trench gate structure; wherein the first doped region separates the source region from the drift region. Through the structural design that the source region is embedded in the bottom of the trench gate structure, the influence of gate oxide electrical stress is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a semiconductor device with trench gate structure and a manufacturing method thereof. BACKGROUND

[0002] After more than 10 years of technical development, SiC MOSFET technology gradually transits from SiC planar gate MOSFET to SiC trench MOSFET. It has been fully proved that, compared with the planar gate structure, the trench structure can effectively reduce the cell size and increase the channel density, and for 4H-SiC material, the vertical crystal plane defect density is low and the channel mobility is high. Therefore, the SiC trench gate MOSFET can reduce the specific on-resistance while using a thicker gate oxide layer to improve the gate oxide reliability.

[0003] However, SiC trench gate MOSFET also faces higher challenges in gate oxide electric field stress shielding: under the same forward conduction capability, SiC wide bandgap power devices have a higher critical breakdown field than Si devices, resulting in a greater electric field stress on the gate oxide layer in the blocking state, and the potential barrier height of the SiO2 / SiC system is lower than that of the SiO2 / Si system, and the electric field strength for FN tunneling current is smaller, which makes the gate oxide reliability of SiC devices face greater risks. SUMMARY

[0004] The purpose of the present application is to reduce the influence of gate oxide electric stress of a silicon carbide semiconductor device with a trench gate structure and avoid the continuous voltage stress from breaking down the weak gate oxide at the bottom of the trench first.

[0005] To achieve the above purpose, the present application provides a semiconductor device with a trench gate structure, comprising:

[0006] a silicon carbide body having a first surface;

[0007] a trench gate structure extending into the silicon carbide body from the first surface;

[0008] a drift region located in the silicon carbide body and adjacent to the sidewall of the trench gate structure;

[0009] a source region located in the silicon carbide body, the source region being located below the trench gate structure and comprising a first part adjacent to the bottom of the trench gate structure and a second part adjacent to the sidewall of the trench gate structure;

[0010] a first doped region having a different doping type from the source region, the first doped region being arranged around the source region and in contact with the sidewall of the trench gate structure; wherein the first doped region separates the source region from the drift region.

[0011] Furthermore, the bottom of the trench gate structure is completely surrounded by the source region.

[0012] Furthermore, semiconductor devices include:

[0013] The source electrode structure includes a source electrode that extends from the first surface into the silicon carbide body and is adjacent to the source region.

[0014] Furthermore, the source electrode structure further includes:

[0015] The first heavily doped region extends from the first surface into the silicon carbide body and is disposed around the source electrode. The first heavily doped region is adjacent to the source region in the vertical direction and is adjacent to the sidewall of the trench gate structure in the lateral direction.

[0016] Furthermore, the first heavily doped region is adjacent to the source region and the first doped region.

[0017] Furthermore, the drift region includes a first drift region and a second drift region. The first drift region extends from the first surface into the silicon carbide body, and the second drift region is located below and adjacent to the first drift region. The doping concentration of the first drift region is greater than that of the second drift region.

[0018] Furthermore, the lower surface of the first drift region is not higher than the lower surface of the first doped region.

[0019] Furthermore, semiconductor devices also include:

[0020] The drain region is located between the second surface of the silicon carbide body and the drift region, and has the same doping type as the source region, wherein the second surface is opposite to the first surface.

[0021] This application also provides a method for manufacturing a semiconductor device with a trench gate structure, the method comprising:

[0022] Provides silicon carbide body;

[0023] A drift region is formed, which is located within the silicon carbide bulk.

[0024] The first doped region is formed in the drift region;

[0025] Source regions with different doping types are formed in the first doped region;

[0026] A trench gate structure is formed that extends from the first surface into the silicon carbide body;

[0027] After the trench gate structure is formed, the source region is generally located below the trench gate structure, including a first portion adjacent to the bottom of the trench gate structure and a second portion adjacent to the sidewall of the trench gate structure; the first doped region is in contact with the sidewall of the trench gate structure; wherein the first doped region separates the source region from the drift region.

[0028] Furthermore, the methods also include:

[0029] An opening is made on the first surface of the silicon carbide body, and a metal is deposited at the opening to form a source electrode. The source electrode extends from the first surface into the silicon carbide body and is adjacent to the source region.

[0030] This application embeds the source region at the bottom of the trench gate structure. When the semiconductor device is turned on, electrons at the bottom of the trench gate structure transfer along the sidewalls to the second doped region, achieving reverse flow of channel carriers. This transfers the electric field pressure to the more voltage-resistant PN junction, reducing the impact of gate oxide electrical stress and preventing breakdown at the weak bottom of the trench due to continuous voltage stress. Furthermore, this solution protects the trench gate structure through device structure design, making it unaffected by gate oxide process fluctuations. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of a semiconductor device provided in the first embodiment of this application;

[0032] Figure 2 for Figure 1 The diagram shows the operation of the semiconductor device in the on-state.

[0033] Figure 3 This is a schematic diagram of the source electrode structure provided in an embodiment of this application;

[0034] Figure 4 This is a schematic diagram of a semiconductor device provided in the second embodiment of this application;

[0035] Figure 5 This is a schematic diagram of a semiconductor device provided in the third embodiment of this application;

[0036] Figure 6 This is a schematic diagram of a semiconductor device provided in the fourth embodiment of this application;

[0037] Figure 7 A vertical cross-sectional view of a semiconductor device and a comparator device provided according to an embodiment is shown;

[0038] Figure 8 for Figure 7 A schematic diagram of the electric field at section A.

[0039] Figure 9 for Figure 8 A magnified view of a portion of point A in the middle;

[0040] Figure 10 for Figure 7 A schematic diagram of the electric field at section B.

[0041] Figure 11 for Figure 10 A magnified view of a portion of point B in the middle;

[0042] Figure 12 This is a schematic diagram of the gate charge curves for comparing the device structure and the semiconductor device structure provided according to the embodiments.

[0043] Explanation of reference numerals in the attached drawings: Semiconductor device 100, trench gate structure 11, conductive gate electrode 111, gate dielectric 112, drift region 12, first drift region 121, second drift region 122, source region 13, first portion of source region 131, second portion of source region 132, first doped region 14, source electrode structure 15, source electrode 151, first heavily doped region 152, drain region 17, drain electrode 18, first surface 101, sidewall 102, second surface 103. Detailed Implementation

[0044] The present application will be described in detail below with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present application. Any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the protection scope of the present application.

[0045] The terms “having,” “containing,” “including,” and “comprising” are open-ended and indicate the presence of the stated structure, element, or feature but do not exclude the presence of additional elements or features. The quantifiers and pronouns “a,” “one,” and “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise.

[0046] The term "electrical connection" describes a permanent low-resistance connection between electrically connected elements, such as a direct contact between related elements or a low-resistance connection via a metal and / or heavily doped semiconductor material. The term "electrical coupling" includes one or more intermediate elements adapted for signal and / or power transmission that can be connected between electrically coupled elements, such as elements controllable to temporarily provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state.

[0047] Each figure illustrates the relative doping concentration by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" means a lower doping concentration than the "n" doped region, while "n+" doped regions have a higher doping concentration than the "n" doped region. Doped regions with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doped regions can have the same or different absolute doping concentrations.

[0048] The term "on" should not be interpreted as simply meaning "directly on". Rather, if an element is "on" another element (e.g., a layer is "on" another layer or "on" a substrate), then a further component (e.g., a further layer) may be located between the two elements (e.g., a further layer may be located between a layer and a substrate, if that layer is "on" the substrate).

[0049] As an optional implementation, the semiconductor device provided in this application includes a silicon carbide body. On the front side, the silicon carbide body of the semiconductor device has a first surface. On the back side, an opposing second surface may extend parallel to the first surface. The normal to the first surface defines a vertical direction, and the direction parallel to the first surface is a horizontal direction.

[0050] like Figure 1 As shown, the semiconductor device 100 provided in this embodiment further includes a trench gate structure 11, which extends from the first surface 101 into the silicon carbide body. In one optional implementation, the opposing sidewalls of the trench gate structure 11 can extend along the vertical direction, and the trench gate structure 11 can be rounded at the bottom to form a U-shaped structure. In another optional implementation, the sidewalls of the trench gate structure 11 can be tilted at a certain angle relative to the vertical direction and gradually taper as the distance to the first surface 101 increases, forming a trapezoidal structure that is wider at the top and narrower at the bottom, extending along the vertical direction.

[0051] The trench gate structure 11 further includes a conductive gate electrode 111 and a gate dielectric 112. The conductive gate electrode 111 may include a heavily doped polysilicon layer and / or a metal-containing layer, or may be composed of a heavily doped polysilicon layer and / or a metal-containing layer.

[0052] The gate dielectric 112 separates the gate electrode from the silicon carbide body along at least one side of the trench gate structure 11. The gate dielectric 112 may include thermally grown or deposited silicon oxide, silicon nitride, silicon oxynitride, other deposited dielectric materials, or any combination thereof, or may be composed of thermally grown or deposited silicon oxide, silicon nitride, silicon oxynitride, other deposited dielectric materials, or any combination thereof.

[0053] The semiconductor device 100 provided in this application embodiment further includes a drift region 12, a source region 13, and a first doped region 14. The drift region 12 extends from the first surface 101 into the silicon carbide body and is adjacent to the sidewall 102 of the trench gate structure 11. The source region 13 is located in the silicon carbide body and below the trench gate structure 11, including a first portion 131 adjacent to the bottom of the trench gate structure 11 and a second portion 132 adjacent to the sidewall 102 of the trench gate structure 11. The first doped region 14 has a doping type different from that of the source region 13, surrounds the source region 13, and contacts the sidewall 102 of the trench gate structure 11; wherein the first doped region 14 separates the source region 13 from the drift region 12, the first doped region 14 and the source region 13 form a first pn junction, and the first doped region 14 and the drift region 12 form a second pn junction.

[0054] It should be noted that the adjacency of object A and object B in the embodiments of this application can mean that object A and object B are adjacent and in contact in terms of position. In one embodiment, the source region 13 and drift region 12 are n-type doped, and the first doped region 14 is p-type doped. In another implementation, the source region 13 and drift region 12 are p-type doped, and the first doped region 14 is n-type doped.

[0055] For ease of explanation, this application uses the implementation of source region 13 being n-type doped as an example to illustrate the working principle of the semiconductor device 100 provided in this application.

[0056] like Figure 2 As shown, the gate dielectric 112 capacitively couples the source region 13 to the gate electrode. When a gate-source voltage is applied to the semiconductor device 100, the electric field causes minority carriers in the first doped region 14 (which is p-type doped, and minority carriers are electrons) to form an inversion channel along the gate dielectric 112. This inversion channel connects the source region 13 and the drift region 12, thereby turning on the semiconductor device 100. In the on-state, the load current flows approximately along the sidewall 102 between the source region 13 and the drift region 12. This application embeds the source region 13 at the bottom of the trench gate structure 11, and the source region 13 completely covers the bottom of the trench gate structure 11. Thus, when the semiconductor device 100 is turned on, electrons at the bottom of the trench gate structure 11 will transfer along the sidewall 102 to the drift region 12, realizing the reverse flow of channel carriers. This transfers the electric field pressure to the PN junction with stronger voltage resistance, reduces the influence of gate oxide electric stress, and avoids continuous voltage stress from breaking down first at the weak bottom of the trench.

[0057] The semiconductor device 100 provided in this application achieves reverse flow of channel carriers by burying the source region 13 at the bottom of the trench gate, thereby transferring the electric field pressure to the PN junction with stronger voltage resistance, reducing the impact of gate oxide electric stress, and avoiding gate oxide quality degradation caused by continuous gate oxide electric stress. Furthermore, this solution protects the trench gate structure 11 through device structure design, so that it is not affected by gate oxide process fluctuations.

[0058] Furthermore, the first doped region 14 separates the drift region 12 from the source region 13. The first doped region 14 contacts the sidewall 102 of the trench gate structure 11, thereby reducing the contact area between the drift region 12 and the sidewall 102 of the trench gate structure 11. This reduces the overlap between the gate and drain, which can lower the Qgd (gate-drain charge). The gate-drain charge Qgd is a characteristic that determines the rise and fall times of the switch. Lowering the gate-drain charge Qgd can effectively increase the switching frequency of the device.

[0059] like Figure 3 As shown, as an optional implementation, the semiconductor device 100 further includes a source electrode structure 15. The source electrode structure 15 includes a source electrode 151 extending from the first surface 101 into the silicon carbide body, the source electrode 151 being adjacent to the source region 13 and forming an ohmic contact with the source region 13 to facilitate applying a voltage to the source region 13. In one embodiment, the source electrode 151 can be formed by creating an opening in a selected area of ​​the silicon carbide body and subsequently depositing metal (e.g., Al).

[0060] like Figure 3 As shown, as an optional implementation, the source electrode structure 15 further includes a first heavily doped region 152, which extends from the first surface 101 into the silicon carbide body and surrounds the source electrode 151, thereby forming a low-resistance ohmic contact with the source electrode 151 so that electrons can tunnel.

[0061] The first heavily doped region 152 is laterally adjacent to the sidewall 102 of the trench gate structure 11. Please refer to... Figure 1 In one embodiment, the first heavily doped region 152 is adjacent only to the source region 13 in the vertical direction. (See reference...) Figure 3 In another embodiment, the first heavily doped region 152 is adjacent to the source region 13 and the first doped region 14 in the vertical direction. Of course, in yet another embodiment, the first heavily doped region 152 may also be adjacent to the source region 13, the first doped region 14 and the drift region 12 in the vertical direction.

[0062] The first heavily doped region 152 has a different doping type than the source region 13; that is, in this embodiment, the first heavily doped region 152 is P-type heavily doped. The high dopant concentration of the first heavily doped region 152 suppresses the formation of an inversion channel along the sidewall 102.

[0063] In one embodiment, the end of the source electrode 151 away from the first surface 101 is lower than the lower surface of the first heavily doped region 152. In another embodiment, the end of the source electrode 151 away from the first surface 101 is flush with the lower surface of the first heavily doped region 152.

[0064] like Figure 4 As shown, the drift region 12 includes a first drift region 121 and a second drift region 122. The first drift region 121 extends from the first surface 101 into the silicon carbide body. The second drift region 122 is located below the first drift region 121 and adjacent to the first drift region 121. The doping concentration of the first drift region 121 is greater than the doping concentration of the second drift region 122.

[0065] like Figure 4 As shown, the second drift region 122 is lightly n-doped. When the semiconductor device 100 is turned on, electrons enter the first drift region 121 along the inversion channel near the sidewall 102 and then diffuse to the second drift region 122. In one embodiment, the average dopant concentration in the first drift region 121 is greater than the average dopant concentration in the second drift region 122.

[0066] As an optional implementation, the lower surface of the first drift region 121 is not higher than the lower surface of the first doped region. It should be noted that, in the embodiments of this application, "high and low" refers to, with the second surface 103 of the silicon carbide body as a reference, for two or more interfaces being compared, if the distance between the first interface and the second surface 103 is closer than the distance between the second interface and the second surface 103, then the first interface is lower than the second interface.

[0067] Specifically, such as Figure 4 As shown, in one embodiment, the lower surface of the first drift region 121 is lower than the lower surface of the first doped region 14. In this embodiment, the JFET resistance is reduced through the relatively highly doped first drift region 121. Figure 5 As shown, in another embodiment, the lower surface of the first drift region 121 is flush with the lower surface of the first doped region 14. In this embodiment, the voltage withstand characteristics of the semiconductor device can be guaranteed while ensuring low JFET resistance.

[0068] Easy to understand, such as Figure 6As shown, the lower surface of the first drift region 121 can also be higher than the lower surface of the first doped region 14. This method can also reduce the JFET resistance, but the JFET resistance will be greater than the case where the lower surface of the first drift region 121 is not higher than the lower surface of the first doped region 14.

[0069] Furthermore, such as Figure 6 As shown, the semiconductor device 100 also includes:

[0070] Drain region 17 is located between the second surface 103 and the second drift region 122 of the silicon carbide body and has the same doping type as the source region 13, wherein the second surface 103 is opposite to the first surface 101.

[0071] The drain region 17 may be or may include a substrate portion obtained from a crystal ingot, and forms an ohmic contact with the drain electrode 18 adjacent to the second surface 103. The average doping concentration in the contact structure is sufficiently high to ensure ohmic contact with the drain electrode 18.

[0072] This application does not limit the shape of the bottom of the trench gate structure 11, and it can be selected as, for example, square, bar, circle, hexagon, etc.

[0073] To further illustrate the semiconductor device provided in the embodiments of this application, a simulation comparison is performed below between the semiconductor device provided in this application and semiconductor devices in related technologies. (Reference) Figure 7 , Figure 8 and Figure 9 As can be seen, at section A, the gate oxide electric field near the bottom of the trench gate in the related technology semiconductor device shows a sharp increase trend (represented by the red curve), with the peak electric field intensity greater than 6e+6MV / cm; while for the semiconductor device provided in this application (represented by the green curve), the peak intensity of the gate oxide electric field at the bottom of the trench gate is about 1e+5MV / cm, which is significantly lower than the electric field intensity at the bottom of the trench gate of the related technology semiconductor device.

[0074] refer to Figure 7 , Figure 10 and Figure 11 Similarly, it can be seen that at section B, the gate oxide electric field strength of the semiconductor device in the related technology is the largest near the bottom of the trench gate, with a peak electric field strength greater than 6e+6MV / cm; while the peak electric field strength of the semiconductor device provided in this application is about 1e+5MV / cm at the bottom of the trench gate, which is significantly lower than the electric field strength at the bottom of the trench gate of the semiconductor device in the related technology.

[0075] As can be seen from the above description, the semiconductor device structure provided in the embodiments of this application can effectively reduce the gate oxide electric field strength at the bottom of the trench gate, and avoid continuous voltage stress from breaking down first at the weak bottom of the trench.

[0076] like Figure 12 As shown, this application also performs gate charge Qg simulation on the semiconductor device provided in the embodiments of this application and the semiconductor device in related technologies. According to Figure 12 It is evident that the semiconductor device structure provided in this application can reduce Qgd and effectively improve the switching frequency of the device.

[0077] This application also provides a method for manufacturing a semiconductor device 100 having a trench gate structure 11, the method comprising:

[0078] Provides silicon carbide body;

[0079] A drift region is formed, which is located within the silicon carbide bulk.

[0080] The first doped region is formed in the drift region;

[0081] Source regions with different doping types are formed in the first doped region;

[0082] A trench gate structure is formed that extends from the first surface into the silicon carbide body;

[0083] After the trench gate structure is formed, the source region is generally located below the trench gate structure, including a first portion adjacent to the bottom of the trench gate structure and a second portion adjacent to the sidewall of the trench gate structure; the first doped region is in contact with the sidewall of the trench gate structure; wherein the first doped region separates the source region from the drift region.

[0084] Specifically, an N-type doped drift region 12 is formed in the silicon carbide body. P-type doping can be performed on selected areas of the drift region 12 to form a first doped region 14 embedded in the silicon carbide body. Then, N-type heavy doping is performed in the first doped region 14 to form a source region 13. After forming the source region 13, it is embedded in the first doped region 14. A trench gate structure 11 is formed, extending from the first surface 101 into the silicon carbide body. Furthermore, the trench gate structure 11 extends into the source region 13, such that at least a portion of the sidewall 102 and the bottom of the trench gate structure 11 are in contact with the source region 13.

[0085] The semiconductor device 100 manufactured using the method provided in this application, when the semiconductor device 100 is turned on, allows electrons at the bottom of the trench gate structure 11 to transfer along the sidewall 102 to the second doped region 12, achieving reverse flow of channel carriers. This transfers the electric field pressure to the PN junction, which has stronger voltage resistance, reducing the impact of gate oxide stress and preventing breakdown at the weak bottom of the trench due to continuous voltage stress. The semiconductor device 100 provided in this application, through its structural design of embedding the source region 13 at the bottom of the trench gate, fully encloses the bottom of the trench gate structure, achieving reverse flow of channel carriers. This transfers the electric field pressure to the PN junction, which has stronger voltage resistance, reducing the impact of gate oxide stress and preventing degradation of gate oxide quality due to continuous gate oxide stress. Furthermore, this solution protects the trench gate structure 11 through device structure design, making it unaffected by gate oxide process fluctuations.

[0086] Furthermore, the methods also include:

[0087] An opening is formed on the first surface 101 of the silicon carbide body, and a metal is deposited at the opening to form a source electrode 151. The source electrode 151 extends from the first surface 101 into the silicon carbide body and is adjacent to the source region 13.

[0088] P-type heavy doping can be performed around the source electrode 151 to form a low-resistance ohmic contact with the source electrode 151.

[0089] The above-disclosed embodiments are merely preferred embodiments of this application, but are not intended to limit the scope of this application. Those skilled in the art will understand that any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and scope of this application and the appended claims are equivalent substitutions and still fall within the scope of the invention.

Claims

1. A semiconductor device having a trench gate structure, characterized in that, include: The silicon carbide body has a first surface; A trench gate structure extends from the first surface into the silicon carbide body; The drift region is located in the silicon carbide body and adjacent to the sidewall of the trench gate structure; The source region is located in the silicon carbide body and is located below the trench gate structure, including a first portion adjacent to the bottom of the trench gate structure and a second portion adjacent to the sidewall of the trench gate structure. A first doped region has a doping type different from that of the source region. The first doped region surrounds the source region and contacts the sidewall of the trench gate structure. The first doped region separates the source region from the drift region.

2. The semiconductor device with a trench gate structure according to claim 1, characterized in that, The bottom of the trench gate structure is completely surrounded by the source region.

3. The semiconductor device with a trench gate structure according to claim 1, characterized in that, The semiconductor device includes: A source electrode structure, the source electrode structure including a source electrode, the source electrode extending from the first surface into the silicon carbide body and adjacent to the source region.

4. The semiconductor device with a trench gate structure according to claim 3, characterized in that, The source electrode structure further includes: The first heavily doped region extends from the first surface into the silicon carbide body and is disposed around the source electrode. The first heavily doped region is adjacent to the source region in the vertical direction and is adjacent to the sidewall of the trench gate structure in the lateral direction.

5. The semiconductor device with a trench gate structure according to claim 4, characterized in that, The first heavily doped region is adjacent to the source region and the first doped region.

6. The semiconductor device with a trench gate structure according to claim 1, characterized in that, The drift region includes a first drift region and a second drift region. The first drift region extends from the first surface into the silicon carbide body. The second drift region is located below and adjacent to the first drift region. The doping concentration of the first drift region is greater than that of the second drift region.

7. The semiconductor device with a trench gate structure according to claim 6, characterized in that, The lower surface of the first drift region is not higher than the lower surface of the first doped region.

8. The semiconductor device having a trench gate structure according to any one of claims 6 to 7, characterized in that, The semiconductor device further includes: The drain region is located between the second surface of the silicon carbide body and the drift region, and has the same doping type as the source region, wherein the second surface is opposite to the first surface.

9. A method for manufacturing a semiconductor device having a trench gate structure, characterized in that, The manufacturing method includes: Provide silicon carbide body; A drift region is formed, the drift region being located within the silicon carbide body; A first doped region is formed in the drift region; Source regions with different doping types are formed in the first doped region; A trench gate structure is formed that extends from the first surface into the silicon carbide body; After the trench gate structure is formed, the source region is generally located below the trench gate structure, including a first portion adjacent to the bottom of the trench gate structure and a second portion adjacent to the sidewall of the trench gate structure; the first doped region is in contact with the sidewall of the trench gate structure; wherein the first doped region separates the source region from the drift region.

10. The method for manufacturing a semiconductor device having a trench gate structure according to claim 9, characterized in that, Also includes: An opening is formed on the first surface of the silicon carbide body, and a metal is deposited at the opening to form a source electrode. The source electrode extends from the first surface into the silicon carbide body and is adjacent to the source region.

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