SiC FINFET power device with electric field shielding structure and manufacturing method thereof

Abstract

The invention discloses a SiC FINFET power device with an electric field shielding structure and a manufacturing method of the SiC FINFET power device, relates to the technical field of semiconductor device manufacturing, and aims to solve the problem of three-dimensional electric field concentration caused when a nanoscale groove in the FINFET power device improves channel mobility. The first type drift region is formed on the substrate; a second type well layer formed on the current diffusion layer; the first type source contact region and the second type source contact region are formed in the well layer; a trench penetrating the well layer; the second type side wall protection region is formed on the side wall of the groove; the second type bottom protection region is formed at the bottom of the groove, is connected with the side wall protection region and is electrically connected to the well layer; the gate oxide layer covers the inner surface of the groove; and a gate conductor filling the trench. According to the SiC FINFET power device with the electric field shielding structure and the manufacturing method of the SiC FINFET power device, the electric field intensity at the bottom of the groove can be reduced while the mobility is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and specifically to a SiCFINFET power device with an electric field shielding structure and its manufacturing method. Background Technology

[0002] With the increasing demand for efficient and miniaturized power devices in power electronic systems, SiC metal-oxide-semiconductor field-effect transistors (MOSFETs), as core devices, still face some technical bottlenecks that urgently need to be overcome. Currently, there are two main technical approaches for SiC MOSFETs: planar gate and trench gate. Planar gate structures suffer from low channel mobility, leading to excessively high channel resistance. Their inherent JFET region further increases series resistance and limits cell size miniaturization. While trench gate structures can reduce lateral dimensions, their channel mobility is also insufficient. Furthermore, in the device's off state, the gate oxide layer at the bottom of the trench is subjected to high electric field stress for extended periods, easily leading to insulation degradation or even premature breakdown, threatening device reliability. These structural defects collectively restrict the reduction of specific on-resistance and the improvement of power density.

[0003] While existing finned field-effect transistor (FFET) power devices improve mobility through three-dimensional channel structures, this has led to new technical challenges. For example, the silicon carbide-based solution (CN116844963A) relies on an integrated Schottky diode to replace the parasitic diode to improve switching speed, but it lacks an electric field shielding structure. This results in the gate oxide layer being directly exposed to the high electric field in the drift region, failing to address reliability degradation. Another patent (CN116666224A) achieves electric field shielding in MOSFETs, but its sidewall and bottom protection zones require two independent photolithography processes, only suitable for micrometer-scale trench structures exceeding 500 nanometers. Furthermore, the alignment accuracy between the two photolithography processes is crucial. Insufficient accuracy will result in incomplete alignment of the trench windows formed by the two etching processes, leading to irregular trench contours or the etching away of part of the electric field shielding structure. This irregularity easily causes localized electric field concentration, ultimately resulting in premature device breakdown. When the channel width is reduced to 50-100 nanometers to trigger the quantum confinement effect and improve mobility, the concentration effect of the three-dimensional electric field becomes more severe. The nanostructure further increases the electric field strength at the bottom, but the inherent deviation of current mainstream photolithography processes exceeds 50 nanometers. This not only makes it impossible to accurately construct a nanoscale protected area, but also disrupts the continuity of electric field shielding. This fundamental contradiction leads power fin field-effect transistors into a technical vicious cycle of improved mobility and deteriorated reliability, urgently requiring innovative solutions. Summary of the Invention

[0004] To address the problem of three-dimensional electric field concentration caused by nanoscale trenches in SiC FINFET power devices to improve channel mobility, this invention proposes a SiC FINFET power device with an electric field shielding structure and its manufacturing method. It provides a three-dimensional electric field shielding solution that can be integrated into the fin structure, thereby reducing the electric field strength at the bottom of the trench while ensuring improved channel mobility.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a SiCFINFET power device with an electric field shielding structure, comprising: a first-type heavily doped substrate; a first-type drift region formed on the substrate; a second-type well layer formed on a current diffusion layer; a first-type source contact region and a second-type source contact region formed in the well layer; a trench penetrating the well layer; a second-type sidewall protection zone formed on the sidewall of the trench; a second-type bottom protection zone formed at the bottom of the trench, connected to the sidewall protection zone and electrically connected to the well layer; a gate oxide layer covering the inner surface of the trench; and a gate conductor filling the trench.

[0006] In this technical solution, the problem of electric field concentration in nanogrooves is solved by using a three-dimensional electric field shielding structure. While overcoming the limitation of on-resistance, it ensures the long-term reliability of the device under high-voltage switching conditions, enabling the SiC FINFET power device to have both high mobility and high reliability.

[0007] Preferably, the drift region includes a lightly doped first-type epitaxial layer formed on the substrate and a moderately doped first-type current diffusion layer located on the epitaxial layer.

[0008] Preferably, the width of the raised channels between the grooves is 50nm to 100nm to form a fin structure.

[0009] Preferably, the impurity concentration in the sidewall protection zone is greater than the impurity concentration in the current diffusion layer and less than the impurity concentration in the first type source contact region.

[0010] Preferably, the trench extends to or through the current diffusion layer, and the trench does not contact the second type source contact area.

[0011] Preferably, when the conductivity type of the first type is N-type, the conductivity type of the second type is P-type; or when the conductivity type of the first type is P-type, the conductivity type of the second type is N-type.

[0012] The present invention also employs the following technical solution: a method for manufacturing a SiC FINFET power device with an electric field shielding structure, comprising the following steps: S1, a first type drift region, a second type well layer, a first type source contact region, and a second type source contact region are sequentially formed on a first type substrate; S2, forming a trench that penetrates the well layer; S3, perform type II ion implantation on the trench sidewalls to form a sidewall protection zone; perform type II ion implantation on the trench bottom to form a bottom protection zone connected to the sidewall protection zone; S4, forming a gate oxide layer and a gate conductor within the trench.

[0013] Preferably, step S1 includes: S11, Prepare a type 1 heavily doped wafer, and form a type 1 lightly doped epitaxial layer and a type 1 medium doped current diffusion layer on the wafer; S12, a second type implantation is performed on the upper surface of the wafer to form a second type well layer with a depth not exceeding that of the current diffusion layer; S13, a first hard mask is grown on the wafer surface to form a first type source contact region with a depth lower than the depth of the well layer; S14, the first hard mask is washed away, and a second hard mask is grown on the wafer surface to form the second type source contact region.

[0014] Preferably, step S2 includes: washing away the second hard mask, growing a third hard mask on the wafer surface, and forming a plurality of trenches that are equally spaced along a first direction through the well layer on the wafer surface, wherein the trenches are spaced 50-100 nm apart in the first direction.

[0015] Preferably, step S3 includes: S31, perform type II sidewall implantation on the wafer surface to form a sidewall protection zone. The concentration of the sidewall protection zone is lower than that of the type I source contact region but higher than that of the current diffusion layer, causing part of the current diffusion layer to be inverted to type II, while the type I source contact region is not inverted. S32, without washing away the third hard mask, form a fourth hard mask on the wafer surface. After etching the wafer surface until the area at the bottom of the trench is exposed, perform type II implantation to form a bottom protection zone connected to the sidewall protection zone at the bottom of the trench.

[0016] The beneficial effects of this invention are: 1) Achieve dynamic optimization of three-dimensional electric field by using the sidewall protection zone and bottom protection zone to shield the field, thereby reducing the electric field strength at the bottom of the trench and breaking through the gate oxide breakdown bottleneck of traditional SiC FINFET; 2) Precisely adapts to nano-quantum effects, improving channel electron mobility and reducing on-resistance; 3) The second type source contact region penetrates the well layer to form an ultra-low resistance path, which increases the parasitic turn-on voltage threshold and eliminates the risk of parasitic bipolar conduction; 4) Hard mask nesting technology achieves nanometer-level positioning accuracy of the bottom protection zone, solving the problem that photolithography cannot adapt to narrow fins; 5) Dynamic equilibrium of concentration gradient electric field isolation and capacitance suppression suppresses parasitic capacitance of gate-protected area and reduces the increase in switching losses. Attached Figure Description

[0017] Figure 1 This is a top view of the wafer during step S11 of embodiment 2 of the present invention.

[0018] Figure 2 This is a top view of the wafer during step S12 of embodiment 2 of the present invention.

[0019] Figure 3 This is a top view of the wafer during step S13 of embodiment 2 of the present invention.

[0020] Figure 4 This is a cross-sectional view of the wafer along A-A' during step S13 of embodiment 2 of the present invention.

[0021] Figure 5 This is a cross-sectional view of the wafer along line B-B' during step S13 of embodiment 2 of the present invention.

[0022] Figure 6 This is a top view of the wafer during step S14 of embodiment 2 of the present invention.

[0023] Figure 7 This is a cross-sectional view of the wafer along A-A' during step S14 of embodiment 2 of the present invention.

[0024] Figure 8 This is a cross-sectional view of the wafer along line B-B' during step S14 of embodiment 2 of the present invention.

[0025] Figure 9 This is a top view of the wafer during step S2 of embodiment 2 of the present invention.

[0026] Figure 10 This is a cross-sectional view of the wafer along A-A' during step S2 of embodiment 2 of the present invention.

[0027] Figure 11 This is a cross-sectional view of the wafer along line B-B' during step S2 of embodiment 2 of the present invention.

[0028] Figure 12 This is a top view of the wafer during step S31 of embodiment 2 of the present invention.

[0029] Figure 13 This is a cross-sectional view of the wafer along A-A' during step S31 of embodiment 2 of the present invention.

[0030] Figure 14 This is a cross-sectional view of the wafer along line B-B' during step S31 of embodiment 2 of the present invention.

[0031] Figure 15 This is a cross-sectional view of the wafer along A-A' during step S32 of embodiment 2 of the present invention.

[0032] Figure 16 This is a cross-sectional view of the wafer along line B-B' during step S32 of embodiment 2 of the present invention.

[0033] Figure 17 This is a cross-sectional view of the wafer along A-A' during step S4 of embodiment 2 of the present invention.

[0034] Figure 18 This is a cross-sectional view of the wafer along line B-B' during step S4 of embodiment 2 of the present invention.

[0035] Figure 19 These are the blocking characteristic curves of devices with and without electric field shielding structures.

[0036] Figure 20 This is the electric field distribution diagram of a device without an electric field shielding structure when the drain-source voltage is 45V.

[0037] Figure 21 This is an electric field distribution diagram of a device without an electric field shielding structure when it breaks down at approximately 450V.

[0038] Figure 22 This is an electric field distribution diagram of a device with an electric field shielding structure at a drain-source voltage of 1.2kV.

[0039] Figure 23 This is an electric field distribution diagram of a device with an electric field shielding structure at a drain-source voltage of 1.8kV.

[0040] Figure 24 It is an output characteristic curve of a device with an electric field shielding structure during the process of gate-source voltage 20V and drain-source voltage rising from 0V to 2V.

[0041] Figure 25 This is a current density distribution diagram of a device with an electric field shielding structure when the drain-source voltage is 2V.

[0042] Reference numerals: 1. Type I heavily doped substrate; 2. Type I drift region; 2a. Type I epitaxial layer; 2b. Type I current diffusion layer; 3. Type II well layer; 4. Type I source contact region; 4-1. Type I hard mask; 5. Type II source contact region; 5-1. Type II hard mask; 6. Trench; 6-1. Type III hard mask; 7. Sidewall protection zone; 8. Bottom protection zone; 8-1. Type IV hard mask; 9. Gate oxide layer; 10. Gate conductor; 11. Fin width xd. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only one preferred embodiment of this invention and are only used to explain this invention. They do not limit the scope of protection of this invention. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0044] Example 1 This embodiment provides a SiC FINFET power device with an electric field shielding structure, comprising the following layered structure: a heavily doped N-type substrate forms the drain conductive channel, on which a lightly doped N-type drift region and a moderately doped N-type current diffusion layer are sequentially formed. The drift region performs high-voltage blocking function, and the current diffusion layer promotes lateral diffusion of charge carriers to reduce on-resistance. A P-type well layer is disposed above the current diffusion layer to form a well channel, and the depth of the well layer is precisely controlled to block the punch-through path.

[0045] A shallow N-type first source contact region is arranged on the surface of the well layer to reduce the source contact resistance. The P-type second source contact region, which penetrates the well layer, is heavily doped and serves as a potential anchor point for the electric field shielding structure. The trench structure penetrates the well layer and extends to or through the current diffusion layer. The trench spacing is 50-100 nm to form a fin array, triggering the quantum confinement effect to enhance gate control capability.

[0046] The trench's double sidewalls are covered with P-type sidewall protection zones, whose impurity concentration is strictly between that of the current diffusion layer and the first source contact area, forming an electric field shielding barrier. A P-type bottom protection zone is set in the central region of the trench bottom, seamlessly connecting with the sidewall protection zones to form a three-dimensional shielding network, ensuring stable potential coupling to the well layer and blocking the electric field concentration path.

[0047] The polysilicon gate electrode fills the remaining space in the trench, the source metal layer connects the first source contact area and the second source contact area, and the drain metal layer covers the back of the substrate to complete the current path.

[0048] Example 2 This embodiment provides a method for manufacturing a SiC FINFET power device with an electric field shielding structure, including the following steps.

[0049] Step S1 involves sequentially forming a first-type drift region 2, a second-type well layer 3, and a first-type source contact region 4 on a first-type heavily doped substrate 1, and forming a second-type source contact region 5 that provides stable body potential and electric field shielding. A specific embodiment of step S1 will be described in detail below with reference to the accompanying drawings. Step S1 includes the following sub-steps.

[0050] Step S11, as follows Figure 1As shown, an N-type heavily doped N+ substrate wafer is prepared. The substrate serves as the drain of the fin field-effect transistor, providing a low-resistance current path and supporting the mechanical structure of the entire device.

[0051] Then, a drift region is formed on the N+ substrate. Specifically, the drift region includes an N-type epitaxial layer 2a and an N-type current diffusion layer 2b. The N-type epitaxial layer withstands high voltage blocking, optimizes the electric field distribution, and expands the depletion region to improve the breakdown voltage. The N-type current diffusion layer laterally expands the current, reduces the specific on-resistance, and reduces the current crowding caused by the JFET effect.

[0052] In this step, the heavy doping of the substrate is relative to the drift region. In this embodiment, the drift region is a composite structure including an epitaxial layer and a current diffusion layer. The epitaxial layer is lightly doped to ensure sufficient breakdown voltage, and the current diffusion layer is moderately doped to reduce the JFET effect. The two drift regions work together, with the epitaxial layer achieving high voltage blocking and the diffusion layer adapting to the current expansion requirements of the narrow trench of the fin.

[0053] Step S12, as follows Figure 2 As shown, P-type implantation is performed on the upper surface of the wafer by generalized implantation to form a P-type well layer. The depth of the P-type well layer does not exceed that of the current diffusion layer.

[0054] Step S13, as follows Figures 3-5 As shown, a first hard mask is grown on the wafer surface, and an N+ type first source contact region is formed on the upper surface of the wafer. The depth of the first source contact region is lower than that of the P-type well layer. Figure 3 This is a top view of the wafer during step S13. Figure 4 yes Figure 3 In the cross-sectional view of A-A', Figure 5 yes Figure 3 The cross-sectional view at B-B' shows a shallow electron injection channel in the N+ type first source contact region, which can significantly reduce the source contact resistance.

[0055] like Figure 3 As shown, a first hard mask forms a covered area and an exposed area on the upper surface of the wafer. The covered area consists of several rectangular regions arranged in an array. The covered area is covered by the first hard mask, and the area outside the covered area is the exposed area, where the upper surface of the wafer is exposed. By using the first hard mask as a mask for photolithography, etching, and N-type ion implantation, an N+ type first source contact region with the same cross-sectional shape as the exposed area can be formed on the upper surface of the wafer.

[0056] Step S14, as follows Figures 6-8 As shown, the first hard mask is washed away, and a second hard mask is grown on the wafer surface. A P+ type second source contact region is formed on the upper surface of the wafer by photolithography, etching, and P-type ion implantation. Figure 6This is a top view of the wafer during step S14. Figure 7 yes Figure 6 In the cross-sectional view of A-A', Figure 8 yes Figure 6 Cross-sectional view at B-B'.

[0057] The first source contact area defines the injection window through the first hard mask, and the second source contact area defines the injection window through the second hard mask.

[0058] like Figure 6 As shown, the second hard mask has several openings, each of which is a first rectangle, and these first rectangles are arranged in an array. The second hard mask also forms a covered area and an exposed area on the upper surface of the wafer. The area where the openings of the first rectangles are located is the exposed area, and the area excluding the exposed area is the covered area. Figure 3 Corresponding to the regions shown, the area covered by the second hard mask is the exposed area of ​​the first hard mask, and vice versa. The wafer surface located in the covered area of ​​the second hard mask is covered by the second hard mask, while the wafer surface located in the exposed area of ​​the second hard mask is exposed. By using the second hard mask as a mask for photolithography, etching, and P-type ion implantation, a P+ type second source contact region with the same cross-sectional shape as the exposed area of ​​the second hard mask can be formed on the wafer surface.

[0059] In this embodiment, the depth of the P+ type second source contact region extends through the P-type well layer. On the one hand, this stabilizes the volume potential and suppresses parasitic bipolar effects; on the other hand, it provides a potential anchor point for the electric field shielding structure. In some other embodiments, the depth of the P+ type second source contact region may also extend through the current diffusion layer.

[0060] Parasitic bipolar transistors naturally exist in SiC power FINFETs. In this embodiment, the first source contact region, well layer, and drift region form a parasitic NPN transistor. When the device is turned off and subjected to high voltage, the drain electric field induces collisional ionization, and the generated holes accumulate in the well layer. If the body potential rises above its threshold voltage, the base-emitter junction of the parasitic NPN transistor is forward biased and conducts, triggering a chain failure.

[0061] In this technical solution, the reliability risk caused by parasitic bipolar effects is eliminated by using a second source contact region, avoiding the cascading failure problem caused by the accidental conduction of parasitic transistors inside the device. The heavy doping of the P+ region provides an ultra-low resistance path, forcibly clamping the body potential to the source potential and blocking the possibility of forward bias between the base and emitter of the parasitic NPN transistor.

[0062] The P+ type second source contact area is electrically connected to the subsequently formed P type protection zone to ensure that the protection zone potential is always bound to the source potential, preventing the protection zone potential from floating and causing the electric field shielding to fail, or the floating capacitor to cause tail current and thus increase switching losses.

[0063] like Figures 9-11 As shown, in step S2, the second hard mask is washed away, and a third hard mask is grown on the wafer surface. Several trenches are formed on the wafer surface by photolithography and etching, which are equally spaced along the first direction (Y direction). The trenches penetrate the P-type well layer in the depth direction, and the spacing of the trenches in the first direction is between 50-100nm.

[0064] like Figure 9 As shown, the third hard mask also has several openings, which are second rectangles arranged in an array. Notably, all the second rectangular openings of the third hard mask fall within the coverage area of ​​the second hard mask. The third hard mask also forms a coverage area and an exposed area on the upper surface of the wafer. The area where the second rectangular openings are located is the exposed area, and the area excluding the exposed area is the coverage area. The upper surface of the wafer located in the coverage area of ​​the third hard mask is covered by the third hard mask, while the upper surface of the wafer located in the exposed area of ​​the third hard mask is exposed. The third hard mask performs photolithography and etching, which can form a trench structure on the upper surface of the wafer with the same cross-sectional shape as the exposed area of ​​the third hard mask. Several trenches are formed as square grooves extending downward from the upper surface of the wafer, and several of these grooves are arranged in an array on the upper surface of the wafer.

[0065] In some other embodiments, the trenches can also penetrate the current diffusion layer in the depth direction, and the channel protrusion between two trenches forms a fin. The fins need to be relatively narrow to have the FINFET effect. In this invention, the fin width needs to meet the range of 50-100nm. Figure 9 This is a top view of the wafer during step S2. Figure 10 yes Figure 9 In the cross-sectional view of A-A', Figure 11 yes Figure 9 Cross-sectional view of B-B'.

[0066] In this embodiment, the fin width is reduced to 50-100nm, so that the gates on both sides of the channel can control the channel simultaneously, thereby causing a stereo inversion phenomenon in the channel region.

[0067] Step S3: Perform second conductive ion implantation on the sidewall of the trench to form a sidewall protection zone; perform second conductive ion implantation on the bottom of the trench to form a bottom protection zone connected to the sidewall protection zone.

[0068] In this technical solution, the third hard mask is not washed away after the sidewall implantation is completed. When performing bottom implantation positioning, the third hard mask is directly used as the self-aligned stop layer for etching the fourth hard mask, which completely avoids the alignment deviation of two independent photolithography processes and can achieve the nanometer-level deviation requirement.

[0069] Specifically, step S3 includes the following sub-steps.

[0070] Step S31, as follows Figures 12-14 As shown, Figure 12 This is a top view of the wafer during step S31. Figure 13 yes Figure 12 In the cross-sectional view of A-A', Figure 14 yes Figure 12 In the cross-sectional view of B-B', P-type sidewall implantation is performed on the wafer surface. One sidewall can be implanted alone, or both sidewalls can be implanted to form a P-type sidewall protection zone. The concentration of the protection zone is much lower than that of the first source contact region and greater than that of the current diffusion layer. The first source contact region will not be inverted, and part of the current diffusion layer is inverted to P-type.

[0071] The electric field on the sidewall of the shielded trench is protected by setting up a sidewall protection zone to prevent the gate oxide layer from breaking down.

[0072] Step S32, as follows Figures 15-16 As shown, Figure 15 This is a cross-sectional view of the wafer along line A-A' during step S32. Figure 16 This is a cross-sectional view of the wafer at B-B' during step S32. Without washing away the third hard mask, a fourth hard mask is deposited on the wafer surface. Then, the wafer surface is etched through a self-aligned process until the area at the bottom of the trench is exposed. Then, P-type implantation is performed to form a P-type bottom protection zone at the bottom of the trench. At the same time, the P-type bottom protection zone and the P-type sidewall protection zone are connected to ensure that the potential of the P-type bottom protection zone is always close to the potential of the P-type well layer.

[0073] The seamless connection between the bottom protection zone and the sidewall zone reduces the electric field strength at the bottom of the trench, thus synergistically improving device reliability.

[0074] This invention utilizes a self-aligned process to precisely control the injection width of the protected area at the bottom of the trench, thereby enabling current to continue flowing on one side of the trench, enhancing the device's conductivity, and reducing device resistance and losses.

[0075] Meanwhile, the fin width is a key parameter for achieving the FINFET effect in this invention, typically only tens of nanometers. Therefore, the bottom protection zones on both sides of the fin need to be precisely designed; otherwise, the fin may be pinched off, preventing current conduction and causing a sharp decline in the device's conductivity. Only through a self-aligned process can the trenches under the fin be precisely protected without losing their conductivity.

[0076] It should be noted that the trench is formed as a square groove extending downward from the upper surface of the wafer. The sidewall protection zone only covers the two sidewalls perpendicular to the X direction, but not the two sidewalls perpendicular to the Y direction. Correspondingly, the bottom protection zone is connected to the sidewall protection zone, covering the bottom area of ​​the trench and forming a shield on both sides of the bottom of the fin. This can reduce the short-circuit current density on the fin side under abnormal operating conditions where the device is short-circuited. Since the channel shielding effect in the area of ​​the trench sidewall not covered by the protection zone is not as obvious as that on the fin side, some current flows to the channel in the area of ​​the trench sidewall not covered by the protection zone, thus making the short-circuit current distribution more uniform, reducing device heat generation, and enhancing the short-circuit performance of the device.

[0077] Meanwhile, since the shielding area is connected to the source, under abnormal operating conditions of surge, the voltage of the device will also decrease under the same surge current, thereby reducing surge heating of the device and enhancing its robustness.

[0078] In the manufacturing process of SiC FINFET power devices, attention needs to be paid to concentration gradient control. The concentration of the protection zone must meet the requirement that the concentration of the current diffusion layer is less than the concentration of the protection zone is less than the concentration of the N+ source region. The P+ source region provides a high-concentration P-type doped anchor point for the protection zone to avoid inversion failure.

[0079] Furthermore, it is required that the P-type bottom protection zone and the P-type sidewall protection zone be connected to ensure that the potential is close to that of the P-type well layer. This requirement includes two key aspects: first, physical continuity, the bottom protection zone must be seamlessly connected to the sidewall protection zone in three-dimensional space to form a U-shaped protection ring; second, potential consistency, the sidewall protection zone is connected to the P+ type first source contact region through the P-type well layer, thereby stabilizing the potential.

[0080] In this invention, the concentration in the sidewall protection zone must be much lower than the concentration in the first source contact zone but greater than the concentration in the current diffusion layer, to ensure that the first source contact zone does not invert and the current diffusion layer partially inverts.

[0081] Specifically, the current diffusion layer is N-doped, with a concentration of 5 × 10⁻⁶. 16 cm -3 ~2×10 17 cm -3 The first source contact region is N+ doped with a concentration of 1×10⁻⁶. 19 cm 3 ~1×10 20 cm -3 The P-type injection concentration in the sidewall protected area was 1×10⁻⁶. 18 cm - 3~3×10 18 cm -3 .

[0082] Step S4, as follows Figures 17-18As shown, all masks are washed away, and an oxide layer, namely the gate oxide layer, is formed on the wafer surface through an oxidation process. Then, the gate polysilicon is formed through a deposition process. The excess oxide layer and polysilicon are removed by photolithography and etching. Finally, through some conventional metallization processes, the SiC FINFET device is formed.

[0083] The gate oxide layer is an insulating layer that fills the trench. The gate electrode is filled in the trench and wrapped around the outside of the gate oxide layer, forming three-dimensional control of the fin channel.

[0084] Traditional planar gates control only one side, while the gate electrode in this invention controls the channel simultaneously from both the side walls and the top surface of the fin through the gate oxide layer, significantly improving the gate control capability.

[0085] This invention, through a three-dimensional electric field shielding structure and a double-layer drift region design, enables SiC FINFET power devices to possess both high mobility and high reliability, enhance the control capability of the device gate, reduce the specific on-resistance of the power device, increase its power density, and enhance the device's blocking capability.

[0086] Example 3 This embodiment provides a 1.2kV silicon carbide power device manufactured using a SiCFINFET power device manufacturing method with an electric field shielding structure based on Embodiment 2. The simulation results obtained from simulating this device are described in detail below.

[0087] In this simulation, the key parameters were set as follows: the epitaxial layer concentration in the drift region was 7 × 10⁻⁶. 15 cm -3 The thickness is 10 μm; the current diffusion layer concentration is 5 × 10⁻⁶. 16 cm -3 The thickness is 1.2 μm; the fin width is 50 nm.

[0088] Figure 19 These are the blocking characteristic curves of devices with and without electric field shielding structures. The curves show that the device without electric field shielding breaks down at approximately 450V, making it unsuitable for 1.2kV voltage levels. In contrast, the device with electric field shielding achieves a breakdown voltage of 1.8kV, providing approximately 50% voltage margin for use in 1.2kV applications.

[0089] Meanwhile, in order to improve the reliability of silicon carbide power devices and ensure their stable operation over a long period of time, the electric field strength of the device oxide layer needs to be controlled within 3MV / cm. Figure 20 The electric field distribution of the device without electric field shielding structure is shown when the drain-source voltage is 45V, at which point the electric field of the gate oxide reaches 3MV / cm. Figure 21This shows the electric field distribution of the device when it breaks down at about 450V. It can be seen that the electric field strength of the gate oxide at this time exceeds 6MV / cm, which is far beyond the normal electric field range that the oxide can withstand.

[0090] Figure 22 The electric field distribution of the device with an electric field shielding structure at a drain-source voltage of 1.2kV is presented. As can be seen from the figure, the maximum electric field of the device is concentrated between the P-shielding region and the current diffusion layer. The electric field of the gate oxide is effectively shielded by the P-shielding region, and its maximum electric field is only 2MV / cm. This structure ensures that the device can operate stably and reliably at a voltage level of 1.2kV. Figure 23 The electric field distribution of the device at a drain-source voltage of 1.8kV is shown, which shows that the electric field of the gate oxide can still be well shielded.

[0091] Figure 24 The output characteristic curves of the device with an electric field shielding structure are shown as follows: gate-source voltage 20V, drain-source voltage rises from 0V to 2V. The curves demonstrate that the device exhibits excellent output characteristics, with a specific on-resistance of approximately 2mΩ·cm. 2 . Figure 25 This shows the current density distribution of the device when the drain-source voltage is 2V. It can be observed that the channel region of the device has undergone stereo inversion and has become a channel for conducting current.

Claims

1. A SiC FINFET power device with an electric field shielding structure, characterized in that, include: A first-type heavily doped substrate (1); a first-type drift region (2) formed on the substrate; a second-type well layer (3) formed on the drift region; a first-type source contact region (4) and a second-type source contact region (5) formed in the well layer; a trench (6) penetrating the well layer; a second-type sidewall protection zone (7) formed on the sidewall of the trench; a second-type bottom protection zone (8) formed at the bottom of the trench, connected to the sidewall protection zone and electrically connected to the well layer; a gate oxide layer (9) covering the inner surface of the trench; and a gate conductor (10) filling the trench.

2. The SiC FINFET power device with an electric field shielding structure according to claim 1, characterized in that, The drift region includes a lightly doped first-type epitaxial layer (2a) formed on the substrate and a medium-doped first-type current diffusion layer (2b) located on the epitaxial layer.

3. A SiC FINFET power device with an electric field shielding structure according to claim 1, characterized in that, The spacing between two adjacent trenches in the first direction is 50 nm to 100 nm.

4. A SiC FINFET power device with an electric field shielding structure according to claim 1, characterized in that, The impurity concentration in the sidewall protection zone is greater than that in the current diffusion layer but less than that in the first type of source contact zone.

5. A SiC FINFET power device with an electric field shielding structure according to claim 1 or 3, characterized in that, The trench extends to or through the current diffusion layer, and the trench does not contact the second type source contact area.

6. A SiC FINFET power device with an electric field shielding structure according to claim 1, 3, or 4, characterized in that, When the conductivity type of the first type is N-type, the conductivity type of the second type is P-type; or when the conductivity type of the first type is P-type, the conductivity type of the second type is N-type.

7. A method for manufacturing a SiC FINFET power device with an electric field shielding structure, realizing the SiC FINFET power device with an electric field shielding structure as described in any one of claims 1-6, characterized in that, Includes the following steps: S1, a first type drift region, a second type well layer, a first type source contact region, and a second type source contact region are sequentially formed on a first type substrate; S2, forming a trench that penetrates the well layer; S3, perform type II ion implantation on the trench sidewalls to form a sidewall protection zone; perform type II ion implantation on the trench bottom to form a bottom protection zone connected to the sidewall protection zone; S4, forming a gate oxide layer and a gate conductor within the trench.

8. The method for manufacturing a SiC FINFET power device with an electric field shielding structure according to claim 7, characterized in that, Step S1 includes: S11, Prepare a type 1 heavily doped wafer, and form a type 1 lightly doped epitaxial layer and a type 1 medium doped current diffusion layer on the wafer; S12, a second type implantation is performed on the upper surface of the wafer to form a second type well layer with a depth not exceeding that of the current diffusion layer; S13, a first hard mask is grown on the wafer surface to form a first type source contact region with a depth lower than the depth of the well layer; S14, the first hard mask is washed away, and a second hard mask is grown on the wafer surface to form the second type source contact region.

9. A method for manufacturing a SiC FINFET power device with an electric field shielding structure according to claim 7, characterized in that, Step S2 includes: washing away the second hard mask, growing a third hard mask on the wafer surface, and forming a plurality of trenches that are equally spaced along a first direction through the well layer on the wafer surface, wherein the trenches are spaced 50-100 nm apart in the first direction.

10. A method for manufacturing a SiC FINFET power device with an electric field shielding structure according to claim 7, 8, or 9, characterized in that, Step S3 includes: S31, a second type sidewall implantation is performed on the wafer surface to form a sidewall protection zone. The concentration of the sidewall protection zone is lower than the concentration of the first type source contact region but higher than the concentration of the current diffusion layer, causing part of the current diffusion layer to be inverted to the second type, while the first type source contact region is not inverted. S32, without washing away the third hard mask, forms a fourth hard mask on the wafer surface, and after general etching the wafer surface until the area at the bottom of the trench is exposed, performs type II implantation to form a bottom protection zone connected to the sidewall protection zone at the bottom of the trench.

Images