Semiconductor device

Abstract

The invention provides a semiconductor device, relates to the technical field of semiconductor chips, and aims to solve the problem of non-uniform electric field distribution of the semiconductor device. The semiconductor device comprises a substrate, an epitaxial layer, a source electrode, a drain electrode, a grid electrode and an electric field modulation region, the epitaxial layer is arranged on the substrate; the source electrode, the drain electrode and the grid electrode are embedded in the epitaxial layer; the electric field modulation region is arranged on one side, far away from the substrate, of the epitaxial layer and is embedded in the epitaxial layer; the electric field modulation region comprises a first electric field modulation sub-region and a second electric field modulation sub-region which are connected with each other, and the second electric field modulation sub-region comprises a first part and a second part; the first part is located at one side of the first electric field modulation sub-region away from the substrate, and the second part is located at one side of the first electric field modulation sub-region away from the drain electrode; the first part is connected with the second part, the doping type of the first electric field modulation sub-region is the same as that of the epitaxial layer, and the doping type of the second electric field modulation sub-region is different from that of the epitaxial layer; and the doping type is P-type doping and N-type doping.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and more particularly to a semiconductor device. Background Technology

[0002] In semiconductor devices, uneven electric field distribution can lead to excessively high local electric fields, which can cause problems such as breakdown or degraded performance of semiconductor devices. Summary of the Invention

[0003] Embodiments of this disclosure provide a semiconductor device aimed at solving the problem of uneven electric field distribution in semiconductor devices.

[0004] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions: A semiconductor device is provided. The semiconductor device includes: a substrate, an epitaxial layer, a source, a drain, a gate, and an electric field modulation region.

[0005] An epitaxial layer is disposed on a substrate. The source, drain, and gate are disposed on the side of the epitaxial layer away from the substrate. The source and drain are embedded in the epitaxial layer, and the gate is located between the source and drain.

[0006] An electric field modulation region is located on the side of the epitaxial layer away from the substrate and is embedded in the epitaxial layer. The electric field modulation region includes a first electric field modulation sub-region and a second electric field modulation sub-region. The second electric field modulation sub-region includes a first part and a second part. The first part is located on the side of the first electric field modulation sub-region away from the substrate, and the second part is located on the side of the first electric field modulation sub-region away from the drain. The first part and the second part are connected. The doping type of the first electric field modulation sub-region is the same as the doping type of the epitaxial layer, and the doping type of the second electric field modulation sub-region is different from the doping type of the epitaxial layer. The doping types are P-type doping and N-type doping.

[0007] The semiconductor device provided in the above embodiments of this disclosure, by setting a second electric field modulator region covering the surface of the first electric field modulator region away from the substrate, and the doping type of the second electric field modulator region being different from the doping type of the epitaxial layer, forms an alternating charge interface with different doping characteristics in the channel region of the semiconductor device. A space charge region (interface potential difference) is formed at the interface, such as a PN junction. The charge interface generates a built-in electric field, thereby introducing a new electric field distribution on the surface of the electric field modulator region to adjust the surface electric field distribution of the semiconductor device, causing the electric field lines to bend at the interface, avoiding the electric field concentration on the surface of the drain and source regions, thereby achieving a uniform distribution of the electric field across the entire surface of the semiconductor device, significantly improving the breakdown voltage capability of the semiconductor device; moreover, the doping type of the first electric field modulator region is the same as that of the epitaxial layer (e.g., both are N-type or P-type), which can ensure the electrical continuity between the first electric field modulator region, the second electric field modulator region and the epitaxial layer, optimize the flow of charge carriers in the semiconductor device, increase the effective charge carrier density of the overall epitaxial layer, and reduce the on-resistance of the semiconductor device. Moreover, the first part is located on the side of the first electric field modulator region away from the substrate, that is, closer to the gate; the second part is located on the side of the first electric field modulator region away from the drain, closer to the source region, which can improve the electric field gradient between the drain region and the electric field modulation region, optimize the electric field distribution between the drain region and the electric field modulation region, thereby reducing the risk of breakdown caused by a higher electric field.

[0008] In some embodiments, the ion doping concentration of the second electric field modulator region is greater than the ion doping concentration of the first electric field modulator region.

[0009] In some embodiments, the ion doping concentration of the first electric field modulator region is greater than the ion doping concentration of the epitaxial layer.

[0010] In some embodiments, the semiconductor device includes a plurality of electric field modulation regions arranged along a first direction, which is the direction from the source to the drain. Of any two adjacent electric field modulation regions, the one closer to the source is the first electric field modulation region, and the one closer to the drain is the second electric field modulation region. A first portion of the first electric field modulation region is shared with a second portion of the second electric field modulation region.

[0011] In some embodiments, the distance from the surface of the plurality of first electric field modulator regions away from the substrate to the surface of the second electric field modulator region away from the substrate gradually decreases along a first direction.

[0012] In some embodiments, the distance between the surface of a plurality of first electric field modulator regions near the substrate and the surface of a second electric field modulator region away from the substrate gradually decreases along a first direction.

[0013] In some embodiments, the interface between the plurality of first electric field modulator regions and the second electric field modulator regions has a stepped morphology.

[0014] In some embodiments, the interface between the plurality of first electric field modulator subregions and the epitaxial layer has a stepped morphology.

[0015] In some embodiments, the ion doping concentration of the plurality of first electric field modulator regions gradually increases along a first direction.

[0016] In some embodiments, the second electric field modulation sub-region further includes a third portion, which is located on the side of the first electric field modulation sub-region near the drain, and there is a gap between the third portion and the drain; the third portion is connected to the first portion.

[0017] In some embodiments, the semiconductor device includes a plurality of electric field modulation regions arranged along a first direction, which is the direction from the source to the drain. In any two adjacent electric field modulation regions, the electric field modulation region closer to the source is the first electric field modulation region, and the electric field modulation region closer to the drain is the second electric field modulation region; the third portion of the first electric field modulation region is shared with the second portion of the second electric field modulation region.

[0018] In some embodiments, the ion doping concentration of the plurality of first electric field modulator regions gradually increases along a first direction.

[0019] In some embodiments, the dimensions of a plurality of first electric field modulator subregions gradually increase along a first direction.

[0020] In some embodiments, the number of first electric field modulation sub-regions is one; the ratio of the size of the first electric field modulation sub-region along the first direction to the size of the electric field modulation region along the first direction is in the range of 0.1 to 0.9; the first direction is the direction from the source to the drain.

[0021] In some embodiments, there are multiple first electric field modulation sub-regions, and the multiple first electric field modulation sub-regions are arranged along a first direction; the ratio of the sum of the dimensions of the multiple first electric field modulation sub-regions along the first direction to the dimension of the electric field modulation region along the first direction is in the range of 0.1 to 0.9. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0023] Figure 1 This is a schematic diagram of the structure of an electronic device provided in some embodiments according to the present disclosure; Figure 2 This is a schematic diagram of the structure of a semiconductor device provided in some embodiments of the present disclosure; Figure 3 This is a schematic diagram of the structure of a semiconductor device provided in some embodiments of the present disclosure; Figure 4 This is a schematic diagram of the structure of a semiconductor device provided in some embodiments of the present disclosure; Figure 5 This is a schematic diagram of the structure of a semiconductor device provided in some embodiments of the present disclosure; Figure 6 This is a schematic diagram of the structure of a semiconductor device provided in some embodiments of the present disclosure; Figure 7 This is a schematic diagram of the structure of a semiconductor device provided in some embodiments of the present disclosure; Figure 8 This is a flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of the present disclosure; Figure 9 This is a structural diagram corresponding to each step in the method for preparing a composite substrate according to Example 1 of this disclosure; Figure 10 This is a structural diagram corresponding to each step in the preparation method of a composite substrate provided in Example 2 of this disclosure; Figure 11 This is a structural diagram corresponding to each step in the preparation method of a composite substrate provided in Example 3 of this disclosure. Detailed Implementation

[0024] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0025] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0026] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, materials, or characteristics may be included in any suitable manner in any one or more embodiments or examples.

[0027] In the following description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0028] In addition, the use of "based on" implies openness and inclusivity, because processes, steps, calculations or other actions "based on" one or more conditions or values ​​can in practice be based on additional conditions or values ​​beyond those conditions.

[0029] As used herein, “about,” “approximately,” or “approximately” includes the value stated and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0030] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0031] As used herein, the term "substrate" refers to a material on which subsequent layers of material can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire substrate.

[0032] The technical terms used in the embodiments of this application are explained below: Semiconductor: A semiconductor is a material whose conductivity at room temperature is between that of a conductor and an insulator; semiconductors include intrinsic semiconductors and impurity semiconductors. A pure semiconductor without impurities or defects, in which the concentration of electrons and holes is equal, is called an intrinsic semiconductor. A semiconductor doped with a certain amount of impurities is called an impurity semiconductor or an intrinsic semiconductor. When the impurities doped into an impurity semiconductor can provide a certain concentration of charge carriers (such as holes or electrons), the conductivity of the intrinsic semiconductor can be improved. Generally, the higher the charge carrier concentration, the lower the resistivity of the semiconductor and the better the conductivity. In the embodiments of this application, this type of impurity semiconductor is also called a conductive semiconductor, for example, conductive silicon carbide material doped with nitrogen (N), boron (B), aluminum (Al), etc. Furthermore, when impurities doped into an impurity semiconductor can compensate for impurities, the donor electrons are just enough to fill the acceptor level, but cannot provide electrons and holes to the conduction and valence bands, resulting in a semiconductor material with a wide bandgap having a resistivity similar to that of an insulator. For example, in the embodiments of this application, doping silicon carbide with transition metals achieves impurity compensation, thereby increasing the resistivity of the silicon carbide material. This type of impurity semiconductor is also called a semi-insulating semiconductor or a semi-insulator, or has semi-insulating characteristics.

[0033] Unless otherwise defined, all technical terms used herein have the same meaning as those known to one of ordinary skill in the art. In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c can be single or multiple. Furthermore, in the embodiments of this application, the words "first," "second," etc., do not limit the quantity or order.

[0034] Furthermore, in this application, directional terms such as "upper" and "lower" are defined relative to the orientation of the components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings.

[0035] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0036] The technical solution of this application can be applied to electronic devices, such as computers, mobile phones, tablets, wearable devices, and vehicle-mounted devices, as well as network devices such as base stations. The electronic device can also be a power amplifier or similar device used in the aforementioned electronic devices. This application does not impose any special limitations on the specific form of the aforementioned electronic devices.

[0037] like Figure 1 As shown, this disclosure provides an electronic device 1000. The electronic device 1000 can be a fast charger, an uninterruptible power supply (UPS), a power motor, or other electronic devices.

[0038] Continue to refer to Figure 1 The electronic device 1000 includes a chip 1001 and a circuit board 1002. The chip 1001 and the circuit board 1002 are electrically connected. The circuit board 1002 converts the external power supply into the voltage or current required for the chip 1001 to operate.

[0039] For example, circuit board 1002 may include a printed circuit board (PCB) or the like.

[0040] For example, circuit board 1002 may include multiple conductive layers. The multiple conductive layers within circuit board 1002 may be separated from each other by dielectric layers.

[0041] Embodiments of this disclosure provide a chip 1001. The chip 1001 includes a semiconductor device.

[0042] Understandably, chip 1001 is part of an electronic device and serves as a carrier for integrated circuits. Semiconductor devices are devices whose conductivity lies between that of conductors and insulators, and can be used to make rectifiers, diodes, transistors, integrated circuits, and so on.

[0043] Embodiments of this disclosure provide a semiconductor device 300. For example... Figure 2 As shown, the semiconductor device 300 includes: a substrate 301, an epitaxial layer 303, a source 306, a drain 307, a gate 311, and an electric field modulation region 390.

[0044] The epitaxial layer 303 is disposed on the substrate 301.

[0045] The source 306, drain 307, and gate 311 are disposed on the side of the epitaxial layer 303 away from the substrate 301. The source 306 and drain 307 are embedded in the epitaxial layer 303, and the gate 311 is located between 306 and drain 307.

[0046] Substrate 301 serves as the base layer of semiconductor device 300, providing a support structure.

[0047] For example, the material of substrate 301 may be silicon carbide.

[0048] The epitaxial layer 303 is a semiconductor layer grown on the substrate 301. It is used to form the active region of the semiconductor device 300 and can provide semiconductor materials with excellent crystal quality. It is used to form the source 306, drain 307 and gate 311 regions to control the current flow path and adjust the performance of the semiconductor device 300.

[0049] For example, such as Figure 3 As shown, an epitaxial sublayer 302 can be disposed between the substrate 301 and the epitaxial layer 303. The conductivity type of the epitaxial sublayer 302 is opposite to that of the substrate 301; the conductivity type of the epitaxial layer 303 is opposite to that of the epitaxial sublayer 302. The doping type is P-type doping and N-type doping. For example, the substrate 301 is N-type doped, the epitaxial sublayer 302 is P-type doped, and the epitaxial layer 303 is N-type doped. Alternatively, the substrate 301 is P-type doped, the epitaxial sublayer 302 is N-type doped, and the epitaxial layer 303 is P-type doped.

[0050] The source 306 serves as the current input terminal, introducing charge carriers into the semiconductor device 300 and embedding them in the epitaxial layer 303, which helps to form good electrical contact.

[0051] The drain 307 serves as the current output terminal, allowing charge carriers to flow to the external circuit through the epitaxial layer. Embedded in the epitaxial layer, it facilitates the flow of charge carriers.

[0052] In some examples, such as Figure 3As shown, the semiconductor device 300 further includes a well region 304 and a body region 305, embedded in the epitaxial layer 303. The well region 304 covers the surface of the body region 305 near the substrate 301, the surface of the source 306 near the substrate 301, and the surface of the source 306 near the drain 307. The body region 305 is located on the side of the source 306 away from the drain 307 and is in contact with the source 306.

[0053] Well region 304 is used to control the carrier type and concentration, forming a shallow channel (N-type or P-type), with the opposite conductivity type to that of epitaxial layer 303. Body region 305 can adjust and control the threshold voltage of semiconductor device 300, and the conductivity type of body region 305 is the same as that of well region 304.

[0054] The gate 311 is located between the source 306 and the drain 307. By applying voltage, the formation and disconnection of the channel are controlled, the carrier flow across the source 306 and the drain 307 is adjusted, and the conduction and cutoff of the channel are controlled to achieve switching or amplification.

[0055] In some examples, such as Figure 3 As shown, the gate oxide layer 310 is located between the gate 311 and the epitaxial layer 303. The gate oxide layer 310 serves as an insulating layer between the gate 311 and the channel, preventing current from directly entering the channel through the gate 311.

[0056] The semiconductor device 300 is a laterally diffused metal-oxide-semiconductor (LDMOS). Unlike the vertical structure of a typical MOSFET, LDMOS employs a lateral double-diffusion structure. This structure results in a lower drain current density (307) and thus allows it to withstand higher voltages and power. LDMOS devices consist of N-type and P-type materials, with the N-type material sandwiched between two P-type materials. Electrons move within the N-type region, enabling conductivity. However, this process suffers from uneven electric field distribution. For example, differences in channel and drift region lengths lead to varying local electric fields, resulting in uneven electric field gradients. Furthermore, variations in doping concentration and incomplete diffusion during the double-diffusion process can cause concentrated electric fields, forming localized electric field spikes.

[0057] Based on this, embodiments of the present disclosure provide a semiconductor device 300. For example... Figure 2As shown, the semiconductor device 300 further includes an electric field modulation region 390. The electric field modulation region 390 is disposed on the side of the epitaxial layer 303 away from the substrate 301 and is embedded in the epitaxial layer 303. The electric field modulation region 390 includes a first electric field modulation sub-region 391 and a second electric field modulation sub-region 392. The second electric field modulation sub-region 392 includes a first portion 392A and a second portion 392B. The first portion 392A is located on the side of the first electric field modulation sub-region 391 away from the substrate 301, and the second portion 392B is located on the side of the first electric field modulation sub-region 391 away from the drain 307. The first portion 392A and the second portion 392B are connected.

[0058] The first electric field modulation sub-region 391 has the same doping type as the epitaxial layer 303, while the second electric field modulation sub-region 392 has a different doping type than the epitaxial layer 303. The doping types are P-type and N-type doping.

[0059] For example, if the epitaxial layer 303 is N-type doped and the first electric field modulation sub-region 391 is N-type doped, then the second electric field modulation sub-region 392 is P-type doped. Similarly, if the epitaxial layer 303 is P-type doped and the first electric field modulation sub-region 391 is P-type doped, then the second electric field modulation sub-region 392 is N-type doped.

[0060] The electric field modulation region 390 is used to adjust the surface electric field distribution in the semiconductor device 300. A second electric field modulation sub-region 392 is provided to cover the surface of the first electric field modulation sub-region 391 away from the substrate 301. The doping type of the second electric field modulation sub-region 392 is different from that of the epitaxial layer 303, resulting in an alternating charge interface with different doping characteristics in the channel region of the semiconductor device 300. A space charge region (interface potential difference), such as a PN junction, is formed at the interface. This charge interface generates a built-in electric field, thereby introducing a new electric field distribution on the surface of the electric field modulation region 390 to adjust the surface electric field distribution of the semiconductor device 300, thus enabling the electric field to... The field lines bend at the interface to avoid the electric field from concentrating on the surface of the drain 307 region and the source 306 region, thereby achieving a uniform distribution of the electric field across the entire surface of the semiconductor device 300 and significantly improving the breakdown voltage capability of the semiconductor device 300. Moreover, the doping type of the first electric field modulator region 391 is the same as that of the epitaxial layer 303 (e.g., both are N-type or P-type), which can ensure the electrical continuity between the first electric field modulator region 391, the second electric field modulator region 392 and the epitaxial layer 303, optimize the flow of charge carriers in the semiconductor device 300, increase the effective charge carrier density of the overall epitaxial layer 303, and reduce the on-resistance of the semiconductor device 300.

[0061] Moreover, the first part 392A is located on the side of the first electric field modulation sub-region 391 away from the substrate 301, that is, closer to the gate 311; the second part 392B is located on the side of the first electric field modulation sub-region 391 away from the drain 307, and closer to the source 306. This can improve the electric field gradient between the drain 307 region and the electric field modulation region 390, optimize the electric field distribution between the drain 307 region and the electric field modulation region 390, thereby reducing the risk of breakdown caused by a higher electric field.

[0062] In some embodiments, the ion doping concentration of the second electric field modulator region 392 is greater than the ion doping concentration of the first electric field modulator region 391.

[0063] Understandably, the second electric field modulator region 392 has a higher ion doping concentration than the first electric field modulator region 391, resulting in a higher space charge density. This allows for the formation of a stronger built-in electric field at the interface between the first and second electric field modulator regions 391 and 392. This more effectively regulates the electric field distribution, slows down or modulates the transmission of external voltage in the semiconductor device 300, reduces local electric field peaks, and prevents the formation of spikes in local areas, thereby increasing the breakdown voltage of the semiconductor device 300. Furthermore, the higher doping concentration in the second electric field modulator region 392 increases the carrier concentration and the number of activated carriers, making it easier for current to pass through and thus reducing the specific on-resistance of the semiconductor device 300.

[0064] In some embodiments, the ion doping concentration of the first electric field modulator region 391 is greater than the ion doping concentration of the epitaxial layer 303.

[0065] Understandably, on the one hand, compared to the ion doping concentration of the epitaxial layer 303, the ion doping concentration of the first electric field modulator region 391 is higher, which allows the first electric field modulator region 391 to enhance the electric field modulation effect, improve the electric field distribution, and enable smoother injection and collection of charge carriers, thereby reducing the specific on-resistance of the semiconductor device 300. On the other hand, in the fabrication process of the semiconductor device 300, after ion implantation of the higher ion doping concentration epitaxial layer 303, ion implantation of the higher ion doping concentration first electric field modulator region 391 is easier and more feasible in terms of fabrication process, thereby simplifying the process and improving the reliability of the semiconductor device 300 fabrication.

[0066] In some embodiments, there is a gap between the electric field modulation region 390 and the drain 307.

[0067] Understandably, by setting a gap between the electric field modulation region 390 and the drain 307, unnecessary current leakage or stray current can be reduced, the withstand voltage performance of the semiconductor device 300 can be improved, and uncontrolled electric field interference can be prevented. It can also adjust the electric field distribution inside the semiconductor device 300, avoid the electric field from concentrating in local areas, reduce the risk of breakdown, reduce stress concentration of the semiconductor device 300 under high voltage operating conditions, and improve the reliability and lifespan of the semiconductor device 300.

[0068] In some embodiments, the second portion 392B of the second electric field modulation sub-region 392 is adjacent to the surface of the substrate 301 and is coplanar with the surface of the first electric field modulation sub-region 391 adjacent to the substrate 301.

[0069] Understandably, the above configuration, on the one hand, allows the second electric field modulation sub-region 392 and the first electric field modulation sub-region 391 of the electric field modulation region 390 to be arranged on the same plane near the surface of the substrate 301 without height differences, which helps to form continuous and smooth electric field lines between the electric field modulation regions 390 and avoid local spikes; on the other hand, the coplanar structure is conducive to the control of flatness in the semiconductor device 300 fabrication process, helps to achieve consistency in thin-layer processes, and improves the matching between the electric field and the semiconductor device 300 structure.

[0070] In some embodiments, the surface of the first portion 392A of the second electric field modulator region 392 near the drain 307 is coplanar with the surface of the first electric field modulator region 391 near the drain 307.

[0071] Understandably, the above configuration allows the surface of the first portion 392A of the second electric field modulation sub-region 392 near the drain 307 to be on the same plane as the surface of the first electric field modulation sub-region 391 near the drain 307. This helps to achieve a uniform electric field between the drain 307 and the electric field modulation region 390, allowing the electric field lines to transition smoothly between the drain 307 and the electric field modulation region 390. The electric field intensity changes gradually from the drain 307 to the electric field modulation region 390, which helps to achieve consistent charge control throughout the modulation region 390.

[0072] In some embodiments, such as Figure 4 As shown, the semiconductor device 300 includes a plurality of electric field modulation regions 390, which are arranged along a first direction X, where the first direction X is the direction from the source 306 to the drain 307.

[0073] For example, the semiconductor device 300 may include 2, 3, 4, or 5 electric field modulation regions 390. In this case, the first electric field modulation sub-region 391 may have 2, 3, 4, or 5 regions, and the second electric field modulation sub-region 392 may have 2, 3, 4, or 5 regions, for example, as shown in the example. Figure 4In one example shown, when there are three electric field modulation regions 390, the first electric field modulation sub-region 391 may include: a first sub-region 3911, a second sub-region 3912, and a third sub-region 3913.

[0074] Of any two adjacent electric field modulation regions 390, the electric field modulation region 390 closer to the source 306 is the first electric field modulation region 3901, and the electric field modulation region 390 closer to the drain 307 is the second electric field modulation region 3902. The first part 392A of the first electric field modulation region 3901 is shared with the second part 390B of the second electric field modulation region 3902.

[0075] For example, such as Figure 4 As shown, in two adjacent electric field modulation regions 390, for example, the first electric field modulation sub-region 391 in the first electric field modulation region 3901 is the first sub-region 3911, and the first electric field modulation sub-region 391 in the second electric field modulation region 3902 is the second sub-region 3912; the first part 392A of the second electric field modulation sub-region 392 located on the side of the first sub-region 3911 away from the substrate 301 is shared with the second part 392B of the second electric field modulation sub-region 392 located on the side of the second sub-region 3912 away from the drain 307. For example, the first electric field modulation sub-region 391 in the second electric field modulation region 3902 is the second sub-region 3912; the first electric field modulation sub-region 391 in the third electric field modulation region 3903 is the third sub-region 3913; the first part 392A of the second electric field modulation sub-region 392 located on the side of the second sub-region 3912 away from the substrate 301 is shared with the second part 392B of the second electric field modulation sub-region 392 located on the side of the second sub-region 3912 away from the drain 307.

[0076] Understandably, the multiple first electric field modulation sub-regions 391 can achieve the superposition of local modulations, and the multiple first electric field modulation sub-regions 391 are arranged along the direction from the source 306 to the drain 307, which helps to gradually guide the transport of charge carriers, reduce electric field abrupt changes, and smooth the flow of charge carriers; and, through the position setting of the multiple first electric field modulation sub-regions 391 and the second electric field modulation sub-regions 392, a gentler electric field gradient can be formed in the epitaxial layer 303 surface region far away from the substrate 301, reducing electric field distortion and local sharp electric fields, and further making the electric field distribution more uniform.

[0077] In some embodiments, the distance between the surface of the plurality of first electric field modulator regions 391 away from the substrate 301 and the surface of the second electric field modulator region 392 away from the substrate 301 gradually decreases along the first direction X.

[0078] For example, such as Figure 4As shown, when there are three first electric field modulation sub-regions 391, the distance from the surface of the first sub-region 3911 away from the substrate 301 to the surface of the second electric field modulation sub-region 392 away from the substrate 301 is L1; the distance from the surface of the second sub-region 3912 away from the substrate 301 to the surface of the second electric field modulation sub-region 392 away from the substrate 301 is L2; ​​the distance from the surface of the third sub-region 3913 away from the substrate 301 to the surface of the second electric field modulation sub-region 392 away from the substrate 301 is L3; and L1 > L2 > L3.

[0079] Alternatively, in some embodiments, the distance between the surface of the plurality of first electric field modulator regions 391 near the substrate 301 and the surface of the second electric field modulator region 392 away from the substrate 301 gradually decreases along the first direction X.

[0080] For example, such as Figure 5 As shown, when there are three first electric field modulation sub-regions 391, the distance from the surface of the first sub-region 3911 near the substrate 301 to the surface of the second electric field modulation sub-region 392 away from the substrate 301 is L1. * The distance from the surface of the second sub-region 3912 near the substrate 301 to the surface of the second electric field modulation sub-region 392 away from the substrate 301 is L2. * The distance from the surface of the third sub-region 3913 near the substrate 301 to the surface of the second electric field modulation sub-region 392 away from the substrate 301 is L3. * And L1 * >L2 * >L3 * .

[0081] Understandably, the above settings enable the electric field to gradually transition between multiple first electric field modulator regions 391 along the first direction X, ensuring smooth transmission of charge carriers along the first direction X, reducing reverse drift and stagnation, avoiding abrupt changes or distortions in the electric field, forming smooth electric field changes, realizing multi-level modulation, and further making the electric field distribution more uniform.

[0082] In some embodiments, the interfaces between the plurality of first electric field modulation sub-regions 391 and the first electric field modulation sub-regions 391 have a stepped morphology.

[0083] Alternatively, in some embodiments, the interfaces between the plurality of first electric field modulator sub-regions 391 and the epitaxial layer 303 have a stepped morphology.

[0084] Understandably, the above settings enable multiple first electric field modulator sub-regions 391 to further achieve multi-level control and a smoother electric field distribution.

[0085] In some embodiments, the surface of the first portion 392A of the second electric field modulation sub-region 392 near the drain 307 is coplanar with the surface of the first electric field modulation sub-region 391 closest to the drain 307 among a plurality of first electric field modulation sub-regions 391.

[0086] For example, such as Figure 5 As shown, when there are three first electric field modulation sub-regions 391, the first electric field modulation sub-region 391 closest to the drain 307 is the third sub-region 3913. That is, the first part 392A of the second electric field modulation sub-region 392 is close to the surface of the drain 307 and is coplanar with the surface of the third sub-region 3913 close to the drain 307.

[0087] Understandably, the above configuration can enable a smooth transition of the electric field in the region near the drain 307 of the semiconductor device 300, avoid electric field concentration caused by surface deviation, thereby reducing the risk of breakdown of the semiconductor device 300 and improving the reliability of the semiconductor device 300.

[0088] In some embodiments, the second portion 392B of the second electric field modulation sub-region 392 is close to the surface of the substrate 301 and is coplanar with the surface of the first electric field modulation sub-region 391 that is furthest from the drain 307 among the plurality of first electric field modulation sub-regions 391 that is close to the substrate 301.

[0089] For example, such as Figure 5 As shown, when there are three first electric field modulation sub-regions 391, the first electric field modulation sub-region 391 that is furthest from the drain 307 is the first sub-region 3911, that is, the second part 392B of the second electric field modulation sub-region 392 is close to the surface of the substrate 301, and the first sub-region 3911 is close to the surface of the substrate 301.

[0090] Understandably, the above configuration can help form a uniform electric field distribution in the region of the semiconductor device 300 near the substrate 301, reduce partial discharge, enable gradual modulation of the electric field, reduce abrupt changes, and increase the withstand voltage performance of the semiconductor device 300.

[0091] In some embodiments, the ion doping concentration of the plurality of first electric field modulator subregions 391 gradually increases along the first direction X.

[0092] For example, such as Figure 5 As shown, when there are three first electric field modulation sub-regions 391, the ion doping concentration of the first sub-region 3911 is less than the ion doping concentration of the second sub-region 3912, which is less than the ion doping concentration of the third sub-region 3913.

[0093] Understandably, along the first direction X, as the ion doping concentration of the multiple first electric field modulator regions 391 gradually increases, the conductivity of the semiconductor device 300 is enhanced, resulting in a decrease in the specific on-resistance of the semiconductor device 300.

[0094] In some embodiments, such as Figure 6 As shown, the second electric field modulation sub-region 392 also includes a third portion 392C. The third portion 392C is located on the side of the first electric field modulation sub-region 391 near the drain 307, and there is a gap between the third portion 392C and the drain 307. The third portion 392C is connected to the first portion 392A.

[0095] Understandably, the third part 392C can reduce the electric field spike in the region between the first electric field modulator region 391 and the drain 307, thereby reducing leakage current, making the electric field more uniform, and avoiding excessively high local electric fields. Furthermore, the distance between the third part 392C and the drain 307 helps to reduce the electric field strength in this region, reduce local electric field distortion and the risk of breakdown caused by high electric fields, and improve the device's withstand voltage capability.

[0096] In some embodiments, the second portion 392B of the second electric field modulation sub-region 392 is adjacent to the surface of the substrate 301, the surface of the first electric field modulation sub-region 391 adjacent to the substrate 301, and the surface of the third portion 392C of the second electric field modulation sub-region 392 adjacent to the substrate 301 are coplanar.

[0097] Understandably, the above configuration allows the second part 392B to be close to the surface of the substrate 301, the surface of the first electric field modulator region 391 close to the substrate 301, and the surface of the third part 392C of the second electric field modulator region 392 close to the substrate 301 to be on the same plane, forming a continuous interface, which helps to form a continuous and smooth electric field distribution, and further makes the electric field distribution more uniform.

[0098] In some embodiments, the semiconductor device 300 includes a plurality of electric field modulation regions 390, which are arranged along a first direction X, where the first direction X is the direction from the source 306 to the drain 307.

[0099] For example, the semiconductor device 300 may include 2, 3, 4, or 5 electric field modulation regions 390. In this case, it may include a first electric field modulation sub-region 391, which may be 2, 3, 4, or 5, and a second electric field modulation sub-region 392, which may be 2, 3, 4, or 5, for example, as... Figure 7 In one example shown, when there are two electric field modulation regions 390, the first electric field modulation sub-region 391 includes: a first sub-region 3911 and a second sub-region 3912.

[0100] In any two adjacent electric field modulation regions 390, the electric field modulation region 390 closer to the source 306 is the first electric field modulation region 3901, and the electric field modulation region 309 closer to the drain 307 is the second electric field modulation region 3902; the third part 392C of the first electric field modulation region 3901 is shared with the second part 392B of the second electric field modulation region 3902.

[0101] For example, such as Figure 7 As shown, in two adjacent electric field modulation regions 390, for example, the first electric field modulation sub-region 391 in the first electric field modulation region 3901 is the first sub-region 3911, and the first electric field modulation sub-region 391 in the second electric field modulation region 3902 is the second sub-region 3912; the third part 392C of the second electric field modulation sub-region 392 located on the side of the first sub-region 3911 near the drain 307 is shared with the second part 392B of the second electric field modulation sub-region 392 located on the side of the second sub-region 3912 away from the drain 307.

[0102] Understandably, multiple first electric field modulation sub-regions 391 can achieve the superposition of local modulations, and the multiple first electric field modulation sub-regions 391 are arranged along the direction from the source 306 to the drain 307. That is, multiple third parts 392C are arranged along the direction from the source 306 to the drain 307, which further reduces the electric field spike in the region between the first electric field modulation sub-regions 391 and the drain 307, thereby reducing the leakage current, making the electric field more uniform, avoiding excessively high or low local electric fields, and further making the electric field distribution more uniform.

[0103] In some embodiments, the ion doping concentration of the plurality of first electric field modulator subregions 391 gradually increases along the first direction X.

[0104] For example, such as Figure 7 As shown, when there are two first electric field modulation sub-regions 391, the ion doping concentration of the first sub-region 3911 is less than the ion doping concentration of the second sub-region 3912.

[0105] Understandably, along the first direction X, as the ion doping concentration of the multiple first electric field modulator regions 391 gradually increases, the conductivity of the semiconductor device 300 is enhanced, resulting in a decrease in the specific on-resistance of the semiconductor device 300.

[0106] In some embodiments, the size of a plurality of first electric field modulator subregions 391 gradually increases along a first direction X.

[0107] For example, such as Figure 7 As shown, when there are two first electric field modulation sub-regions 391, the first sub-region 3911 has a dimension of D1 along the first direction X, and the second sub-region 3912 has a dimension of D2 along the first direction X, then D1 < D2.

[0108] Understandably, the above configuration allows the gradually increasing first electric field modulator region 391 to act as a buffer, effectively alleviating electric field concentration and making the electric field distribution in the semiconductor device 300 along the direction from the source 306 to the drain 307 smoother, avoiding abrupt changes, thereby reducing electric field distortion and further making the electric field distribution more uniform.

[0109] In some embodiments, the number of first electric field modulation sub-regions 391 is one. The ratio of the size of the first electric field modulation sub-region 391 along the first direction X to the size of the electric field modulation region 390 along the first direction X ranges from 0.1 to 0.9. The first direction X is the direction from the source 306 to the drain 307.

[0110] For example, such as Figure 3 As shown, the first electric field modulation sub-region 391 has a dimension D along the first direction X, and the electric field modulation region 390 has a dimension d along the first direction X. The ratio of D to d ranges from 0.1 to 0.9.

[0111] For example, such as Figure 6 As shown, the first electric field modulation sub-region 391 has a dimension D along the first direction X, and the electric field modulation region 390 has a dimension d along the first direction X. The ratio of D to d ranges from 0.1 to 0.9.

[0112] For example, the ratio of D to d can be 0.1, 0.3, 0.5, 0.7 or 0.9, etc., and there is no limitation here.

[0113] Understandably, the above settings can optimize the electric field changes of the first electric field modulator region 391, adjust the electric field gradient of the semiconductor device 300, reduce potential spikes and enhance withstand voltage, and further make the electric field distribution more uniform.

[0114] In some embodiments, there are multiple first electric field modulation sub-regions 391. The multiple first electric field modulation sub-regions 391 are arranged along a first direction X. The ratio of the sum of the dimensions of the multiple first electric field modulation sub-regions 391 along the first direction X to the dimension of the electric field modulation region 390 along the first direction X ranges from 0.1 to 0.9.

[0115] For example, such as Figure 4 As shown, when there are three first electric field modulation sub-regions 391, the sum of the dimensions of the first sub-region 3911 along the first direction X, the second sub-region 3912 along the first direction X, and the third sub-region 3913 along the first direction X is D*, and the dimension of the electric field modulation region 390 along the first direction X is d. Then the ratio of D* to d is in the range of 0.1 to 0.9.

[0116] For example, such as Figure 7As shown, when there are two first electric field modulation sub-regions 391, the first sub-region 3911 has a dimension D1 along the first direction X, the second sub-region 3912 has a dimension D2 along the first direction X, and the electric field modulation region 390 has a dimension d along the first direction X. Then the ratio of D1+D2 to d is in the range of 0.1~0.9.

[0117] For example, the ratio of D1+D2 to d can be 0.1, 0.3, 0.5, 0.7 or 0.9, etc., and there is no limitation here.

[0118] Understandably, the above settings can optimize the electric field changes of multiple first electric field modulator sub-regions 391, adjust the electric field gradient of semiconductor device 300, reduce potential spikes and enhance withstand voltage, and further make the electric field distribution more uniform.

[0119] In some embodiments, in a positive projection onto the substrate 301, the boundary of the second electric field modulating sub-region 392 away from the drain 307 overlaps with the boundary of the gate 311 near the drain 307.

[0120] Understandably, by setting the boundary of the second electric field modulator region 392 away from the drain 307 to overlap with the boundary of the gate 311 near the drain 307 in the orthogonal projection onto the substrate 301, the gate 311 and the second electric field modulator region 392 can be coupled to each other, which is beneficial for more precise control of the conduction state. Moreover, during the fabrication of the semiconductor device 300, the overlap of the boundary of the second electric field modulator region 392 away from the drain 307 with the boundary of the gate 311 near the drain 307 is more conducive to the implementation of the process and improves the feasibility of the process.

[0121] In some other embodiments, the second electric field modulator region 392 may also partially overlap with the gate 311 in the orthogonal projection onto the substrate 301, or there may be a gap between the second electric field modulator region 392 and the gate 311.

[0122] In some embodiments, in a positive projection onto the substrate 301, there is a gap between the boundary of the first electric field modulating sub-region 391 away from the drain 307 and the boundary of the gate 311 near the drain 307.

[0123] Understandably, the spacing between the boundary of the first electric field modulator region 391 away from the drain 307 and the boundary of the gate 311 near the drain 307 in the orthogonal projection onto the substrate 301 helps to regulate the effective carrier density of the epitaxial layer 303 and further reduce the on-resistance of the semiconductor device 300.

[0124] In some other embodiments, in a normal projection onto the substrate 301, there is no gap between the boundary of the first electric field modulator region 391 away from the drain 307 and the boundary of the gate 311 near the drain 307.

[0125] Embodiments of this disclosure provide a method for fabricating a semiconductor device 300. For example... Figure 8 As shown, the method for fabricating the semiconductor device 300 includes steps S1 to S3.

[0126] S1: An epitaxial layer 303 is formed on the substrate 301.

[0127] S2: A source 306, a drain 307, and a gate 311 are formed on the side of the epitaxial layer 303 away from the substrate 301; the source 306 and the drain 307 are embedded in the epitaxial layer 303, and the gate 311 is located between the source 306 and the drain 307.

[0128] S3: An electric field modulation region 390 is formed on the side of the epitaxial layer 303 away from the substrate 301. The electric field modulation region 390 is embedded in the epitaxial layer 303 and includes a first electric field modulation sub-region 391 and a second electric field modulation sub-region 392 that are interconnected. The second electric field modulation sub-region 392 covers the surface of the first electric field modulation sub-region 391 away from the substrate 301. The doping type of the first electric field modulation sub-region 391 is the same as that of the epitaxial layer 303, and the doping type of the second electric field modulation sub-region 392 is different from that of the epitaxial layer 303.

[0129] The semiconductor device 300 can be prepared by the preparation method of one of the above embodiments. The preparation method of the semiconductor device 300 disclosed herein will be further described below through specific preparation methods.

[0130] In some embodiments, a semiconductor device 300 is provided. For example... Figure 9 As shown, the fabrication method of the semiconductor device 300 includes: T1~T6.

[0131] Step T1: An epitaxial sublayer 302 is formed on the substrate 301.

[0132] For example, a suitable epitaxial growth process, such as chemical vapor deposition (CVD), is used to epitaxially grow an epitaxial sublayer 302 of a second conductivity type on a bulk substrate 301 of a first conductivity type. The substrate 301 is made of silicon carbide. For example, the first conductivity type is P-type and the second conductivity type is N-type.

[0133] Step T2: An epitaxial layer 303 of the first conductivity type is epitaxially grown on the side of the epitaxial sublayer 302 away from the substrate 301.

[0134] Step T3: Form the trap region 304.

[0135] For example, a well region 304 is patterned on an epitaxial layer 303 of the first conductivity type using a photolithography process. Ions of the second conductivity type are implanted using an ion implantation process to form the well region 304.

[0136] Step T4: Forming the active region. Ions of the second conductivity type are implanted into the second conductivity type (e.g., P-type) well region 304 on the side away from the substrate 301 to form a body region 305. Ions of the first conductivity type are implanted into the well region 304 on the side away from the substrate 301 and the contact body region 305 to form the source region 306. Ions of the first conductivity type are implanted into the pre-formed drain region 307 to form the drain region 307. Multilayer metals (including but not limited to Ti / Ni / Ag) are deposited using electron beam evaporation to form the source 306 and drain 307, respectively.

[0137] Step T5: Form electric field modulation region 390.

[0138] For example, ions of a first conductivity type are implanted on the side of the epitaxial layer 303 away from the substrate 301 to form a first electric field modulation sub-region 391, and the photolithography mask is adjusted to implant ions of a second conductivity type on the surface of the first electric field modulation sub-region 391 to form a second electric field modulation sub-region 392.

[0139] Step T6: Form gate 311.

[0140] For example, a gate oxide layer 310 with a thickness of 20nm to 80nm is grown on the surface of the epitaxial layer 303 away from the substrate 301. A polysilicon layer with a thickness of 200nm to 700nm is deposited by a deposition process (such as low-pressure chemical vapor deposition, LPCVD, etc.). The gate 311 region is formed by photolithography and dry etching. Multilayer metals (including but not limited to Ti / Ni / Ag) are deposited by an electron beam evaporation process to form the gate 311.

[0141] In some embodiments, a semiconductor device 300 is provided. For example... Figure 10 As shown, the method for fabricating the semiconductor device 300 includes N1 to N6.

[0142] Step N1: Form an epitaxial sublayer 302 on the substrate 301.

[0143] For example, a suitable epitaxial growth process, such as chemical vapor deposition (CVD), is used to epitaxially grow an epitaxial sublayer 302 of a second conductivity type on a bulk substrate 301 of a first conductivity type. The substrate 301 is made of silicon carbide. For example, the first conductivity type is P-type and the second conductivity type is N-type.

[0144] Step N2: An epitaxial layer 303 of the first conductivity type is epitaxially grown on the side of the epitaxial sublayer 302 away from the substrate 301.

[0145] Step N3: Form the trap region 304.

[0146] For example, a well region 304 is patterned on an epitaxial layer 303 of the first conductivity type using a photolithography process. Ions of the second conductivity type are implanted using an ion implantation process to form the well region 304.

[0147] Step N4: Forming the active region. Ions of the second conductivity type are implanted into the second conductivity type (e.g., P-type) well region 304 on the side away from the substrate 301 to form a body region 305. Ions of the first conductivity type are implanted into the well region 304 on the side away from the substrate 301 and the contact body region 305 to form the source region 306. Ions of the first conductivity type are implanted into the pre-formed drain region 307 to form the drain region 307. Multilayer metals (including but not limited to Ti / Ni / Ag) are deposited using electron beam evaporation to form the source 306 and drain 307, respectively.

[0148] Step N5: Form electric field modulation region 390.

[0149] For example, a first electric field modulation sub-region 391 is formed by implanting ions of a first conductivity type on the side of the epitaxial layer 303 away from the substrate 301. The photomask is adjusted so that a second electric field modulation sub-region 392 covers the surface of the first electric field modulation sub-region 391 away from the substrate 301. A second electric field modulation sub-region 392 is formed by implanting ions of a second conductivity type. The first electric field modulation sub-region 391 includes a first sub-region 3911, a second sub-region 3912, and a third sub-region 3913.

[0150] Step N6: Form gate 311.

[0151] For example, a gate oxide layer 310 with a thickness of 20nm to 80nm is grown on the surface of the epitaxial layer 303 away from the substrate 301. A polysilicon layer with a thickness of 200nm to 700nm is deposited by a deposition process (such as low-pressure chemical vapor deposition, LPCVD, etc.). The gate 311 region is formed by photolithography and dry etching. Multilayer metals (including but not limited to Ti / Ni / Ag) are deposited by an electron beam evaporation process to form the gate 311.

[0152] In some embodiments, a semiconductor device 300 is provided. For example... Figure 11 As shown, the method for fabricating the semiconductor device 300 includes M1 to M6.

[0153] Step M1: Form an epitaxial sublayer 302 on the substrate 301.

[0154] For example, a suitable epitaxial growth process, such as chemical vapor deposition (CVD), is used to epitaxially grow an epitaxial sublayer 302 of a second conductivity type on a bulk substrate 301 of a first conductivity type. The substrate 301 is made of silicon carbide. For example, the first conductivity type is P-type and the second conductivity type is N-type.

[0155] Step M2: An epitaxial layer 303 of the first conductivity type is epitaxially grown on the side of the epitaxial sublayer 302 away from the substrate 301.

[0156] Step M3: Form the trap region 304.

[0157] For example, a well region 304 is patterned on an epitaxial layer 303 of the first conductivity type using a photolithography process. Ions of the second conductivity type are implanted using an ion implantation process to form the well region 304.

[0158] Step M4: Forming the active region. Ions of the second conductivity type are implanted into the second conductivity type (e.g., P-type) well region 304 on the side away from the substrate 301 to form a body region 305. Ions of the first conductivity type are implanted into the well region 304 on the side away from the substrate 301 and the contact body region 305 to form the source region 306. Ions of the first conductivity type are implanted into the pre-formed drain region 307 to form the drain region 307. Multilayer metals (including but not limited to Ti / Ni / Ag) are deposited using electron beam evaporation to form the source 306 and drain 307, respectively.

[0159] Step M5: Form electric field modulation region 390.

[0160] For example, a first electric field modulation sub-region 391 is formed by implanting ions of a first conductivity type on the side of the epitaxial layer 303 away from the substrate 301. The photomask is adjusted so that a second electric field modulation sub-region 392 covers the surface of the first electric field modulation sub-region 391 away from the substrate 301. A second electric field modulation sub-region 392 is formed by implanting ions of a second conductivity type. The first electric field modulation sub-region 391 includes a first sub-region 3911 and a second sub-region 3912.

[0161] Step M6: Form gate 311.

[0162] For example, a gate oxide layer 310 with a thickness of 20nm to 80nm is grown on the surface of the epitaxial layer 303 away from the substrate 301. A polysilicon layer with a thickness of 200nm to 700nm is deposited by a deposition process (such as low-pressure chemical vapor deposition, LPCVD, etc.). The gate 311 region is formed by photolithography and dry etching. Multilayer metals (including but not limited to Ti / Ni / Ag) are deposited by an electron beam evaporation process to form the gate 311.

[0163] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate; an epitaxial layer on the substrate; a source, a drain and a gate on a side of the epitaxial layer away from the substrate, the source and the drain being embedded in the epitaxial layer, and the gate being between the source and the drain; a field modulation region on a side of the epitaxial layer away from the substrate and embedded in the epitaxial layer, the field modulation region comprising a first field modulation sub-region and a second field modulation sub-region, the second field modulation sub-region comprising a first part and a second part, the first part being on a side of the first field modulation sub-region away from the substrate, and the second part being on a side of the first field modulation sub-region away from the drain, the first part and the second part being connected; the first field modulation sub-region and the second field modulation sub-region having different doping types, the doping type being P-type doping and N-type doping.

2. The semiconductor device according to claim 1, wherein The ion doping concentration of the second field modulation sub-region is greater than the ion doping concentration of the first field modulation sub-region. The ion doping concentration of the first field modulation sub-region is greater than the ion doping concentration of the epitaxial layer.

3. The semiconductor device of claim 1, wherein The semiconductor device comprises a plurality of field modulation regions arranged along a first direction, the first direction being the direction in which the source points to the drain. In any two adjacent field modulation regions, the field modulation region closer to the source is a first field modulation region, and the field modulation region closer to the drain is a second field modulation region. The first part of the first field modulation region and the second part of the second field modulation region are shared.

4. The semiconductor device according to claim 3, wherein The distance from the surface of the first field modulation sub-region away from the substrate to the surface of the second field modulation sub-region away from the substrate gradually decreases along the first direction; and / or The distance from the surface of the first field modulation sub-region close to the substrate to the surface of the second field modulation sub-region away from the substrate gradually decreases along the first direction.

5. The semiconductor device of claim 4, wherein The interface between the first field modulation sub-region and the second field modulation sub-region has a stepped morphology; and / or The interface between the first field modulation sub-region and the epitaxial layer has a stepped morphology.

6. The semiconductor device of claim 4, wherein, The ion doping concentration of the first field modulation sub-region gradually increases along the first direction.

7. The semiconductor device of claim 1, wherein The second field modulation sub-region further comprises a third part, the third part being on a side of the first field modulation sub-region close to the drain, and the third part having a spacing from the drain; the third part and the first part being connected.

8. The semiconductor device of claim 7, wherein, The semiconductor device comprises a plurality of field modulation regions arranged along a first direction, the first direction being the direction in which the source points to the drain. In any two adjacent field modulation regions, the field modulation region closer to the source is a first field modulation region, and the field modulation region closer to the drain is a second field modulation region. The third part of the first electric field modulation region shares with the second part of the second electric field modulation region.

9. The semiconductor device of claim 8, wherein, The ion doping concentration of the plurality of first electric field modulation sub-regions gradually increases along the first direction; and / or, The size of the plurality of first electric field modulation sub-regions gradually increases along the first direction.

10. The semiconductor device according to any one of Claims 1 to 9, wherein The number of the first electric field modulation sub-regions is one; the ratio of the size of the first electric field modulation sub-region along the first direction to the size of the electric field modulation region along the first direction ranges from 0.1 to 0.9; the first direction is the direction from the source to the drain; Or, The number of the first electric field modulation sub-regions is multiple, and the plurality of first electric field modulation sub-regions are arranged along the first direction; the ratio of the sum of the size of the plurality of first electric field modulation sub-regions along the first direction to the size of the electric field modulation region along the first direction ranges from 0.1 to 0.9.

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