Vertical diffusion metal oxide semiconductor transistor structure and manufacturing method thereof

Abstract

The invention provides a vertical diffusion metal-oxide semiconductor transistor structure and a manufacturing method thereof. The vertical diffusion metal-oxide semiconductor transistor structure comprises a substrate, a first conductive type epitaxial layer, a gate structure and a second conductive type main body region. The first conductive epitaxial layer is disposed on the substrate. The gate structure is disposed on the first conductive epitaxial layer and has a gate conductive layer and a gate protection layer, and the gate protection layer covers two sidewalls of the gate conductive layer. The second conductive type main body region is arranged in the first conductive type epitaxial layer and is provided with two first conductive type source electrode regions and a second conductive type highly-doped region, and the second conductive type highly-doped region is clamped between the two first conductive type source electrode regions. The gate protection layer defines a width range of each of the first conductive source regions and the second conductive highly doped regions.

Description

Technical Field

[0001] This invention relates to a transistor structure and a method for manufacturing the same, and more particularly to a vertically diffused metal-oxide-semiconductor transistor structure and a method for manufacturing the same. Background Technology

[0002] Figures 1A to 1C This diagram shows a cross-sectional view of the conventional manufacturing process for a vertically diffused metal-oxide-semiconductor (VDMOS) field-effect transistor (FET). Figure 1A As shown, an N-type lightly doped epitaxial layer 12 is formed on an N-type heavily doped substrate 10 using an epitaxial process. A gate structure 14 is formed on the surface of the N-type lightly doped epitaxial layer 12. This gate structure 14 has a gate oxide layer and a gate polysilicon layer above it. Next, using the gate structure 14 as a mask, a blanket ion implantation process and a furnace tube heated ion diffusion process are performed to form two P-type main regions 16.

[0003] Secondly, please refer to Figure 1B A photolithography process is performed in two P-type host regions 16 to define the source regions of the VDMOS field-effect transistor. Specifically, this photolithography process involves forming a patterned photoresist 18 in the two P-type host regions 16 using a photomask. Then, using this patterned photoresist 18 as a mask, a blanket-type ion implantation process is performed to form two N-type source regions 20 in each P-type host region 16. Subsequently, as... Figure 1C As shown, after removing the patterned photoresist 18, a blanket-type ion implantation process and a furnace tube heating ion diffusion process are performed to form a P-type highly doped region 22 sandwiched between two N-type source regions 20.

[0004] The traditional manufacturing process for vertically diffused metal-oxide-semiconductor (MOSFET) field-effect transistors (FETs) involves a series of steps, including photoresist application, lithography, exposure, ion implantation, and photoresist removal, to define the source region and the highly doped P-type region. This process is time-consuming and costly. To overcome these problems, the industry urgently needs an innovative vertically diffused MOSFET structure and its manufacturing method to provide an efficient manufacturing process that reduces manufacturing costs. Summary of the Invention

[0005] The main objective of this invention is to provide an innovative vertically diffused metal-oxide-semiconductor field-effect transistor structure and its manufacturing method, which can not only reduce process time and cost, but also improve the gate-to-source leakage (IGSS) problem of VDMOS transistor devices.

[0006] To achieve the above objectives, the present invention provides a vertically diffused metal-oxide-semiconductor (MOSFET) transistor structure, comprising a substrate, a first conductivity type epitaxial layer, a gate structure, and a second conductivity type body region. The first conductivity type epitaxial layer is disposed on the substrate. The gate structure is disposed on the first conductivity type epitaxial layer, having a gate conductive layer and a gate protective layer, the gate protective layer covering the two sidewalls of the gate conductive layer. The second conductivity type body region is disposed within the first conductivity type epitaxial layer, having two first conductivity type source regions and a second conductivity type highly doped region, the second highly doped region being sandwiched between the two first conductivity type source regions. The gate protective layer defines a width range for each first conductivity type source region and each second highly doped region.

[0007] In one embodiment of the vertically diffused metal-oxide-semiconductor transistor structure of the present invention, the gate protection layer is a silicon dioxide layer with a thickness of 10 nanometers to 1500 nanometers.

[0008] In one embodiment of the vertically diffused metal-oxide-semiconductor transistor structure of the present invention, the gate protection layer is a silicon oxynitride layer with a thickness of 10 nanometers to 1500 nanometers.

[0009] In one embodiment of the vertically diffused metal-oxide-semiconductor transistor structure of the present invention, the gate protection layer is a silicon dioxide / silicon nitride composite layer, the silicon dioxide / silicon nitride composite layer having a silicon dioxide layer and a silicon nitride layer, the thickness of the silicon dioxide layer being 10 nanometers to 1000 nanometers, and the thickness of the silicon nitride layer being 10 nanometers to 1000 nanometers.

[0010] In one embodiment of the vertically diffused metal-oxide-semiconductor transistor structure of the present invention, the gate protection layer is a silicon dioxide / silicon nitride / silicon dioxide composite layer, which has an outer silicon dioxide layer, a silicon nitride layer and an inner silicon dioxide layer. The thickness of the outer silicon dioxide layer is 10 nanometers to 1000 nanometers, the thickness of the silicon nitride layer is 10 nanometers to 1000 nanometers, and the thickness of the inner silicon dioxide layer is 10 nanometers to 1000 nanometers.

[0011] To achieve the above objectives, the present invention provides a method for manufacturing a vertically diffused metal-oxide-semiconductor (MOSFET) transistor structure, comprising the following steps: providing a substrate; providing a first conductivity type epitaxial layer formed on the substrate; providing a gate structure formed on the first conductivity type epitaxial layer; providing a first conductivity type ion implantation using the gate structure as a mask; providing a gate protection layer formed on two sidewalls of the gate structure; and providing a second conductivity type ion implantation using the gate structure and the gate protection layer as a mask to define a width range of two first conductivity type source regions and a second conductivity type highly doped region, wherein the second conductivity type highly doped region is sandwiched between the two first conductivity type source regions.

[0012] In one embodiment of the manufacturing method of the vertically diffused metal-oxide-semiconductor transistor structure of the present invention, the step of providing a first conductivity type ion implantation with the gate structure as a mask is to provide a second conductivity type low-doped ion implantation with the gate structure as a mask, and then provide a first conductivity type high-doped ion implantation with the gate structure as a mask.

[0013] In one embodiment of the manufacturing method of the vertically diffused metal-oxide-semiconductor transistor structure of the present invention, the step of providing a gate protective layer formed on two sidewalls of the gate structure is to provide a gate protective layer covering the gate structure and then etch a portion of the gate protective layer to expose an upper surface of the gate structure.

[0014] In one embodiment of the manufacturing method of the vertically diffused metal-oxide-semiconductor transistor structure of the present invention, the step of providing a gate protection layer is to provide a silicon dioxide layer with a thickness of 10 nanometers to 1500 nanometers.

[0015] In one embodiment of the manufacturing method of the vertically diffused metal-oxide-semiconductor transistor structure of the present invention, the step of providing a gate protection layer is to provide a silicon oxynitride layer with a thickness of 10 nanometers to 1500 nanometers.

[0016] In one embodiment of the manufacturing method of the vertically diffused metal-oxide-semiconductor transistor structure of the present invention, the step of providing a gate protection layer is to provide a silicon dioxide / silicon nitride composite layer, the silicon dioxide / silicon nitride composite layer having a silicon dioxide layer and a silicon nitride layer, the thickness of the silicon dioxide layer being 10 nanometers to 1000 nanometers, and the thickness of the silicon nitride layer being 10 nanometers to 1000 nanometers.

[0017] In one embodiment of the manufacturing method of the vertically diffused metal-oxide-semiconductor transistor structure of the present invention, the step of providing a gate protection layer is to provide a silicon dioxide / silicon nitride / silicon dioxide composite layer. The silicon dioxide / silicon nitride / silicon dioxide composite layer has a silicon dioxide outer layer, a silicon nitride layer and a silicon dioxide inner layer. The thickness of the silicon dioxide outer layer is 10 nanometers to 1000 nanometers, the thickness of the silicon nitride layer is 10 nanometers to 1000 nanometers, and the thickness of the silicon dioxide inner layer is 10 nanometers to 1000 nanometers.

[0018] Other objects of the present invention, as well as the technical means and implementation methods of the present invention, will be understood by those skilled in the art upon referring to the accompanying drawings and the embodiments described below. Attached Figure Description

[0019] Figures 1A to 1C A cross-sectional schematic diagram of a conventionally manufactured vertically diffused metal-oxide-semiconductor field-effect transistor;

[0020] Figures 2A to 2E This is a cross-sectional schematic diagram of fabricating a vertically diffused metal-oxide-semiconductor field-effect transistor according to an embodiment of the present invention; and

[0021] Figure 3 This is a schematic diagram of the process steps for manufacturing a vertically diffused metal-oxide-semiconductor field-effect transistor according to one embodiment of the present invention.

[0022] Explanation of reference numerals in the attached figures

[0023] 10 base

[0024] 12 N-type low-doped epitaxial layer

[0025] 14 Gate Structure

[0026] 16 P-type main area

[0027] 18 Patterned photoresist

[0028] 20 N-type source region

[0029] 22 P-type highly doped region

[0030] 100 base

[0031] 110 First conductivity type epitaxial layer

[0032] 112 Gate Structure

[0033] 114 Second conductivity type main region

[0034] 116 First conductivity type highly doped region

[0035] 118 Gate protection layer

[0036] 120 Second conductivity type highly doped region

[0037] 122 First conductivity type source region

[0038] Steps S01 to S06. Detailed Implementation

[0039] The following embodiments will explain the content of this invention. These embodiments are not intended to limit the implementation of this invention to any specific environment, application, or special method described in the embodiments. Therefore, the descriptions of the embodiments are merely illustrative of the invention and not intended to limit it. It should be noted that in the following embodiments and drawings, elements not directly related to this invention have been omitted and are not shown, and the dimensional relationships between the elements in the drawings are for ease of understanding only and are not intended to limit the actual scale.

[0040] This invention discloses a semiconductor structure and its manufacturing method, particularly a vertically diffused metal-oxide-semiconductor transistor and its manufacturing method. Figures 2A to 2E This shows a cross-sectional schematic diagram of a vertically diffused gold-oxide-semiconductor transistor manufactured according to an embodiment of the present invention. First, please refer to... Figure 2A An epitaxial layer 110 of a first conductivity type is formed on a substrate 100 having a first conductivity type. The substrate 100 may be an N-type heavily doped semiconductor substrate. The material of the substrate 100 may be, for example, but not limited to, silicon, silicon carbide, or gallium nitride. The first conductivity type epitaxial layer 110 may be an N-type lightly doped epitaxial layer, and the formation method may be metal-organic chemical vapor deposition epitaxy. Specifically, the thickness of this N-type lightly doped epitaxial layer may be, for example, but not limited to, 40 to 150 micrometers (μm), and its doping concentration may be, for example, but not limited to, 10. 14 ~10 15 cm -3 The first conductive epitaxial layer 110 is doped with phosphorus, arsenic or antimony.

[0041] Please continue reading. Figure 2A A gate structure 112 is formed on the first conductivity epitaxial layer 110. This gate structure 112 includes a gate oxide layer and a gate conductive layer. The gate oxide layer can be a silicon dioxide layer formed on the surface of the first conductivity epitaxial layer 110. The gate conductive layer can be a polysilicon layer formed on the gate oxide layer. Next, using the gate structure 112 as a mask, a second conductivity low-doped ion implantation process is performed on the first conductivity epitaxial layer 110 to form a second conductivity main region 114 within the first conductivity epitaxial layer 110. Specifically, the second conductivity main region 114 can be a P-type well region, and its doping concentration can be, for example, 10.14 ~10 15 cm -3 However, this is not the limit.

[0042] Please see Figure 2B Next, using the gate structure 112 as a mask, a blanket-type first conductivity type highly doped ion implantation process is performed to form a first conductivity type highly doped region 116 in the second conductivity type main region 114. Specifically, the first conductivity type highly doped region 116 is an N-type highly doped region with a doping concentration of 10. 16 ~10 17 cm -3 Secondly, please refer to Figure 2C A deposition process is performed to form a gate protection layer 118 covering the gate structure 112 and the first conductivity-type highly doped region 116 between the gate structures 112. The gate protection layer 118 can be a single layer or a composite layer structure; specifically, it can be, for example, but not limited to, a silicon dioxide layer, a silicon oxynitride layer, a silicon dioxide / silicon nitride composite layer, or a silicon dioxide / silicon nitride / silicon dioxide composite layer. Next, a portion of the gate protection layer 118 is removed using anisotropic etching until an upper surface of the gate structure 112 is exposed, such as... Figure 2D As shown. At this point, the gate protection layer 118 will still be present on the two sidewalls of the gate structure 112.

[0043] Next, please refer to Figure 2E Using the gate structure 112 and the gate protection layer 118 on the two sidewalls of the gate structure 112 as a mask, a blanket-type second conductivity type ion implantation is provided to define a second conductivity type highly doped region 120 and a width range of two first conductivity type source regions 122. The second conductivity type highly doped region 120 is sandwiched between the two first conductivity type source regions 122. Specifically, as... Figure 2E The blanket-type second conductivity type ion implantation shown involves P-type ion implantation in the exposed area between the sidewalls of two adjacent gate structures 112, transforming the exposed area between the two sidewalls into a second conductivity type highly doped region 120, i.e., a P-type highly doped region, with a doping concentration of 10. 16 ~10 17 cm -3 The first conductivity type highly doped region 116 between the two adjacent gate structures 112 (excluding the sidewalls) will retain only the two side regions of the second conductivity type highly doped region 120, thereby defining two first conductivity type source regions 122.

[0044] This invention utilizes the gate guard layer 118 on the two sidewalls of the gate structure 112 to define a width range for two first conductivity type source regions and a second conductivity type highly doped region. In a preferred embodiment, when the gate guard layer 118 is a silicon dioxide layer, the thickness of the silicon dioxide layer is 10 nanometers to 1500 nanometers. When the gate guard layer 118 is a silicon oxynitride layer, the thickness of the silicon oxynitride layer is 10 nanometers to 1500 nanometers. When the gate guard layer 118 is a silicon dioxide / silicon nitride composite layer, the thickness of the silicon dioxide layer in the silicon dioxide / silicon nitride composite layer is 10 nanometers to 1000 nanometers, and the thickness of the silicon nitride layer is 10 nanometers to 1000 nanometers. When the gate protection layer 118 is a silicon dioxide / silicon nitride / silicon dioxide composite layer, the thickness of the outer silicon dioxide layer in the silicon dioxide / silicon nitride / silicon dioxide composite layer is 10 nanometers to 1000 nanometers, the thickness of the silicon nitride layer is 10 nanometers to 1000 nanometers, and the thickness of the inner silicon dioxide layer is 10 nanometers to 1000 nanometers.

[0045] Please see Figure 3 This invention illustrates a method for manufacturing a vertically diffused metal-oxide-semiconductor transistor structure. In step S01, a substrate is provided. Next, in step S02, a first conductivity epitaxial layer is provided over the substrate. Then, in step S03, a gate structure is provided on the first conductivity epitaxial layer. Subsequently, in step S04, a first conductivity ion implant is provided using the gate structure as a mask. In step S05, a gate protection layer is formed on the two sidewalls of the gate structure. Finally, in step S06, a second conductivity ion implant is provided using the gate structure and the gate protection layer as a mask to define a width range of two first conductivity source regions and a second conductivity highly doped region.

[0046] As described above, the gate structure of the vertically diffused metal-oxide-semiconductor transistor structure disclosed in this invention has a gate protection layer sidewall. Therefore, the width of this sidewall can be used to define the width range of the N-type highly doped source region and the width range of the P-type highly doped region sandwiched between the two source regions. Compared with conventional transistor structures and processes, the process steps disclosed in this invention can omit the lithography process required to define the source region and the P-type highly doped region, significantly reducing process time and related costs. Furthermore, it should be noted that because the gate structure of the vertically diffused metal-oxide-semiconductor transistor structure disclosed in this invention has a gate protection sidewall, during the application of gate voltage while operating the device, the leakage current between the gate and source can be reduced due to the sidewall protection, thus improving the IGSS problem of the device.

[0047] The above embodiments are merely illustrative of the implementation methods of the present invention and to explain the technical features of the present invention, and are not intended to limit the scope of protection of the present invention. Any changes or equivalent arrangements that can be easily made by those skilled in the art are within the scope of the present invention, and the scope of protection of the present invention should be determined by the claims.

Claims

1. A vertically diffused gold-oxide-semiconductor transistor structure, comprising: One base; A first conductivity epitaxial layer is disposed on the substrate; A gate structure is disposed on the first conductivity epitaxial layer, having a gate conductive layer and a gate protective layer, the gate protective layer covering the two sidewalls of the gate conductive layer; and A second conductivity type main body region is disposed within the first conductivity type epitaxial layer, having two first conductivity type source regions and a second conductivity type highly doped region, wherein the second conductivity type highly doped region is sandwiched between the two first conductivity type source regions. in, The gate protection layer defines a width range for each of the first conductivity type source regions and the second conductivity type highly doped regions.

2. The vertically diffused metal-oxide-semiconductor transistor structure of claim 1, wherein the gate protection layer is a silicon dioxide layer having a thickness of 10 nanometers to 1500 nanometers.

3. The vertically diffused metal-oxide-semiconductor transistor structure as described in claim 1, wherein the gate protection layer is a silicon oxynitride layer with a thickness of 10 nanometers to 1500 nanometers.

4. The vertically diffused metal-oxide-semiconductor transistor structure as claimed in claim 1, wherein the gate protection layer is a silicon dioxide / silicon nitride composite layer, the silicon dioxide / silicon nitride composite layer having a silicon dioxide layer and a silicon nitride layer, the thickness of the silicon dioxide layer being 10 nanometers to 1000 nanometers, and the thickness of the silicon nitride layer being 10 nanometers to 1000 nanometers.

5. The vertically diffused metal-oxide-semiconductor transistor structure as described in claim 1, wherein the gate protection layer is a silicon dioxide / silicon nitride / silicon dioxide composite layer, the silicon dioxide / silicon nitride / silicon dioxide composite layer having an outer silicon dioxide layer, a silicon nitride layer and an inner silicon dioxide layer, the outer silicon dioxide layer having a thickness of 10 nanometers to 1000 nanometers, the silicon nitride layer having a thickness of 10 nanometers to 1000 nanometers, and the inner silicon dioxide layer having a thickness of 10 nanometers to 1000 nanometers.

6. A method for manufacturing a vertically diffused gold-oxide-semiconductor transistor structure, comprising: Provide a base; A first conductivity epitaxial layer is provided and formed on the substrate; A gate structure is provided, formed above the first conductivity epitaxial layer; and Using this gate structure as a cover, a first type of conductive ion implantation is provided; A gate protection layer is provided and formed on the two sidewalls of the gate structure; and Using the gate structure and the gate protective layer as a mask, a second conductivity type ion implantation is provided to define a width range of two first conductivity type source regions and a second conductivity type highly doped region, wherein... The second conductivity type highly doped region is sandwiched between the two first conductivity type source regions.

7. The manufacturing method of claim 6, wherein the step of providing the first conductivity type ion implantation with the gate structure as a mask is to provide a second conductivity type low-doped ion implantation with the gate structure as a mask, and then provide a first conductivity type high-doped ion implantation with the gate structure as a mask.

8. The manufacturing method of claim 6, wherein the step of providing the gate protective layer formed on the two sidewalls of the gate structure comprises providing a gate protective layer covering the gate structure and then etching a portion of the gate protective layer to expose an upper surface of the gate structure.

9. The manufacturing method of claim 6, wherein the step of providing the gate protection layer is to provide a silicon dioxide layer having a thickness of 10 nanometers to 1500 nanometers.

10. The manufacturing method of claim 6, wherein the step of providing the gate protection layer is to provide a silicon oxynitride layer having a thickness of 10 nanometers to 1500 nanometers.

11. The manufacturing method of claim 6, wherein the step of providing the gate protection layer comprises providing a silicon dioxide / silicon nitride composite layer having a silicon dioxide layer and a silicon nitride layer, wherein the thickness of the silicon dioxide layer is 10 nanometers to 1000 nanometers and the thickness of the silicon nitride layer is 10 nanometers to 1000 nanometers.

12. The manufacturing method of claim 6, wherein the step of providing the gate protection layer comprises providing a silicon dioxide / silicon nitride / silicon dioxide composite layer having an outer silicon dioxide layer, a silicon nitride layer and an inner silicon dioxide layer, wherein the outer silicon dioxide layer has a thickness of 10 nanometers to 1000 nanometers, the silicon nitride layer has a thickness of 10 nanometers to 1000 nanometers, and the inner silicon dioxide layer has a thickness of 10 nanometers to 1000 nanometers.

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