Power semiconductor device and preparation method thereof

Abstract

The invention discloses a power semiconductor device and a preparation method thereof, and the power semiconductor device comprises a substrate; the buffer layer is located on one side of the substrate, and the channel layer is located on the side, away from the substrate, of the buffer layer; the first barrier layer is positioned on one side, far away from the substrate, of the channel layer; the barrier layer is located on the side, away from the substrate, of the first barrier layer; the second barrier layer is located on the side, away from the substrate, of the barrier layer; the second barrier layer is provided with a first groove, and the bottom of the first groove stops at the barrier layer; the gate structure is positioned on one side, far away from the substrate, of the first groove; the source electrode and the drain electrode are located on the side, away from the substrate, of the second barrier layer, and the source electrode and the drain electrode are located on the two sides of the gate structure. The depth of the first groove can be controlled, and the consistency of the depth of the first groove is guaranteed.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a power semiconductor device and its fabrication method. Background Technology

[0002] For enhancement-mode gallium nitride (GaN) high electron mobility transistor (HEMT) power devices, the thickness of the barrier layer and the aluminum composition are limited due to the limited depletion capability of the doped group III-V semiconductor layer located below the gate, resulting in a low saturation current for GaNHEMT devices.

[0003] Currently, to improve the saturation current of GaN HEMT devices while ensuring the depletion capability of the doped III-V semiconductor layer, a trench is formed by etching the barrier layer. Then, another barrier layer is formed within the trench and on the surface of the barrier layer. However, this method has the following drawbacks: If the trench etching does not reach the heterojunction between the barrier layer and the channel layer, leaving a barrier layer of a certain thickness, it may make it difficult for the GaN HEMT device to achieve enhancement mode. Alternatively, if the channel layer is over-etched during the trench etching, it will result in very low two-dimensional electron gas mobility, affecting the saturation current. Furthermore, for current methods of improving the saturation current of GaN HEMT devices, it is difficult to guarantee the consistency of the trench depth formed by etching the barrier layer, leading to poor threshold voltage consistency. Summary of the Invention

[0004] This invention provides a power semiconductor device and its fabrication method to solve the problem of difficulty in ensuring the consistency of the depth of the groove formed by etching the barrier layer.

[0005] In a first aspect, the present invention provides a power semiconductor device, wherein the power semiconductor device comprises:

[0006] Substrate;

[0007] The buffer layer and the channel layer are located on one side of the substrate, and the channel layer is located on the side of the buffer layer away from the substrate.

[0008] The first barrier layer is located on the side of the channel layer away from the substrate;

[0009] A barrier layer is located on the side of the first barrier layer away from the substrate;

[0010] The second barrier layer is located on the side of the barrier layer away from the substrate; the second barrier layer is provided with a first groove, the bottom of the first groove stopping at the barrier layer;

[0011] A gate structure comprising stacked doped III-V semiconductor layers and a gate; the doped III-V semiconductor layer is located on the side of the first groove away from the substrate, and the gate is located on the side of the doped III-V semiconductor layer away from the substrate;

[0012] The source and drain are both located on the side of the second barrier layer away from the substrate, and the source and drain are located on both sides of the gate structure.

[0013] The thickness of the second barrier layer is greater than the thickness of the first barrier layer, and the thickness of the second barrier layer is greater than the thickness of the barrier layer.

[0014] The aluminum content in the barrier layer is higher than that in the second barrier layer.

[0015] Optionally, the aluminum content in the barrier layer is higher than that in the first barrier layer.

[0016] Optionally, the first barrier layer includes a first Al x Ga 1-x N layers, the second barrier layer includes the second Al x Ga 1-x N layers; where 0.1 ≤ x ≤ 1;

[0017] The barrier layer includes an AlN layer or an Al layer. y Ga 1-y There are N layers, where 0.1 ≤ y ≤ 1 and y > x.

[0018] Optionally, the thickness of the barrier layer is 0.2nm-1.5nm, and / or the thickness of the first barrier layer is 0.3nm-3nm, and / or the thickness of the second barrier layer is 10nm-40nm.

[0019] Optionally, the power semiconductor device also includes a third barrier layer;

[0020] The third barrier layer is located on the side of the second barrier layer away from the substrate, and the third barrier layer fills the first groove;

[0021] The gate structure is located on the side of the third barrier layer corresponding to the first groove that is away from the substrate. The source and drain are both located on the side of the third barrier layer that is away from the substrate, and the source and drain are located on both sides of the gate structure.

[0022] The third barrier layer is in contact with the gate structure, and the vertical projection of the third barrier layer onto the substrate covers the vertical projection of the first barrier layer onto the substrate.

[0023] Optionally, the thickness of the third barrier layer is 0.5nm-20nm.

[0024] Optionally, the doped group III-V semiconductor layer includes a P-type doped nitride layer, which includes a P-type doped gallium nitride layer.

[0025] Secondly, the present invention provides a method for fabricating a power semiconductor device, wherein the fabrication method includes:

[0026] Provide substrate;

[0027] A buffer layer is formed on one side of the substrate;

[0028] A channel layer is formed on one side of the buffer layer;

[0029] A first barrier layer is formed on the side of the channel layer away from the substrate;

[0030] A barrier layer is formed on the side of the first barrier layer away from the substrate;

[0031] A second barrier layer is formed on the side of the barrier layer away from the substrate; the thickness of the second barrier layer is greater than the thickness of the first barrier layer, and the thickness of the second barrier layer is greater than the thickness of the barrier layer; the aluminum content in the barrier layer is higher than the aluminum content in the second barrier layer.

[0032] The second barrier layer is etched to form the first groove, and the bottom of the first groove stops at the barrier layer;

[0033] A gate structure is formed on the side of the first groove away from the substrate;

[0034] On the side of the second barrier layer away from the substrate, the source and drain are formed on both sides of the gate structure.

[0035] Optionally, before forming the gate structure on the side of the first groove away from the substrate, the method further includes:

[0036] A third barrier layer is formed on the side of the second barrier layer away from the substrate, and within the first groove;

[0037] A gate structure is formed on the side of the first groove away from the substrate, including:

[0038] A gate structure is formed on the side of the third barrier layer corresponding to the first groove away from the substrate; the third barrier layer is in contact with the gate structure, and the vertical projection of the third barrier layer on the substrate covers the vertical projection of the first barrier layer on the substrate.

[0039] On the side of the second barrier layer away from the substrate, and on both sides of the gate structure, a source and a drain are formed, including:

[0040] On the side of the third barrier layer away from the substrate, the source and drain are formed on both sides of the gate structure.

[0041] Optionally, a gate structure is formed on the side of the first groove away from the substrate, including:

[0042] A doped group III-V semiconductor layer is formed on the side of the first groove away from the substrate;

[0043] A gate is formed on the side of the doped group III-V semiconductor layer away from the substrate.

[0044] The technical solution of this invention provides a composite barrier layer consisting of a first barrier layer, a blocking layer, and a second barrier layer on the side of the channel layer away from the substrate. The thickness of the first barrier layer and the blocking layer is much smaller than the thickness of the second barrier layer. The thicker second barrier layer can effectively increase the two-dimensional electron gas concentration and mobility, thereby increasing the saturation current of the GaN HEMT device. The etching rate of the blocking layer located below the second barrier layer is much smaller than that of the second barrier layer. When etching the second barrier layer to form the first groove, the bottom of the first groove stops at the surface of the blocking layer, and the blocking layer is not damaged by etching. This embodiment of the invention can greatly reduce the etching damage when etching to form the first groove, effectively reducing interface defects. The blocking layer allows for controllable depth of the first groove. When etching the second barrier layer to form the first groove, under-etching (i.e., incomplete etching) and over-etching (i.e., damage to the channel layer) will not occur. The technical solution of this invention, by setting a barrier layer, can ensure the consistency of the depth of the first groove in different GaN HEMT devices and in the same GaN HEMT device, and further ensure the consistency of the threshold voltage of different GaN HEMT devices and the same GaN HEMT device.

[0045] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0048] Figure 2 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0049] Figure 3 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0050] Figures 4-6 This is a schematic diagram of some steps in a method for fabricating a semiconductor device provided in an embodiment of the present invention;

[0051] Figure 7This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention;

[0052] Figure 8 This is a schematic diagram of some steps in another method for fabricating a semiconductor device provided in this embodiment of the invention.

[0053] Figure 9 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention;

[0054] Figures 10-11 This is a schematic diagram of some steps in a method for fabricating another semiconductor device provided in an embodiment of the present invention. Detailed Implementation

[0055] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0056] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0057] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention, such as... Figure 1As shown, the semiconductor device includes: a substrate 11, a buffer layer 12, and a channel layer 13. The buffer layer 12 is located on one side of the substrate 11, and the channel layer 13 is located on the side of the buffer layer 12 away from the substrate 11. A first barrier layer 14 is located on the side of the channel layer 13 away from the substrate 11. A barrier layer 15 is located on the side of the first barrier layer 14 away from the substrate 11. A second barrier layer 16 is located on the side of the barrier layer 15 away from the substrate 11. The second barrier layer 16 has a first groove 161, the bottom of which stops at the barrier layer 15. A gate structure 17 is located on the side of the first groove 161 away from the substrate 11. A source 18 and a drain 19 are both located on the side of the second barrier layer 16 away from the substrate 11, and the source 18 and drain 19 are located on opposite sides of the gate structure 17. The thickness of the second barrier layer 16 is greater than the thickness of the first barrier layer 14, and the thickness of the second barrier layer 16 is greater than the thickness of the barrier layer 15; the aluminum content in the barrier layer 15 is higher than the aluminum content in the second barrier layer 16.

[0058] Specifically, substrate 11 can be a Si substrate, sapphire substrate, or GaN substrate, etc. The material of buffer layer 12 can include aluminum nitride, aluminum gallium nitride, a multilayer superlattice structure with alternating aluminum nitride / gallium nitride growth, a multilayer superlattice structure with alternating aluminum gallium nitride / gallium nitride growth, or carbon-doped gallium nitride, etc. Channel layer 13 can be intrinsic GaN as the channel layer.

[0059] Both the first barrier layer 14 and the second barrier layer 16 can be made of aluminum gallium nitride (AlGaN), and the aluminum composition in both layers can be the same. A barrier layer 15 is disposed on the entire surface of the first barrier layer 14 away from the substrate 11. The aluminum composition of the barrier layer 15 is higher than that of the second barrier layer 16, resulting in a much lower etching rate for the barrier layer 15 compared to the second barrier layer 16. The first barrier layer 14, the barrier layer 15, and the second barrier layer 16 can constitute a composite barrier layer. To ensure that the saturation current of the GaN HEMT device meets practical requirements, the second barrier layer 16 can be made thicker, significantly greater than the thicknesses of the first barrier layer 14 and the barrier layer 15. For example, the thickness of the second barrier layer 16 can be 10 nm to 40 nm. A thicker second barrier layer 16 can effectively increase the two-dimensional electron gas concentration and mobility, thereby improving the saturation current of the GaN HEMT device. Meanwhile, the GaN HEMT device provided in this embodiment of the invention is an enhancement-mode GaN HEMT device. The gate structure 17 may include a doped III-V semiconductor layer 171 and a gate 172. In order for the doped III-V semiconductor layer 171 to deplete the two-dimensional electron gas in the conductive channel of the GaN HEMT device when the voltage difference between the gate 172 and the source 18 of the GaN HEMT device is less than the threshold voltage, that is, in order to ensure the depletion capability of the doped III-V semiconductor layer 171, it is necessary to etch the second barrier layer 16 to form a first groove 161. The aluminum composition of the barrier layer 15 is higher than that of the aluminum composition in the second barrier layer 16, so that the etching rate of the barrier layer 15 located below the second barrier layer 16 is much lower than the etching rate of the second barrier layer 16. When etching the second barrier layer 16 to form the first groove 161, the bottom of the first groove 161 just stops on the surface of the barrier layer 15, and the barrier layer 15 will not be damaged by etching. The depth of the first groove 161 can be the same as the thickness of the second barrier layer 16. In existing technologies, when etching the barrier layer to form grooves, even without over-etching, the exposed channel layer will still suffer etching damage. However, in this invention, the etching rate of the barrier layer 15 located below the second barrier layer 16 is much lower than the etching rate of the second barrier layer 16, so the barrier layer 15 will not be etched and damaged.

[0060] Then, a gate structure 17 is formed on the side of the first groove 161 away from the substrate 11. For example, the gate structure 17 can be located within the first groove 161. The thickness of the barrier layer 15 and the first barrier layer 14 below the gate structure 17 is much smaller than the thickness of the second barrier layer 16. When the voltage difference between the gate 172 and the source 18 of the GaN HEMT device is less than the threshold voltage, the doped III-V semiconductor layer 171 can completely deplete the two-dimensional electron gas in the conductive channel of the GaN HEMT device, thereby turning off the GaNHEMT device. At the same time, since the thickness of the second barrier layer 16 can be much larger than the thickness of the first barrier layer 14 and the barrier layer 15, the thicker second barrier layer 16 makes it difficult for the two-dimensional electron gas in the conductive channel between the channel layer 13 and the first barrier layer 14 to cross the first barrier layer 14, the barrier layer 15 and the second barrier layer 16 and jump to the surface of the second barrier layer 16 away from the substrate 11, thereby avoiding the reduction of the two-dimensional electron gas concentration in the conductive channel and effectively increasing the two-dimensional electron gas concentration in the conductive channel. Furthermore, the aluminum content in the barrier layer 15 is relatively high, and the band gap of the barrier layer 15 with a higher aluminum content is larger, which further restricts the two-dimensional electron gas in the conductive channel from crossing the first barrier layer 14, the barrier layer 15 and the second barrier layer 16 to jump to the surface of the second barrier layer 16 away from the substrate 11, thereby further increasing the concentration of two-dimensional electron gas in the conductive channel.

[0061] like Figure 1 As shown, the gate structure 17 can contact the second barrier layer 16, and the second barrier layer 16 can cover the entire first barrier layer 14 outside the area covered by the gate structure 17. This arrangement can effectively increase the two-dimensional electron gas concentration in the drift region and improve the dynamic performance of the device.

[0062] The source 18 can be located on the side of the second barrier layer 16 away from the substrate 11, and the source 18 can also pass through the second barrier layer 16 and the barrier layer 15 to contact the first barrier layer 14. The drain 19 can be located on the side of the second barrier layer 16 away from the substrate 11, and the drain 19 can also pass through the second barrier layer 16 and the barrier layer 15 to contact the first barrier layer 14.

[0063] In this embodiment of the invention, a composite barrier layer consisting of a first barrier layer 14, a barrier layer 15, and a second barrier layer 16 is disposed on the side of the channel layer 13 away from the substrate 11. The thickness of the first barrier layer 14 and the barrier layer 15 is much smaller than the thickness of the second barrier layer 16. The thicker second barrier layer 16 can effectively increase the two-dimensional electron gas concentration and mobility, thereby increasing the saturation current of the GaN HEMT device. The etching rate of the barrier layer 15 located below the second barrier layer 16 is much smaller than the etching rate of the second barrier layer 16. When etching the second barrier layer 16 to form the first groove 161, the bottom of the first groove 161 just stops on the surface of the barrier layer 15, and the barrier layer 15 is not etched and damaged. This embodiment of the invention can greatly reduce the etching damage when etching to form the first groove 161 and effectively reduce interface defects. The barrier layer 15 allows for controllable depth of the first groove 161. When etching the second barrier layer 16 to form the first groove 161, under-etching (incomplete etching) and over-etching (damaging the channel layer 13) are avoided. The technical solution of this embodiment, by setting the barrier layer 15, ensures the consistency of the depth of the first groove 161 in different GaN HEMT devices and within the same GaN HEMT device, further guaranteeing the consistency of the threshold voltage between different GaN HEMT devices and within the same GaN HEMT device.

[0064] Optionally, based on the above embodiments, refer to... Figure 1 The aluminum content in the barrier layer 15 is higher than that in the first barrier layer 14.

[0065] Specifically, the aluminum composition in the first barrier layer 14 and the second barrier layer 16 can be the same, while the aluminum composition in the barrier layer 15 can be higher than that in both the first barrier layer 14 and the second barrier layer 16. This results in the etching rate of the barrier layer 15, with its higher aluminum composition, being much lower than that of the second barrier layer 16, with its lower aluminum composition. To ensure the depletion capability of the doped III-V semiconductor layer 171, the second barrier layer 16 needs to be etched to form a first groove 161. The etching rate of the barrier layer 15, located below the second barrier layer 16, is much lower than that of the second barrier layer 16. When etching the second barrier layer 16 to form the first groove 161, the bottom of the first groove 161 stops precisely on the surface of the barrier layer 15, preventing the barrier layer 15 from being damaged by etching. The arrangement of the barrier layer 15 allows for controllable depth of the first groove 161. By setting the barrier layer 15, the consistency of the depth of the first groove 161 in different GaN HEMT devices and in the same GaN HEMT device can be ensured, which further ensures the consistency of the threshold voltage of different GaN HEMT devices and the same GaN HEMT device.

[0066] The barrier layer 15 and the first barrier layer 14 below the gate structure 17 are relatively thin. For example, the thickness of the barrier layer 15 can be 0.2nm-1.5nm, which can effectively ensure the depletion capability of the doped III-V semiconductor layer 171.

[0067] The high-aluminum barrier layer 15 can also slightly increase the two-dimensional electron gas concentration and mobility, thereby increasing the saturation current of the GaNHEMT device. At the same time, the high-aluminum barrier layer 15 can also effectively ensure the depletion capability of the doped III-V semiconductor layer 171.

[0068] The aluminum composition in the barrier layer 15 can be higher than that in the first barrier layer 14 and the second barrier layer 16. The barrier layer 15 can effectively modulate the energy band and effectively suppress the hot electron effect, thereby improving the dynamic characteristics of the GaN HEMT device. At the same time, since the barrier layer 15 can effectively modulate the energy band, the setting of the barrier layer 15 can improve the gate breakdown voltage and effectively improve the gate leakage current.

[0069] Optionally, based on the above embodiments, refer to... Figure 1 The first barrier layer 14 includes the first Al x Ga 1- x N layers, the second barrier layer 16 includes the second Al x Ga 1-x N layers; where 0.1 ≤ x ≤ 1. Barrier layer 15 includes an AlN layer or an Al... y Ga 1-y There are N layers, where 0.1 ≤ y ≤ 1 and y > x.

[0070] Specifically, the aluminum composition in the first barrier layer 14 and the second barrier layer 16 can be the same, while the aluminum composition in the barrier layer 15 can be higher than that in both the first barrier layer 14 and the second barrier layer 16. The first barrier layer 14 may include a first Al x Ga 1-x N layers, the second barrier layer 16 includes the second Al x Ga 1-x N layer, where x can be 0.15-0.3. Barrier layer 15 may include an AlN layer, wherein the aluminum content in the AlN layer is greater than that in Al. x Ga 1-x The aluminum component in the N layer. The barrier layer 15 may also include Al. y Ga 1-y There are N layers, where y can be greater than 0.5 and less than 1.

[0071] The above configuration ensures that the etching rate of the barrier layer 15, which has a higher aluminum content, is significantly lower than that of the second barrier layer 16, which has a lower aluminum content. Etching the second barrier layer 16 forms the first groove 161. Since the etching rate of the barrier layer 15, located below the second barrier layer 16, is much lower than that of the second barrier layer 16, the bottom of the first groove 161 stops precisely on the surface of the barrier layer 15 during etching, preventing damage to the barrier layer 15. The barrier layer 15 allows for controllable depth of the first groove 161. By setting the barrier layer 15, the consistency of the depth of the first groove 161 in different GaN HEMT devices and within the same GaN HEMT device can be guaranteed, further ensuring the consistency of the threshold voltage between different GaN HEMT devices and within the same GaN HEMT device.

[0072] Optionally, based on the above embodiments, refer to... Figure 1 The thickness of the barrier layer 15 is 0.2nm-1.5nm, and / or the thickness of the first barrier layer 14 is 0.3nm-3nm, and / or the thickness of the second barrier layer 16 is 10nm-40nm.

[0073] Specifically, the first barrier layer 14, the blocking layer 15, and the second barrier layer 16 can constitute a composite barrier layer. To ensure that the saturation current of the GaN HEMT device meets practical requirements, in this embodiment of the invention, the thickness of the second barrier layer 16 can be much greater than the thickness of the first barrier layer 14 and the blocking layer 15. For example, the thickness of the second barrier layer 16 can be 10nm-40nm. A thicker second barrier layer 16 can effectively increase the concentration and mobility of two-dimensional electron gas, thereby increasing the saturation current of the GaNHEMT device. At the same time, since the thickness of the second barrier layer 16 can be much greater than the thickness of the first barrier layer 14 and the blocking layer 15, the thicker second barrier layer 16 makes it difficult for the two-dimensional electron gas in the conductive channel between the channel layer 13 and the first barrier layer 14 to cross the first barrier layer 14, the blocking layer 15, and the second barrier layer 16 and jump to the surface of the second barrier layer 16 away from the substrate 11, thus avoiding the reduction of the two-dimensional electron gas concentration in the conductive channel and effectively increasing the two-dimensional electron gas concentration in the conductive channel.

[0074] For example, the gate structure 17 can be located in the first groove 161. The thickness of the barrier layer 15 and the first barrier layer 14 below the gate structure 17 is much smaller than the thickness of the second barrier layer 16. For example, the thickness of the first barrier layer 14 is 0.3nm-3nm, and the thickness of the barrier layer 15 can be 0.2nm-1.5nm, which can effectively ensure the depletion capability of the doped III-V semiconductor layer 171.

[0075] Optionally, based on the above embodiments, Figure 2 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention, such as... Figure 2 As shown, the semiconductor device also includes a third barrier layer 20. The third barrier layer 20 is located on the side of the second barrier layer 16 away from the substrate 11, and fills the first recess 161. The gate structure 17 is located on the side of the third barrier layer 20 corresponding to the first recess 161 away from the substrate 11. The source 18 and drain 19 are both located on the side of the third barrier layer 20 away from the substrate 11, and are located on opposite sides of the gate structure 17. The third barrier layer 20 is in contact with the gate structure 17, and the vertical projection of the third barrier layer 20 onto the substrate 11 covers the vertical projection of the first barrier layer 14 onto the substrate 11.

[0076] Specifically, the semiconductor device may further include a third barrier layer 20, which may be disposed within the first recess 161 and on the side of the second barrier layer 16 away from the substrate 11. The thickness of the third barrier layer 20 may be set to 0.5 nm-20 nm, and the material of the third barrier layer 20 may include aluminum gallium nitride (AlGaN), and the aluminum composition in the third barrier layer 20 may be the same as the aluminum composition in the second barrier layer 16. By regrowing the third barrier layer 20 within the first recess 161 and on the side of the second barrier layer 16 away from the substrate 11, the thickness of the barrier layer in the drift region of the GaN HEMT device can be effectively increased, effectively improving the two-dimensional electron gas concentration and mobility, thereby enhancing the saturation current of the GaN HEMT device. The presence of the third barrier layer 20 can further enhance the saturation current of the GaN HEMT device.

[0077] By setting a third barrier layer 20, the gate structure 17 is located on the side of the third barrier layer 20 away from the substrate 11. The doped III-V semiconductor layer 171 in the gate structure 17 can contact the third barrier layer 20. Since the aluminum composition of the third barrier layer 20 can be the same as that of the second barrier layer 16, that is, the aluminum composition of the third barrier layer 20 is lower than that of the barrier layer 15, the lattice difference between the doped III-V semiconductor layer 171 and the third barrier layer 20 with lower aluminum composition is much smaller than the lattice difference between the doped III-V semiconductor layer 171 and the barrier layer 15 with higher aluminum composition. Therefore, setting the gate structure 17 on the side of the third barrier layer 20 away from the substrate 11 can improve the interface formation quality of the gate structure 17 and further improve the performance of the power device. Meanwhile, the third barrier layer 20 further restricts the two-dimensional electron gas in the conductive channel from crossing the first barrier layer 14, the barrier layer 15, the second barrier layer 16 and the third barrier layer 20 to jump to the surface of the third barrier layer 20 away from the substrate 11, thereby further increasing the concentration of two-dimensional electron gas in the conductive channel.

[0078] In existing technologies, when forming a barrier layer within a groove, the high growth temperature causes the channel layer to decompose, resulting in poor quality at the interface of the regenerated barrier layer. This affects the two-dimensional electron gas mobility and consequently the saturation current. The technical solution of this invention involves a barrier layer 15 on the side of the first barrier layer 14 away from the substrate 11, and a second barrier layer 16 on the side of the barrier layer 15 away from the substrate 11. A first groove 161 is formed by etching the second barrier layer 16. The bottom of the first groove 161 can effectively stop on the surface of the barrier layer 15 without causing etching damage to the barrier layer 15. Then, a third barrier layer 20 is formed on the side of the barrier layer 15 away from the substrate 11 within the first groove 161. The growth temperature of the third barrier layer 20 is higher, but compared to the channel layer 13, the barrier layer 15 is more difficult to decompose. Therefore, the growth of the third barrier layer 20 does not affect the surface quality of the barrier layer 15, thereby improving the growth quality at the interface of the third barrier layer 20 and further enhancing the two-dimensional electron gas mobility.

[0079] A gate structure 17 is disposed on the side of the third barrier layer 20 in the first groove 161 away from the substrate 11. The total thickness and aluminum composition of the first barrier layer 14, the barrier layer 15, and the third barrier layer 20 below the gate structure 17 do not affect the depletion capability of the doped III-V semiconductor layer 171. When the voltage difference between the gate 172 and the source 18 of the GaN HEMT device is less than the threshold voltage, the doped III-V semiconductor layer 171 can completely deplete the two-dimensional electron gas in the conductive channel of the GaN HEMT device, thereby turning off the GaN HEMT device. The third barrier layer 20 can directly contact the gate structure 17, so that the third barrier layer 20 completely covers the first barrier layer 14. This arrangement can effectively increase the two-dimensional electron gas concentration in the drift region and improve the dynamic performance of the device.

[0080] The source electrode 18 can be located on the side of the third barrier layer 20 away from the substrate 11. The source electrode 18 can also pass through the third barrier layer 20 to contact the second barrier layer 16. The source electrode 18 can also pass through the third barrier layer 20, the second barrier layer 16, and the barrier layer 15 to contact the first barrier layer 14. The drain electrode 19 can be located on the side of the third barrier layer 20 away from the substrate 11. The drain electrode 19 can also pass through the third barrier layer 20 to contact the second barrier layer 16. The drain electrode 19 can also pass through the third barrier layer 20, the second barrier layer 16, and the barrier layer 15 to contact the first barrier layer 14.

[0081] Optionally, based on the above embodiments, refer to... Figure 2 The thickness of the third barrier layer 20 is 0.5nm-20nm.

[0082] Specifically, the thickness of the third barrier layer 20 can be set to 0.5nm-20nm. The setting of the third barrier layer 20 can further and effectively increase the thickness of the barrier layer in the drift region of the GaN HEMT device, effectively improving the two-dimensional electron gas concentration and mobility, thereby enhancing the saturation current of the GaN HEMT device. The total thickness and aluminum composition of the first barrier layer 14, the barrier layer 15, and the third barrier layer 20 below the gate structure 17 will not affect the depletion capability of the doped III-V semiconductor layer 171.

[0083] Optionally, based on the above embodiments, refer to... Figure 1 and Figure 2 The doped III-V semiconductor layer 171 includes a P-type doped nitride layer, which includes a P-type doped gallium nitride layer.

[0084] Specifically, the doped III-V semiconductor layer 171 can be a p-type doped gallium nitride layer. The doped III-V semiconductor layer 171 can be located within the first groove 161, or the doped III-V semiconductor layer 171 can be located on the side of the third barrier layer 20 in the first groove 161 away from the substrate 11. When the voltage difference between the gate 172 and the source 18 of the GaN HEMT device is less than the threshold voltage, the doped III-V semiconductor layer 171 can completely deplete the two-dimensional electron gas in the conductive channel of the GaN HEMT device, thereby turning off the GaN HEMT device.

[0085] Gate 172 is located on the side of the doped III-V semiconductor layer 171 away from the substrate 11, and source 18 and drain 19 are located on opposite sides of gate 172. Figure 1 and Figure 2 As shown, the vertical distance between the gate 172 and the source 18 can be less than the vertical distance between the gate 172 and the drain 19. In some embodiments of the present invention, the vertical distance between the gate 172 and the source 18 can be greater than or equal to the vertical distance between the gate 172 and the drain 19, which is not specifically limited here.

[0086] Figure 3 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. Figures 4-6 This is a schematic diagram of some steps in a method for fabricating a semiconductor device according to an embodiment of the present invention, as shown below. Figure 3 As shown, the preparation method includes:

[0087] S100: Provides a substrate.

[0088] Specifically, such as Figure 4 As shown, a substrate 11 is first provided, which can be a Si substrate, a sapphire substrate or a GaN substrate.

[0089] S110: A buffer layer and a channel layer are formed sequentially on one side of the substrate.

[0090] For details, please refer to [link / reference]. Figure 4 A buffer layer 12 is formed on one side of the substrate 11, and a channel layer 13 is formed on the side of the buffer layer 12 away from the substrate 11. The material of the buffer layer 12 may include aluminum nitride, aluminum gallium nitride, a multilayer superlattice structure with alternating aluminum nitride / gallium nitride growth, a multilayer superlattice structure with alternating aluminum gallium nitride / gallium nitride growth, or carbon-doped gallium nitride, etc. The channel layer 13 may be intrinsic GaN as the channel layer.

[0091] S120: A first barrier layer is formed on the side of the channel layer away from the substrate.

[0092] Specifically, such as Figure 5 As shown, a first barrier layer 14 is formed on the side of the channel layer 13 away from the substrate 11, and the thickness of the first barrier layer 14 is 0.3nm-3nm.

[0093] S130: A barrier layer is formed on the side of the first barrier layer away from the substrate.

[0094] For details, please refer to [link / reference]. Figure 5 A barrier layer 15 is formed on the entire surface of the first barrier layer 14 away from the substrate 11, and the thickness of the barrier layer 15 can be 0.2nm-1.5nm.

[0095] S140: A second barrier layer is formed on the side of the barrier layer away from the substrate; the thickness of the second barrier layer is greater than the thickness of the first barrier layer, and the thickness of the second barrier layer is greater than the thickness of the barrier layer; the aluminum composition in the barrier layer is higher than the aluminum composition in the second barrier layer.

[0096] For details, please refer to [link / reference]. Figure 5A second barrier layer 16 is formed on the side of the barrier layer 15 away from the substrate 11. The first barrier layer 14, the barrier layer 15, and the second barrier layer 16 can constitute a composite barrier layer. To ensure that the saturation current of the GaN HEMT device meets practical requirements, the second barrier layer 16 can be made thicker, significantly greater than the thicknesses of the first barrier layer 14 and the barrier layer 15. For example, the thickness of the second barrier layer 16 can be 10nm-40nm. A thicker second barrier layer 16 can effectively increase the two-dimensional electron gas concentration and mobility, thereby improving the saturation current of the GaN HEMT device. Meanwhile, since the thickness of the second barrier layer 16 can be much greater than the thickness of the first barrier layer 14 and the barrier layer 15, the thicker second barrier layer 16 makes it difficult for the two-dimensional electron gas in the conductive channel between the channel layer 13 and the first barrier layer 14 to cross the first barrier layer 14, the barrier layer 15 and the second barrier layer 16 and jump to the surface of the second barrier layer 16 away from the substrate 11, thereby avoiding the reduction of the two-dimensional electron gas concentration in the conductive channel and effectively increasing the two-dimensional electron gas concentration in the conductive channel.

[0097] Furthermore, the aluminum content in the barrier layer 15 is relatively high, and the band gap of the barrier layer 15 with a higher aluminum content is larger, which further restricts the two-dimensional electron gas in the conductive channel from crossing the first barrier layer 14, the barrier layer 15 and the second barrier layer 16 to jump to the surface of the second barrier layer 16 away from the substrate 11, thereby further increasing the concentration of two-dimensional electron gas in the conductive channel.

[0098] S150: Etch the second barrier layer to form the first groove, the bottom of the first groove stopping at the barrier layer.

[0099] Specifically, such as Figure 6 and Figure 1 As shown, the GaN HEMT device provided in this embodiment of the invention is an enhancement-mode GaN HEMT device. The gate structure 17 may include a doped III-V semiconductor layer 171 and a gate 172. In order for the doped III-V semiconductor layer 171 to deplete the two-dimensional electron gas in the conductive channel of the GaN HEMT device when the voltage difference between the gate 172 and the source 18 of the GaN HEMT device is less than the threshold voltage, that is, in order to ensure the depletion capability of the doped III-V semiconductor layer 171, it is necessary to etch the second barrier layer 16 to form a first groove 161. The aluminum composition of the barrier layer 15 is higher than that of the second barrier layer 16, so that the etching rate of the barrier layer 15 is much lower than that of the second barrier layer 16. When etching the second barrier layer 16 to form the first groove 161, the bottom of the first groove 161 just stops on the surface of the barrier layer 15, and the barrier layer 15 will not be etched and damaged.

[0100] The aluminum composition in the first barrier layer 14 and the second barrier layer 16 can be the same, while the aluminum composition in the barrier layer 15 can be higher than that in both the first barrier layer 14 and the second barrier layer 16. This results in the etching rate of the barrier layer 15, with its higher aluminum composition, being significantly lower than the etching rate of the second barrier layer 16, with its lower aluminum composition. For example, the first barrier layer 14 may include a first Al... x Ga 1-x N layers, the second barrier layer 16 includes the second Al x Ga 1-x N layer, where x can be 0.15-0.3. Barrier layer 15 may include an AlN layer, wherein the aluminum content in the AlN layer is greater than that in Al. x Ga 1-x The aluminum component in the N layer. The barrier layer 15 may also include Al. y Ga 1-y There are N layers, where y can be greater than 0.5 and less than 1.

[0101] S160: A gate structure is formed on the side of the first groove away from the substrate.

[0102] Specifically, such as Figure 1 As shown, a gate structure 17 is formed on the side of the first groove 161 away from the substrate 11. For example, the gate structure 17 can be located in the first groove 161. The barrier layer 15 and the first barrier layer 14 below the gate structure 17 are relatively thin. When the voltage difference between the gate 172 and the source 18 of the GaN HEMT device is less than the threshold voltage, the doped III-V semiconductor layer 171 can completely deplete the two-dimensional electron gas in the conductive channel of the GaN HEMT device, thereby turning off the GaN HEMT device.

[0103] like Figure 1 As shown, the gate structure 17 can contact the second barrier layer 16, and the second barrier layer 16 can cover the entire first barrier layer 14 outside the area covered by the gate structure 17. This arrangement can effectively increase the two-dimensional electron gas concentration in the drift region and improve the dynamic performance of the device.

[0104] S170: The source and drain are formed on the side of the second barrier layer away from the substrate, and on both sides of the gate structure.

[0105] Specifically, such as Figure 1 As shown, on the side of the second barrier layer 16 away from the substrate 11, the source 18 and drain 19 are formed on both sides of the gate structure 17.

[0106] In this embodiment of the invention, a composite barrier layer consisting of a first barrier layer 14, a barrier layer 15, and a second barrier layer 16 is sequentially formed on the side of the channel layer 13 away from the substrate 11. The thicknesses of the first barrier layer 14 and the barrier layer 15 are much smaller than the thickness of the second barrier layer 16. The thicker second barrier layer 16 can effectively increase the two-dimensional electron gas concentration and mobility, thereby increasing the saturation current of the GaN HEMT device. The etching rate of the barrier layer 15 located below the second barrier layer 16 is much smaller than the etching rate of the second barrier layer 16. When etching the second barrier layer 16 to form the first groove 161, the bottom of the first groove 161 stops just on the surface of the barrier layer 15, and the barrier layer 15 is not damaged by etching. This embodiment of the invention can greatly reduce the etching damage when etching to form the first groove 161, effectively reducing interface defects. The barrier layer 15 allows for controllable depth of the first groove 161. When etching the second barrier layer 16 to form the first groove 161, under-etching (incomplete etching) and over-etching (damaging the channel layer 13) are avoided. The technical solution of this embodiment, by setting the barrier layer 15, ensures the consistency of the depth of the first groove 161 in different GaN HEMT devices and within the same GaN HEMT device, further guaranteeing the consistency of the threshold voltage between different GaN HEMT devices and within the same GaN HEMT device.

[0107] Optionally, based on the above embodiments, Figure 7 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention. Figure 8 This is a schematic diagram of some steps in another method for fabricating a semiconductor device provided in this embodiment of the invention, as shown below. Figure 7 As shown, the preparation method includes:

[0108] S200: Provides a substrate.

[0109] S210: A buffer layer and a channel layer are formed sequentially on one side of the substrate.

[0110] S220: A first barrier layer is formed on the side of the channel layer away from the substrate.

[0111] S230: A barrier layer is formed on the side of the first barrier layer away from the substrate.

[0112] S240: A second barrier layer is formed on the side of the barrier layer away from the substrate; the thickness of the second barrier layer is greater than the thickness of the first barrier layer, and the thickness of the second barrier layer is greater than the thickness of the barrier layer; the aluminum composition in the barrier layer is higher than the aluminum composition in the second barrier layer.

[0113] S250: The second barrier layer is etched to form the first groove, and the bottom of the first groove stops at the barrier layer.

[0114] S260: A third barrier layer is formed on the side of the second barrier layer away from the substrate, and within the first groove.

[0115] Specifically, such as Figure 8 As shown, a third barrier layer 20 is formed on the side of the second barrier layer 16 away from the substrate 11 and within the first groove 161. The thickness of the third barrier layer 20 can be set to 0.5 nm-20 nm, and the material of the third barrier layer 20 can include aluminum gallium nitride (AlGaN), and the aluminum composition in the third barrier layer 20 can be the same as the aluminum composition in the second barrier layer 16. By regrowing the third barrier layer 20 within the first groove 161 and on the side of the second barrier layer 16 away from the substrate 11, the thickness of the barrier layer in the drift region of the GaNHEMT device can be effectively increased, effectively improving the two-dimensional electron gas concentration and mobility, thereby enhancing the saturation current of the GaNHEMT device. The presence of the third barrier layer 20 can further enhance the saturation current of the GaN HEMT device.

[0116] By setting a third barrier layer 20, the gate structure 17 is located on the side of the third barrier layer 20 away from the substrate 11. The doped III-V semiconductor layer 171 in the gate structure 17 can contact the third barrier layer 20. Since the aluminum composition of the third barrier layer 20 can be the same as that of the second barrier layer 16, that is, the aluminum composition of the third barrier layer 20 is lower than that of the barrier layer 15, the lattice difference between the doped III-V semiconductor layer 171 and the third barrier layer 20 with lower aluminum composition is much smaller than the lattice difference between the doped III-V semiconductor layer 171 and the barrier layer 15 with higher aluminum composition. Therefore, setting the gate structure 17 on the side of the third barrier layer 20 away from the substrate 11 can improve the interface formation quality of the gate structure 17 and further improve the performance of the power device. Meanwhile, the third barrier layer 20 further restricts the two-dimensional electron gas in the conductive channel from crossing the first barrier layer 14, the barrier layer 15, the second barrier layer 16 and the third barrier layer 20 to jump to the surface of the third barrier layer 20 away from the substrate 11, thereby further increasing the concentration of two-dimensional electron gas in the conductive channel.

[0117] A barrier layer 15 is disposed on the side of the first barrier layer 14 away from the substrate 11, and a second barrier layer 16 is disposed on the side of the barrier layer 15 away from the substrate 11. A first groove 161 is formed by etching the second barrier layer 16. The bottom of the first groove 161 can effectively stop on the surface of the barrier layer 15 without causing etching damage to the barrier layer 15. Then, a third barrier layer 20 is formed on the side of the barrier layer 15 away from the substrate 11 within the first groove 161. The growth temperature of the third barrier layer 20 is higher, but compared with the channel layer 13, the barrier layer 15 is more difficult to decompose. That is, the growth of the third barrier layer 20 does not affect the surface quality of the barrier layer 15, thereby improving the growth quality at the interface of the third barrier layer 20 and further improving the two-dimensional electron gas mobility.

[0118] S270: A gate structure is formed on the side of the third barrier layer corresponding to the first groove away from the substrate.

[0119] Specifically, such as Figure 2 As shown, a gate structure 17 is disposed on the side of the third barrier layer 20 in the first groove 161 away from the substrate 11. The total thickness and aluminum composition of the first barrier layer 14, the barrier layer 15 and the third barrier layer 20 below the gate structure 17 do not affect the depletion capability of the doped III-V semiconductor layer 171. When the voltage difference between the gate 172 and the source 18 of the GaN HEMT device is less than the threshold voltage, the doped III-V semiconductor layer 171 can completely deplete the two-dimensional electron gas in the conductive channel of the GaN HEMT device, thereby turning off the GaN HEMT device.

[0120] The third barrier layer 20 can be in direct contact with the gate structure 17, so that the third barrier layer 20 completely covers the first barrier layer 14. This arrangement can effectively increase the two-dimensional electron gas concentration in the drift region and improve the dynamic performance of the device.

[0121] S280: The source and drain are formed on the side of the third barrier layer away from the substrate, and on both sides of the gate structure.

[0122] Specifically, such as Figure 2 As shown, a source 18 and a drain 19 are formed on the side of the third barrier layer 20 away from the substrate 11, and on both sides of the gate structure 17.

[0123] Optionally, based on the above embodiments, Figure 9 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention. Figures 10-11 This is a schematic diagram of some steps in a method for fabricating another semiconductor device provided in this embodiment of the invention, as shown below. Figure 9 As shown, the preparation method includes:

[0124] S300: Provides a substrate.

[0125] S310: A buffer layer and a channel layer are formed sequentially on one side of the substrate.

[0126] S320: A first barrier layer is formed on the side of the channel layer away from the substrate.

[0127] S330: A barrier layer is formed on the side of the first barrier layer away from the substrate.

[0128] S340: A second barrier layer is formed on the side of the barrier layer away from the substrate; the thickness of the second barrier layer is greater than the thickness of the first barrier layer, and the thickness of the second barrier layer is greater than the thickness of the barrier layer; the aluminum composition in the barrier layer is higher than the aluminum composition in the second barrier layer.

[0129] S350: The second barrier layer is etched to form the first groove, and the bottom of the first groove stops at the barrier layer.

[0130] S360: A third barrier layer is formed on the side of the second barrier layer away from the substrate, and within the first groove.

[0131] S370: A doped III-V semiconductor layer is formed on the side of the third barrier layer corresponding to the first groove away from the substrate.

[0132] Specifically, such as Figure 10 As shown, a doped group III-V semiconductor layer 171 is first formed on the entire surface of the third barrier layer 20 away from the substrate 11, as follows: Figure 11 As shown, the doped III-V semiconductor layer 171 is then retained on the side of the third barrier layer 20 away from the substrate 11 by photolithography and etching processes.

[0133] The doped III-V semiconductor layer 171 in the gate structure 17 can contact the third barrier layer 20. Since the aluminum composition of the third barrier layer 20 can be the same as that of the second barrier layer 16, that is, the aluminum composition of the third barrier layer 20 is lower than that of the barrier layer 15, the lattice difference between the doped III-V semiconductor layer 171 and the third barrier layer 20 with lower aluminum composition is much smaller than the lattice difference between the doped III-V semiconductor layer 171 and the barrier layer 15 with higher aluminum composition. Therefore, setting the gate structure 17 on the side of the third barrier layer 20 away from the substrate 11 can improve the interface formation quality of the gate structure 17 and further improve the performance of the power device.

[0134] like Figure 1 As shown, when the GaN HEMT device does not include the third barrier layer 20, a doped III-V semiconductor layer 171 can be formed in the first groove 161 and on the entire surface of the second barrier layer 16 away from the substrate 11. Then, the doped III-V semiconductor layer 171 in the first groove 161 can be retained by photolithography and etching processes.

[0135] S380: A gate is formed on the side of the doped III-V semiconductor layer away from the substrate.

[0136] Specifically, such as Figure 2 As shown, a gate 172 is formed on the side of the doped III-V semiconductor layer 171 away from the substrate 11.

[0137] S390: The source and drain are formed on the side of the third barrier layer away from the substrate, and on both sides of the gate structure.

[0138] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0139] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A power semiconductor device, characterized in that, include: Substrate; A buffer layer and a channel layer, wherein the buffer layer is located on one side of the substrate and the channel layer is located on the side of the buffer layer away from the substrate; The first barrier layer is located on the side of the channel layer away from the substrate; A barrier layer is located on the side of the first barrier layer away from the substrate; A second barrier layer is located on the side of the barrier layer away from the substrate; the second barrier layer is provided with a first groove, the bottom of the first groove stopping at the barrier layer; A gate structure comprising stacked doped III-V semiconductor layers and a gate; the doped III-V semiconductor layer is located on the side of the first groove away from the substrate, and the gate is located on the side of the doped III-V semiconductor layer away from the substrate; The source and the drain are both located on the side of the second barrier layer away from the substrate, and the source and the drain are located on opposite sides of the gate structure; The thickness of the second barrier layer is greater than the thickness of the first barrier layer, and the thickness of the second barrier layer is greater than the thickness of the barrier layer; The aluminum content in the barrier layer is higher than that in the second barrier layer.

2. The power semiconductor device according to claim 1, characterized in that, The aluminum content in the barrier layer is higher than that in the first barrier layer.

3. The power semiconductor device according to claim 2, characterized in that, The first barrier layer includes a first Al x Ga 1-x N layers, the second barrier layer includes a second Al x Ga 1-x N layers; where 0.1 ≤ x ≤ 1; The barrier layer includes an AlN layer or an Al layer. y Ga 1-y There are N layers, where 0.1 ≤ y ≤ 1 and y > x.

4. The power semiconductor device according to claim 1, characterized in that, The thickness of the barrier layer is 0.2nm-1.5nm, and / or the thickness of the first barrier layer is 0.3nm-3nm, and / or the thickness of the second barrier layer is 10nm-40nm.

5. The power semiconductor device according to claim 1, characterized in that, It also includes a third barrier layer; The third barrier layer is located on the side of the second barrier layer away from the substrate, and the third barrier layer fills the first groove; The gate structure is located on the side of the third barrier layer corresponding to the first groove away from the substrate, the source and the drain are both located on the side of the third barrier layer away from the substrate, and the source and the drain are located on both sides of the gate structure; The third barrier layer is in contact with the gate structure, and the vertical projection of the third barrier layer onto the substrate covers the vertical projection of the first barrier layer onto the substrate.

6. The power semiconductor device according to claim 5, characterized in that, The thickness of the third barrier layer is 0.5nm-20nm.

7. The power semiconductor device according to claim 1, characterized in that, The doped group III-V semiconductor layer includes a P-type doped nitride layer, which in turn includes a P-type doped gallium nitride layer.

8. A method for fabricating a power semiconductor device, characterized in that, include: Provide substrate; A buffer layer is formed on one side of the substrate; A channel layer is formed on one side of the buffer layer; A first barrier layer is formed on the side of the channel layer away from the substrate; A barrier layer is formed on the side of the first barrier layer away from the substrate; A second barrier layer is formed on the side of the barrier layer away from the substrate; the thickness of the second barrier layer is greater than the thickness of the first barrier layer, and the thickness of the second barrier layer is greater than the thickness of the barrier layer; the aluminum content in the barrier layer is higher than the aluminum content in the second barrier layer. The second barrier layer is etched to form a first groove, the bottom of which stops at the barrier layer; A gate structure is formed on the side of the first groove away from the substrate; On the side of the second barrier layer away from the substrate, and on both sides of the gate structure, the source and drain are formed.

9. The method for fabricating a power semiconductor device according to claim 8, characterized in that, Before forming the gate structure on the side of the first groove away from the substrate, the method further includes: A third barrier layer is formed on the side of the second barrier layer away from the substrate, and within the first groove; A gate structure is formed on the side of the first groove away from the substrate, including: The gate structure is formed on the side of the third barrier layer corresponding to the first groove away from the substrate; the third barrier layer is in contact with the gate structure, and the vertical projection of the third barrier layer on the substrate covers the vertical projection of the first barrier layer on the substrate. On the side of the second barrier layer away from the substrate, and on both sides of the gate structure, a source and a drain are formed, including: The source and drain are formed on the side of the third barrier layer away from the substrate and on both sides of the gate structure.

10. The method for fabricating a power semiconductor device according to claim 8, characterized in that, A gate structure is formed on the side of the first groove away from the substrate, including: A doped group III-V semiconductor layer is formed on the side of the first groove away from the substrate; A gate is formed on the side of the doped III-V semiconductor layer away from the substrate.

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