Method and apparatus for manufacturing semiconductor device

Abstract

Methods of manufacturing semiconductor devices, manufactured semiconductor devices, and apparatuses for manufacturing semiconductor devices are described in which by-products of an etch process are independently heated separately from a semiconductor wafer. In an embodiment, a dielectric material is deposited into a trench over a semiconductor substrate, and the dielectric material is recessed using an etching process. The etching process includes heating the semiconductor substrate and individually heating by-products of the etching process.

Description

Technical Field

[0001] Embodiments of this disclosure relate to methods and apparatus for manufacturing semiconductor devices. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the individual material layers to form circuit components and elements on the material layers.

[0003] By continuously reducing the minimum component size, the semiconductor industry has been improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.), allowing more components to be integrated into a given area. As the semiconductor industry continues to move towards increased device density, higher performance, and lower costs, challenges from manufacturing and design have led to stacked device configurations, such as stacked transistors, including complementary field-effect transistors (CFETs). However, as the minimum component size decreases, additional components are introduced. Summary of the Invention

[0004] Embodiments of this disclosure provide a method for manufacturing a semiconductor device, the method comprising: depositing a dielectric material in a trench above a semiconductor substrate; and recessing the dielectric material using an etching process, wherein the etching process includes: heating the semiconductor substrate; and separately heating a byproduct of the etching process.

[0005] Another embodiment of this disclosure provides a method for manufacturing a semiconductor device, the method comprising: placing a semiconductor wafer in an etching chamber, the etching chamber including a first heating element, the semiconductor wafer including a dielectric material located in a first recess; reacting the dielectric material to form a gas and recessing the dielectric material, the reaction of the dielectric material also producing byproducts; and heating the byproducts using a second heating element different from the first heating element.

[0006] Another embodiment of this disclosure provides an apparatus for manufacturing semiconductor devices, the apparatus comprising: an etching chamber; a mounting platform; a first heating element; and a second heating element, independent of the first heating element. Attached Figure Description

[0007] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the individual components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the individual components may be increased or decreased in any way.

[0008] Figure 1 A perspective view of an example complementary field-effect transistor (CFET) according to some embodiments is shown.

[0009] Figures 2 to 14 This is a view of an intermediate stage in the fabrication of a CFET according to some embodiments. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the discussed embodiments and / or configurations.

[0011] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Besides the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0012] Embodiments will now be described with respect to specific examples, wherein byproducts of the etching process are heated independently of the semiconductor wafer during the fabrication of a complementary field-effect transistor (CFET) structure. However, the embodiments described herein are intended to illustrate the proposed concepts and are not intended to limit the embodiments to the precise descriptions presented. Rather, these concepts can be implemented in a wide range of processes and devices, and all such processes and devices are fully intended to be included within the scope of the embodiments.

[0013] Figure 1 An example of a stacked transistor 10 (including FETs 10U and 10L) according to some embodiments is shown. Figure 1 It is a 3D view, and for clarity, some components of the stacked transistors have been omitted.

[0014] The stacked transistor comprises multiple vertically stacked FETs. For example, the stacked transistor may include a lower nanostructure FET 10L of a first device type (e.g., n-type / p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type / n-type). When the stacked transistor is a CFET, the second device type of the upper nanostructure FET 10U is opposite to the first device type of the lower nanostructure FET 10L. The nanostructure FETs 10U and 10L include a semiconductor nanostructure 26 (including a lower semiconductor nanostructure 26L and an upper semiconductor nanostructure 26U), wherein the semiconductor nanostructure 26 serves as the channel region of the nanostructure FET. The lower semiconductor nanostructure 26L is used for the lower nanostructure FET 10L, and the upper semiconductor nanostructure 26U is used for the upper nanostructure FET 10U. In other embodiments, the stacked transistor may also be applied to other types of transistors (e.g., finFETs, etc.).

[0015] A gate dielectric 78 surrounds the corresponding semiconductor nanostructure 26. Gate electrodes 80 (including a lower gate electrode 80L and an upper gate electrode 80U) are located above the gate dielectric 78. Source / drain regions 62 (including a lower source / drain region 62L and an upper source / drain region 62U) are disposed on opposite sides of the gate dielectric 78 and the corresponding gate electrode 80. Each source / drain region 62 may refer to a source or a drain, individually or collectively, depending on the context. Isolation components (not shown) may be formed to separate the desired source / drain regions 62 and / or the desired gate electrode 80.

[0016] exist Figure 2 The invention provides a wafer including a semiconductor substrate 20. The semiconductor substrate 20 may be a semiconductor substrate, such as a bulk semiconductor, and may be doped (e.g., with p-type or n-type dopants) or undoped. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the semiconductor substrate 20 may include silicon, germanium, carbon-doped silicon, III-V compound semiconductors, etc.; or combinations thereof.

[0017] Semiconductor strips 28 are formed extending upward from the semiconductor substrate 20. Each semiconductor strip 28 includes a semiconductor strip 20' (a patterned portion of the semiconductor substrate 20, also referred to as a semiconductor fin 20') and a multilayer stack 22. The stacked components of the multilayer stack 22 are referred to hereinafter as nanostructures. Specifically, the multilayer stack 22 includes pseudo-nanostructures 24A and 24B, a lower semiconductor nanostructure 26L, and an upper semiconductor nanostructure 26U. Pseudo-nanostructures 24A and 24B can also be collectively referred to as pseudo-nanostructure 24, and the lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U can also be collectively referred to as semiconductor nanostructure 26.

[0018] The pseudo-nanostructure 24A is formed of a first semiconductor material, and the pseudo-nanostructure 24B is formed of a second semiconductor material different from the first semiconductor material. The first and second semiconductor materials can be selected from candidate semiconductor materials of the semiconductor substrate 20. The first and second semiconductor materials have high etch selectivity towards each other. Therefore, in subsequent processes, the pseudo-nanostructure 24B can be removed at a faster rate than the pseudo-semiconductor layer 24A.

[0019] Semiconductor nanostructure 26 (including lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U) is formed of one or more third semiconductor materials. The third semiconductor material can be selected from candidate semiconductor materials of the semiconductor substrate 20. The lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U can be formed of the same semiconductor material or different semiconductor materials. Furthermore, the first and second semiconductor materials of the pseudo-nanostructure 24 have high etch selectivity relative to the third semiconductor material of the semiconductor nanostructure 26. Therefore, the pseudo-nanostructure 24 can be selectively removed in subsequent process steps without significantly removing the semiconductor nanostructure 26. In some embodiments, the pseudo-semiconductor nanostructure 24A is formed of or includes silicon-germanium, the semiconductor nanostructure 26 is formed of silicon, and the pseudo-nanostructure 24B can be formed of germanium or silicon-germanium (with a higher atomic percentage of germanium than semiconductor nanostructure 24A).

[0020] The lower semiconductor nanostructure 26L will provide the channel region for the lower nanostructure FET of the CFET. The upper semiconductor nanostructure 26U will provide the channel region for the upper nanostructure FET of the CFET. The semiconductor nanostructure 26 immediately above / below (e.g., as a contact) the pseudo-nanostructure 24B can be used for isolation and may or may not be used as the channel region of the CFET. Subsequently, the pseudo-nanostructure 24B will be replaced by an isolation structure defining the boundary between the lower nanostructure FET and the upper nanostructure FET.

[0021] To form the semiconductor strip 28, layers of a first semiconductor material, a second semiconductor material, and a third semiconductor material (as shown and arranged above) can be deposited over the semiconductor substrate 20. These layers can be grown using processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited using processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). A patterning process can then be applied to the layers of the first, second, and third semiconductor materials and the semiconductor substrate 20 to define the semiconductor strip 28, which includes a semiconductor strip 20', a pseudo-nanostructure 24, and a semiconductor nanostructure 26.

[0022] Semiconductor fins and nanostructures can be patterned using any suitable method. For example, the patterning process can include one or more photolithography processes, including dual or multiple patterning processes. Typically, dual or multiple patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with pitches, for example, smaller than those achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers are used as an etch mask for the patterning process to etch layers of a first semiconductor material, a second semiconductor material, and a third semiconductor material, as well as the semiconductor substrate 20. Etching can be performed using any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching can be anisotropic.

[0023] Also Figure 2 As shown, an STI region 32 is formed over the semiconductor substrate 20 and between adjacent semiconductor strips 28. The STI region 32 may include a dielectric pad and a dielectric material located above the dielectric pad. Each of the dielectric pad and the dielectric material may include an oxide (such as silicon oxide), a nitride (such as silicon nitride), or a combination thereof. Forming the STI region 32 may include depositing a dielectric layer and performing a planarization process (such as a chemical mechanical polishing (CMP) process, a mechanical polishing process, etc.) to remove excess portions of the dielectric material. The deposition process may include ALD, high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof. In some embodiments, the STI region 32 comprises silicon oxide formed by an FCVD process and a subsequent annealing process. The dielectric layer is then recessed to define the STI region 32. The dielectric layer may be recessed such that the upper portion of the semiconductor strip 28 (including the multilayer stack 22) protrudes above the remaining STI region 32.

[0024] After forming the STI region 32, a dummy gate stack 42 can be formed above and along the sidewalls of the upper portion of the semiconductor strip 28 (the portion protruding above the STI region 32). Forming the dummy gate stack 42 may include forming a dummy dielectric layer 36 on the semiconductor strip 28. The dummy dielectric layer 36 may be formed or include silicon oxide, silicon nitride, combinations thereof, etc., and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 38 is formed above the dummy dielectric layer 36. The dummy gate layer 38 may be deposited, for example, by physical vapor deposition (PVD), CVD, or other techniques, and then planarized, for example, by a CMP process. The material of the dummy gate layer 38 may be conductive or non-conductive and may be selected from the group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (polycrystalline SiGe), etc. A mask layer 40 is formed above the planarized dummy gate layer 38 and may include, for example, silicon nitride, silicon oxynitride, etc. Next, the mask layer 40 can be patterned using photolithography and etching processes to form a mask, which is then used to etch and pattern the dummy gate layer 38 and possibly the dummy dielectric layer 36. The remaining portions of the mask layer 40, the dummy gate layer 38, and the dummy dielectric layer 36 form the dummy gate stack 42.

[0025] exist Figure 3 In this process, a gate spacer 44 and a source / drain recess 46 or trench are formed. First, the gate spacer 44 is formed over the multilayer stack 22 and on the exposed sidewalls of the dummy gate stack 42. The gate spacer 44 can be formed by conformally forming one or more dielectric layers and subsequently anisotropically etching the dielectric layers. Suitable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., which can be formed by deposition processes such as CVD, ALD, etc.

[0026] Subsequently, source / drain recesses 46 are formed in semiconductor strip 28. The source / drain recesses 46 are formed by etching and can extend through the multilayer stack 22 and into semiconductor strip 20'. The bottom surface of the source / drain recesses 46 can be located above, below, or at a level flush with the top surface of the STI region 32. During the etching process, gate spacers 44 and dummy gate stacks 42 mask portions of semiconductor strip 28. Etching can include a single etching process or multiple etching processes. A timing etching process can be used to stop the etching of the source / drain recesses 46 when they reach a desired depth.

[0027] exist Figure 4In this process, internal spacers 54 and dielectric isolation layers 56 are formed. Forming the internal spacers 54 and dielectric isolation layers 56 may include an etching process that laterally etches pseudo-nanostructures 24A and removes pseudo-nanostructures 24B. The etching process may be isotropic and selective for the material of pseudo-nanostructures 24, such that pseudo-nanostructures 24 are etched at a faster rate than semiconductor nanostructures 26. The etching process may also be selective for the material of pseudo-nanostructures 24B, such that pseudo-nanostructures 24B are etched at a faster rate than pseudo-nanostructures 24A. In this way, pseudo-nanostructures 24B can be completely removed from between the lower semiconductor nanostructures 26L (collectively) and the upper semiconductor nanostructures 26U (collectively), without completely removing pseudo-nanostructures 24A. In some embodiments, wherein pseudo-nanostructures 24B are formed of germanium or silicon-germanium with a high percentage of germanium atoms, pseudo-nanostructures 24A are formed of silicon-germanium with a low percentage of germanium atoms, and semiconductor nanostructures 26 are formed of germanium-free silicon, the etching process may include a dry etching process using chlorine gas, with or without plasma. Because the dummy gate stack 42 wraps around the sidewalls of the semiconductor nanostructure 26 (see...) Figure 2 The dummy gate stack 42 can support the upper semiconductor nanostructure 26U, preventing it from collapsing when the dummy nanostructure 24B is removed. Furthermore, although the sidewalls of the dummy nanostructure 24A appear straight after etching, they can be concave or convex.

[0028] An inner spacer 54 is formed on the sidewall of the recessed pseudo-nanostructure 24A, and a dielectric isolation layer 56 is formed between the upper semiconductor nanostructure 26U (collectively referred to as the upper semiconductor nanostructure 26U) and the lower semiconductor nanostructure 26L (collectively referred to as the lower semiconductor nanostructure 26L). As described in more detail later, source / drain regions will subsequently be formed in the source / drain recess 46, and the pseudo-nanostructure 24A will be replaced with a corresponding gate structure. The inner spacer 54 serves as an isolation component between the subsequently formed source / drain regions and the subsequently formed gate structure. In addition, the inner spacer 54 can be used to prevent subsequent etching processes (such as etching processes for forming the gate structure) from damaging the subsequently formed source / drain regions. On the other hand, the dielectric isolation layer 56 is used to isolate the upper semiconductor nanostructure 26U (collectively referred to as the upper semiconductor nanostructure 26U) from the lower semiconductor nanostructure 26L (collectively referred to as the lower semiconductor nanostructure 26L). In addition, the intermediate semiconductor nanostructure (the semiconductor nanostructure 26 in contact with the dielectric isolation layer 56) and the dielectric isolation layer 56 can define the boundary between the lower nanostructure FET and the upper nanostructure FET.

[0029] The internal spacer 54 and dielectric isolation layer 56 can be formed by conformally depositing an insulating material in the source / drain trench 46, on the sidewalls of the pseudo-nanostructure 24, and between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26, and then etching the insulating material. The insulating material can be a hard dielectric material, such as a carbon-containing dielectric material, such as silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, etc. Other low dielectric constant (low k) materials with a k value less than about 3.5 can be used. The insulating material can be formed by deposition processes such as ALD, CVD, etc. The etching of the insulating material can be anisotropic or isotropic. When etched, the insulating material has portions retained in the sidewalls of the pseudo-nanostructure 24A (thus forming the internal spacer 54) and portions retained between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L (thus forming the dielectric isolation layer 56).

[0030] like Figure 4 As shown, a lower epitaxial source / drain region 62L is formed. The lower epitaxial source / drain region 62L is formed in the lower portion of the source / source recess 46. The lower epitaxial source / drain region 62L is in contact with the lower semiconductor nanostructure 26L, but not with the upper semiconductor nanostructure 26U. Figure 4 Not shown in the text, but mentioned below. Figure 7 (Further illustration and discussion). The internal spacer 54 electrically insulates the lower epitaxial source / drain region 62L from the pseudo-nanostructure 24A, which will be replaced by a replacement gate in a subsequent process.

[0031] A lower epitaxial source / drain region 62L is epitaxially grown, and the lower epitaxial source / drain region 62L has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source / drain region 62L is an n-type source / drain region, the corresponding material may include silicon or carbon-doped silicon, which are doped with n-type dopants such as phosphorus, arsenic, etc. When the lower epitaxial source / drain region 62L is a p-type source / drain region, the corresponding material may include silicon or silicon-germanium, which are doped with p-type dopants such as boron, indium, etc. The lower epitaxial source / drain region 62L may be in-situ doped and may or may not be implanted with the corresponding p-type or n-type dopants. During the epitaxy of the lower epitaxial source / drain region 62L, the exposed surfaces (e.g., sidewalls) of the upper semiconductor nanostructure 26U may be masked to prevent undesirable epitaxial growth on the upper semiconductor nanostructure 26U. After growing the lower epitaxial source / drain region 62L, the mask on the upper semiconductor nanostructure 26U can then be removed.

[0032] As a result of the epitaxial process used to form the lower epitaxial source / drain regions 62L, the upper surface of the lower epitaxial source / drain regions 62A has small planes that extend laterally outward beyond the sidewalls of the multilayer stack 22. In some embodiments, adjacent lower epitaxial source / drain regions 62L remain separated after the epitaxial process is completed. In other embodiments, these small planes cause adjacent lower epitaxial source / drain regions 62L of the same FET to merge.

[0033] A first contact etch stop layer (CESL) 66 and a first ILD 68 are formed above the lower epitaxial source / drain region 62L. The first CESL 66 can be formed from a dielectric material with high etch selectivity for etching the first ILD 68, such as silicon oxide, silicon nitride, silicon oxynitride, etc., which can be formed by any suitable deposition process, such as CVD, ALD, etc. The first ILD 68 can be formed from a dielectric material that can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Suitable dielectric materials for the first ILD 68 may include silicon oxide, SiOC, SiON, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass, undoped silicate glass (USG), etc. The formation process may include depositing a conformal CESL layer, depositing the material for the first ILD 68, followed by a planarization process.

[0034] Figure 5A The first recessed portion of the first ILD 68 is shown. In embodiments, one or more etching processes (in...) Figure 5A (Indicated by the arrow marked 501) To recess the first ILD 68, the etching process uses an etchant or combination of etchants that is selective to the material of the first ILD 68. Therefore, while the precise etchant used will depend at least in part on the material of the first ILD 68, in certain embodiments where the first ILD 68 comprises silicon oxide, etchants such as hydrogen fluoride (HF) and ammonia (NH3) may be used to recess the material of the first ILD 68. However, any suitable etchant may be used.

[0035] By placing the semiconductor substrate 20 in, for example Figure 5BThe etching system 500 shown is used to initiate the etching process 501. In some embodiments, the etching system 500 may include an etchant delivery system 503 that delivers one or more gaseous etchants to the etching chamber 504. The etchant delivery system 503 supplies various desired etchants to the etching chamber 504 via an etchant controller 513 and a manifold 505. The etchant delivery system 503 may also help control the flow rate of one or more etchants entering the etching chamber 504 by controlling the flow rate and pressure of the carrier gas passing through the etchant delivery system 503.

[0036] In an embodiment, the etchant delivery system 503 may include a plurality of etchant suppliers 511 and a carrier gas supplier 507. Although Figure 5B Only two etchant suppliers 511 are shown, but this is only for clarity, as any suitable number of etchant suppliers 511 can be used, such as one etchant supplier 511 for each etchant desired to be used within the etching system 500. For example, in an embodiment that will utilize five separate etchants, five etchant suppliers 511 may be present.

[0037] Each etchant supplier 511 may be a container, such as a gas storage tank, located locally or remotely from the etching chamber 504. In other embodiments, the etchant supplier 511 may be a facility for independently preparing and delivering the desired etchant. Any suitable source for the desired etchant may be used as the etchant supplier 511, and all such sources are fully intended to be included within the scope of the embodiments.

[0038] In some embodiments, each etchant supplier 511 supplies etchant to an etchant controller 513 via a first line 502 having a first valve 508. The first valve 508 is controlled by a controller 528, which controls and regulates the introduction of various etchants and carrier gases into the etching chamber 504.

[0039] The carrier gas supplier 507 can supply a desired carrier gas or dilution gas, which can be used to help push or "carry" various desired etchants into the etching chamber 504. The carrier gas can be an inert gas or other gas that does not react with the etchant itself or byproducts of the etchant reaction. For example, the carrier gas can be nitrogen (N2), helium (He), argon (Ar), combinations thereof, etc., but other suitable carrier gases can also be used.

[0040] The carrier gas supplier 507 or diluent supplier may be a container, such as a gas tank, located locally within or away from the etching chamber 504. In other embodiments, the carrier gas supplier 507 may be a facility that independently prepares and delivers carrier gas to the etchant controller 513. Any suitable carrier gas source may be used as the carrier gas supplier 507, and all such sources are intended to be included within the scope of this embodiment. The carrier gas supplier 507 may supply the desired carrier gas to the etchant controller 513 via a second line 510 having a second valve 506, which connects the carrier gas supplier 507 to the first line 502. The second valve 506 is also controlled by a controller 528, which controls and regulates the introduction of various etchants and carrier gases into the etching chamber 504. Once combined, the line may be directed toward the etchant controller 513 for controlled access into the etching chamber 504.

[0041] The etching chamber 504 can be of any desired shape, which can be adapted to disperse the etchant and bring the etchant into contact with the semiconductor substrate 20. Figure 5B In the illustrated embodiment, the etching chamber 504 has cylindrical sidewalls and a bottom. However, the etching chamber 504 is not limited to a cylindrical shape and can utilize any other suitable shape, such as a hollow square tube, an octagon, etc. Furthermore, the etching chamber 504 can be surrounded by an etching chamber housing 515 made of a material inert to various process materials. Therefore, while the etching chamber housing 515 can be any suitable material capable of withstanding the chemicals and pressures involved in the etching process, in some embodiments, the etching chamber housing 515 can be steel, stainless steel, nickel, aluminum, alloys of these, combinations thereof, etc.

[0042] Furthermore, the etching chamber 504 and the mounting platform 545 may be part of a cluster tooling system (not shown). The cluster tooling system may be used in conjunction with an automated processing system to position and place the semiconductor substrate 20 in the etching chamber 504 prior to the etching process, position and hold the semiconductor substrate 20 during the etching process, and remove the semiconductor substrate 20 from the etching chamber 504 after the etching process.

[0043] Mounting platform 545 is located within etching chamber 504 to position and control semiconductor substrate 20 during the etching process. Mounting platform 545 may use electrostatic force, clamps, vacuum pressure, combinations thereof to hold semiconductor substrate 20, and may also include heating and cooling mechanisms to control the temperature of semiconductor substrate 20 during the process.

[0044] Furthermore, the mounting platform 545 may include one or more first heating elements 530 for raising and controlling the temperature of the semiconductor substrate 20 during the etching process. In embodiments, the one or more first heating elements 530 may be resistance heaters or other types of heaters to help control and maintain the temperature. However, any suitable type of heating element may be utilized.

[0045] In some embodiments, the etching chamber 504 includes a nozzle 532. In embodiments, the nozzle 532 receives various etchants from the manifold 505 and helps disperse the various etchants into the etching chamber 504. The nozzle 532 may be designed to uniformly disperse the etchant in order to minimize undesirable process conditions that may be caused by uneven dispersion. In embodiments, the nozzle 532 may have a circular design with its openings uniformly distributed around the nozzle 532 to allow the desired etchant to be dispersed into the etching chamber 504. However, any suitable method of introducing the desired etchant (such as an inlet) may be used to introduce the desired etchant into the etching chamber 504.

[0046] The etching chamber 504 can also be connected to a vacuum pump 525. In this embodiment, the vacuum pump 525 is controlled by a controller 528 and can be used to control the pressure within the etching chamber 504 to a desired pressure. Furthermore, once the etching process is complete, the vacuum pump 525 can be used to evacuate the etching chamber 504 in preparation for the removal of the semiconductor substrate 20.

[0047] Furthermore, while several specific components of the etching system 500 have been described above, other suitable components may also be included. For example, end mounts, gaskets, and any other components that may aid in operating or controlling the etching process may also be included. All such components are intended to be included within the scope of this embodiment.

[0048] To begin recessing the first ILD 68, the process can be started by placing the semiconductor substrate 20 on the mounting platform 545. Once the semiconductor substrate 20 has been placed on the mounting platform 545, an attachment process can be used to attach the semiconductor substrate 20 to the mounting platform 545. In embodiments where the mounting platform 545 is an electrostatic chuck, the semiconductor substrate 20 can be attached to the mounting platform 545 by applying a first current (e.g., alternating current), such that an electrostatic force will be applied to hold the semiconductor substrate 20 to the attachment surface of the mounting platform 545.

[0049] Once the semiconductor substrate 20 is placed and attached to the mounting platform 545, the controller 528 can initiate the recess process by setting the temperature of the semiconductor substrate 20 using the first heating element 530. In an embodiment, the first heating element 530 can be used to adjust the temperature to between approximately -60°C and approximately 80°C. However, any suitable temperature can be used.

[0050] Once the temperature is set using the first heating element 530, the controller 528 can connect one or more etchant suppliers 511 and a carrier gas supplier 507 to the etching chamber 504 to introduce a first etch combination of etchant (e.g., hydrogen fluoride (HF) and ammonia (NH3)) into the semiconductor substrate 20. In embodiments where the first ILD 68 is recessed using hydrogen fluoride and ammonia when the first ILD 68 comprises silicon oxide, the etching process can proceed according to the following chemical equation:

[0051] SiO 2(g) +4HF (g) +4NH 3(g) →SiF 4(g) +2H2O (g) +4NH3

[0052] As can be seen, silicon oxide will react with the etchant to form silicon fluoride (SiF4) and water, thereby removing the material of the first ILD 68 from the structure.

[0053] However, the above-described reaction is not the only reaction that occurs during the removal process, and other side reactions can occur, in which undesirable byproducts 531 and / or salts can be generated and remain within the source / drain trench 46 and on the surface of the semiconductor substrate 20. As an example of such a side reaction, the silicon fluoride generated in the main reaction can continue to react according to the following chemical equation:

[0054] SiF 4(g) +2HF (g) +2NH 3(g) →(NH4)2SiF 6(s)

[0055] This side reaction will produce an undesirable byproduct 531, such as ammonium hexafluorosilicate (AFS). Furthermore, this byproduct 531 will form as a solid within the forming source / drain trench 46. Unless this situation is improved, the solid form of ammonium hexafluorosilicate will interfere with further etching and can lead to significant variations in the depth of formation in different source / drain trenches 46.

[0056] Therefore, as Figures 6A to 6BAs shown, to aid in the removal of unwanted byproducts 531 (e.g., ASF) and ensure that they do not interfere with the remainder of the removal process 501, a secondary heating element 527 is included within the etching chamber 504. In one particular embodiment, the secondary heating element 527 includes a laser device that can output a laser beam 529 toward the semiconductor substrate 20, and more specifically, toward the unwanted byproducts 531 located within the source / drain recess 46. In some embodiments, the secondary heating element 527 may have an adjustable orientation to adjust the angle of incidence of the laser beam 529 striking the semiconductor substrate 20.

[0057] In embodiments, the laser beam 529 is also tunable, such that it includes light of one or more wavelengths that aid in the decomposition of the undesirable byproduct 531. For example, in an embodiment where the undesirable byproduct 531 is AFS, the laser beam 529 includes light along a spectrum, wherein the light along the spectrum is absorbed by bonds present within the AFS (e.g., the AFS absorption spectrum). By using such a spectrum, the decomposition of the AFS is facilitated by inducing decomposition according to the following chemical formula when the laser beam 529 strikes the AFS:

[0058] (NH4)2SiF 6(s) →SiF 4(g) +2HF (g) +2NH 3(g)

[0059] By using the laser beam 529, unwanted byproducts 531 can be removed more easily during the recess of the first ILD 68. Therefore, in the absence of byproducts 531, they cannot interfere with the remainder of the etching process 501, and variations between different source / drain recesses 46 can be reduced.

[0060] Figure 7 As shown, once the first ILD 68 has been recessed, an anisotropic etching process is then performed to remove the portion of the first CESL 66 above the recessed first ILD 68. After recessing, the sidewalls of the upper semiconductor nanostructure 26U are exposed.

[0061] Then, an upper epitaxial source / drain region 62U is formed in the upper portion of the source / drain recess 46. The upper epitaxial source / drain region 62U can be epitaxially grown from the exposed surface of the upper semiconductor nanostructure 26U. The material of the upper epitaxial source / drain region 62U can be selected from the same group of candidate materials used to form the lower epitaxial source / drain region 62L, depending on the desired conductivity type of the upper epitaxial source / drain region 62U. In embodiments where the stacked transistor is a CFET, the conductivity type of the upper epitaxial source / drain region 62U can be opposite to that of the lower epitaxial source / drain region 62L. For example, the upper epitaxial source / drain region 62U can be doped in opposite directions to the lower epitaxial source / drain region 62L. Alternatively, the upper epitaxial source / drain region 62U and the lower epitaxial source / drain region 62L can have the same conductivity type. The upper epitaxial source / drain region 62U can be doped in situ and / or implanted with n-type or p-type dopants. Adjacent upper source / drain regions 62U can remain separated after the epitaxial process, or they can be merged.

[0062] After forming the epitaxial source / drain region 62U, a second CESL 70 and a second ILD 72 are formed. The materials and formation methods can be similar to those of the first CESL 66 and the first ILD 68, respectively, and will not be discussed in detail here. The formation process may include depositing layers for CESL 70 and ILD 72, and performing a planarization process to remove excess portions of the respective layers. After the planarization process, the top surfaces of the second ILD 72, the gate spacer 44, and the mask 86 (if present) or dummy gate 84 are substantially coplanar (within process variations). Therefore, the top surface of the mask 40 (if present) or dummy gate 38 is exposed through the second ILD 72. In the illustrated embodiment, the mask 40 is retained after the removal process. In other embodiments, the mask 40 is removed such that the top surface of the dummy gate 38 is exposed through the second ILD 72.

[0063] Figure 8A replacement gate process is illustrated, in which a gate stack 90 replaces the dummy gate stack 42 and the dummy nanostructure 24A. The replacement gate process includes first removing the remaining portions of the dummy gate stack 42 and the dummy nanostructure 24A. The dummy gate stack 42 is removed in one or more etching processes, such that a groove is defined between the gate spacers 44, and the upper portion of the semiconductor strip 28 is exposed. The remaining portions of the dummy nanostructure 24A are then removed by etching, such that the groove extends between the semiconductor nanostructures 26. In the etching process, the dummy nanostructure 24A is etched at a faster rate than the semiconductor nanostructures 26, the dielectric isolation layer 56, and the internal spacers 54. The etching can be isotropic. For example, when the dummy nanostructure 24A is formed of silicon germanium and the semiconductor nanostructure 26 is formed of silicon, the etching process can include a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0064] Then, a gate dielectric 78 is deposited in the grooves between the gate spacers 44 and on the exposed semiconductor nanostructure 26. The gate dielectric 78 is conformally formed on the exposed surface of the grooves (removed gate stack 42 and pseudo nanostructure 24A) including the semiconductor nanostructure 26 and the gate spacers 44. In some embodiments, the gate dielectric 78 encapsulates all (e.g., four) sides of the semiconductor nanostructure 26. Specifically, the gate dielectric 78 may be formed on the top surface of the fin 20'; the top, sidewalls, and bottom surfaces of the semiconductor nanostructure 26; and the sidewalls of the gate spacers 44. The gate dielectric 78 may include oxides such as silicon oxide or metal oxides, silicates such as metal silicates, combinations thereof, multilayers thereof, etc. The gate dielectric 78 may include high dielectric constant (high k) materials with a k value greater than about 7.0, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods for forming the gate dielectric 78 may include molecular beam deposition (MBD), ALD, PECVD, etc., followed by a planarization process (e.g., CMP) to remove portions of the gate dielectric 78 above the second ILD 72. Although a single-layer gate dielectric 78 is shown, the gate dielectric 78 may comprise multiple layers, such as an interface layer and an overlying high-k dielectric layer.

[0065] A lower gate electrode 80L is formed on a gate dielectric 78 surrounding the lower semiconductor nanostructure 26L. For example, the lower gate electrode 80L encapsulates the lower semiconductor nanostructure 26L. The lower gate electrode 80L can be formed of a metallic material, such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, or multilayers thereof. Although a single-layer gate electrode is shown, the lower gate electrode 80L may include any number of work function conditioning layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0066] The lower gate electrode 80L is formed of a material suitable for the device type of the lower nanostructure FET. For example, the lower gate electrode 80L may include one or more work function modulation layers formed of a material suitable for the device type of the lower nanostructure FET. In some embodiments, the lower gate electrode 80L includes an n-type work function modulation layer, which may be formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, etc. In some embodiments, the lower gate electrode 80L includes a p-type work function modulation layer, which may be formed of titanium nitride, tantalum nitride, combinations thereof, etc. Additionally or optionally, the lower gate electrode 80L may include a dipole inducing element suitable for the device type of the lower nanostructure FET. Acceptable dipole inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0067] The lower gate electrode 80L can be formed by conformally depositing one or more gate electrode layers and recessing the gate electrode layers. Any acceptable etching process (such as dry etching, wet etching, or combinations thereof) can be performed to recess the gate electrode layers. The etching can be isotropic. Etching the lower gate electrode 80L can expose the upper semiconductor nanostructure 26U.

[0068] In some embodiments, an isolation layer (not explicitly shown) may optionally be formed on the lower gate electrode 80L. The isolation layer serves as an isolation component between the lower gate electrode 80L and the subsequently formed upper gate electrode 80U. The isolation layer can be formed by conformally depositing a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof, etc.) and subsequently recessing the dielectric material to expose the upper semiconductor nanostructure 26U.

[0069] Then, an upper gate electrode 80U is formed on the aforementioned isolation layer (if present) or the lower gate electrode 80L. The upper gate electrode 80U is disposed between the upper semiconductor nanostructures 26U. In some embodiments, the upper gate electrode 80U encapsulates the upper semiconductor nanostructures 26U. The upper gate electrode 80U may be formed from the same candidate materials and candidate processes used to form the lower gate electrode 80L. The upper gate electrode 80U is formed from a material suitable for the device type of the upper nanostructure FET. For example, the upper gate electrode 80U may include one or more work function modulation layers (e.g., n-type work function modulation layers and / or p-type work function modulation layers) formed from a material suitable for the device type of the upper nanostructure FET. Although a single-layer gate electrode 80U is shown, the upper gate electrode 80U may include any number of work function modulation layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0070] Furthermore, a removal process is performed to make the top surfaces of the upper gate electrode 80U and the second ILD 72 flush. The removal process used to form the gate dielectric 78 can be the same as the removal process used to form the upper gate electrode 80U. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, and combinations thereof can be utilized. After the planarization process, the top surfaces of the upper gate electrode 80U, the gate dielectric 78, the second ILD 72, and the gate spacer 44 are substantially coplanar (within process variations). The gate dielectric 78 and gate electrode 80 of each corresponding pair (including the upper gate electrode 80U and / or the lower gate electrode 80L) can be collectively referred to as the “gate structure” 90 (including the upper gate structure 90U and the lower gate structure 90L). Each gate structure 90 is along the semiconductor nanostructure 26 (see Figure 1 The lower gate structure 90L extends along three sides (e.g., top, sidewall, and bottom) of the channel region of the semiconductor fin 20'.

[0071] Also Figure 8 As shown, a gate mask 92 is formed over a gate stack 90. ​​The formation process may include recessing the gate stack 90, filling the resulting recess with a dielectric material (such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbonitride, etc.), and performing a planarization process to remove excess dielectric material over the second ILD 72.

[0072] exist Figure 9 In this configuration, a metal-semiconductor alloy region 94 and a source / drain contact 96 are formed through the second ILD 72 to be electrically coupled to an upper epitaxial source / drain region 62U and / or a lower epitaxial source / drain region 62L. As an example of forming the source / drain contact 96, an opening is formed through the second ILD 72 and the second CESL 70 using acceptable photolithography and etching techniques. Pads (not shown separately) (such as diffusion barrier layers, adhesive layers, etc.) and conductive material are formed in the opening. The pads may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc. A removal process may be performed to remove excess material from the gate spacer 44 and the top surface of the second ILD 72. The remaining pads and conductive material form the source / drain contact 96 in the opening. In some embodiments, planarization processes such as CMP, etch-back processes, and combinations thereof are utilized. After the planarization process, the top surfaces of the gate spacer 44, the second ILD 72, and the source / drain contact 96 are substantially coplanar (within process variations).

[0073] Optionally, a metal-semiconductor alloy region 94 is formed at the interface between the source / drain region 62 and the source / drain contact 96. The metal-semiconductor alloy region 94 can be a silicide region formed from metal silicides (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed from metal germanides (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), or a silicon-germanide region formed from both metal silicides and metal germanides. The metal-semiconductor alloy region 94 can be formed before the material of the source / drain contact 96 by depositing metal in the opening for the source / drain contact 96 and then performing a thermal annealing process. The metal can be any metal capable of reacting with the semiconductor material of the source / drain region 62 (e.g., silicon, silicon-germanium, germanium, etc.) to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The metal can be deposited by deposition processes such as ALD, CVD, PVD, etc. Following the thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from the openings used for the source / drain contacts 96 (such as from the surface of the metal-semiconductor alloy region 94). The material for the source / drain contacts 96 can then be formed on the metal-semiconductor alloy region 94.

[0074] Then, ESL 104 and the third ILD 106 are formed. In some embodiments, ESL 104 may include a dielectric material with high etch selectivity for etching the third ILD 106, such as alumina, aluminum nitride, silicon carbide, etc. The third ILD 106 can be formed using flowable CVD, ALD, etc., and the material may include PSG, BSG, BPSG, USG, etc., which can be deposited by any suitable method, such as CVD, PECVD, etc.

[0075] Subsequently, gate contact 108 and source / drain via 110 are formed to contact the upper gate electrode 80U and source / drain contact 96, respectively. As an example of forming gate contact 108 and source / drain via 110, openings for gate contact 108 and source / drain via 110 are formed through the third ILD 106 and ESL 104. The openings can be formed using acceptable photolithography and etching techniques. Pads (not shown separately) (such as diffusion barrier layers, adhesive layers, etc.) and conductive material are formed in the openings. Pads may include titanium, titanium nitride, tantalum, tantalum nitride, etc. Conductive material may be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc. A planarization process (such as CMP) can be performed to remove excess material from the top surface of the third ILD 106. The remaining pads and conductive material form gate contact 108 and source / drain via 110 in the openings. The gate contact 108 and the source / drain via 110 can be formed in different processes or in the same process. Although shown as being formed in the same cross-section, it should be understood that each of the gate contact 108 and the source / drain via 110 can be formed in different cross-sections, which can prevent short circuits in the contacts.

[0076] A front interconnect structure 114 is formed on device layer 112. The front interconnect structure 114 includes a dielectric layer 116 and a layer of conductive components 118 located within the dielectric layer 116. The dielectric layer 116 may include a low-k dielectric layer formed of a low-k dielectric material. The dielectric layer 116 may also include a passivation layer located above the low-k dielectric material, the passivation layer being formed of a non-low-k and dense dielectric material, such as undoped silicate glass (USG), silicon oxide, silicon nitride, or combinations thereof. The dielectric layer 116 may also include a polymer layer.

[0077] Conductive components 118 may include wires and vias that can be formed using an inlay process. Conductive components 118 may include metal wires and metal vias, which include diffusion barriers and copper-containing material above the diffusion barriers. Aluminum pads electrically connected to the metal wires and vias may also be present above the metal wires and vias. In some embodiments, the lower gate structure 90L and the lower source / drain region 80L may be contacted via the back side of device layer 112 (e.g., the side opposite to the front interconnect structure 114).

[0078] By utilizing the secondary heating element 527, the unwanted byproduct 531 can be heated independently. Furthermore, this heating is separate from and independent of the heating controlled by the first heating element 530. Therefore, through this independent heating, the byproduct 531 can be removed and decomposed without affecting the remainder of the etching process.

[0079] Furthermore, although the above description describes the use of the secondary heating element 527 as occurring after the start of the etching process 501, this is not intended to limit the embodiments. Rather, the secondary heating element 527 can be started at any desired point in the process, such as simultaneously with the start of the etching process 501.

[0080] Figure 10 Another embodiment of the secondary heating element 527 is shown. In this embodiment, the secondary heating element 527 may be an ultraviolet light emitter, an infrared light emitter, a light-emitting diode (LED), or a vacuum ultraviolet light emitter that outputs a laser beam 1001, rather than a laser that outputs a laser beam (as described above regarding...). Figure 5B (as described above). However, light of any suitable wavelength can be used.

[0081] Furthermore, in some embodiments, the secondary heating element 527 can be tunable relative to the wavelength of the output light and also tunable relative to a scan. For example, in some embodiments, the wavelength of the generated light can be adjusted in part based on at least the byproduct 531 to be decomposed. Additionally, if the output beam 1001 is insufficient to illuminate all desired areas, a scanning process can be used, in which one or more of the semiconductor substrate 20 or the secondary heating element 527 are rotated relative to each other. Any suitable adjustment can be utilized.

[0082] Figure 11 Another embodiment of the secondary heating element 527 is shown. In this embodiment, the secondary heating element 527 may be an electron beam generator, rather than a laser that outputs a laser beam (as described above regarding...). Figure 5B The above-mentioned) or light-emitting diodes (LEDs) (as mentioned above) Figure 10 (as described above). In this embodiment, the secondary heating element 527 outputs an electron beam 1101, which is used to independently heat the byproduct 531 separately from the remainder of the semiconductor substrate 20.

[0083] Furthermore, in this embodiment, the secondary heating element 527 can be adjusted relative to the wavelength and incident angle of the output electron beam 1101, and also relative to the scan. For example, in some embodiments, the wavelength of the generated electron beam 1101 can be adjusted in part based on the desired at least byproduct 531. Additionally, if the output electron beam 1101 is insufficient to illuminate all desired areas, a scanning process can be utilized, in which one or more of the semiconductor substrate 20 or the secondary heating element 527 are rotated relative to each other.

[0084] Figure 12 Another embodiment of the secondary heating element 527 is shown. In this embodiment, the secondary heating element 527 may be a thermally neutral injection device, rather than a laser that outputs a laser beam (as described above regarding...). Figure 5BAs mentioned above), light-emitting diodes (LEDs) (as described above) Figure 10 The aforementioned) or electron beam generator (as described above regarding Figure 11 (as described above). In this embodiment, the secondary heating element 527 introduces gas or free radicals from, for example, a neutral heating chamber into the etching chamber 504. In this embodiment, the neutral heating chamber receives the gas and / or free radicals and heats the gas and / or free radicals using a heating method such as laser, microwave (MW), light-emitting diode, plasma process, combinations thereof, etc. However, any suitable heating method can be used.

[0085] Once the gas and / or free radicals are heated within the neutral heating chamber, they are injected into the etching chamber 504 through one or more secondary nozzles 1203. In an embodiment, the one or more secondary nozzles 1203 may resemble nozzle 532 (mentioned above). Figure 5B (as described above). However, any suitable method or device can be used to inject heater-neutral particles into etching chamber 504.

[0086] Furthermore, in this embodiment, the secondary heating element 527 can be adjusted relative to the introduction of thermally neutral particles. For example, if the introduction of thermally neutral particles is insufficient to introduce them into all desired areas, a scanning process can be used, in which one or more of the semiconductor substrate 20 or the secondary heating element 527 are rotated relative to each other.

[0087] Figure 13 Another embodiment of the secondary heating element 527 is shown. In this embodiment, the secondary heating element 527 may be an electron bombardment device, rather than a laser that outputs a laser beam (as described above regarding...). Figure 5B As mentioned above), light-emitting diodes (LEDs) (as described above) Figure 10 The electron beam generator (as mentioned above) Figure 11 The above-mentioned) or thermally neutral injector (as described above) Figure 12 (as described above). In this embodiment, the secondary heating element 527 introduces electrons 1301 from, for example, an electron injector into the etching chamber 504. Once electrons 1301 have been injected into the etching chamber 504, electrodes 1303 can be used to provide a DC bias to accelerate the electrons 1301 toward the semiconductor substrate 20.

[0088] Of course, while a specific number of embodiments have been presented above, these ideas are not intended to limit them to the precise embodiments described. Rather, any other suitable method may be used to decompose the byproduct 531 by independently heating it. All such methods are intended to be included within the scope of the embodiments.

[0089] Figure 14As shown, while a specific structure has been presented above, the proposed concept is not intended to be limited to the precise structure described. Rather, the concept can be used with any suitable material (e.g., first material 1401) that is recessed into any other suitable material (e.g., second material 1403). In such an embodiment, the first material 1401 may be a material such as silicon oxide, silicon carbide, silicon oxynitride, or combinations thereof, while the second material 1403 may be a material such as silicon, silicon nitride, silicon carbonitride, SiOCN, aluminum oxide, titanium nitride, tungsten, or combinations thereof. However, any suitable material can be utilized.

[0090] Once the first material 1401 is deposited within the second material 1403, the first material 1401 is recessed. This can be achieved using the information above regarding... Figures 1 to 14 The process described involves recessing the first material 1401, including the use of a separate heat source to heat and decompose unwanted byproducts 531 during the etching process 501. Therefore, byproducts 531 can be removed without interfering with the remainder of the etching process 501.

[0091] By utilizing the embodiments described herein, a separate heat source is employed to remove byproduct 531 and salt generated during the chemical etching process. This feature allows for the temperature control of the semiconductor substrate 20 and byproduct 531 to be separated from each other. This separation helps to improve depth variation and avoids a decrease in etching rate by using generally high temperatures.

[0092] According to an embodiment, a method of manufacturing a semiconductor device includes: depositing a dielectric material in a trench above a semiconductor substrate; recessing the dielectric material using an etching process, wherein the etching process includes: heating the semiconductor substrate; and separately heating a byproduct of the etching process. In an embodiment, the byproduct is ammonium hexafluorosilicate. In an embodiment, separate heating is performed at least partially using a laser. In an embodiment, separate heating is performed at least partially using a light-emitting diode. In an embodiment, separate heating is performed at least partially using electron injection. In an embodiment, separate heating is performed at least partially using thermally neutral particles. In an embodiment, separate heating is performed at least partially using an electron beam.

[0093] According to another embodiment, a method of manufacturing a semiconductor device includes: placing a semiconductor wafer in an etching chamber, the etching chamber including a first heating element, the semiconductor wafer including a dielectric material located within a first recess; reacting the dielectric material to form a gas and recessing the dielectric material, the reaction of the dielectric material also producing byproducts; and heating the byproducts using a second heating element different from the first heating element. In an embodiment, the second heating element is an electron injector. In an embodiment, the second heating element is an electron beam generator. In an embodiment, the second heating element is a neutral heating chamber. In an embodiment, the second heating element is a light-emitting diode. In one embodiment, the second heating element is a laser. In an embodiment, the byproduct is ammonium hexafluorosilicate.

[0094] According to another embodiment, an apparatus for manufacturing a semiconductor device includes: an etching chamber; a mounting platform; a first heating element; and a second heating element, independent of the first heating element. In one embodiment, the first heating element is a resistance heating element. In another embodiment, the second heating element is a laser. In another embodiment, the second heating element is an electron beam generator. In another embodiment, the second heating element is a light-emitting diode. In another embodiment, the second heating element is an infrared generator.

[0095] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: Dielectric material is deposited in trenches above a semiconductor substrate; as well as The dielectric material is recessed using an etching process, wherein the etching process includes: Heating the semiconductor substrate; and The byproducts of the etching process are heated separately.

2. The method according to claim 1, wherein, The byproduct is ammonium hexafluorosilicate.

3. The method according to claim 1, wherein, The individual heating is performed at least partially using a laser.

4. The method according to claim 1, wherein, The individual heating is performed at least partially using light-emitting diodes.

5. The method according to claim 1, wherein, The individual heating is performed at least partially using electron injection.

6. The method according to claim 1, wherein, The individual heating is performed at least partially using thermally neutral particles.

7. The method according to claim 1, wherein, The individual heating is performed at least partially using an electron beam.

8. A method for manufacturing a semiconductor device, the method comprising: A semiconductor wafer is placed in an etching chamber, the etching chamber including a first heating element, and the semiconductor wafer including a dielectric material located in a first groove; The dielectric material is reacted to form a gas and the dielectric material is recessed, and the reaction of the dielectric material also produces byproducts; and The byproduct is heated using a second heating element that is different from the first heating element.

9. The method according to claim 8, wherein, The second heating element is an electron injector.

10. An apparatus for manufacturing a semiconductor device, the apparatus comprising: Etching chamber; Installation platform; First heating element; as well as The second heating element is independent of the first heating element.

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