Semiconductor device with current propagation region and method of manufacture

Abstract

The invention relates to a semiconductor device with a current propagation region and a manufacturing method. A semiconductor device includes a base layer (200) and a transistor layer (100). The base layer (200) is based on single crystal silicon carbide and includes a current propagation region (230) of a first conductivity type and a non-depletable shield structure (260) of a second conductivity type. The transistor layer (100) is based on epitaxially grown single crystal silicon carbide, and includes a transistor cell (TC) configured to control a current through the current propagation region (230). After forming the shielding structure (260) in the base layer (200), a transistor layer (100) is formed on the base layer (200) such that an epitaxial interface (201) is formed between the base layer (200) and the transistor layer (100). A current propagation region (230) extends from the epitaxial interface (201) between adjacent partial regions of the shielding structure (260). The change in net dopant concentration at the location of the pn junction is at least 1 e171 / cm3 per 0.1 [mu] m along a vertical line orthogonal to the epitaxial interface (201) and passing through the pn junction between the shielding structure (260) and the region of the first conductivity type in the transistor layer (100).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a silicon carbide-based semiconductor device having a current spreading region. The present disclosure also relates to a method of manufacturing a silicon carbide-based semiconductor device. BACKGROUND

[0002] In a silicon carbide MOSFET with a planar gate, a gate dielectric and a gate conductor are formed on a first major surface. In a silicon carbide trench MOSFET, a gate dielectric and a gate conductor are formed in a gate trench extending from the first major surface at the front side of a silicon carbide portion into the silicon carbide portion. In both types of silicon carbide MOSFETs (SiC-MOSFETs), the gate dielectric separates the gate conductor from a weakly doped p-conducting body region formed in the silicon carbide portion. In the on-state of the SiC-MOSFET, an electron channel is formed in a channel portion of the body region along the gate dielectric. An n-conducting drift layer is formed in a portion of the silicon carbide portion between the body region and a second major surface of the silicon carbide portion opposite the first major surface. A heavily doped p-conducting shield region formed between the weakly doped p-conducting body region and the drift layer shields the body region with the channel portion from the electric potential of the drift layer and reduces the electric field in the body region. The shield region of a trench SiC-MOSFET can be formed by implanting a dopant ion through the bottom of the gate trench before depositing the gate conductor material in the gate trench. For a SiC-MOSFET with a planar gate, the dopant ion is implanted through the first major surface, wherein a high implant energy is used to reach a deeper implant depth compared to the weakly doped p-conducting body region.

[0003] There is an ongoing need to improve the on-state resistance of SiC-MOSFETs (e.g., SiC-MOSFETs with a trench gate and SiC-MOSFETs with a planar gate). SUMMARY

[0004] A semiconductor device according to the present disclosure comprises a base layer and a transistor layer. The base layer is based on single crystalline silicon carbide and comprises a current spreading region of a first conductivity type and a non-depletable shield structure of a second conductivity type. The transistor layer is based on single crystalline silicon carbide grown in an epitaxial manner and comprises a transistor cell controlling a current through the current spreading region. The transistor layer is formed on the base layer after forming the shield structure in the base layer, wherein an epitaxial interface is formed between the base layer and the transistor layer. The current spreading region extends from the epitaxial interface between adjacent portion regions of the shield structure. Along a vertical line orthogonal to the epitaxial interface and through a pn-junction between a region of the first conductivity type in the shield structure and the transistor layer, the net dopant concentration change is at least 1e17l / cm3per 0.1 pm at the location of the pn-junction. 3 .

[0005] Since the acceptor ions of the shielding structure can be implanted before the transistor layer is formed, the acceptor ions do not pass through the transistor layer. Lateral spreading can be reduced. The formation of implant tails in the transistor layer can be prevented or at least slowed down. The absence of implant tails can facilitate the formation of a narrow current path through the shielding structure. Since the energy required for implanting the shielding structure into the base layer can be comparatively low, the implant mask can be significantly thinner compared to implanting acceptor ions through the transistor layer. As a result, the lateral dimensions of the shielding structure and the lateral transition between the shielding structure and the current path can be more precisely defined. The semiconductor device can combine a low on-state resistance RDSon with a very efficient shielding of the body region.

[0006] The present disclosure relates to a semiconductor device based on silicon carbide and having a transistor cell. Particular examples of such semiconductor devices include an n-channel SiC-MOSFET or n-channel SiC-TMOSFET with a planar gate. However, the present disclosure is also applicable to a p-channel SiC-MOSFET.

[0007] Those skilled in the art will, through reading the following detailed description and viewing the attached drawings, appreciate additional features and advantages of the embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0008] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this description. The drawings illustrate embodiments of semiconductor devices and methods of manufacturing semiconductor devices, and together with the description, serve to explain the principles of the embodiments. Additional embodiments are described in the detailed description below and in the claims. Features of various embodiments can be combined with each other.

[0009] Figure 1A is a schematic vertical sectional view of a portion of a semiconductor device according to an embodiment, the current propagation region being laterally confined by regions of a non-depletable shielding structure.

[0010] Figure 1B is a schematic diagram illustrating the dopant concentration along the vertical line B-B in Figure 1A

[0011] Figure 1C is a schematic diagram illustrating the dopant concentration along the horizontal line C-C in Figure 1A

[0012] Figure 2 is a schematic vertical sectional view of a portion of a semiconductor device according to an embodiment, the current propagation region being laterally confined by regions of a non-depletable shielding structure, the embodiment relating to a transistor cell having a planar gate electrode.

[0013] Figure 3 ​​is a schematic vertical cross-sectional view of a portion of a semiconductor device according to an embodiment, the current propagation region laterally confined by regions of non-depletable shielding structure, the embodiment involving a trench gate structure in direct contact with the shielding structure.

[0014] Figure 4 is a schematic vertical cross-sectional view of a portion of a semiconductor device according to an embodiment, the current propagation region laterally confined by regions of non-depletable shielding structure, the embodiment involving a trench gate structure spaced apart from the shielding structure.

[0015] Figure 5 is a schematic diagram illustrating a dopant concentration gradient along a vertical line through an epitaxial interface between a current propagation region and a current collection region according to an embodiment.

[0016] Figure 6A is a schematic diagram illustrating a dopant concentration gradient along a vertical line through an epitaxial interface between a shielding structure and a connection region according to an embodiment.

[0017] Figure 6B is a schematic diagram illustrating a dopant concentration gradient along a vertical line through an epitaxial interface between a shielding structure and a current collection region of a transistor cell having a trench gate structure according to an embodiment.

[0018] Figure 7 and Figure 8 is a schematic vertical cross-sectional view of a portion of a semiconductor device according to an embodiment, the embodiment involving a transistor cell having a planar gate electrode.

[0019] Figure 9 is a schematic vertical cross-sectional view of a portion of a semiconductor device according to an embodiment, the embodiment involving a transistor cell having a trench gate electrode and a single-sided transistor channel.

[0020] Figure 10 is a schematic vertical cross-sectional view of a portion of a semiconductor device according to an embodiment, the embodiment involving a transistor cell having a trench gate electrode and a double-sided transistor channel.

[0021] Figure 11 is a schematic vertical cross-sectional view of a portion of a semiconductor device according to an embodiment, the embodiment involving a transistor cell having a metal contact plug extending from a top surface into a transistor layer 100.

[0022] Figure 12 is a schematic horizontal cross-sectional view of a portion of a semiconductor device according to an embodiment having a striped-shaped trench gate structure, n-conducting source regions and p-conducting contact regions alternating along a horizontal longitudinal axis of the trench gate structure.

[0023] Figure 13A andFigure 13B is a schematic vertical sectional view along the lines I-I and II-II of Figure 12 the embodiment relates to a wide n-conducting channel portion laterally confined by a shielding structure.

[0024] Figure 14A and Figure 14B is a schematic vertical sectional view along the lines I-I and II-II of Figure 12 the embodiment relates to a narrow n-conducting channel portion laterally confined by a shielding structure.

[0025] Figure 15A and Figure 15B is a schematic vertical sectional view along the lines I-I and II-II of Figure 12 the embodiment relates to a narrow n-conducting channel portion and a trench gate structure not reaching the base layer.

[0026] Figure 16A and Figure 16B is a schematic vertical sectional view along the lines I-I and II-II of Figure 12 the embodiment relates to a p-conducting narrow auxiliary region separating the trench gate structure and the shielding structure in vertical direction, wherein the pillars of the compensation structure run parallel to the stripe-shaped trench gate structure.

[0027] Figure 17A , Figure 17B , Figure 17C is a schematic vertical sectional view along the lines I-I, II-II and IV-IV of Figure 12 the embodiment relates to a p-conducting narrow auxiliary region separating the trench gate structure and the grid-shaped shielding structure in vertical direction, wherein the pillars of the compensation structure run orthogonal to the stripe-shaped trench gate structure.

[0028] Figure 17D is a schematic vertical sectional view along a line parallel to the line I-I of Figure 12 the pillars of the compensation structure run orthogonal to the stripe-shaped trench gate structure and the stripe-shaped portion regions of the shielding structure run parallel to the stripe-shaped trench gate structure.

[0029] Figure 18A and Figure 18B is a schematic vertical sectional view along the lines I-I and II-II of Figure 12 the pillars of the compensation structure run orthogonal to the stripe-shaped trench gate structure and the shielding structure comprises shielding islands laterally separated.

[0030] Figure 19A , Figure 19B and Figure 19Cis a schematic vertical sectional view along the lines I-I, II-II and III-III of a semiconductor device according to an embodiment, wherein the columnar shape of the compensating structure and the stripe shape of the shielding structure are orthogonal to the stripe shape trench gate structure. Figure 12

[0031] Figure 20 is a schematic vertical sectional view of a portion of a semiconductor device according to an embodiment, which embodiment relates to a current spreading region having a central channel portion and a heavily doped sidewall portion between the central channel portion and the shielding structure.

[0032] Figures 21A-21B is a schematic vertical sectional view of a portion of a semiconductor device according to an embodiment, which illustrates a method of manufacturing a semiconductor device, before and after forming a transistor layer on a base layer in which the shielding structure is formed.

[0033] Figures 22A-22D is a schematic vertical sectional view of a portion of a semiconductor device according to another embodiment, which illustrates a method of manufacturing a semiconductor device having a compensating structure.

[0034] Figures 23A-23D is a schematic vertical sectional view of a portion of a semiconductor device according to an embodiment, which illustrates a method of manufacturing a semiconductor device, which embodiment relates to a current spreading region having a central channel portion and a heavily doped sidewall portion between the central channel portion and the shielding structure. DETAILED DESCRIPTION

[0035] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown, by way of illustration, certain embodiments of a semiconductor device and a method of manufacturing a semiconductor device. Structural or logical modifications of the illustrated embodiments can be made without departing from the scope of the present disclosure. For example, certain features of one embodiment can be used on or in combination with other embodiments, resulting in yet another embodiment. This disclosure is intended to include such modifications and variations. The embodiments are described in such a way that the features of the disclosure are not limited to one embodiment but can be used in combination with other embodiments. The drawings are not necessarily to scale and are solely for purposes of illustration. Unless otherwise indicated, like numbers in the various drawings indicate the same or similar elements. The following detailed description should be taken in conjunction with the drawings, in which:

[0036] The terms "have," "having," "contain," "containing," "include," "including," and the like are open-ended, and the terms specify the presence of certain elements or features but do not preclude the presence or addition of other elements or features. The articles "a," "an," and "the" are used herein to refer to one or to more than one (i.e., to "at least one") of the associated element, unless the context clearly indicates otherwise.

[0037] ​The terms "signal connection" and "electrically connected" can include a permanent low resistance ohmic connection between the elements connected electrically, for example a direct contact between the elements involved or a low resistance connection via metal and / or heavily doped semiconductor material, but do not exclude that further passive and / or active elements are present in the signal path between the elements "signal connected" or "electrically connected". For example, the further elements can include resistors, resistive conductor lines, capacitors and / or inductors, transistors, semiconductor diodes, Schottky diodes, transformers, optocouplers and other elements.

[0038] The term "directly electrically connected" can describe a permanent low resistance ohmic connection between the elements connected electrically, for example a direct contact between the elements involved or a low resistance connection via metal and / or heavily doped semiconductor material.

[0039] The term "power semiconductor device" refers to a semiconductor device having a high voltage blocking capability of at least 30 V (e.g., 48 V, 100 V, 600 V, 1.6 kV, 3.3 kV or more) and having a nominal on-state current or forward current of at least 200 mA (e.g., 1 A, 10 A or more).

[0040] The safe operating area (SOA) of a semiconductor device is defined as the voltage and current conditions at which the semiconductor device can be expected to operate without self-damage.

[0041] An ohmic contact describes a non-rectifying electrical junction between two conductors (e.g., between a semiconductor material and a metal). An ohmic contact has a linear or approximately linear current-voltage (I-V) curve in the first and third quadrant of the I-V diagram as per Ohm's law.

[0042] Ranges given for physical sizes include the boundary values. For example, a range of from a to b for a parameter y reads as a < y < b. The same applies to ranges having one boundary value, such as "at most" and "at least".

[0043] The term "on" should not be interpreted as meaning "directly on". Rather, if a component is disposed "on" another component (e.g., a layer "on" another layer or "on" a substrate), another component (e.g., another layer) can be disposed between the two components (e.g., if a layer is "on" a substrate, another layer can be disposed between the layer and the substrate).

[0044] Two adjoining doped regions in a semiconductor layer form a semiconductor junction. Two adjoining doped regions of the same conductivity type and having different dopant concentrations form a unipolar junction, e.g., an n / n+ or p / p+ junction along a boundary surface between the two doped regions. At a unipolar junction, a dopant concentration profile orthogonal to the unipolar junction can show a step or a kink at which the dopant concentration profile changes from concave to convex or vice versa. Two adjoining doped regions of complementary conductivity type form a pn junction.

[0045] The figures illustrate relative doping concentrations by indicating a "-" or "+" next to the doping type "n" or "p". For example, "n-" means a lower doping concentration than the doping concentration of an "n" doped region, while an "n+" doped region has a higher doping concentration than an "n" doped region. Doped regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doped regions can have the same or different absolute doping concentrations.

[0046] The shield region laterally confines the transistor on-state current and increases the on-state resistance RDSon of SiC-MOSFETs with planar gates as well as with trench gates. The high-energy implant through the first major surface results in a large lateral spread, which blurs the lateral edges of the shield region. The high-energy implant also requires a thick implant mask to prevent the acceptor ions from reaching the current path between the shield regions. With increasing thickness, the undesired side effects of the implant mask become more pronounced. A slight tilt of the mask edge results in a lateral spread and a partial blockage of the ions. The partial blockage results in implant tails ("duck tails") reaching the first major surface. The implant tails can increase the channel resistance and / or change the threshold voltage of the SiC-MOSFET. The negative side effects of the high-energy implant can be mitigated by increasing the lateral distance between adjacent gate trenches, which in turn reduces the area efficiency.

[0047] The present disclosure relates to a semiconductor device having a base layer and a transistor layer. The base layer is based on single crystalline silicon carbide and includes a current spreading region of a first conductivity type and a non-depletable shield structure of a second conductivity type. The transistor layer is based on single crystalline silicon carbide grown in an epitaxial manner and includes a transistor cell configured to control a current through the current spreading region. The transistor layer is formed on the base layer after forming the shield structure in the base layer such that an epitaxial interface is formed between the base layer and the transistor layer. The current spreading region extends from the epitaxial interface between adjacent partial regions of the shield structure. Along a vertical line orthogonal to the epitaxial interface and through a pn junction between the region of the first conductivity type in the shield structure and the transistor layer, a net dopant concentration change can be at least 1e171 / cm3per 0.1 pm at the location of the pn junction. 3 , for example, at least 2e171 / cm3per 0.1 pm. 3 .

[0048] According to an example, the first conductivity type is n-conductivity and the second conductivity type is p-conductivity. According to another example, the first conductivity type is p-conductivity and the second conductivity type is n-conductivity.

[0049] The base layer can have two rectangular main surfaces extending in two essentially parallel horizontal planes. A distance between a first main surface (base layer surface) at the front side and a second main surface opposite to the first main surface defines a thickness of the base layer in a vertical direction orthogonal to the horizontal planes. The current spreading region and the shielding structure can extend from the epitaxial interface into the base layer.

[0050] The transistor layer can be formed directly on the base layer surface. The transistor layer can be formed by epitaxial growth of crystalline silicon carbide after forming the shielding structure.

[0051] The transistor layer can comprise further components to provide functionality of a plurality of transistor cells. For example, the transistor layer can comprise structures made of materials other than single crystalline silicon carbide, such as dielectric structures and / or metal structures. The top surface of the transistor layer can be essentially planar except for trench gate electrodes and metal contact structures extending from an exposed surface at the front side of the transistor layer into the transistor layer. The drain current of the transistor cells is controlled by controlling an electric field modulating the drain current through the transistor cells. The drain current passes through the current spreading region.

[0052] The epitaxial growth transforms the base layer surface into an epitaxial interface between the base layer and the transistor layer. The epitaxial interface can be essentially planar or can comprise a co-planar first segment region and a co-planar second segment region spaced apart from the first segment region by a vertical distance. The first segment region and the second segment region can be connected by a further segment region. In other examples, the interface 201 can be wavy or can have a zigzag shape.

[0053] On opposite sides of the epitaxial interface, the content of one or more electrically active and / or electrically inactive impurities can differ significantly. For example, the average concentration of nitrogen, sulfur, iodine, oxygen and / or hydrogen in the transistor layer can differ significantly from the average concentration of the same elements in the base layer.

[0054] The shield structure can be formed directly along the epitaxial interface. The shield structure can comprise: partial regions (shield regions) separated from each other in at least one horizontal direction. For example, rectangular, circular or elliptical gap-separated shield structure adjacent partial regions with opposite doping type to the shield structure. The shield structure can comprise a plurality of stripe-shaped partial regions separated from each other along a horizontal direction by stripe-shaped regions with opposite doping type, or can comprise shield islands separated from each other along two orthogonal horizontal directions by grid-shaped regions with opposite doping type. A segment region of the shield structure valid for the same transistor cell TC and the same current spreading region can also be referred to as a shield region below. The shield structure is not completely depleted under operating conditions within the safe operating area (SOA).

[0055] An abrupt change in net dopant concentration along a vertical line through a pn junction between the shield structure and a region of the first conductivity type in the transistor layer indicates the absence of implant tails, which are typically observed in case of high-energy ion implantation through openings in a thick implant mask. In the absence of implant tails, the gaps in the shield structure can be designed narrower and with better defined dimensions and doping profiles.

[0056] Alternatively or in addition, along a horizontal line parallel to the epitaxial interface, and through a pn junction formed between the current spreading region and the shield structure, the change in net dopant concentration can be at least 1e17l / cm 3 , for example at least 2e17l / cm 3 .

[0057] Alternatively or in addition, a width w0 of the current spreading region defined by the shortest horizontal distance between two points of zero net doping located on opposite sides of the current spreading region can be at most 0.6 pm, for example at most 0.1 pm, a vertical extension v0 of the shield structure can be at least 0.8 pm, for example at least 0.4 pm, and / or an aspect ratio v0 / w0 of the gaps in the shield structure can be at least 0.3, at least 0.5, at least 1 or at least 5.

[0058] The current spreading region and the regions of the shield structure contiguous to the current spreading region define a JFET structure, which has a large impact on the on-state resistance RDSon of the semiconductor device. Various embodiments allow for a precisely defined JFET structure even at low lateral center-to-center distances between adjacent transistor cells TC. The number of transistor cells TC per area unit can be increased and the total on-state resistance RDSon is further reduced. In addition, a JFET design with a high aspect ratio of channel length / channel width can facilitate an improved trade-off between low on-state resistance RDSon and long short-circuit endurance time.

[0059] According to embodiments, the base layer can include a current drift portion of the first conductivity type, wherein the current spreading region extends into the current drift portion.

[0060] In a vertical projection of some or all of the transistor cells formed in the transistor layer, the current drift portion can be a continuous horizontal layer extending through the base layer along a lateral direction. Alternatively, the current drift portion can be part of a compensation structure. The current spreading region and the current drift portion can form a unipolar junction.

[0061] Along a vertical line orthogonal to the epitaxial interface and passing through a pn junction formed between the shielding structure and the current drift portion, the net dopant concentration change can be at least 1e161 / cm 3 , for example, at least 2e161 / cm 3 per 0.1 pm.

[0062] According to embodiments, the semiconductor device can include a connection region of the second conductivity type, wherein the connection region extends through the transistor layer to the shielding structure and directly contacts the shielding structure along a first segment of the epitaxial interface. A vertical dopant profile through the first segment of the epitaxial interface can show a step at the epitaxial interface. The connection region can extend through the entire transistor layer, or only downward through a vertical segment of the transistor layer to the shielding structure.

[0063] If an average dopant concentration in the connection region is higher or lower than an average dopant concentration in the shielding structure, a vertical dopant profile through the connection region and the shielding structure can show a steep slope at the epitaxial interface, with a net dopant concentration change of at least 1e181 / cm 3 , for example, at least 2e181 / cm 3 per 0.1 pm. The steep slope can be a result of forming the transistor layer after forming the shielding structure in the base layer.

[0064] When the metal contact plug extends from a plane coplanar with a top surface of the transistor layer into the transistor layer, the connection region 160 can include a buried portion extending from a bottom of the metal contact plug to or into the shielding structure, with a dopant peak in the buried portion formed directly under the metal for improved contact.

[0065] According to embodiments, the connection region can extend from a top surface of the transistor layer to the shielding structure.

[0066] The top surface can be parallel to the epitaxial interface. The epitaxial interface and the top surface are located on opposite sides of the transistor layer. The connection region can extend down to the epitaxial interface or beyond the epitaxial interface, such that the connection region extends into the base layer.

[0067] According to embodiments, the transistor element can be configured to control a current flow through the body region between the source region and the current collection region, wherein the current collection region can be electrically connected with the current propagation region.

[0068] The current collection region can be in direct contact with the current propagation region or can be electrically connected with the current propagation region by a low-resistance ohmic connection (e.g., by another doped region having a net dopant concentration different from the net dopant concentration in the current collection region and the current propagation region).

[0069] During formation of the transistor layer or after formation of the transistor layer, the current collection region can receive a dopant defining the electrical conductivity of the current collection region. For example, during epitaxial growth of the transistor layer, the current collection region can be doped in situ.

[0070] The current propagation region can comprise a channel portion and an extension portion. The channel portion extends through the gap in the shielding structure, wherein the vertical extension of the channel portion and the vertical extension of the shielding structure 260 are equal. The extension portion separates the shielding structure and the current drift portion along the vertical direction. The channel portion and the extension portion of the current propagation region can have the same dopant concentration. The dopant concentration in the extension portion of the current propagation region can be higher than the dopant concentration in the current drift portion. For example, the dopant concentration in the extension portion is at least two times or at least ten times higher compared to the current drift portion.

[0071] According to embodiments, the body region can separate the source region and the current collection region in a horizontal direction parallel to the epitaxial interface. The transistor element controls a horizontal current flow through the body region between the source region and the current collection region.

[0072] According to another embodiment, the body region separates the source region and the current collection region along a vertical direction. The transistor element controls a vertical or almost vertical current flow through the body region between the source region and the current collection region.

[0073] According to embodiments, the trench gate structure can extend from a top surface of the transistor layer into the transistor layer, wherein the source region, the body region, and the current collection region are in direct contact with a sidewall of the trench gate structure.

[0074] According to embodiments, the current collection region and the current propagation region can be in direct contact with each other along the second segment of the epitaxial interface, wherein the vertical dopant profile through the second segment of the epitaxial interface shows a step at the epitaxial interface.

[0075] If the average dopant concentration in the current collection region is higher or lower than the average dopant concentration in the current propagation region, the vertical dopant profile through the current collection region and the current propagation region can show a steep slope at the epitaxial interface. The change in the net dopant concentration is at least 2e171 / cm per 0.1 pm. 3e.g. at least 4e171 / cm per 0.1 pm 3 The steep slope can be a result of forming the transistor layer with the current collection region after forming the current propagation region in the base layer.

[0076] According to embodiments, the trench gate structure can end in the transistor layer and the auxiliary region of the second conductivity type can extend from the bottom of the trench gate structure to the shield structure. The auxiliary region can be formed self-aligned to the trench gate structure.

[0077] According to embodiments, the current propagation region can extend along a vertical direction through the gap in the shield structure, wherein the gap has a vertical extension v0 and a horizontal width w0, and wherein an aspect ratio v0 / w0 of the gap in the shield structure can be at least 1.

[0078] The aspect ratio v0 / w0 of the gap is equal to the aspect ratio of the channel portion of the current propagation region. The width w0 is measured parallel to the first horizontal direction. The aspect ratio v0 / w0 can be at least 0.5. For example, the aspect ratio v0 / w0 is at least 1, e.g. at least 5. A high aspect ratio v0 / w0 of at least 1 or 5 promotes a long maximum short-circuit endurance time.

[0079] According to embodiments, the semiconductor device can further comprise a depletable first pillar region of the first conductivity type and a depletable second pillar region of the second conductivity type, wherein the first pillar region is formed in the base layer in direct contact with the current propagation region, and wherein the second pillar region is formed in the base layer in direct contact with the shield structure.

[0080] The doped first pillar region 241 can alternate along the horizontal direction(s) with a doped second pillar region 242 of the complementary conductivity type, wherein the first and second pillar regions 241, 242 form a compensation structure configured to fully deplete a nominal breakdown voltage of the semiconductor device within the SOA.

[0081] According to embodiments, the transistor cell can be stripe-shaped with a horizontal longitudinal axis along the first horizontal direction, wherein the first and second pillar regions can be stripe-shaped with a horizontal longitudinal axis along the first horizontal direction.

[0082] The stripe-shaped transistor cell TC comprises a stripe-shaped planar gate structure or a stripe-shaped trench gate structure with a horizontal longitudinal axis parallel to the first horizontal direction. The horizontal longitudinal axis of the gate structure and the horizontal longitudinal axes of the first and second pillar regions run parallel to each other.

[0083] According to embodiments, the transistor cell is stripe-shaped with a longitudinal axis along the first horizontal direction and the first and second pillar regions are stripe-shaped with a horizontal longitudinal axis skewed with respect to the first horizontal direction.

[0084] The stripe-shaped transistor cell TC comprises a stripe-shaped planar gate structure or a stripe-shaped trench gate structure, wherein the horizontal longitudinal axis of the stripe-shaped gate structure and the horizontal longitudinal axis of the first and second pillar regions are skewed relative to each other in the horizontal plane by at least 10 degrees, for example 30 degrees, 45 degrees or 90 degrees.

[0085] According to embodiments, the current spreading region can comprise a central portion formed in a gap in the shielding structure and a heavily doped sidewall portion between the central channel portion and the shielding structure.

[0086] The heavily doped sidewall portion can separate the central portion and the shielding structure from each other in the lateral direction. The central portion and the sidewall portion form a channel portion of the current spreading region.

[0087] According to embodiments, a method of forming a semiconductor device can comprise forming a single-crystalline silicon carbide-based base layer, wherein the base layer comprises a non-depletable shielding structure of a second conductivity type and a current spreading region of a first conductivity type, the current spreading region extending from a base layer surface of the base layer through a gap in the shielding structure. A transistor layer can be formed on the base layer surface, wherein the transistor layer comprises a transistor cell configured to control a current through the current spreading region. Along a vertical line orthogonal to an epitaxial interface between the transistor layer and the base layer and passing through a pn junction between the shielding structure and a region of the first conductivity type in the transistor layer, a net dopant concentration variation can be at least 1e171 / cm 3 , at least 2e171 / cm 3 or at least 4e171 / cm 3 .

[0088] At the pn junction between the current spreading region and the shielding structure, along a horizontal line parallel to the epitaxial interface, a net dopant concentration variation can be at least 1e171 / cm 3 .

[0089] According to embodiments, forming the transistor layer can comprise, after forming the shielding structure in the base layer, growing the transistor layer on the base layer surface by epitaxy.

[0090] The current spreading region can comprise an extension portion formed between the shielding region and a current drift portion of the first conductivity type and separating the shielding region and the current drift portion of the first conductivity type in a vertical direction, wherein the current drift portion is formed between the extension portion and a drain layer located at a backside of the base layer, and wherein a dopant concentration in the shielding region is at least two times, for example at least ten times, compared to in the current drift region. Forming the extension portion can comprise implanting dopants prior to epitaxial growth of the transistor layer.

[0091] According to embodiments, forming the base layer can include forming a depletable first pillar region of the first conductivity type and a depletable second pillar region of the second conductivity type in the base layer before forming the shield structure, wherein the shield structure is formed between the base layer surface and the first and second pillar regions.

[0092] Forming the base layer can include forming at least lower section regions of the first and second pillar regions in a first base layer of the base layer, then growing a second base layer of the base layer on a first base layer surface of the first base layer, then forming the shield structure on the lower section regions of the first and second pillar regions or forming upper section regions of the first and second pillar regions and the shield structure.

[0093] According to embodiments, forming the transistor layer can include forming a gate trench extending into the transistor layer from a major surface of the transistor layer, implanting dopants of the first conductivity type through a bottom of the gate trench to form an auxiliary region between the gate trench and the shield structure, and forming a trench gate structure in the gate trench.

[0094] The dopants of the first conductivity type can be acceptor ions. The auxiliary region can extend from the bottom of the gate trench to the shield structure or into the shield structure.

[0095] According to embodiments, forming the base layer can include forming a channel trench in the gap of the shield structure before forming the transistor layer, and filling the channel trench with a doped semiconductor material to form at least a portion of the current spreading region.

[0096] The channel trench can be filled during an epitaxial process of forming the transistor layer. The gap in the shield structure can be created by etching the channel trench in a continuous shield layer, and the shield structure can be obtained from a non-etched portion of the shield layer.

[0097] According to embodiments, dopant atoms can be implanted in sidewalls of the channel trench before filling the channel trench.

[0098] Figure 1A A semiconductor device is shown having a base layer 200 and a transistor layer 100. The base layer 200 and the transistor layer 100 are made of single-crystalline silicon carbide of 4H polytype and are formed on opposite sides of a horizontal epitaxial interface 201.

[0099] The base layer 200 has two essentially parallel rectangular major surfaces, wherein a first major surface on a front side extends in a first horizontal plane and a second major surface on a back side extends in a second horizontal plane. In a vertical direction orthogonal to the two horizontal planes, the base layer 200 has a thickness.

[0100] The n-conducting current drift portion 240, the n-conducting current spreading region 230, and the non-depletable p-conducting shield structure 260 are formed as doped regions in the base layer 200.

[0101] The current drift portion 240 is formed as a continuous horizontal layer extending laterally through the base layer 200. The current propagation region 230 is formed between partial regions of the shielding structure 260 and extends from the epitaxial interface 201 to the n-conducting current drift portion 240. The n-conducting current drift portion 240 and the n-conducting current propagation region 230 form a horizontal unipolar junction.

[0102] The shielding structure 260 extends from the epitaxial interface 201 into the base layer 200. Partial regions of the shielding structure 260 located on opposite sides of the current propagation region 230 can be separated from each other or can be connected to each other laterally in a plane parallel to the plane of the cross section to form a continuous single piece shielding structure 260. Within the shielding structure 260, the dopant concentration is approximately uniform along the horizontal direction. The shielding structure 260 does not become fully depleted under operating conditions within the safe operating area of the semiconductor device.

[0103] After forming the shielding structure 260 in the base layer 200, the transistor layer 100 is formed on the first major surface of the base layer 200 by epitaxy, whereby silicon and carbon atoms continue the single crystalline crystal lattice of the base layer 200. The top surface 101 of the transistor layer 100 is substantially planar, except for trench gate electrodes and / or metal contact structures extending into the transistor layer 100 from the exposed top surface 101 on the front side of the transistor layer 100. The transistor layer 100 comprises a plurality of transistor cells TC. Load paths of the transistor cells TC between the source electrodes S and the current drift portions 240 are electrically connected in parallel to each other.

[0104] By field effect, a suitable electric potential applied to the gate electrodes G of the transistor cells TC controls the load current through the transistor cells TC. The load current through the transistor cells TC passes through the current propagation region 230.

[0105] Figure 1B A vertical net dopant concentration gradient (vertical doping profile) along the line B-B in Figure 1A is shown. N1 indicates donor concentration (donor density). N2 indicates acceptor concentration (acceptor density). The position of the horizontal axis indicates the plane of zero net doping.

[0106] The first segment region of the line B-B intersects the upper pn junction 261 between the p-conducting shielding structure 260 and the n-conducting region in the transistor layer 100. In the vicinity of the upper pn junction 261, the net dopant concentration change ANc / Δyc is at least 1e171 / cm 3 , for example, at least 2e171 / cm 3 , per 0.1 pm.

[0107] The second section of line B-B intersects the lower pn-junction 262 between the p-conducting shield structure 260 and the current drift portion 240. In the vicinity of the second pn-junction 262, the net dopant concentration change ANb / Δyb is at least 1 e161 / cm per 0.1 pm 3 , for example, at least 2 e161 / cm per 0.1 pm 3 . The net dopant concentration change ANc / Δyc at the upper pn-junction 261 is larger (steeper) compared to the net dopant concentration change ANb / Δyb at the lower pn-junction 262, being 5...10 times larger.

[0108] The thickness v0 of the shield structure 260 is defined by the vertical distance between the upper pn-junction 261 and the lower pn-junction 262. For a semiconductor device with a trench gate, the thickness v0 can be equal to the distance between the bottom of the trench gate structure and the pn-junction towards the drift layer. The thickness v0 of the shield structure 260 is approximately uniform and lies in the range from 400 nm to 0.8 pm.

[0109] Figure 1C Fig. 2 shows a horizontal dopant concentration gradient in the base layer 200 in a horizontal plane intersecting the current spreading region 230 and the shield structure 260 as indicated by line C-C in Fig. 2. Figure 1A

[0110] The vertical pn-junction 263 between the shield structure 260 and the current spreading region 230, the net dopant concentration change ANa / Δxa is at least 1 e171 / cm per 0.1 pm 3 , for example, at least 2 e171 / cm per 0.1 pm 3 .

[0111] The width w0 of the current spreading region 230 is defined by the horizontal distance between the vertical pn-junctions 263 located at opposite sides of the current spreading region 230. The width w0 of the current spreading region 230 lies in the range from 100 nm to 600 pm.

[0112] The aspect ratio v0 / w0 of the gap in the shield structure 260 is at least 1, for example at least 5. The current spreading region 230 completely fills the gap and forms the channel region of the JFET structure that influences the on-state resistance RDSon. A JFET design with a high aspect ratio v0 / w0 of the length / width is able to achieve an improved trade-off between low RDSon and long short-circuit endurance time.

[0113] Figure 2 , Figure 3 and Figure 4 each show details of a different transistor cell TC in combination with a p-conducting connection region 160 that extends from the top surface 101 of the transistor layer 100 downwards to the p-conducting shield structure 260.​

[0114] Each transistor cell TC includes an n-conductivity source region 110, a p- conductivity body region 120, an n-conductivity current-collecting region 130, a gate conductor 155 electrically connected to a gate electrode G, and a gate dielectric 151 separating the gate conductor 155 and the body region 120. The body region 120 separates the source region 110 and the current-collecting region 130 from each other. By field effect, an electric potential applied to the gate electrode G controls a current through the body region 120 between the source region 110 and the current-collecting region 130.

[0115] The current-collecting region 130 and the current-spreading region 230 are in direct contact with each other and can have the same dopant concentration or can form a unipolar junction. The current-collecting region 130 can receive a dopant defining its conductivity during formation of the transistor layer 100 or after formation of the transistor layer 100. For example, the current-collecting region 130 can be doped in situ during epitaxial growth of the transistor layer 100.

[0116] The connecting region 160 is in direct contact with the shielding structure 260, wherein the connecting region 160 and the shielding structure 260 form a horizontal unipolar junction along the first segment of the epitaxial interface 201. The vertical dopant profile through the first segment of the epitaxial interface 201 shows a step at the epitaxial interface 201.

[0117] Figure 2 A semiconductor device is shown with a planar gate structure 150, wherein the gate conductor 155 and the gate dielectric 151 are formed on a top surface 101 of the transistor layer 100. The source region 110, the body region 120, and the current-collecting region 130 are formed in the transistor layer 100 in this order along the top surface 101, wherein the body region 120 separates the source region 110 and the current-collecting region 130 in a horizontal direction parallel to the epitaxial interface 201.

[0118] A first vertical pn-junction is formed between the current-collecting region 130 and the body region 120. A second vertical pn-junction is formed between the body region 120 and the source region 110. The gate conductor 155 is formed on the transistor layer 100 and spans from approximately above the first vertical pn-junction to approximately above the second vertical pn-junction. The gate dielectric 151 separates the gate conductor 155 and the transistor layer 100 from each other. The gate conductor 155 is capacitively coupled to the body region 120.

[0119] The shielding structure 260 is formed along the epitaxial interface 201 of the base layer 200 in direct contact with the body region 120 and the source region 110. The p-conductivity connecting region 160 with a higher average dopant concentration than the body region 120 extends from the top surface 101 of the transistor layer 100 to the shielding structure 260 next to the source region 110.

[0120] The current propagation region 230 comprises a channel portion 231 and an extension portion 232. The channel portion 231 extends through a gap in the shield structure 260 or between two adjacent stripe-shaped portion regions (shield regions) of the shield structure 260. The vertical extension of the channel portion 231 and the vertical extension of the shield structure 260 are equal. The extension portion 232 separates the shield structure 260 and the current drift portion 240 along the vertical direction. The channel portion 231 and the extension portion 232 of the current propagation region 230 have the same dopant concentration.

[0121] Figure 3 and Figure 4 A semiconductor device is shown having a trench gate structure 150 extending into or through the transistor layer 100 from the top surface 101 of the transistor layer 100. Each trench gate structure 150 comprises a gate conductor 155 and a gate dielectric 151, wherein the gate dielectric 151 lines a gate trench and the gate conductor 155 fills the rest of the gate trench. The gate dielectric 151 separates the gate conductor 155 from the transistor layer 100 and, if applicable, from the base layer 200. A source region 110, a body region 120 and a current collection region 130 are formed along at least one sidewall of the trench gate structure 150 in this order and in direct contact with the sidewall of the trench gate structure 150. The source region 110 extends into the transistor layer 100 from the top surface 101. The body region 120 separates the source region 110 and the current collection region 130 along the vertical direction.

[0122] Figure 3 A semiconductor device is shown having a trench gate structure 150 and a transistor cell TC having a single-sided transistor channel. The channel portion 231 of the current propagation region 230 is formed at a lateral distance from the trench gate structure 150. The bottom portion of the trench gate structure 150 is in direct contact with the shield structure 260. A connection region 160 can be formed on the side of the trench gate structure 150 opposite to the body region 120 and extending from the top surface 101 down to or into the shield structure 260 or in the same side as the transistor channel in a plane parallel to the cross-sectional plane.

[0123] In Figure 4 , the channel portion 231 of the current propagation region 230 is formed without lateral distance from the trench gate structure 150. The channel portion 231 separates the bottom portion of the trench gate structure 150 and the shield structure 260 along the lateral direction.

[0124] In Figure 2 , Figure 3 and Figure 4In each of the semiconductor devices, the current collecting region 130 and the current spreading region 230 directly contact each other along the second segment of the epitaxial interface 201. The channel portion 231 of the current collecting region 130 and the current spreading region 230 can have the same dopant content. On the other hand, the vertical dopant profile through the second segment of the epitaxial interface 201 can have a steep step at the epitaxial interface 201.

[0125] Figure 5 Reference is made to the example where the average donor concentration ND1 in the current collecting region 130 is lower than the average donor concentration ND2 in the current spreading region 230. The vertical dopant profile through the current collecting region 130 and the current spreading region 230 shows a steep slope at the epitaxial interface 201. The net dopant concentration change is at least 2el7l / cm 3 , for example, at least 4el7l / cm 3 per 0.1 pm. The steep slope can be a result of forming the transistor layer 100 with the current collecting region 130 by epitaxy after forming the current spreading region 230 in the base layer 200.

[0126] Figure 6A Reference is made to the example where the average acceptor concentration NA2 in the connection region 160 is lower than the average acceptor concentration NA1 in the shield structure 260. Then, the vertical dopant profile through the connection region 160 and the shield structure 260 can show a steep slope at the epitaxial interface 201. The net dopant concentration change is at least 1el8l / cm 3 , for example, at least 2el8l / cm 3 per 0.1 pm. The steep slope can result from forming the transistor layer 100 after forming the shield structure 260 in the base layer 200.

[0127] Figure 6B Reference is made to a transistor cell with a trench gate structure. For example, in Figure 3 , the current spreading region 230 can include a layered extension portion 232 formed between the shield structure 260 and the current drift portion 240. When the dopant of the extension portion 232 is implanted through the transistor layer 100, the implantation tail reaches up into the current collecting region 130 and the body region 120. In contrast, the formation of the transistor layer 100 after the implantation of the dopant of the extension portion 232 and the shield region 260 forms a well-defined abrupt transition between the shield region 260 and the current collecting region 130. The doping in the body region 120 and the current collecting region 130 can be precisely defined. The net dopant concentration change at the epitaxial interface 201 is at least 1el7l / cm 3 , for example, at least 2el7l / cm 3 per 0.1 pm.

[0128] Figure 7 and Figure 8 A symmetric transistor cell TC is shown with a planar gate structure 150. A symmetry plane 490 is orthogonal to the top surface 101 of the transistor layer 100 and runs in the lateral center of the current collection region 130 and the channel portion 231 of the current propagation region 230. The current collection region 130 and the channel portion 231 are shared between the two symmetric transistor cells TC.

[0129] The current drift portion 240 is homogenously doped and separates the current propagation region 230 from a heavily doped drain layer 290 formed along the backside surface 202 of the base layer 200 in the vertical direction. The dopant concentration in the drain layer 290 is high enough to form an ohmic contact with a backside metallization 320 forming a drain electrode D of the semiconductor device or electrically connected to a drain electrode D of the semiconductor device. On the frontside, a cladding dielectric 305 separates the gate conductor 155 from a frontside metallization 310. The frontside metallization 310 forms an ohmic contact with the source region 110 and the connection region 160 and forms a source electrode S of the semiconductor device or electrically connected to a source electrode S of the semiconductor device.

[0130] In Figure 7 , the gate conductor 155 completely spans the current collection region 130. In Figure 8 , the gate conductor 155 is split into two parts and missing over a central portion of the current collection region 130.

[0131] Figure 9 The semiconductor device illustrated in Figure 3 includes a transistor cell TC with a single-sided transistor channel as described with reference to . A stripe-shaped trench gate structure 150 with a horizontal longitudinal axis along a first horizontal direction orthogonal to the cross-sectional plane extends from the top surface 101 of the transistor layer 100 into the shielding structure 260. The channel portion 231 of the current propagation region 230 is formed at a lateral distance from the trench gate structure 150. The connection region 160 is formed on the side of the trench gate structure 150 opposite to the bulk region 120 and extends from the top surface 101 down the sidewall of the trench gate structure 150 to the shielding structure 260.

[0132] Figure 10 The semiconductor device illustrated in Figure 4The transistor cell TC with two-sided transistor channels. The stripe-shaped trench gate structure 150 with a horizontal longitudinal axis along a first horizontal direction orthogonal to the cross-sectional plane extends down into or down to the channel portion 231 of the current spreading region 230 and the base layer 200. The channel portion 231 of the current spreading region 230 is in direct contact with the trench gate structure 150. The connection region 160 extends from the top surface 101 down to the shielding structure 260 between adjacent transistor cells TC. The shielding structure 260 comprises stripe-shaped portion regions with a horizontal longitudinal axis orthogonal to the cross-sectional plane or forms a grid, the channel portion 231 of the current spreading region being formed in a mesh of the grid.

[0133] Figure 9 and Figure 10 The semiconductor device in

[0134] The n-conductive first pillar region 241 and the p-conductive second pillar region 242 are stripe-shaped with a horizontal longitudinal axis along the first horizontal direction. The n-conductive first pillar region 241, the p-conductive second pillar region 242 and the trench gate structure 150 run parallel to each other. The n-conductive first pillar region 241 and the p-conductive second pillar region 242 alternate along a second horizontal direction (x-axis) orthogonal to the first horizontal direction. The first and second pillar regions 241, 242 form a compensation structure configured to fully deplete the nominal breakdown voltage of the semiconductor device within the SOA.

[0135] In Figure 11 , the metal contact plug 315 extends from the top surface 101 into the connection region 160 in the transistor layer 100. The connection region 160 is in contact with the bottom and sidewalls of the metal contact plug 315. The metal contact plug 315 and the connection region 160 form a low resistance ohmic contact. The connection region 160 comprises a portion extending from the bottom of the metal contact plug 315 to or into the shielding structure 260, wherein a doping peak directly below the metal contact plug 315 improves the ohmic contact. Alternatively, the metal contact plug 315 can extend into the shielding structure 260.

[0136] In Figure 10 and Figure 11 , the connection region 160 is formed between adjacent source regions 110 of adjacent stripe-shaped transistor cells TC and alternates with the source regions 110 along the second horizontal direction (x-axis), whereas Figure 12The connection regions 160 are shown to alternate with the source regions 110 along the first horizontal direction (y-axis). Each connection region 160 extends along the second horizontal direction (x-axis) from a first trench gate structure 150 to an adjacent second trench gate structure 150. Each source region 110 extends along the second horizontal direction from a first trench gate structure 150 to an adjacent second trench gate structure 150. The connection regions 160 and the source regions 110 strictly alternate along the first horizontal direction (y-axis).

[0137] Figure 13A and Figure 13B A parallel cross-section of the planar transistor cell layout of Figure 12 is shown for an example with the n-conducting pillar region 241 in direct contact with the channel portion 231 of the current spreading region.

[0138] Figure 14A and Figure 14B A parallel cross-section of the planar transistor cell layout of Figure 12 is shown for an example with a narrow channel portion 231. The aspect ratio v0 / w0 of the channel portion 231 is at least 1, or at least 5.

[0139] In Figure 15A and Figure 15B , the trench gate structure 150 is fully formed in the transistor layer 100 and ends at a distance from the base layer 200.

[0140] In Figure 16A and Figure 16B , the trench gate structure 150 ends in the transistor layer 100. The p-conducting auxiliary region 170 extends from the bottom of the trench gate structure 150 to the shield structure 260. The p-conducting auxiliary region 170 and the shield structure 260 are in direct contact and form a unipolar junction along the epitaxial interface 201. The vertical dopant profile through the unipolar junction of the p-conducting auxiliary region 170 and the shield structure 260 can have a steep slope at the epitaxial interface 201.

[0141] The auxiliary region 170 can be formed to be self-aligned to the trench gate structure 150. The alignment between the trench gate structure 150 in the transistor layer 100 and the gap in the shield structure 260 in the base layer 200 is less critical.

[0142] In Figure 17A , Figure 17B , Figure 17C and Figure 17DIn the embodiment shown, the stripe-shaped first and second pillar regions 241, 242 have a horizontal longitudinal axis orthogonal to the second horizontal direction (x-axis). The stripe-shaped transistor cell includes a stripe-shaped planar gate structure 150 or a stripe-shaped trench gate structure 150 having a horizontal longitudinal axis parallel to the first horizontal direction. The first and second pillar regions 241, 242 extend orthogonally to the gate structure 150.

[0143] Figure 17A 、 Figure 17B and Figure 17C A grid-shaped shielding structure 260 with openings is shown directly below and in direct contact with the n-conductive current collecting regions 130.

[0144] As shown in Figure 17A , the shielding structure 260 connects the p-conductive second pillar regions 242 with the plurality of connection regions 160.

[0145] According to Figure 17B , the n-conductive current spreading regions 230 in the openings of the shielding structure 260 connect each n-conductive first pillar region 241 with the plurality of current collecting regions 130.

[0146] Figure 17C It is shown that the p-conductive second pillar regions 242, which are wider than the p+-conductive connection regions 160, undercut the comparatively wide transistor regions with n+-conductive source regions 110 and n-conductive current collecting regions 130. In the illustrated cross-section, a shielding region 260 is formed between the second pillar regions 242 and the n-conductive current collecting regions 130.

[0147] Figure 17D A shielding structure 260 is shown, which has stripe-shaped partial regions with a horizontal longitudinal axis parallel to the first horizontal direction of the gate structure 150. Each partial region of the shielding structure 260 connects the p-conductive second pillar regions 242 with the plurality of connection regions 160. The n-conductive current spreading regions 230 separate the partial regions of the shielding structure 260 from each other laterally.

[0148] Similar to Figure 17B , the conductive current spreading regions 230 connect each n-conductive first pillar region 241 with the plurality of current collecting regions 130.

[0149] In Figure 18A and Figure 18B , the shielding structure 260 is patterned along the first horizontal direction. The shielding structure 260 includes shielding islands separated from each other laterally above the n-conductive first pillars 241 along the first and second horizontal directions. At the expense of the area of the shielding structure 260, the area of the current spreading regions is increased to improve the efficiency of the current spreading function of the current spreading regions 230.

[0150] In Figures 19A-19C n-conducting first pillar regions 241 and p-conducting second pillar regions 242 extend with horizontal longitudinal axes parallel to the second horizontal direction (x-axis) and are laterally aligned to source regions 110 and connection regions 160 in the transistor layer 100. The shielding structure 260 comprises stripe-shaped partial regions with horizontal longitudinal axes parallel to the second horizontal direction (x-axis). The stripe-shaped current spreading regions 230 above the n-conducting first pillars 241 separate the stripe-shaped partial regions of the shielding structure 260 from each other laterally. Each stripe-shaped current spreading region 230 connects the n-conducting first pillar regions 241 to a plurality of current collecting regions 130. Each stripe-shaped partial region of the shielding structure 260 connects the p-conducting second pillar regions 242 to a plurality of connection regions 160.

[0151] Figure 20 A current spreading region 230 is shown, which comprises a channel portion 231 with a center portion 237 and a heavily doped sidewall portion 238 between the center portion 237 and the shielding structure 260. The heavily doped sidewall portion 238 separates the center portion 237 from the shielding structure 260. The heavily doped sidewall portion 238 allows for a precise tuning of the JFET structure and can be created by an inclined ion implantation.

[0152] Figures 21A-21B A method of manufacturing a semiconductor device is shown. By means of photolithography, a first implantation mask 410 is formed on the basis layer surface 205 on the front side of a basis layer 200, wherein the basis layer 200 is based on a single crystalline silicon carbide with an n-type bulk doping. By means of openings in the first implantation mask 410, acceptor ions are implanted.

[0153] Figure 21A A p-conducting shielding structure 260 is shown, which is obtained by activating the acceptor ions implanted in the regions of the basis layer 200 exposed by the first implantation mask 410. The portions of the basis layer 200 covered by the first implantation mask 410 form n-conducting current spreading regions 230. The portions of the basis layer 200 below the shielding structure 260 and the current spreading regions 230 form a current drift region 240.

[0154] Then, by means of epitaxy, a transistor layer 100 is formed on the basis layer surface 205. Doped regions and gate structures of a transistor cell TC are formed in the transistor layer 100.

[0155] Figure 21B A method of manufacturing a semiconductor device is shown. By means of photolithography, a first implantation mask 410 is formed on the basis layer surface 205 on the front side of a basis layer 200, wherein the basis layer 200 is based on a single crystalline silicon carbide with an n-type bulk doping. By means of openings in the first implantation mask 410, acceptor ions are implanted. Figure 21AThe transistor layer 100 and the base layer 200 form a horizontal epitaxial interface 201 in the plane of the base layer surface 205. A transistor cell TC in the transistor layer 100 controls a drain current IC through a current spreading region 230 in the base layer 200. Along a vertical line orthogonal to the epitaxial interface 201 and passing through a pn-junction between the shielding structure 260 and the n-conducting region in the transistor layer 100, the net dopant concentration change is at least 1 e171 / cm per 0.1 μm 3 .

[0156] Figures 22A-22D A method of using epitaxy on a base layer with previously formed doped regions is shown. By means of photolithography, a first auxiliary implantation mask 420 is formed on a first base layer surface 215 on a front side of a first base layer 210, wherein the first base layer 210 is based on a single crystalline silicon carbide with an n-type bulk doping. Through openings in the first auxiliary implantation mask 420, acceptor ions are implanted.

[0157] Figure 22A It is shown that p-conducting second pillar regions 242 are obtained from activated acceptor ions implanted through the openings in the auxiliary implantation mask 420 and that n-conducting first pillar regions 241 are formed in segment regions of the first base layer 210 covered by the auxiliary implantation mask 420.

[0158] The first auxiliary implantation mask 420 is removed and by means of epitaxy, a second base layer 220 is formed on the first base layer surface 215. The second base layer 220 can be doped in situ with donor atoms. The first base layer 210 and the second base layer 220 form a base layer 200 with an exposed base layer surface 205. Using photolithography, a second auxiliary implantation mask 430 is formed on the base layer surface 205. By means of ion implantation, acceptor atoms are implanted into the second base layer 220.

[0159] Figure 22B It is shown that p-conducting shielding structures 260 are obtained by activating acceptor ions implanted through the openings in the second auxiliary implantation mask 430 and that n-conducting current spreading regions 230 are formed in segment regions of the second base layer 220 covered by the second auxiliary implantation mask 430. Each p-conducting shielding structure 260 is in direct contact with a p-conducting second pillar region 242. Each n-conducting current spreading region 230 is in direct contact with an n-conducting first pillar region 241.

[0160] An epitaxial bottom interface 211 is formed between the first base layer 210 and the second base layer 220. The thickness vi of the second base layer 220 and the vertical extension vo of the shielding structure 260 are at least approximately equal.

[0161] The second assist implant mask 430 is removed, and the transistor layer 100 is grown on the base layer surface 205 by epitaxy. The transistor layer 100 can be doped in situ with donor atoms or acceptor atoms. A trench etch mask is formed on the top surface 101 of the transistor layer 100. Above the shield structures 260, gate trenches 159 are etched into the transistor layer 100. Sacrificial oxides 440 are formed on the exposed surfaces of the transistor layer 100. Through the bottoms of the gate trenches 159, acceptor atoms are implanted.

[0162] Figure 22C The p-conducting assist regions 170 are shown, obtained from activated acceptor ions implanted through the bottoms of the gate trenches 159. Each p-conducting assist region 170 is in direct contact with a p-conducting shield structure 260. The assist regions 170 extend from the trench gate structures 150 to the shield structures 260.

[0163] The sacrificial oxides 440 are removed. Dielectric liners are formed on the exposed surfaces of the transistor layer 100, for example by oxidation and / or deposition. Conductive material (e.g., heavily doped polysilicon) is deposited and removed from the top surface 101.

[0164] Figure 22D The gate structures 150 are shown, having gate conductors 155 formed of deposited conductive material filling the gate trenches 159. Figure 22C

[0165] Figures 23A-23D A method for more precisely defining the JFET structure is shown. A hard mask 450 is formed on the base layer surface 205 on the front side of the base layer 200, where the base layer 200 includes either the shield structures 260 formed along the base layer surface 205 or a continuous p-conducting layer.

[0166] As shown in Figure 23A , the hard mask 450 covers the shield structures 260 and exposes portions of the base layer 200 between or surrounded by the shield structures 260. Using the hard mask 450 as an etch mask, channel trenches 239 are etched into the base layer 200.

[0167] Figure 23B The channel trenches 239 are shown. The sidewalls of the channel trenches 239 expose the p-conducting shield structures 260. Through angled ion implantation, donor atoms are implanted through the sidewalls of the channel trenches 239.

[0168] According to Figure 23C ​Doped n- side wall portions 238 of the heavily doped n-conducting side wall portions of the channel portion of the current spreading region are formed on opposite sides of the channel trench. Then, as described above, the transistor layer 100 is grown on the base layer surface 205 by epitaxy. The transistor layer 100 can be doped in situ with donor atoms.

[0169] According to Figure 23D , the segment region of the grown transistor layer 100 fills Figure 23C the channel trench 239. Figure 23C The in situ doped segment region of the transistor layer 100 in the channel trench 239 forms the lightly doped central portion 237 of the channel portion 231 of the current spreading region.

Claims

1. A semiconductor device, comprising: A base layer (200) is based on single-crystal silicon carbide and includes a current propagation region (230) of a first conductivity type and a non-depletable shielding structure (260) of a second conductivity type; and A transistor layer (100) is based on a single crystal silicon carbide grown epitaxially and includes a transistor element (TC) configured to control the current through the current propagation region (230). After the shielding structure (260) is formed in the base layer (200), the transistor layer (100) is formed on the base layer (200) such that an epitaxial interface (201) is formed between the base layer (200) and the transistor layer (100). The current propagation region extends from the epitaxial interface (201) between adjacent portions of the shielding structure (260); and Along a vertical line orthogonal to the epitaxial interface (201) and passing through the pn junction between the shielding structure (260) and the region of the first conductivity type in the transistor layer (100), at the location of the pn junction, the net dopant concentration variation is at least 1e171 / cm per 0.1 μm. 3 .

2. The semiconductor device of the preceding claim, wherein the base layer (200) further comprises a current drift portion (240, 241) of a first conductivity type, and wherein the current propagation region (230) extends to the current drift portion (240, 241).

3. The semiconductor device as claimed in any of the preceding claims, further comprising: The second conductivity type connection region (160) extends through the transistor layer (100) to the shielding structure (260) and is in direct contact with the shielding structure (260) along a first segment of the epitaxial interface (201), wherein the vertical dopant profile of the first segment of the epitaxial interface (201) shows a step on the epitaxial interface (201).

4. The semiconductor device of the preceding claim, wherein the connection region (160) extends from the top surface (101) of the transistor layer (100) to the shielding structure (260).

5. The semiconductor device as claimed in any of the preceding claims, wherein the transistor element (TC) is configured to control current through a body region (120) between a source region (110) and a current collection region (130), and wherein the current collection region (130) is electrically connected to the current propagation region (230).

6. The semiconductor device of the preceding claim, wherein the body region (120) separates the source region (110) and the current collection region (130) in a horizontal direction parallel to the epitaxial interface (201).

7. The semiconductor device of claim 5, wherein the body region (120) separates the source region (110) and the current collection region (130) in a vertical direction.

8. The semiconductor device of claim 1, further comprising: A trench gate structure (150) extends from the top surface (101) of the transistor layer (100) into the transistor layer (100), wherein the source region (110), the body region (120) and the current collection region (130) are in direct contact with the sidewalls of the trench gate structure (150).

9. The semiconductor device of the preceding claim, wherein the current collection region (130) and the current propagation region (230) are in direct contact with each other along a second segment of the epitaxial interface (201), and wherein the vertical dopant profile of the second segment of the epitaxial interface (201) shows a step on the epitaxial interface (201).

10. The semiconductor device of any one of the preceding two claims, wherein the trench gate structure (150) terminates in the transistor layer (100), and wherein the auxiliary region (160) of the second conductivity type extends from the bottom of the trench gate structure (150) to the shielding structure (260).

11. The semiconductor device of any of the preceding claims, wherein the current propagation region (230) extends vertically through a gap in the shielding structure (260), wherein the gap has a vertical extension v0 and a horizontal width w0, and wherein the aspect ratio v0 / w0 of the gap in the shielding structure (260) is at least 0.3, for example at least 1 or at least 5.

12. The semiconductor device as claimed in any of the preceding claims, further comprising: The first conductive type has a depletable first pillar region (241) and the second conductive type has a depletable second pillar region (242), wherein the first pillar region (241) is formed in the base layer (200) and directly contacts the current propagation region (230), and wherein the second pillar region (242) is formed in the base layer (200) and directly contacts the shielding structure (260).

13. The semiconductor device of the preceding claim, wherein the transistor element (TC) is striped and has a horizontal longitudinal axis along a first horizontal direction, and wherein the first and second pillar regions (241, 242) are striped and have a horizontal longitudinal axis along the first horizontal direction.

14. The semiconductor device of claim 12, wherein the transistor element (TC) is striped and has a longitudinal axis along a first horizontal direction, and wherein the first and second pillar regions (241, 242) are striped and have a horizontal longitudinal axis skewed relative to the first horizontal direction.

15. The semiconductor device of any of the preceding claims, wherein the current propagation region (230) includes a central portion (237) in the gap in the shielding structure (260) and a heavily doped sidewall portion (238) between the central portion (237) and the shielding structure (260).

16. A method of manufacturing a semiconductor device, the method comprising: A base layer (200) based on single-crystal silicon carbide is formed, the base layer (200) including a non-depletable shielding structure (260) of a second conductivity type and a current propagation region (230) of a first conductivity type, the current propagation region (230) extending from the base layer surface (205) of the base layer (200) through a gap in the shielding structure (260); and A transistor layer (100) is formed on the surface (205) of the base layer. The transistor layer (100) includes transistor elements (TCs) configured to control the current through the current propagation region (230). Along a vertical line orthogonal to the epitaxial interface (201) between the transistor layer (100) and the base layer (200) and passing through the pn junction between the shielding structure (260) and the region of the first conductivity type in the transistor layer (100), at the location of the pn junction, the net dopant concentration variation is at least 1e171 / cm per 0.1 μm. 3 .

17. The method of claim 1, wherein forming the transistor layer (100) comprises: After the shielding structure (260) is formed in the base layer (200), the transistor layer (100) is grown on the surface (205) of the base layer by epitaxy.

18. The method of any one of the preceding two claims, wherein forming the base layer (200) comprises: Before forming the shielding structure (260), a first depletable first pillar region (241) of the first conductivity type and a second depletable second pillar region (242) of the second conductivity type are formed in the base layer (200), wherein the shielding structure (260) is formed between the epitaxial interface (201) and the first and second pillar regions (241, 242).

19. The method of any one of the preceding three claims, wherein forming the transistor layer (100) comprises: A gate trench (159) is formed extending from the main surface (101) of the transistor layer (100) into the transistor layer (100). A dopant of the first conductivity type is injected through the bottom of the gate trench (159) to form an auxiliary region (160) between the gate trench (159) and the shielding structure (260), and a trench gate structure (150) is formed in the gate trench (159).

20. The method of any one of the preceding four claims, wherein forming the base layer (200) comprises: Before forming the transistor layer (100), a channel trench (239) is formed in the gap of the shielding structure (260), and the channel trench (239) is filled with a doped semiconductor material to form at least a portion of the current propagation region (230).

21. The method of claim 1, further comprising: Before filling the channel trench (239), dopant atoms are injected into the sidewalls of the channel trench (239).

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