Battery preparation method, solar battery and photovoltaic module

Abstract

The invention relates to the technical field of photovoltaic, and discloses a battery preparation method, a solar battery and a photovoltaic module, and the battery preparation method comprises the steps: providing a substrate; the substrate is provided with a first surface and a second surface far away from the first surface, and a first doping layer is formed on the first surface; forming a second doping layer covering the second surface and the side wall of the substrate; forming at least one mask layer on the second doping layer covering the side wall; performing first etching treatment on the second doping layer covering the side wall, and removing a part of the second doping layer which is not covered by the mask layer in the second doping layer covering the side wall, so that the second doping layer covered by the mask layer forms an electric leakage channel; the electric leakage channel is connected with the first doping layer and the second doping layer; and performing second etching treatment on the mask layer to remove the mask layer. Therefore, the heating condition of the shielded part of the battery is reduced, the problem of hot spot effect of the battery is solved, and the hot spot risk resistance of the battery is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of photovoltaics, in particular to a cell preparation method, a solar cell and a photovoltaic module. BACKGROUND

[0002] At present, the photovoltaic module formed by the existing Topcon cell has a shaded area, the unshaded area normally generates electricity, but the shaded area cannot accept light to generate electricity, that is, the shaded area is equivalent to a resistor, which not only does not generate electricity, but also consumes existing electricity and converts it into heat energy, thereby forming a hot spot effect. The hot spot effect poses a serious threat to the safe operation of the photovoltaic power station. The high temperature generated by the hot spot can accelerate the aging process of the photovoltaic module, reduce the power generation efficiency of the photovoltaic module, and long-term high-temperature effect can damage the packaging material of the photovoltaic module, leading to a decrease in the sealing performance of the module and further exacerbating the aging of the photovoltaic module.

[0003] The existing anti-hot spot scheme of the Topcon cell usually adopts a cell with low leakage and sets a bypass diode. However, this scheme requires that the leakage current of the Topcon cell be controlled to be very small, which has a high requirement on the process. Any defect in the preparation process of the Topcon cell will cause the leakage current to exceed the control range, which cannot effectively solve the hot spot effect and reduce the anti-hot spot risk ability of the photovoltaic module. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide a cell preparation method, a solar cell and a photovoltaic module, so as to form a leakage channel at the edge of the substrate, reduce the heating of the shaded part of the cell, solve the problem of cell hot spot effect, and improve the anti-hot spot risk ability of the cell.

[0005] To solve the above technical problems, the embodiments of the present application provide a cell preparation method, which comprises: providing a substrate; the substrate has a first surface and a second surface away from the first surface, and a first doped layer is formed on the first surface; a second doped layer covering the second surface and the sidewall of the substrate is formed; at least one mask layer is formed on the second doped layer covering the sidewall; the second doped layer covering the sidewall is subjected to first etching treatment, and the second doped layer not covered by the mask layer is removed from the second doped layer covering the sidewall, so that the second doped layer covered by the mask layer forms a leakage channel; the leakage channel connects the first doped layer and the second doped layer; the mask layer is subjected to second etching treatment to remove the mask layer.

[0006] Embodiments of the present application also provide a solar cell, comprising: a substrate; a first doped layer covering a first surface of the substrate; a second doped layer covering a second surface of the substrate away from the first doped layer; at least one leakage channel located on a sidewall of the substrate, the leakage channel connecting the first doped layer and the second doped layer.

[0007] Embodiments of the present application also provide a photovoltaic module, comprising: the above solar cell.

[0008] In some embodiments, the forming the second doped layer covering the second surface and the sidewall of the substrate comprises: forming a polysilicon layer covering the second surface and the sidewall of the substrate; and performing a doping treatment on the polysilicon layer to form the second doped layer and a silicon glass layer; the second doped layer covers the second surface and the sidewall of the substrate, and the silicon glass layer covers a surface of the second doped layer away from the substrate; and before the performing the first etching treatment on the second doped layer covering the sidewall, the method further comprises: performing a third etching treatment on the silicon glass layer to remove a portion of the silicon glass layer not covered by the mask layer.

[0009] In some embodiments, the first etching treatment is to remove a portion of the second doped layer not covered by the mask layer in the second doped layer covering the sidewall using a hydrofluoric acid solution or a buffered oxide etching solution; and the second etching treatment is to remove the mask layer using an acetone solution.

[0010] In some embodiments, the third etching treatment is to remove a portion of the silicon glass layer not covered by the mask layer using a hydrofluoric acid solution.

[0011] In some embodiments, the doping treatment is performed at a temperature of 900-950 degrees Celsius for 10-60 minutes, and the phosphorus source has a concentration of 1x10 19 to 1x10 21 atoms / cm 3 .

[0012] In some embodiments, the first doped layer and the second doped layer are of different types.

[0013] In some embodiments, the mask layer has a width of 2-10 microns, a thickness of 0.2-20 microns, and a material selected from any one of silicon nitride, silicon oxide, titanium nitride, and photoresist.

[0014] The technical solutions provided by the embodiments of the present application have at least the following advantages:

[0015] The embodiment forms at least one mask layer on the second doped layer, and after the first etching treatment, the second doped layer covered by the mask layer forms a leakage channel, and the leakage channel connects the first doped layer and the second doped layer. Due to the design of the leakage channel, when part of the battery is blocked, the reverse voltage of the blocked part of the battery is reduced, thereby reducing the heating of the blocked part of the battery, solving the problem of battery hot spot effect, and improving the anti-hot spot risk ability of the battery. BRIEF DESCRIPTION OF DRAWINGS

[0016] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which are illustrative, but not restrictive, of the embodiments, wherein elements having the same reference number designates like elements throughout the various figures, and wherein the figures are not necessarily drawn to scale. The figures illustrate various embodiments of the disclosure and, together with the detailed description below, provide further appreciation and understanding of the inventive subject matter.

[0017] FIG. 1A A flowchart of a battery manufacturing method according to an embodiment of the present application;

[0018] FIG. 1B A structure diagram of a substrate and a first doped layer;

[0019] FIG. 1C A structure diagram after a first polysilicon layer is formed on the substrate;

[0020] FIG. 1D A structure diagram after the first polysilicon layer is doped;

[0021] FIG. 1E A structure diagram after the first silicon glass layer is etched;

[0022] FIG. 2A A structure diagram after a second doped layer is formed on the substrate;

[0023] FIG. 2B A structure diagram after a polysilicon layer is formed on the substrate;

[0024] FIG. 2C A structure diagram after the polysilicon layer is doped;

[0025] FIG. 3A A structure diagram after a mask layer is formed on the second doped layer;

[0026] FIG. 3B Another structure diagram after the mask layer is formed on the second doped layer;

[0027] FIG. 3C Still another structure diagram after the mask layer is formed on the second doped layer;

[0028] FIG. 4AStructure after first etching treatment on second doped layer;

[0029] FIG. 4B Another structure after first etching treatment on second doped layer;

[0030] FIG. 5A Structure after second etching treatment on mask layer;

[0031] FIG. 5B Another structure after second etching treatment on mask layer;

[0032] FIG. 6A Structure after forming mask layer on silicon glass layer;

[0033] FIG. 6B Another structure after forming mask layer on silicon glass layer;

[0034] FIG. 6C Still another structure after forming mask layer on silicon glass layer;

[0035] FIG. 7A Structure after third etching treatment on silicon glass layer;

[0036] FIG. 7B Another structure after third etching treatment on silicon glass layer;

[0037] FIG. 8A Structure after first etching treatment on second doped layer;

[0038] FIG. 8B Another structure after first etching treatment on second doped layer;

[0039] FIG. 9 Still another structure after second etching treatment on mask layer;

[0040] FIG. 10A Structure after fourth etching treatment on silicon glass layer covering leakage channel;

[0041] FIG. 10B Another structure after fourth etching treatment on silicon glass layer covering leakage channel.

[0042] Reference numerals

[0043] Base (10), first doped layer (20), first polysilicon layer (21), first silicon glass layer (22), second doped layer (30), polysilicon layer (31), silicon glass layer (32), leakage channel (33), mask layer (40). DETAILED DESCRIPTION

[0044] As can be known from the background art, the hot spot effect problem of the current Topcon battery still cannot be solved well.

[0045] To solve the above technical problems, the embodiment of the present application provides a battery preparation method, which comprises the following steps: providing a substrate; the substrate has a first surface and a second surface away from the first surface, and a first doped layer is formed on the first surface; forming a second doped layer covering the second surface and the sidewall of the substrate; forming at least one mask layer on the second doped layer covering the sidewall; performing a first etching treatment on the second doped layer covering the sidewall, removing the part of the second doped layer not covered by the mask layer, so that the second doped layer covered by the mask layer forms a leakage channel; the leakage channel is connected with the first doped layer and the second doped layer; and performing a second etching treatment on the mask layer to remove the mask layer.

[0046] According to the embodiment, at least one mask layer is formed on the second doped layer, and after the first etching treatment, the second doped layer covered by the mask layer forms a leakage channel, and the leakage channel is connected with the first doped layer and the second doped layer. Due to the design of the leakage channel, when part of the battery is blocked, the reverse voltage of the blocked part of the battery will be reduced, thereby reducing the heating of the blocked part of the battery, solving the problem of the hot spot effect of the battery, and improving the anti-hot spot risk ability of the battery.

[0047] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise explicitly and specifically limited. Similarly, "multiple groups" means two or more groups (including two groups), and "multiple pieces" means two or more pieces (including two pieces).

[0048] In this document, the term "embodiment" means that the specific features, structures or characteristics described in connection with the embodiment can be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily mean the same embodiment, nor is it independent or alternative to other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0049] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which means that there are three cases of A, A and B, and B. In addition, the character " / " in this document generally means that the front and rear associated objects are in an "or" relationship.

[0050] In the description of the embodiments of the present application, the orientations or positional relationships indicated by the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", and the like are based on the orientations or positional relationships shown in the drawings, and are merely for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the embodiments of the present application. For example, if the devices or elements in the drawings are inverted, the elements described as "below" or "under" or "lower" or "bottom" of other elements or features will be oriented "above" or "top" of the other elements or features. Therefore, the term "below" can encompass both upward and downward orientations depending on the context in which the term is used, which will be apparent to those of ordinary skill in the art. The materials can be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatially relative descriptors used herein can be interpreted accordingly.

[0051] In the description of the embodiments of the present application, unless otherwise explicitly specified and limited, the technical terms "mounting", "connecting", "connecting", "fixing", and the like should be broadly understood, for example, can be fixedly connected, or can be detachably connected, or can be integrated; can be mechanically connected, or can be electrically connected; can be directly connected, or can be indirectly connected through an intermediate medium; can be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0052] In the corresponding drawings of the embodiments of the present application, the thickness and area of the layers are exaggerated for better understanding and ease of description. In addition, when it is described that one component is "formed substantially" on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a part of the edge of the entire surface.

[0053] In the description of the embodiments of the present application, when a certain component "includes" another component, unless otherwise specified, other components are not excluded and can further include. Formed or disposed on the first component or on the surface of the first component or on the side of the first component, the second component can include an embodiment in which the first component and the second component are in direct contact, and can also include an embodiment in which additional components can be between the first component and the second component, so that the first component and the second component can not be in direct contact. For the sake of simplicity and clarity, various components can be arbitrarily drawn in different proportions. In the drawings, some layers / components can be omitted for simplicity. Unless otherwise specified, the first component formed or disposed with the second component on the surface of the first component means that the first component is in direct contact with the second component. Among them, the "component" mentioned above can refer to a layer, a film, a region, a part, a structure, etc.

[0054] The terms used in the description of various embodiments herein are only used to describe specific embodiments and are not intended to be limiting. As used in the description of various embodiments and the appended claims, "component" is also intended to include the plural form, unless the context clearly indicates otherwise. Among them, the component includes layers, films, regions, or plates, etc.

[0055] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art can understand that in the embodiments of the present disclosure, many technical details are proposed in order to enable the reader to better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be realized even without these technical details and various changes and modifications based on the following embodiments.

[0056] An embodiment of the present application relates to a battery preparation method, and a specific flowchart is shown as FIG. 1A The method comprises the following steps:

[0057] Step S1, providing a substrate; the substrate has a first surface and a second surface away from the first surface, and a first doped layer is formed on the first surface.

[0058] Step S2, forming a second doped layer covering the second surface and the sidewall of the substrate.

[0059] Step S3, forming at least one mask layer on the second doped layer covering the sidewall.

[0060] Step S4, performing a first etching process on the second doped layer covering the sidewall, removing the part of the second doped layer not covered by the mask layer in the second doped layer covering the sidewall, so that the second doped layer covered by the mask layer forms a leakage channel; the leakage channel connects the first doped layer and the second doped layer.

[0061] Step S5, a second etching treatment is performed on the mask layer to remove the mask layer.

[0062] The embodiment forms at least one mask layer on the second doped layer, and after the first etching treatment, the second doped layer covered by the mask layer forms a leakage channel, and the leakage channel connects the first doped layer and the second doped layer. Due to the design of the leakage channel, when part of the battery is blocked, the reverse voltage of the blocked part of the battery will be reduced, thereby reducing the heating of the blocked part of the battery, solving the problem of battery hot spot effect, and improving the anti-hot spot risk ability of the battery.

[0063] The battery preparation method of the embodiment, the specific preparation process is referred to FIG. 1B to FIG. 5B .

[0064] Reference FIG. 1B , a structural schematic diagram of a substrate and a first doped layer.

[0065] The embodiment provides a substrate 10, which has a first surface and a second surface away from the first surface, and a first doped layer 20 is formed on the first surface.

[0066] The battery of the embodiment can be a Topcon battery, and the front and back surfaces of the Topcon battery substrate 10 are respectively used to set P-type doped layers and N-type doped layers. The substrate 10 can be an N-type single crystal silicon wafer. Compared with a P-type silicon wafer, the N-type silicon wafer hardly experiences light decay under light, can maintain stable performance, and can significantly improve the conversion efficiency of the Topcon battery.

[0067] The first doped layer 20 and the second doped layer 30 of the embodiment are different in type. The first doped layer 20 of the embodiment can be a P-type doped layer or an N-type doped layer, and is specifically set according to actual needs, which is not limited in the embodiment. The first doped layer 20 is taken as a P-type doped layer and the second doped layer 30 is taken as an N-type doped layer as an example for description below.

[0068] The embodiment forms the first doped layer 20 on the first surface of the substrate 10, and the first doped layer 20 can be obtained by the following method.

[0069] Reference FIG. 1C , a structural schematic diagram after a first polysilicon layer is formed on a substrate.

[0070] The first polysilicon layer 21 is formed on the first surface of the substrate 10 and covers the first surface and the sidewall of the substrate 10. During the process of forming the first polysilicon layer 21 on the first surface of the substrate 10, the first polysilicon layer 21 is also formed on the sidewall of the substrate 10, which causes some around-plating. This phenomenon is inevitable during the process of forming the first polysilicon layer 21, and thus the first polysilicon layer 21 on the sidewall of the substrate 10 needs to be removed subsequently.

[0071] Specifically, the first polysilicon layer 21 can be formed by performing a laser annealing process on the first surface of the substrate 10 to convert the single crystal silicon of the substrate 10 into the first polysilicon layer 21, thereby providing a basis for subsequent doping treatment (such as boron diffusion or phosphorus diffusion).

[0072] In some embodiments, before the first polysilicon layer 21 is formed on the substrate 10, the substrate 10 needs to be cleaned and textured. The cleaning and texturing includes a cleaning process, a texturing process, a post-processing process, and a drying process. The cleaning process includes pre-cleaning, acid cleaning, and alkali cleaning, which aims to remove impurities, organic contaminants, metal ions, and the like on the surface of the silicon wafer, thereby providing a clean surface for the subsequent texturing process. The purpose of the texturing process is to form a pyramid-shaped textured structure on the surface of the silicon wafer to reduce light reflection and improve light absorption efficiency. The purpose of the post-processing process is to remove residual chemicals in the texturing process and the oxide layer on the surface of the silicon wafer. The purpose of the drying process is to remove moisture on the surface of the substrate 10.

[0073] Reference FIG. 1D The structure after the first polysilicon layer is doped.

[0074] After the first polysilicon layer 21 is formed on the first surface and the sidewall of the substrate 10, the first polysilicon layer 21 is doped, for example, boron diffusion, so that the first polysilicon layer 21 forms a first doped layer 20 and a first silicon glass layer 22.

[0075] In the case where the first doped layer 20 is a P-type doped layer, the first polysilicon layer 21 is doped by boron diffusion. For example, liquid boron tribromide (BBr3) or gaseous boron trichloride (BCl3) is used as a boron source, and the generated boron atoms diffuse into the silicon substrate to form the first doped layer 20, i.e., the P-type doped layer. During the boron diffusion process, B2O3 generated by the decomposition of the boron source is deposited on the surface of the silicon wafer. B2O3 reacts with silicon to generate SiO2 and boron atoms. The reaction products, i.e., SiO2 and boron atoms, form a first silicon glass layer 22, i.e., boron silicon glass (BSG), on the surface of the silicon wafer. However, boron silicon glass (BSG) has a metal gettering effect, which affects the normal operation of the solar cell, and thus needs to be removed in subsequent processes.

[0076] The temperature of boron diffusion in this embodiment is 800-1000℃, the diffusion time is 10-60 minutes, and the boron source concentration is 1x10 19 to 1x10 21 atoms / cm 3 .

[0077] Reference FIG. 1E is a schematic diagram of the structure after etching the first silicon glass layer.

[0078] After the first doped layer 20 and the first silicon glass layer 22 (i.e., borosilicate glass) are formed by doping the first polysilicon layer 21 in this embodiment, the first silicon glass layer 22 (i.e., borosilicate glass) needs to be removed because it will affect the normal operation of the solar cell. Only the first doped layer 20 exists on the first surface of the substrate 10 and the sidewall to improve the stability of the solar cell. For example, chemical reagents such as hydrofluoric acid can be used to etch and clean the first silicon glass layer 22 (i.e., borosilicate glass) to remove its impact on the solar cell.

[0079] Since the first doped layer 20 on the sidewall part is inevitable around the plating, the first doped layer 20 on the sidewall part of the substrate 10 is etched after the first doped layer 20 is formed in this embodiment, forming a first doped layer 20 covering only the first surface of the substrate 10 as shown in FIG. 1B In practical applications, wet etching process, laser treatment combined with wet etching, reactive ion etching, atomic layer deposition (ALD) combined with etching can be used to remove the first doped layer 20 on the sidewall of the substrate 10, thereby preventing a large amount of first doped layer 20 on the sidewall of the substrate 10, causing the P-type and N-type doped layers of the solar cell to be short-circuited, and improving the efficiency of the solar cell.

[0080] The first doped layer 20, i.e., the P-type doped layer, of this embodiment is located on the front surface of the cell and is used to form a PN junction. The PN junction is responsible for separating and transporting photo-generated carriers (electrons and holes) to the external circuit.

[0081] Reference FIG. 2A is a schematic diagram of the structure after forming the second doped layer on the substrate.

[0082] After providing the substrate 10 with the first doped layer 20 in this embodiment, the second doped layer 30 covering the second surface and the sidewall of the substrate 10 is formed on the second surface of the substrate 10.

[0083] The second doped layer 30 also covers the edges of the first doped layer 20, so that the subsequent formed leakage channel can well connect the first doped layer 20 and the second doped layer 30, improving the stability of the leakage effect.

[0084] The second doped layer 30 of the embodiment can be a P-type doped layer or an N-type doped layer, which is specifically set according to actual needs, and the embodiment is not limited in particular. The following is described by taking the second doped layer 30 as an N-type doped layer as an example.

[0085] The second doped layer 30 covering the second surface and the sidewall of the substrate 10 can be formed in the following manner.

[0086] Reference FIG. 2B is a structural schematic diagram after a polysilicon layer formed on the substrate 10.

[0087] The embodiment forms a polysilicon layer 31 covering the second surface and the sidewall of the substrate 10 on the second surface of the substrate 10 and the sidewall of the substrate 10, wherein the polysilicon layer 31 also covers the edge of the first doped layer 20. In the process of forming the polysilicon layer 31 on the second surface of the substrate 10, the polysilicon layer 31 is also formed on the sidewall of the substrate 10. The embodiment forms the polysilicon layer 31 on the sidewall to provide a basis for forming a leakage channel later.

[0088] Specifically, the polysilicon layer 31 can be formed by performing a laser annealing process on the second surface and the sidewall of the substrate 10 to convert the single crystal silicon of the substrate 10 into the polysilicon layer 31, thereby providing a basis for subsequent doping treatment (such as boron diffusion or phosphorus diffusion).

[0089] In some embodiments, before forming the polysilicon layer 31, a tunneling oxide layer can also be formed on the second surface and the sidewall of the substrate 10, that is, the tunneling oxide layer is located between the substrate 10 and the polysilicon layer 31. The tunneling oxide layer is an ultrathin silicon oxide (SiO x ) layer, which can achieve high-efficiency carrier selective passivation contact, effectively passivate the defect states on the surface of the silicon wafer, reduce the recombination of photo-generated carriers, and thus improve the efficiency of the battery. Specifically, the tunneling oxide layer can be formed on the second surface and the sidewall of the substrate 10 by using a thermal oxidation method, a wet oxidation method (nitric acid oxidation method, hydrogen peroxide method, ozone oxidation method), a plasma-assisted oxidation method, an anodic oxidation method, and the like.

[0090] Reference FIG. 2C is a structural schematic diagram after doping treatment is performed on the polysilicon layer.

[0091] After forming the polysilicon layer 31 on the second surface and the sidewall of the substrate 10, the embodiment performs doping treatment, such as phosphorus diffusion, on the polysilicon layer 31, so that the polysilicon layer 31 forms a second doped layer 30 and a silicon glass layer 32. The second doped layer 30 covers the second surface and the sidewall of the substrate 10 and the edge of the first doped layer 20, and the silicon glass layer 32 covers the surface of the second doped layer 30 away from the substrate 10.

[0092] In the case that the second doped layer 30 is an N-type doped layer, the embodiment performs a doping treatment on the polysilicon layer 31, i.e. phosphorus diffusion. For example, a liquid phosphorus source (such as phosphorus oxychloride POCl3) is used as the phosphorus source, the phosphorus source is decomposed at high temperature, and phosphorus atoms diffuse into the polysilicon layer 31 to form the second doped layer 30, i.e. the N-type doped layer. During the phosphorus diffusion process, the phosphorus generated by the decomposition of the phosphorus source reacts with silicon, and a phosphorus-rich silicon dioxide layer, i.e. a phosphosilicate glass (PSG), is formed on the surface of the silicon wafer. However, although the phosphosilicate glass (PSG) plays a protective and doping source role during the diffusion process, it has an adverse effect on the solar cell, such as causing PN junction leakage. Therefore, the phosphosilicate glass (PSG) needs to be removed in subsequent processes.

[0093] The temperature for the doping treatment on the polysilicon layer 31 in the embodiment is 800-950°C, the doping time is 10-60 minutes, and the concentration of the phosphorus source is 1x10 19 to 1x10 21 atoms / cm 3 . The temperature for boron diffusion is higher than the temperature for phosphorus diffusion.

[0094] After that, the silicon glass layer 32, i.e. the phosphosilicate glass layer (PSG), is etched to form the structure of the second doped layer 30 as shown in FIG. 4. FIG. 2A Specifically, since the silicon glass layer 32, i.e. the phosphosilicate glass layer (PSG), has an adverse effect on the solar cell, the silicon glass layer 32, i.e. the phosphosilicate glass layer (PSG), needs to be removed in the embodiment, and the second doped layer 30 is only formed on the second surface of the substrate 10 and the sidewall to improve the stability of the solar cell. For example, a chemical reagent (such as hydrofluoric acid) can be used to etch and clean the silicon glass layer 32, i.e. the phosphosilicate glass layer (PSG), to remove its adverse effect on the solar cell.

[0095] The second doped layer 30, i.e. the N-type doped layer, in the embodiment is located on the back surface of the cell and is used to form a passivated contact structure to reduce the recombination of carriers in the metal contact area.

[0096] Since the second doped layer 30 includes a non-metal contact area and a metal contact area, the non-metal contact area is the second doped layer 30 not covered by a metal electrode, and the metal contact area is the second doped layer 30 directly covered by a back surface metal electrode (such as silver paste or aluminum paste), the embodiment can reduce the doping amount of the non-metal contact area of the second doped layer 30 and increase the doping amount of the metal contact area of the second doped layer 30. Reducing the doping amount of the non-metal contact area of the second doped layer 30 can reduce recombination, and increasing the doping amount of the metal contact area of the second doped layer 30 can reduce the contact resistance, thereby solving the contradictory requirements of metal semiconductor recombination and contact resistance.

[0097] Due to the large light absorption coefficient of the second doped layer 30, if the entire back surface is used, it will cause current loss problems. In this embodiment, the local passivation contact method is adopted, and the passivation contact structure is only reserved under the metal electrode area, and the structure is removed or thinned in the non-metal contact area, thereby reducing the parasitic absorption and high-efficiency technical path of the compound loss, solving the inherent shortcomings of the passivation contact technology, and taking into account the requirements of passivation contact and light absorption.

[0098] In this embodiment, the first doped layer 20 is a P-type doped layer, and the second doped layer 30 is an N-type doped layer. In actual application, the first doped layer 20 can be an N-type doped layer, and the second doped layer 30 can be a P-type doped layer.

[0099] In this embodiment, the first doped layer 20 is a P-type doped layer, and the second doped layer 30 is an N-type doped layer. In actual application, the first doped layer 20 can be an N-type doped layer, and the second doped layer 30 can be a P-type doped layer.

[0100] Reference FIG. 3A , which is a structural schematic diagram after forming a mask layer on the second doped layer, reference FIG. 3B , which is another structural schematic diagram after forming a mask layer on the second doped layer; reference FIG. 3C , which is still another structural schematic diagram after forming a mask layer on the second doped layer.

[0101] In this embodiment, at least one mask layer 40 is formed on the second doped layer 30 covering the side wall after forming the second doped layer 30, wherein the mask layer 40 also extends to the second doped layer 30 covering the edge of the first doped layer 20; FIG. 3A only shows a cross-sectional schematic diagram of the area where the mask layer 40 is located, FIG. 3B shows a structural schematic diagram of forming a mask layer 40 on the side wall of the substrate 10, FIG. 3C shows a top view of the first surface of the substrate 10. It can be seen that one or more mask layers 40 can be formed on the second doped layer 30 covering the side wall in this embodiment, thereby protecting the part of the second doped layer 30 covered by the mask layer 40, thereby providing a protection basis for subsequent formation of a leakage channel.

[0102] The width of the mask layer 40 in this embodiment is 2-10 microns. By setting the width of the mask layer 40 in this range, the width of the formed leakage channel is also 2-10 microns. On the one hand, this avoids the effect of reducing the reverse voltage of the battery being poor due to the reverse leakage channel being too narrow, so that when part of the battery is shaded, the reverse leakage channel can better reduce the reverse voltage of the battery, reduce the heating of the shaded part of the battery, solve the problem of battery hot spot effect, improve the anti-hot spot risk ability of the battery. On the other hand, it also avoids the problem of excessive leakage of the battery due to the excessive width of the leakage channel, which reduces the efficiency and performance of the battery, thereby ensuring the efficiency and performance of the battery.

[0103] The thickness of the mask layer 40 in this embodiment is 0.2-20 microns. By setting the thickness of the mask layer 40 in this range, on the one hand, it can avoid the problem of poor leakage effect of the leakage channel due to the thin thickness of the mask layer 40, which damages the mask layer 40 in the subsequent etching process. On the other hand, it can avoid the problem of long process time of the mask layer 40 during etching due to the thick thickness of the mask layer 40, thereby improving the efficiency of battery preparation.

[0104] Specifically, the material of the mask layer 40 is any one of the following: silicon nitride, silicon oxide, titanium nitride, and photoresist.

[0105] Reference FIG. 4A is a structural schematic diagram after the first etching process is performed on the second doped layer 30. Reference FIG. 4B is another structural schematic diagram after the first etching process is performed on the second doped layer 30. Among them, FIG. 4A shows a cross-sectional schematic diagram of the uncovered area of the mask layer 40, FIG. 4B shows a top view structural schematic diagram of the first surface of the substrate 10.

[0106] After the one or more mask layers 40 are formed, the second doped layer 30 covering the sidewall is subjected to a first etching treatment to remove the part of the second doped layer 30 not covered by the mask layer 40 in the second doped layer 30 covering the sidewall, so that the second doped layer 30 covered by the mask layer 40 forms a leakage channel 33; at the same time, the second doped layer 30 covering the edge of the first doped layer 20 is also subjected to the first etching treatment, and only the second doped layer 30 covered by the mask layer 40 is reserved, so that under the protection of the mask layer 40, the second doped layer 30 located at the edge of the first doped layer 20 and the second doped layer 30 of the sidewall of the substrate 10 jointly form the leakage channel 33; the remaining second doped layer 30 is only located on the second surface of the substrate 10, so that the leakage channel 33 connects the first doped layer 20 and the second doped layer 30; due to the design of the leakage channel 33, when part of the battery is blocked, the reverse voltage of the blocked part of the battery will be reduced, thereby reducing the heating of the blocked part of the battery, solving the problem of battery hot spot effect and improving the anti-hot spot risk ability of the battery.

[0107] The first etching treatment can be a chemical etching method, for example, using a hydrofluoric acid (HF) solution or a buffered oxide etching solution (BOE) to remove the part of the second doped layer 30 not covered by the mask layer 40 in the second doped layer 30 covering the sidewall; so as to effectively remove the second doped layer 30, i.e. the N-type doped layer, but the etching rate of the mask layer 40 (such as silicon nitride, silicon oxide, titanium nitride, photoresist, etc.) is low, thereby realizing selective etching and reserving the second doped layer 30 covered by the mask layer 40 to form the leakage channel 33.

[0108] The first etching treatment can also be dry etching, for example, using reactive ion etching (RIE) or plasma etching technology and selecting appropriate etching gas (such as CF4, CHF3, etc.) to remove the part of the second doped layer 30 not covered by the mask layer 40 in the second doped layer 30 covering the sidewall; by accurately controlling etching parameters such as gas flow, pressure, power, etc., selective etching of the second doped layer 30, i.e. the N-type doped layer, can be realized without damaging the mask layer 40, thereby reserving the second doped layer 30 covered by the mask layer 40 to form the leakage channel 33.

[0109] Reference FIG. 5A is a structural schematic diagram after the second etching treatment is performed on the mask layer 40, FIG. 5B is another structural schematic diagram after the second etching treatment is performed on the mask layer 40. Among them, FIG. 5A is a cross-sectional schematic diagram of the area where the leakage channel 33 is located, FIG. 5B is a top view schematic diagram of the first surface of the substrate 10.

[0110] After the leakage channel 33 is formed, the mask layer 40 is subjected to a second etching treatment to remove the mask layer 40.

[0111] The second etching process can adopt a wet etching method, and different wet etching solutions can be set according to the material of the mask layer 40. For example, in the case of a photoresist mask layer 40, the second etching process is to remove the mask layer 40 using an acetone solution; in the case of a silicon nitride mask layer 40, a hot phosphoric acid solution can be used to remove the mask layer 40; in the case of a silicon oxide mask layer 40, the second etching process is to remove the mask layer 40 using hydrofluoric acid (HF) or a buffered oxide etching solution; in the case of a titanium nitride mask layer 40, the second etching process is to remove the mask layer 40 using a hydrogen peroxide-ammonia mixture. The second etching process can also adopt a dry etching process, specifically a reactive ion etching (RIE) method, for example, using a chlorine-containing or fluorine-containing gas to etch the mask layer 40, thereby forming only the leakage channel 33 on the side of the substrate 10.

[0112] After the second etching process of the mask layer 40 is performed and the mask layer 40 is removed, the following steps can also be performed in this embodiment:

[0113] Front side aluminum oxide deposition: a plasma-enhanced chemical vapor deposition process is used to deposit an aluminum oxide passivation layer with a thickness of 10-50 nm on the front side of the substrate 10.

[0114] Front and back side silicon nitride deposition: a plasma-enhanced chemical vapor deposition process is used to deposit a silicon nitride passivation layer with a thickness of 10-50 nm on the front and back sides of the substrate 10, respectively.

[0115] Screen printing: a silver paste screen printing process is used to print silver paste on the front and back sides of the silicon wafer of the substrate 10 to form metal grid lines.

[0116] Sintering: sintering is performed at 800-1000°C for 30 minutes to form a good ohmic contact between the metal grid lines and the silicon wafer. Test sorting: the prepared solar cell is tested for electrical performance, including open-circuit voltage, short-circuit current, fill factor, and conversion efficiency, and is sorted according to the test results.

[0117] Laser-assisted sintering: the sorted qualified cell is subjected to a laser-assisted sintering process to improve the contact performance of the metal grid lines with the silicon wafer, with a laser power of 0.5-2 W and a scanning speed of 100-500 mm / s.

[0118] The embodiment forms at least one mask layer 40 on the second doped layer 30, and after a first etching treatment, the second doped layer 30 covered by the mask layer 40 forms a leakage channel 33, which connects the first doped layer 20 and the second doped layer 30. Due to the design of the leakage channel 33, when part of the battery is blocked, the reverse voltage of the blocked part of the battery is reduced, thereby reducing the heating of the blocked part of the battery, solving the problem of battery hot spot effect, and improving the anti-hot spot risk ability of the battery.

[0119] Another embodiment of the present application relates to a battery preparation method, and the preparation process is specifically referred to FIG. 1B 、 FIG. 2B 、 FIG. 2C 、 FIG. 6A to FIG. 10B It should be noted that the same or corresponding parts of the present embodiment and the previous embodiment are not repeated here to avoid repetition. Accordingly, the related technical details of the present embodiment can also be applied to the previous embodiment.

[0120] Referring to FIG. 1B , a substrate 10 is provided, which has a first surface and a second surface away from the first surface, and a first doped layer 20 is formed on the first surface.

[0121] Referring to FIG. 2B , a polysilicon layer 31 covering the second surface and the sidewall of the substrate 10 is formed. The polysilicon layer 31 also covers the edge of the first doped layer 20, so that the subsequently formed leakage channel can well connect the first doped layer 20 and the second doped layer 30, and improve the stability of the leakage effect.

[0122] Referring to FIG. 2C , the polysilicon layer 31 is doped to form a second doped layer 30 and a silicon glass layer 32; the second doped layer 30 covers the second surface and the sidewall of the substrate 10, and the edge of the first doped layer 20, and the silicon glass layer 32 covers the surface of the second doped layer 30 away from the substrate 10.

[0123] Referring to FIG. 6A , the structure after forming the mask layer 40 on the silicon glass layer is shown in FIG. 8A, referring to FIG. 6B , another structure after forming the mask layer 40 on the silicon glass layer is shown in FIG. 8B; referring to FIG. 6C , still another structure after forming the mask layer 40 on the silicon glass layer is shown in FIG. 8C.

[0124] After the polysilicon layer 31 is doped to form the second doped layer 30 and the silicon glass layer 32, at least one mask layer 40 is formed on the silicon glass layer 32 covering the sidewall, wherein the mask layer 40 also extends to the silicon glass layer 32 covering the edge of the first doped layer 20; FIG. 6AThe cross-sectional view of the region where the mask layer 40 is located is shown, FIG. 6B The structure view of the sidewall of the substrate 10 where the mask layer 40 is formed is shown, FIG. 6C The top view of the first surface of the substrate 10 is shown. It can be seen that one or more mask layers 40 can be formed on the silicon glass layer 32 covering the sidewall, so as to protect the part of the silicon glass layer 32 and the second doped layer 30 covered by the mask layer 40, thereby providing a protection basis for the subsequent formation of the leakage channel 33.

[0125] Reference FIG. 7A The structure view after the third etching treatment of the silicon glass layer is shown, FIG. 7B Another structure view after the third etching treatment of the silicon glass layer is shown. In this embodiment, FIG. 7A The cross-sectional view of the region where the mask layer 40 is not covered is shown, FIG. 7B The top view of the first surface of the substrate 10 is shown.

[0126] After the formation of one or more mask layers 40, the third etching treatment is performed on the silicon glass layer 32 to remove the part of the silicon glass layer 32 not covered by the mask layer 40. Specifically, the third etching treatment can etch away the silicon glass layer 32 at the second surface of the substrate 10, the part of the silicon glass layer 32 not covered by the mask layer 40 at the sidewall of the substrate 10, and the part of the silicon glass layer 32 not covered by the mask layer 40 at the edge of the first mask layer 20. That is, during the third etching treatment, the silicon glass layer 32 in other regions is etched away under the protection of the mask layer 40, and only the silicon glass layer 32 covered by the mask layer 40 is reserved.

[0127] The third etching treatment can use a chemical reagent (such as hydrofluoric acid) to etch and clean the silicon glass layer 32, i.e., the phosphosilicate glass layer (PSG), so as to avoid etching the second doped layer 30 covering the second surface by the chemical reagent, and ensure the performance and integrity of the second doped layer 30.

[0128] Reference FIG. 8A The structure view after the first etching treatment of the second doped layer is shown, FIG. 8B Another structure view after the first etching treatment of the second doped layer is shown. In this embodiment, FIG. 8A The cross-sectional view of the region where the mask layer is not covered is shown, FIG. 8B The top view of the first surface of the substrate is shown.

[0129] The second doped layer 30 covering the sidewall is subjected to a first etching treatment after the silicon glass layer 32, i.e. the phosphosilicate glass layer (PSG), is removed, and the part of the second doped layer 30 not covered by the mask layer 40 is removed in the second doped layer 30 covering the sidewall, so that the second doped layer 30 covered by the mask layer 40 forms the leakage channel 33; at the same time, the second doped layer 30 covering the edge of the first mask layer 20 is also subjected to the first etching treatment, and only the second doped layer 30 covered by the mask layer 40 is reserved.

[0130] Reference is made to FIG. 9 Fig. 4 is a structural schematic diagram of the structure after the mask layer 40 is subjected to a second etching treatment in the embodiment.

[0131] The mask layer 40 is subjected to a second etching treatment after the leakage channel 33 is formed in the embodiment, and the mask layer 40 is removed.

[0132] Since the part of the silicon glass layer 32 covered by the mask layer 40 is reserved in the etching process, there is still a layer of silicon glass layer 32 between the leakage channel 33 and the mask layer 40 in the embodiment, so that the silicon glass layer 32 can protect the covered leakage channel 33 when the mask layer 40 is subjected to the second etching treatment, guarantee the integrity of the leakage channel 33, and avoid the influence of the second etching treatment on the structure and performance of the leakage channel 33.

[0133] Reference is made to FIG. 10A Fig. 6 is a structural schematic diagram of the structure after the silicon glass layer covering the leakage channel 33 is subjected to a fourth etching treatment, and reference is made to FIG. 10B Fig. 7 is another structural schematic diagram of the structure after the silicon glass layer covering the leakage channel 33 is subjected to a fourth etching treatment. In the figure, FIG. 10A Fig. 8 shows a cross-sectional structural schematic diagram of the region covering the leakage channel 33, FIG. 10B Fig. 9 shows a plan view structural schematic diagram of the first surface of the substrate 10.

[0134] The silicon glass layer 32 covering the leakage channel 33 can be selectively subjected to a fourth etching treatment after the mask layer 40 is removed in the embodiment.

[0135] The fourth etching treatment can use a chemical reagent (such as hydrofluoric acid) to etch and clean the phosphosilicate glass layer (PSG), so as to avoid etching the leakage channel 33 by the chemical reagent, and ensure the performance and integrity of the leakage channel 33.

[0136] In the process of removing the mask layer 40, if the mask layer 40 is in direct contact with the leakage channel 33, the leakage channel 33 covered by the mask layer 40 may be etched, thereby damaging the leakage channel 33 and reducing the leakage performance of the leakage channel 33, which affects the anti-hot spot effect. Therefore, at least one mask layer 40 is formed on the silicon glass layer 32 in the embodiment, so that after the leakage channel 33 is formed, the silicon glass layer 32 is between the leakage channel 33 and the mask layer 40. On the one hand, the silicon glass layer 32 can protect the leakage channel 33 when the mask layer 40 is etched, so as to avoid damaging the leakage channel 33 and ensure the performance of the leakage channel 33. On the other hand, when the silicon glass layer 32 covering the leakage channel 33 is etched, the etching process of the silicon glass layer 32 has negligible effect on the leakage channel 33 compared with the etching process of the mask layer 40, which can ensure the performance and integrity of the leakage channel 33 and further improve the anti-hot spot risk ability of the battery.

[0137] An embodiment of the present application relates to a solar cell, and a specific circuit structure schematic diagram is shown in FIG. 5A 、 FIG. 5B and FIG. 10A 、 FIG. 10B The solar cell comprises a substrate 10, a first doped layer 20 covering a first surface of the substrate 10, a second doped layer 30 covering a second surface of the substrate 10 away from the first doped layer 20, and at least one leakage channel 33 located on a side wall of the substrate 10 and connecting the first doped layer 20 and the second doped layer 30.

[0138] The solar cell of the embodiment forms the leakage channel 33 connecting the first doped layer 20 and the second doped layer 30. Due to the design of the leakage channel 33, when part of the solar cell is shaded, the reverse voltage of the shaded part of the solar cell is reduced, thereby reducing the heating of the shaded part of the solar cell, solving the problem of hot spot effect of the solar cell, and improving the anti-hot spot risk ability of the solar cell.

[0139] In order to further consider the anti-hot spot risk ability of the solar cell and the stability of the solar cell, the leakage intensity of the solar cell of the embodiment is 1 mA / cm 2 to 10 mA / cm 2 . The total area of the leakage channel 33 is directly proportional to the leakage intensity of the solar cell, that is, the larger the total area of the leakage channel 33, the greater the leakage intensity of the solar cell. Therefore, by setting a reasonable width and length of the leakage channel 33, the rationality of the leakage intensity can be ensured, and the anti-hot spot risk ability of the solar cell and the stability of the solar cell can be considered.

[0140] An embodiment of the present application also relates to a photovoltaic module, comprising the solar cell of the above embodiment.

[0141] The photovoltaic module of the embodiment comprises the solar cell of the above embodiment, and when part of the solar cell is shaded, the reverse voltage of the shaded part of the solar cell is reduced due to the design of the leakage channel 33, so that the heating of the shaded part of the solar cell is reduced, the problem of hot spot effect of the photovoltaic module is solved, and the anti-hot spot risk ability of the photovoltaic module is improved.

[0142] Those skilled in the art can understand that the above embodiments are specific embodiments for implementing the present application, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the present application.

Claims

1. A method for preparing a battery, characterized in that, include: Provide a base; The substrate has a first surface and a second surface away from the first surface, and a first doped layer is formed on the first surface; A second doped layer is formed covering the second surface and the sidewalls of the substrate; At least one mask layer is formed on the second doped layer covering the sidewall; The second doped layer covering the sidewall is subjected to a first etching process to remove the portion of the second doped layer not covered by the mask layer, so that the second doped layer covered by the mask layer forms a leakage channel. The leakage channel connects the first doped layer and the second doped layer; The mask layer is then subjected to a second etching process to remove it.

2. The battery preparation method according to claim 1, characterized in that, The formation of the second doped layer covering the second surface and the sidewalls of the substrate includes: A polycrystalline silicon layer is formed covering the second surface and the sidewalls of the substrate; The polycrystalline silicon layer is doped to form a second doped layer and a silicon glass layer; the second doped layer covers the second surface and the sidewalls of the substrate, and the silicon glass layer covers the surface of the second doped layer away from the substrate; Before performing the first etching process on the second doped layer covering the sidewall, the method further includes: The silicon glass layer is subjected to a third etching process to remove the portion of the silicon glass layer not covered by the mask layer.

3. The battery preparation method according to claim 1, characterized in that, The first etching process involves using a hydrofluoric acid solution or a buffered oxide etching solution to remove the portion of the second doped layer not covered by the mask layer in the second doped layer covering the sidewall; the second etching process involves using an acetone solution to remove the mask layer.

4. The battery preparation method according to claim 2, characterized in that, The third etching process involves using a hydrofluoric acid solution to remove the portion of the silicon glass layer not covered by the mask layer.

5. The battery preparation method according to claim 2, characterized in that, The doping treatment was performed at a temperature of 850°C to 950°C for 10 to 60 minutes, with a phosphorus source concentration of 1 × 10⁻⁶. 19 Up to 1×10 21 atoms / cm3.

6. The battery preparation method according to any one of claims 1 to 5, characterized in that, The first doped layer and the second doped layer are of different types.

7. The battery preparation method according to claim 1, characterized in that, The width of the mask layer is 2 micrometers to 10 micrometers; the thickness of the mask layer is 0.2 micrometers to 20 micrometers. The material of the mask layer is any one of the following: silicon nitride, silicon oxide, titanium nitride, or photoresist.

8. A solar cell, characterized in that, include: Base; A first doped layer, the first doped layer covering a first surface of the substrate; A second doped layer covers a second surface of the substrate away from the first doped layer; At least one leakage channel is located on the sidewall of the substrate and the leakage channel connects the first doped layer and the second doped layer.

9. The solar cell according to claim 8, characterized in that, The leakage current of the solar cell is 1 mA / cm. 2 Up to 10 mA / cm 2 The larger the total area of ​​the leakage current channel, the greater the leakage current intensity of the solar cell.

10. A photovoltaic module, characterized in that, include: The solar cell according to claim 9.

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