Sintering method of solar cell

Abstract

The invention relates to the field of photovoltaic technology, and discloses a sintering method of a solar cell, which comprises the following steps of: applying voltage or current to two ends of a homo-polar auxiliary grid on the surface of a silicon substrate sample, controlling the applying time of the voltage or the current to be less than or equal to 120s, and controlling the absolute value of the applied voltage to be less than or equal to 30V (or the absolute value of the applied current to be less than or equal to 20A); according to the invention, a large amount of joule heat is generated on the auxiliary grid, and the joule heat is utilized to etch a non-conductive layer, such as a passivation layer, in the auxiliary grid region, so that the auxiliary grid is in contact with the conductive layer, and a good sintering effect of sintering a grid line region and not sintering a non-grid line region is realized. Moreover, according to the sintering method of the solar cell, mask alignment is not needed, and laser does not need to be used in a matched mode. Therefore, according to the sintering method of the solar cell, good contact of the metalized area is guaranteed, meanwhile, the damage and passivation attenuation effect of the non-metalized area is effectively avoided, the cell efficiency is improved, the process is simplified, and the cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of photovoltaic technology, and particularly relates to a sintering method of a solar cell. BACKGROUND

[0002] The metallization of the existing solar cell usually adopts a sintering process to realize the contact between the metal grid line and the carrier transport layer, but the high-temperature sintering process will cause damage to the internal structure of the solar cell, resulting in a loss of battery efficiency. For example, the TOPCon solar cell adopts an ultrathin tunnel oxide layer and a doped polysilicon layer as a passivation contact structure, and the passivation contact structure (i.e. the ultrathin tunnel oxide layer and the doped polysilicon layer) will have a large degree of attenuation under the condition of excessively high temperature. The existing sintering furnace device can only sinter the metal grid line area and the non-metal grid line area as a whole (i.e. without distinction between the metal grid line area and the non-metal grid line area), so that the passivation contact structure in the non-metal grid line area will have a large degree of attenuation after sintering, thereby reducing the battery efficiency.

[0003] For this purpose, the existing technology, as shown in CN119277840A, applies a bias voltage to the sub-grid and performs laser-assisted sintering treatment at the sub-grid to achieve the purpose of sintering. According to the description and the description of the drawings in the specification of CN119277840A, it can be known that the bias voltage applied in this technology is on the positive and negative grid lines of the cell piece, and the bias voltage is a reverse bias (the conductive support device carries the solar cell and is electrically connected with the back grid line of the solar cell; the probe is electrically connected with the sub-grid line on the front of the solar cell; and the laser-assisted sintering needs to be combined with the reverse bias), and also needs to be combined with the laser to generate a large number of photo-generated carriers to achieve auxiliary sintering (the principle is to use laser to generate a large number of photo-generated carriers at the grid line, and to separate the photo-generated carriers to form a large current by combining the reverse bias, so that a large amount of Joule heat is generated at the contact between the grid line and the cell, forming a sintering effect). Therefore, the implementation process of this technology is more complicated and the process is complex (for example, it needs to add a conductive support device structure, and the process of applying a bias voltage is more complicated. For example, it also needs to be combined with laser operation, and the laser and the bias voltage need to be adapted and debugged complicatedly), the sintering cost is high (for example, the conductive device needs to add a conductive support device structure, which increases the cost, and also needs to add a laser device, which further increases the cost), and the laser still causes damage.

[0004] Alternatively, the prior art, as shown in CN117637916A, uses a mask to perform temperature sintering on the battery piece. When sintering the metallized area of the battery piece to be sintered at high temperature, the non-metallized area of the battery piece to be sintered is sintered at low temperature. In this technology, the temperature sintering method is a mask method, which not only increases the mask process, but also makes it difficult to accurately align the mask, and also needs to be matched with a mask carrier, which is complex and has high sintering cost. Moreover, the non-metallized area will still be sintered (although the sintering temperature is reduced), which still has certain sintering damage, which is not conducive to the improvement of battery efficiency.

[0005] Therefore, how to effectively avoid the damage and passivation decay effect of the non-metallized area while ensuring good contact of the metallized area, and at the same time simplify the process and reduce the cost, is a technical problem that the technical personnel in the field need to solve at present. SUMMARY

[0006] The purpose of the present application is to overcome the shortcomings of the prior art and provide a sintering method for a solar cell.

[0007] Based on this, the present application discloses a sintering method for a solar cell, comprising the following steps:

[0008] Step 1, preparing a silicon substrate sample with a conductive layer and a passivation layer prepared on the surface in sequence;

[0009] Step 2, printing a subgrid on the surface of the silicon substrate sample and drying; wherein the surface of the silicon substrate sample is the front and / or back surface of the silicon substrate sample;

[0010] Step 3, applying voltage or current to both ends of the same polarity subgrid on the surface of the silicon substrate sample to generate Joule heat on the subgrid, and etching the passivation layer in the subgrid area by using the Joule heat to make the subgrid contact with the conductive layer; wherein the application time of voltage or current is ≤120s; the absolute value of the applied voltage is ≤30V, or the absolute value of the applied current is ≤20A.

[0011] Preferably, the conductive layers on the same surface of the silicon substrate sample are of the same conductive type, which is P-type or N-type;

[0012] In step 2, a plurality of same polarity subgrids are printed on the same surface of the silicon substrate sample and arranged at intervals.

[0013] Further preferably, in step 3, voltage or current is applied to both ends of each same polarity subgrid on the same surface of the silicon substrate sample to generate Joule heat on the subgrid.

[0014] Further preferably, in step 3, two conductive tools are pressed on both ends of each sub-grid of the same polarity respectively, and voltage or current is applied to the two conductive tools to generate Joule heat on the sub-grid; the two conductive tools are two conductive rods or two rows of probes.

[0015] Preferably, the conductive layers on the same surface of the silicon substrate sample are of the same conductive type, which is P-type or N-type.

[0016] In step 2, a plurality of sub-grids of the same polarity are printed on the same surface of the silicon substrate sample, and the plurality of sub-grids on the same surface of the silicon substrate sample are sequentially connected end to end to form a series of sub-grids.

[0017] In the present application, preferably, the conductive layers on the same surface of the silicon substrate sample are of the same conductive type, such as P-type or N-type; therefore, the sub-grids on the same surface of the silicon substrate sample are either all positive or all negative. Therefore, the voltage or current in step 3 of the present application is applied to the sub-grids of the same polarity on the surface of the silicon substrate sample (either applied to the negative sub-grids or applied to the positive sub-grids), and there is no positive or negative requirement for the applied voltage or current.

[0018] Further preferably, in step 3, voltage or current is applied to both ends of the series of sub-grids on the same surface of the silicon substrate sample to generate Joule heat on the series of sub-grids.

[0019] Further preferably, in step 3, two conductive tools are pressed on both ends of a series of sub-grids, and voltage or current is applied to the two conductive tools to generate Joule heat on the series of sub-grids; the two conductive tools are two conductive rods or two probes.

[0020] Further preferably, the material of the conductive tool is an alloy composed of one or more of tungsten, gold, silver, aluminum, and copper.

[0021] Preferably, in step 3, for the sub-grids of the same polarity on the same surface of the silicon substrate sample, the number of times of applying voltage or current is ≥1, and each time the applied voltage or current is one of constant, gradual, and sudden.

[0022] Preferably, before step 2, further comprising: printing a main grid on the surface of the silicon substrate sample and drying.

[0023] Alternatively, after step 3, further comprising: printing a main grid on the surface of the silicon substrate sample and drying.

[0024] Further preferably, a plurality of main grids of the same polarity are printed on the same surface of the silicon substrate sample and arranged at intervals, and the sub-grids of the same polarity on the same surface of the silicon substrate sample intersect with and are electrically connected to the main grids of the same polarity.

[0025] Compared with the prior art, the present application at least includes the following beneficial effects:

[0026] The sintering method of the solar cell of the present application applies voltage or current to both ends of the same polarity sub-grid on the surface of the silicon substrate sample, controls the amount and time of application of the voltage or current, generates a potential difference on the sub-grid, generates a large amount of Joule heat on the sub-grid, etches the non-conductive layer such as the passivation layer in the sub-grid area using the Joule heat, and further makes the sub-grid contact with the conductive layer, thereby achieving a better sintering effect of sintering the grid line area and not sintering the non-grid line area.

[0027] Furthermore, compared with the prior art such as CN119277840A (which requires that the bias voltage be applied to the positive and negative grid lines of the cell piece synchronously, and the bias voltage must be a reverse bias, and further needs to be combined with laser-assisted sintering), the sintering method of the present application applies voltage or current to the sub-grid of the same polarity in step 3, and the applied voltage or current has no positive and negative requirements, and further does not need to be used with laser; compared with the prior art such as CN117637916A (which needs to mask the non-metallized area), the sintering method of the present application also does not need to align the mask. Therefore, the sintering method of the present application, while simplifying the sintering process of the prior art such as CN119277840A and CN117637916A and reducing the sintering cost, can also achieve a better sintering effect of sintering the grid line area and not sintering the non-grid line area, thereby effectively avoiding damage to the non-metallized area and passivation decay while ensuring excellent contact in the metallized area, and further effectively avoiding efficiency loss of the cell in the sintering process, and improving the photoelectric conversion efficiency of the solar cell. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 Structure diagram of applying current to both ends of each sub-grid of a sintering method of a solar cell of embodiment 1.

[0029] Figure 2 Structure diagram of applying current to both ends of a series sub-grid of a sintering method of a solar cell of embodiment 2.

[0030] Explanation of reference numerals: silicon substrate sample 1; sub-grid 2; current application end one 21; current application end two 22; main grid 3. DETAILED DESCRIPTION

[0031] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0032] Embodiment 1

[0033] A sintering method of a solar cell in this embodiment, taking an N-type TOPCon solar cell as an example (of course, in addition to the TOPCon solar cell, this method can also be used to sinter the grid lines of other existing types of solar cells) Figure 1 , which comprises the following steps:

[0034] Step 1, print a plurality of main grids 3 on the back surface of the silicon substrate sample 1 with a pre-prepared conductive layer and a passivation layer, and dry.

[0035] In step 1, the plurality of main grids 3 on the back surface are arranged at intervals from each other. The preparation process of the silicon substrate sample 1 with a conductive layer and a passivation layer is referred to the preparation process before metallization of the existing N-type TOPCon solar cell, so it is not described in detail.

[0036] Step 2, continue to print a plurality of secondary grids 2 on the back surface of the silicon substrate sample 1, and dry.

[0037] In step 2, the plurality of secondary grids 2 on the back surface are also arranged at intervals from each other; and the secondary grids 2 on the back surface intersect (such as perpendicular intersect) with the main grids 3 on the back surface and are electrically connected (such as shown in the figure) with the main grids 3 on the back surface. Figure 1

[0038] In practice, the grid paste (such as main grid paste or secondary grid paste) is printed on the surface (such as the back surface or the front surface) of the silicon substrate sample 1 in a specific pattern, and the specific pattern formed on the surface of the silicon substrate sample 1 generally includes a plurality of linear lines, i.e. grid lines.

[0039] Step 3, after using a constant current source (i.e. a power supply providing a constant output current) to apply a current of 0.3 A to both ends of each secondary grid 2 on the back surface of the silicon substrate sample 1 for 10 s, and then continue to apply a current of 0.6 A for 3 s, a large amount of Joule heat is generated on the secondary grid 2 on the back surface, so as to etch away the back passivation layer in the area of the secondary grid 2 on the back surface by using the Joule heat, so as to make the secondary grid 2 on the back surface contact with the conductive layer on the back surface (for example, in the case of a TOPCon solar cell, the conductive layer on the back surface is the doped polysilicon layer of the passivation contact structure).

[0040] In this embodiment, the entire conductive layer on the back surface is of the same conductive type.

[0041] Step 4, print a plurality of main grids 3 on the front surface of the silicon substrate sample 1, and dry.

[0042] In step 4, the plurality of main grids 3 on the front surface are arranged at intervals from each other.

[0043] Step 5, continue to print a plurality of secondary grids 2 on the front surface of the silicon substrate sample 1, and dry.

[0044] ​In Step 5, the several busbars 2 on the front surface are also arranged at intervals from each other; and the busbars 2 on the front surface intersect (e.g., perpendicularly intersect) the main busbars 3 and are electrically connected (e.g., as shown) to the main busbars 3. Figure 1

[0045] The main busbars 3 and the busbars 2 of the solar cell of the present embodiment are both silver busbars. The number, polarity and distribution position on the silicon substrate sample 1 of the main busbars 3 and the busbars 2 of the solar cell of the present embodiment, and the silicon substrate sample 1 (including the passivation layer and the conductive layer thereon) used, etc. all refer to the existing N-type TOPCon solar cell, and thus are not described in detail.

[0046] In Step 6, the constant current source is used to apply a current of 0.3 A to both ends of each busbar 2 on the front surface of the silicon substrate sample 1 for 10 s, and a current of 0.6 A is continuously applied for 3 s, so as to generate a large amount of Joule heat in the busbars 2 on the front surface, and to etch away the front surface passivation layer in the busbar area on the front surface by using the Joule heat, so as to make the busbars 2 on the front surface contact the front surface conductive layer.

[0047] In the present embodiment, the conductive layer on the entire front surface is of the same conductive type, and the conductive type of the front surface conductive layer is opposite to that of the back surface conductive layer.

[0048] In Steps 3 and 6, two conductive rods or two rows of probes (e.g., two rows of silver probes) are respectively pressed on both ends of each busbar 2, and the two output terminals of the constant current source are respectively applied to the two conductive rods or two rows of probes, so as to generate a potential difference on the busbar 2 and make the current flow (e.g., as shown in the silicon substrate sample 1 on the same surface, the current application end one 21 and the current application end two 22 of each busbar are respectively applied by two rows of silver probes). Figure 1

[0049] After the above Steps 1-6, the existing other subsequent processes such as EL screening (electroluminescence screening), IV test (current-voltage characteristic test), etc. are continuously completed, and the solar cell of the present embodiment is obtained.

[0050] Embodiment 2

[0051] The sintering method of a solar cell of the present embodiment takes the N-type TOPCon solar cell as an example, and participates in Figure 2 , which includes the following steps:

[0052] Step 1, printing several busbars 2 on the back surface of the silicon substrate sample 1 with a pre-prepared conductive layer and passivation layer, and drying.

[0053] In Step 1, the several busbars 2 on the back surface are sequentially connected end to end to form a series busbar on the back surface of the silicon substrate sample 1.

[0054] ​​Step 2, use a constant current source to apply a current of 0.3A to both ends of the back surface series sub-grid for 10s, and continue to apply a current of 0.6A for 3s, so that the back surface series sub-grid generates a large amount of Joule heat, and the back surface passivation layer in the back surface series sub-grid area is etched away by using the Joule heat, so that the back surface series sub-grid is in contact with the back surface conductive layer (for example, in a TOPCon solar cell, the back surface conductive layer is the doped polysilicon layer of the passivation contact structure).

[0055] In this embodiment, the entire back surface conductive layer is of the same conductive type.

[0056] Step 3, print several main grids 3 on the back surface of the silicon substrate sample 1, and dry them.

[0057] In step 3, there are also multiple back surface main grids 3, which are distributed at intervals, and each back surface main grid 3 is electrically connected to the back surface series sub-grid; the back surface main grid 3 intersects (such as vertically intersects) with the sub-grid 2.

[0058] Step 4, print several sub-grids 2 on the front surface of the silicon substrate sample 1, and dry them.

[0059] In step 4, the several sub-grids 2 on the front surface are connected end to end in sequence to form a series sub-grid on the front surface of the silicon substrate sample 1.

[0060] Step 5, use a constant current source to apply a current of 0.3A to both ends of the front surface series sub-grid for 10s, and continue to apply a current of 0.6A for 3s, so that the front surface series sub-grid generates a large amount of Joule heat, and the front surface passivation layer in the front surface series sub-grid area is etched away by using the Joule heat, so that the front surface series sub-grid is in contact with the front surface conductive layer (for example, in a TOPCon solar cell, the back surface conductive layer is the doped polysilicon layer of the passivation contact structure).

[0061] In this embodiment, the entire front surface conductive layer is of the same conductive type, and the conductive type of the front surface conductive layer is opposite to that of the back surface conductive layer.

[0062] In steps 2 and 5, two conductive rods or two probes (such as two silver probes) are respectively pressed on both ends of a series sub-grid, and the two output ends of the constant current source are respectively applied to the two conductive rods or two probes, so that a potential difference is generated on the series sub-grid, and a current flows through (such as Figure 2 As shown in the silicon substrate sample 1, the current applying end one 21 and the current applying end two 22 of a series sub-grid on the same surface are respectively applied with a current through two rows of silver probes).

[0063] Step 6, print several main grids 3 on the front surface of the silicon substrate sample 1, and dry them.

[0064] In Step 6, the front main grid 3 also has multiple roots, and the multiple front main grids 3 are distributed at intervals, and each main grid 3 on the front is electrically connected with the front series sub-grid; the front main grid 3 intersects (such as vertically intersects) with the sub-grid 2.

[0065] In practice, the material, number, polarity and distribution position on the silicon substrate sample 1 of the main grid 3 and the sub-grid 2 of Example 2, and the silicon substrate sample 1 used (including the passivation layer and the conductive layer thereon) are consistent with Example 1.

[0066] After the above steps 1-6, the existing other subsequent processes such as EL screening and IV testing are continued to complete, and the solar cell of the embodiment is obtained.

[0067] Comparative Example 1

[0068] The sintering method of a solar cell of the present comparative example takes an N-type TOPCon solar cell as an example, which includes the following steps:

[0069] Step 1, print a plurality of main grids on the back of the silicon substrate sample with a pre-prepared conductive layer and passivation layer, and dry.

[0070] In Step 1, the plurality of main grids on the back are arranged at intervals.

[0071] Step 2, continue to print a plurality of sub-grids on the back of the silicon substrate sample, and dry.

[0072] In Step 2, the plurality of sub-grids on the back are also arranged at intervals; and the sub-grids on the back vertically intersect and are electrically connected with the main grids.

[0073] Step 3, print a plurality of main grids on the front of the silicon substrate sample, and dry.

[0074] In Step 3, the plurality of main grids on the front are arranged at intervals.

[0075] Step 4, continue to print a plurality of sub-grids on the front of the silicon substrate sample, and dry.

[0076] In Step 4, the plurality of sub-grids on the front are also arranged at intervals; and the sub-grids on the front vertically intersect and are electrically connected with the main grids.

[0077] Step 5, use a sintering furnace to sinter the entire silicon substrate sample treated in Step 4 at a high temperature (the peak sintering temperature is 720°C and the sintering time is 1 min), so that the back sub-grid is sintered through the back passivation layer to contact the back conductive layer, and the front sub-grid is sintered through the front passivation layer to contact the front conductive layer.

[0078] In the present comparative example, the conductive layer on the entire back surface is of the same conductive type; the conductive layer on the entire front surface is of the same conductive type, and the conductive type of the front conductive layer is opposite to that of the back conductive layer.

[0079] In practice, the material, number, polarity of the main grid and auxiliary grid of Comparative Example 1, the distribution position on the silicon substrate sample, and the silicon substrate sample used (including the passivation layer and conductive layer thereon) are consistent with those of Example 1.

[0080] After the above steps 1-5, the existing other subsequent processes such as EL screening and IV testing are continued to complete, and the solar cell of the present comparative example is obtained.

[0081] Performance test

[0082] The solar cell pieces of Examples 1-2 and Comparative Example 1 were respectively subjected to performance tests, and the test results are shown in Table 1:

[0083] Table 1

[0084] Experimental group Eta / % Voc / mV Isc / A FF / % Comparative example 1 26.45 742.3 14.319 83.31 Example 1 26.49 742.5 14.322 83.39 Example 2 26.48 742.4 14.320 83.36

[0085] As can be seen from Table 1, compared with the existing high-temperature sintering method using a sintering furnace, the fill factor (FF), short-circuit current (Isc), open-circuit voltage (Voc), and cell photoelectric conversion effect (referred to as cell efficiency, represented by Eta) of the solar cell piece prepared by the sintering method of Examples 1 and 2 of the present application are all improved.

[0086] In addition, compared with the prior art such as CN119277840A (which requires that the bias voltage be applied synchronously on the positive and negative grid lines of the cell piece, and the bias voltage must be a reverse bias, and also needs to be combined with laser-assisted sintering), the voltage or current of step 3 of the sintering method of Examples 1 and 2 of the present application is applied on the auxiliary grid of the same polarity, and the applied voltage or current has no positive and negative requirements, and also does not need to be used with laser; compared with the prior art such as CN117637916A (which needs to mask the non-metalized area), the sintering method of Examples 1 and 2 of the present application also does not need to mask the alignment. Therefore, the sintering method of Examples 1 and 2 of the present application achieves a better sintering effect of sintering the grid line area and not sintering the non-grid line area (the metalized area achieves excellent contact, and effectively avoids damage and passivation decay of the non-metalized area), improves the photoelectric conversion efficiency of the solar cell, and at the same time simplifies the sintering process of the prior art such as CN119277840A and CN117637916A, and reduces the sintering cost.

[0087] While the preferred embodiments of the application have been described, additional variations and modifications can be made to these embodiments by those skilled in the art once they have the benefit of the present disclosure. Therefore, the appended claims are intended to encompass all such variations and modifications as falling within the scope of the embodiments of the application.

[0088] The above describes the technical solutions provided by the present application in detail, and the principles and implementation manners of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, the specific implementation manners and application ranges can be changed according to the idea of the present application. In summary, the content of the present description should not be understood as a limitation of the present application.

Claims

1. A sintering method of a solar cell, characterized by, The method comprises the following steps: Step 1, preparing a silicon substrate sample with a conductive layer and a passivation layer on the surface in sequence; Step 2, printing a sub-grid on the surface of the silicon substrate sample, and drying; wherein the surface of the silicon substrate sample is the front surface and / or the back surface of the silicon substrate sample; Step 3, applying voltage or current to the two ends of the homopolar sub-grid on the surface of the silicon substrate sample to generate Joule heat on the sub-grid, etching the passivation layer in the sub-grid area by the Joule heat, and making the sub-grid contact with the conductive layer; wherein the application time of the voltage or current is less than or equal to 120 seconds; the absolute value of the applied voltage is less than or equal to 30V, or the absolute value of the applied current is less than or equal to 20A.

2. The sintering method of a solar cell according to claim 1, wherein The conductive layer on the same surface of the silicon substrate sample is of the same conductive type, which is P-type or N-type; In step 2, a plurality of homopolar sub-grids are printed on the same surface of the silicon substrate sample and arranged at intervals.

3. The sintering method of a solar cell according to claim 2, wherein In step 3, voltage or current is applied to the two ends of each homopolar sub-grid on the same surface of the silicon substrate sample to generate Joule heat on the sub-grid.

4. The sintering method of a solar cell according to claim 3, wherein In step 3, two conductive tools are pressed on the two ends of each homopolar sub-grid, and voltage or current is applied to the two conductive tools to generate Joule heat on the sub-grid; the two conductive tools are two conductive rods or two rows of probes.

5. The sintering method of a solar cell according to claim 1, wherein The conductive layer on the same surface of the silicon substrate sample is of the same conductive type, which is P-type or N-type; In step 2, a plurality of homopolar sub-grids are printed on the same surface of the silicon substrate sample and arranged at intervals.

6. The sintering method of a solar cell according to claim 5, wherein In step 3, voltage or current is applied to the two ends of each homopolar sub-grid on the same surface of the silicon substrate sample to generate Joule heat on the sub-grid.

7. The sintering method of a solar cell according to claim 6, wherein In step 3, two conductive tools are pressed on the two ends of each homopolar sub-grid, and voltage or current is applied to the two conductive tools to generate Joule heat on the sub-grid; the two conductive tools are two conductive rods or two rows of probes.

8. The sintering method of a solar cell according to claim 4 or 7, wherein The conductive tools are made of tungsten, gold, silver, aluminum, copper or an alloy composed of one or more of the above materials.

9. The sintering method of a solar cell according to claim 1, wherein In step 3, for the homopolar sub-grids on the same surface of the silicon substrate sample, the number of times of applying voltage or current is greater than or equal to 1, and each time the applied voltage or current is one of constant, gradual change and sudden change.

10. The sintering method of a solar cell according to claim 1, wherein Before step 2, it further comprises printing a main grid on the surface of the silicon substrate sample and drying; Or, after step 3, it further comprises printing a main grid on the surface of the silicon substrate sample and drying; A plurality of homopolar main grids are printed on the same surface of the silicon substrate sample and arranged at intervals, and the homopolar sub-grid on the same surface of the silicon substrate sample intersects with the homopolar main grid and is electrically connected.

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