Solar cell and method of manufacturing the same, stacked cell, photovoltaic module

Abstract

The application relates to a solar cell and a preparation method thereof, a laminated cell and a photovoltaic module. The preparation method comprises the following steps: providing a silicon wafer; performing laser scanning on the surface of the silicon wafer to form a plurality of grooves arranged at intervals and a plurality of pits distributed and superposed on the grooves; and performing wet etching treatment on the surface formed with the grooves and the pits to make the adjacent pits connected, form a plurality of distributed conical protrusions and obtain a textured structure. The preparation method can realize a multi-stage light trapping effect. The grooves can inhibit Fresnel reflection, and the pits can enhance wide-angle scattering. In combination with laser pre-ablation and wet etching, the distributed plurality of conical protrusions can guide light to the surface of other conical protrusions, extend the propagation path of light in the cell through multiple reflections, and effectively reduce the reflectivity of the cell surface.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, and in particular to solar cells and their preparation methods, tandem cells, and photovoltaic modules. Background Technology

[0002] The light-trapping structure of solar cells is one of the key technologies for improving their photoelectric conversion efficiency. The core principle is to optimize the surface or internal structure of the cell to reduce light reflection loss and extend the light propagation path within the active layer, thereby increasing photon absorption. Forming a pyramidal textured structure on the surface of solar cells is one of the most widely used light-trapping techniques. Its core involves constructing a micron-scale pyramid array on the cell surface to significantly reduce light reflection and extend the light propagation path inside the cell. Currently, alkaline etching is commonly used to prepare pyramidal textured structures. However, traditional alkaline texturing suffers from high reflectivity, typically exceeding 10%, which limits the improvement of photoelectric conversion efficiency. Summary of the Invention

[0003] Therefore, it is necessary to provide a solar cell and its preparation method, a tandem cell, and a photovoltaic module to reduce the surface reflectivity of the cell.

[0004] A method for preparing a solar cell includes the following steps:

[0005] Silicon wafers are supplied;

[0006] The surface of the silicon wafer is laser-scanned to form multiple trenches spaced apart and multiple pits distributed and superimposed on the trenches;

[0007] The surface with the grooves and pits is subjected to wet etching to connect adjacent pits, forming multiple distributed conical protrusions to obtain a textured surface.

[0008] In some embodiments, the trenches are formed using femtosecond laser scanning.

[0009] In some embodiments, the femtosecond laser has a wavelength of 900 nm to 1100 nm, a pulse width of 150 fs to 500 fs, and an energy density of 0.5 J / cm². 2 ~2J / cm 2 .

[0010] In some embodiments, the pit is formed using nanosecond laser scanning.

[0011] In some embodiments, the nanosecond laser has a wavelength of 266 nm to 532 nm, a pulse width of 5 ns to 20 ns, and an energy density of 1 J / cm² to 3 J / cm². 2 .

[0012] In some embodiments, the femtosecond laser and the nanosecond laser are coaxially scanned, and the scanning path is a spiral progressive path.

[0013] In some embodiments, the pulses of the femtosecond laser and the nanosecond laser are triggered alternately, and at the same position, the femtosecond laser scan is performed first, followed by the nanosecond laser scan.

[0014] In some embodiments, the distance between the centerlines of adjacent trenches is 300nm to 600nm, the width of the trench is 10nm to 50nm, and the depth is 50nm to 200nm.

[0015] In some embodiments, the opening width of the pit is 2μm to 5μm, and the depth is 0.5μm to 2μm.

[0016] In some embodiments, the number density of the pits is 1×102 4 pcs / cm 2 ~1×10 5 pcs / cm 2 .

[0017] In some embodiments, the wet etching process uses an etching solution containing at least one alkaline agent selected from potassium hydroxide, sodium hydroxide, tetramethylammonium hydroxide, and choline.

[0018] In some embodiments, the wet etching process takes 10 to 30 seconds.

[0019] In some embodiments, the height of the tapered protrusion is 150nm to 500nm.

[0020] In some embodiments, the bottom diameter of the conical protrusion is 40nm~100nm, and the top diameter is 8nm~20nm.

[0021] In some embodiments, the preparation method further includes the following steps:

[0022] A passivation layer is prepared on the textured structure. The passivation layer includes an aluminum oxide layer, an aluminum silicon oxide layer, and a silicon nitride layer stacked sequentially. The aluminum oxide layer is closer to the silicon wafer than the silicon nitride layer.

[0023] In some embodiments, the proportion of silicon atoms in the aluminum-silicon oxide layer gradually increases from the side closest to the aluminum oxide layer to the side closest to the silicon nitride layer.

[0024] In some embodiments, the thickness of the alumina layer is 5nm~20nm, the thickness of the aluminum silicon oxide layer is 2nm~3nm, and the thickness of the silicon nitride layer is 80nm~100nm.

[0025] A solar cell is prepared by the preparation method described in any of the above embodiments.

[0026] A tandem solar cell includes a bottom cell and a top cell disposed on the bottom cell, wherein the bottom cell is a solar cell prepared by the preparation method described in any of the above embodiments.

[0027] A photovoltaic module includes a first encapsulation component, a second encapsulation component, and a solar cell disposed between the first encapsulation component and the second encapsulation component, wherein the solar cell is a solar cell or a tandem cell as described in any of the above embodiments.

[0028] Compared with traditional methods, the above-mentioned solar cells, their fabrication methods, tandem cells, and photovoltaic modules have the following advantages:

[0029] The aforementioned method for fabricating solar cells utilizes laser scanning to form multiple trenches spaced apart and multiple pits superimposed on the trenches, achieving a multi-level light-trapping effect. Specifically, the spaced trenches suppress Fresnel reflection, while the pits enhance wide-angle scattering. Furthermore, combining laser pre-ablation and wet etching to form multiple distributed conical protrusions guides light to the surfaces of other conical protrusions, extending the light propagation path within the cell through multiple reflections, thereby effectively reducing the cell's surface reflectivity.

[0030] The bottom cell in the above-mentioned tandem battery is a solar cell prepared by the preparation method described in any of the above embodiments. The above-mentioned photovoltaic module includes the above-mentioned solar cell or tandem battery, and thus has the corresponding technical features and can obtain the corresponding beneficial effects. Attached Figure Description

[0031] Figure 1 A schematic diagram showing the formation of trenches and pits on a silicon wafer;

[0032] Figure 2 This is a schematic diagram of the passivation layer being formed on a silicon wafer.

[0033] Figure 3 This is a schematic diagram of the structure of a solar cell in Example 1;

[0034] Figure 4 This is a schematic diagram of the structure of a solar cell in Example 2;

[0035] Figure 5 This is a schematic diagram of the structure of a solar cell in Example 3;

[0036] Figure 6 This is a schematic diagram of the structure of a solar cell in Example 4;

[0037] Figure 7 This is a schematic diagram of the structure of a stacked battery according to one embodiment;

[0038] Figure 8 The image shows a SEM image of the velvety structure obtained by the preparation method in Example 1.

[0039] Figure 9 This is a SEM image of the velvety structure obtained by the preparation method in Example 1 from another perspective.

[0040] Explanation of reference numerals in the attached figures:

[0041] 11. Silicon wafer; 12. Trench; 13. Pits; 110. Silicon wafer; 120. Passivation layer; 121. Alumina layer; 122. Aluminum silicon oxide layer; 123. Silicon nitride layer; 200. Solar cell; 210. Silicon wafer; 211. First side; 220. Emitter; 230. Front passivation layer; 240. Front electrode; 212. Second side; 250. Back passivation layer; 260. Localized aluminum back field; 270. Back electrode; 300. Solar cell; 310. Silicon wafer; 311. First side; 320. Emitter; 330. Front passivation layer; 340. Front electrode; 312. Second side; 350. Tunneling layer; 360. Doped polycrystalline silicon layer; 370. Back passivation layer; 380. Back electrode; 400. Solar cell; 410. Silicon wafer; 411. One side; 420, First intrinsic amorphous silicon layer; 430, First doped silicon material layer; 440, First transparent conductive layer; 450, Front electrode; 412, Second side; 460, Second intrinsic amorphous silicon layer; 470, Second doped silicon material layer; 480, Second transparent conductive layer; 490, Back electrode; 500, Solar cell; 510, Silicon wafer; 511, First side; 520, Front passivation layer; 512, Second side; 530, N-type doped layer; 540, P-type doped layer; 550, Back passivation layer; 560, First electrode; 570, Second electrode; 600, Stacked cell; 610, Bottom cell; 620, Top cell; 621, Transparent conductive substrate; 622, Hole transport layer; 623, Perovskite light-absorbing layer; 624, Electron transport layer; 625, Top electrode. Detailed Implementation

[0042] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein; these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0043] It should be noted that when an element is referred to as being "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0044] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number or order of the indicated technical features.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0046] A method for preparing a solar cell according to an embodiment of the present invention includes the following steps:

[0047] Step S1: Provide a silicon wafer.

[0048] Step S2: Laser scanning is performed on the surface of the silicon wafer to form multiple trenches arranged at intervals and multiple pits distributed and superimposed on the trenches.

[0049] Step S3: Perform wet etching on the surface with grooves and pits to connect adjacent pits and form multiple distributed cone-shaped protrusions to obtain a textured surface structure.

[0050] Figure 1 The surface structure of a silicon wafer 11 after laser scanning is shown. The trenches 12 are strip-shaped groove structures arranged on the silicon wafer 11. In some examples, the characteristic dimensions of the trenches 12 (the width w of the trench, the depth, and the distance l between the centerlines of adjacent trenches 12) are in the range of 1 nm to 1000 nm. The pits 13 are dot-shaped recesses distributed on the silicon wafer 11. In some examples, the characteristic dimensions of the pits 13 (the opening width d and the depth) are in the range of 0.1 μm to 1000 μm.

[0051] The textured structure obtained by the above-mentioned method for preparing solar cells includes conical protrusions and grooves, with the grooves located between the conical protrusions.

[0052] The aforementioned method for fabricating solar cells utilizes laser scanning to form multiple trenches 12 spaced apart and multiple pits 13 distributed and superimposed on the trenches 12, achieving a multi-level light-trapping effect. Specifically, the spaced trenches 12 suppress Fresnel reflection, while the pits 13 enhance wide-angle scattering. Furthermore, by combining laser pre-ablation and wet etching, multiple distributed conical protrusions are formed, guiding light to the surfaces of other conical protrusions. Through multiple reflections, the propagation path of light within the cell is extended, effectively reducing the surface reflectivity of the cell.

[0053] The textured surface structure prepared by the above method can reduce the surface reflectivity of the battery to 1%~1.5%, which is significantly lower than that of traditional alkaline texturing methods (usually above 10%). This reflectivity can be obtained by full-band measurement using a UV-Vis spectrometer under AM1.5G conditions.

[0054] Optionally, in step S1, the silicon wafer 11 can be one or more of monocrystalline silicon and polycrystalline silicon. Optionally, the silicon wafer 11 can be N-type doped, such as phosphorus doped, arsenic doped, antimony doped, etc.; the silicon wafer 11 can also be P-type doped, such as boron doped, aluminum doped, gallium doped, indium doped, etc.

[0055] In some examples, in step S2, the trench 12 is formed using a femtosecond laser scanning method. Using a femtosecond laser facilitates the formation of nanoscale trenches.

[0056] In some examples, the wavelength of a femtosecond laser is 900 nm to 1100 nm. In other examples, the wavelength is 1000 nm to 1050 nm. The pulse width of a femtosecond laser is 150 fs to 500 fs, specifically 150 fs, 200 fs, 250 fs, 300 fs, 350 fs, 400 fs, 450 fs, and 500 fs. The energy density of a femtosecond laser is 0.5 J / cm². 2 ~2J / cm 2 For example, 0.5 J / cm 2 0.7J / cm 2 0.9J / cm 2 1.1 J / cm 2 1.3J / cm 2 1.5J / cm 2 1.7J / cm 2 1.9J / cm 2 In this example, by selecting the femtosecond laser parameters, a trench 12 that suppresses Fresnel reflection can be effectively formed on the silicon wafer 11, while minimizing thermal damage to the silicon wafer 11.

[0057] In some examples, the distance l between the centerlines of adjacent trenches 12 is 300nm to 600nm, specifically 300nm, 350nm, 400nm, 450nm, 500nm, 550nm, 600nm, etc. In some examples, the width w of the trench 12 is 10nm to 50nm, specifically 10nm, 20nm, 30nm, 40nm, 50nm, etc. In some examples, the depth of the trench 12 is 50nm to 200nm, specifically 50nm, 70nm, 80nm, 110nm, 130nm, 150nm, 170nm, 190nm, etc. In the above examples, by selecting the size parameters of the trench 12, a good effect of suppressing Fresnel reflection can be obtained. The size parameters of the trench 12 can be measured by electron microscopy analysis, specifically by software measurement using a scanning electron microscope at magnifications of 50,000 to 500,000.

[0058] In some examples, the trenches 12 extend along a first direction. Multiple trenches 12 are spaced apart along a second direction. In some examples, the first and second directions are perpendicular. In some examples, the distance l between the centerlines of adjacent trenches 12 is the same.

[0059] In some examples, in step S2, the pit 13 is formed using a nanosecond laser scan. Using a nanosecond laser facilitates the formation of micron-scale pit structures.

[0060] In some examples, the wavelength of a nanosecond laser is 266 nm to 532 nm. In other examples, the wavelength is 300 nm to 400 nm. The pulse width of a nanosecond laser is 5 ns to 20 ns, specifically 5 ns, 8 ns, 11 ns, 14 ns, 17 ns, 20 ns, etc. The energy density of a nanosecond laser is 1 J / cm² to 3 J / cm². 2 Specifically, these include 1 J / cm², 1.5 J / cm², 2 J / cm², 2.5 J / cm², and 3 J / cm². 2 In this example, by selecting nanosecond laser parameters, it is possible to effectively form a pit 13 that enhances wide-angle scattering on the silicon wafer 11, while minimizing thermal damage to the silicon wafer 11.

[0061] In some examples, the opening width d of the pit 13 is 2μm to 5μm, specifically one or more of the following dimensions: 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, etc. When the opening of the pit 13 is circular, the opening width is the same as the opening diameter. The depth of the pit 13 is 0.5μm to 2μm, specifically one or more of the following dimensions: 0.5μm, 0.7μm, 0.9μm, 1.1μm, 1.3μm, 1.5μm, 1.7μm, 1.9μm, etc. In this example, by selecting the size parameters of the pit 13, a good effect of enhancing wide-angle scattering can be obtained. The above size parameters of the pit 13 can be measured by electron microscopy analysis, specifically by software measurement using a scanning electron microscope at magnifications of 1,000 to 10,000.

[0062] In some examples, the number density of pit 13 is 1×10⁻⁶. 4 pcs / cm 2 ~1×10 5 pcs / cm 2 For example, 1×10 4 pcs / cm 2 1.1×10 4 pcs / cm 2 1.2×10 4 pcs / cm 2 1.3×10 4 pcs / cm 2 1.4×10 4 pcs / cm 2 1.5×10 4 pcs / cm 2 1.6×10 4 pcs / cm 2 1.7×10 4 pcs / cm 2 1.8×10 4 pcs / cm 2 1.9×10 4 pcs / cm 2 1×10 5 pcs / cm 2 The number density of pits 13 is controlled within the above range, which can effectively form a light-trapping effect and facilitate the subsequent formation of conical protrusions by wet etching. The number density of pits 13 can be measured by electron microscopy analysis, specifically, for example, by using a scanning electron microscope at a magnification of 10,000 to 50,000.

[0063] In some examples, femtosecond and nanosecond lasers are scanned coaxially with a spiral-progressive scanning path. "Coaxial scanning" means the beam propagation axes of the femtosecond and nanosecond lasers coincide, i.e., both laser beams are emitted from the same optical path. "Spiral-progressive path" means the laser beam's trajectory is a spiral, with the spiral radius gradually increasing. In some examples, the coaxial deviation between the femtosecond and nanosecond lasers is no greater than 5 μm, such as 0–4 μm. The radius expansion rate of the femtosecond and nanosecond lasers is 10 μm / revolution to 30 μm / revolution, the rotation speed is 5 rpm to 10 rpm, the scanning speed is 5 m / s to 10 m / s, and the initial radius R0 of the spiral path is 10 μm to 100 μm.

[0064] Furthermore, femtosecond and nanosecond laser pulses are triggered alternately. At the same location, femtosecond laser scanning is performed first, followed by nanosecond laser scanning.

[0065] The aforementioned laser scanning method enables control of the heat-affected zone and increases processing speed. Specifically, femtosecond lasers have unique cold processing characteristics. The energy deposition time of their ultrashort pulses (<500 fs) is much shorter than the lattice thermal diffusion time (e.g., the thermal diffusion time of silicon is about 1 ns), enabling non-thermal ablation. At the same time, the plasma cloud induced by the femtosecond laser reflects the energy of subsequent pulses, forming a plasma shielding effect and reducing heat accumulation on the silicon wafer 11.

[0066] Furthermore, femtosecond laser pretreatment creates nanoscale defects, such as vacancy clusters, on the material surface, significantly enhancing the absorption rate of the nanosecond laser. Data shows that with nanosecond laser treatment alone, the absorption rate is 35%, and the heat-affected zone depth reaches 800 nm. However, after femtosecond laser pretreatment, the absorption rate increases from 35% to 68%, and the heat-affected zone depth is only 150 nm. Moreover, the energy threshold is significantly reduced; the energy density required for nanosecond lasers is reduced by approximately 45%, from the conventional 3-5 J / cm². 2 Reduced to 1~3 J / cm 2 This can greatly reduce heat input and control the heat-affected zone.

[0067] By employing a coaxial helical scanning method using femtosecond and nanosecond lasers, the start-stop delay of traditional grating scanning can be eliminated. Furthermore, the alternating pulse triggering of the femtosecond and nanosecond lasers avoids plasma interference, further improving processing efficiency.

[0068] In some examples, the overlap rate of femtosecond laser scanning is 10% to 30%, specifically 10%, 15%, 20%, 25%, 30%, etc.

[0069] In some examples, the overlap rate of nanosecond laser scanning is 10% to 30%, specifically 10%, 15%, 20%, 25%, 30%, etc.

[0070] In some examples, in step S3, the wet etching process uses an etching solution containing at least one alkaline agent selected from potassium hydroxide (KOH), sodium hydroxide (NaOH), tetramethylammonium hydroxide (TMAH), and choline. In some examples, the etching solution includes potassium hydroxide at a mass concentration of 5% to 10%. In some examples, the etching solution includes sodium hydroxide at a mass concentration of 3% to 8%. In some examples, the etching solution includes tetramethylammonium hydroxide at a mass concentration of 1% to 3% and an oxidant at a mass concentration of 0.1% to 0.5%. In some examples, the etching solution includes potassium hydroxide at a mass concentration of 3% to 5% and isopropanol (IPA) at a mass concentration of 5% to 10%.

[0071] In some examples, the wet etching process takes 10 to 30 seconds, specifically 10 seconds, 15 seconds, 20 seconds, 25 seconds, 30 seconds, etc.

[0072] The above wet etching conditions can form a well-shaped cone-shaped protrusion structure.

[0073] In some examples, the height of the tapered protrusion is 200nm to 500nm. Further, the height of the tapered protrusion is 150nm to 400nm. In some specific examples, the height of the tapered protrusion is one or more of the following dimensions: 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm, etc.

[0074] In some examples, the bottom diameter of the conical protrusion is 40nm to 100nm. Further, the bottom diameter of the conical protrusion is 50nm to 80nm. In some specific examples, the bottom diameter of the conical protrusion is one or more of the following dimensions: 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, etc. In some examples, the top diameter of the conical protrusion is less than or equal to 20nm. Further, the top diameter of the conical protrusion is 8nm to 20nm. Further, the top diameter of the conical protrusion is 10nm to 15nm. In some specific examples, the top diameter of the conical protrusion is one or more of the following dimensions: 8nm, 10nm, 12nm, 14nm, 16nm, 18nm, 20nm, etc. The shape and size of the aforementioned conical protrusions can guide light to the surface of other conical protrusions, extending the light propagation path inside the battery through multiple reflections, effectively reducing reflectivity. The dimensional parameters of the above-mentioned conical protrusions can be measured by electron microscopy analysis, specifically by using a scanning electron microscope at magnifications of 50,000 to 500,000.

[0075] In some examples, the method for fabricating solar cells also includes the following steps:

[0076] Step S4: Prepare a passivation layer on the velvety structure.

[0077] like Figure 2 As shown, in some examples, the passivation layer 120 includes an aluminum oxide layer 121, an aluminum silicon oxide layer 122, and a silicon nitride layer 123 stacked sequentially. The aluminum oxide layer 121 is closer to the silicon wafer 110 than the silicon nitride layer 123.

[0078] The band gap of the aluminum silicon oxide layer 122 is between the aluminum oxide layer (band gap of about 6.5 eV) and the silicon nitride layer (band gap of about 5.1 eV). By setting the aluminum silicon oxide layer 122 between the aluminum oxide layer 121 and the silicon nitride layer 123, a gradient band structure is formed, which can reduce the transport barrier of charge carriers and increase the fixed charge density.

[0079] In some examples, the thickness ratio of the aluminum oxide layer 121 to the silicon nitride layer 123 is 1:(5~10), specifically 1:5, 1:6, 1:7, 1:8, 1:9, 1:10, etc.

[0080] In some examples, the thickness of the alumina layer 121 is 5nm to 20nm, specifically 6nm, 8nm, 10nm, 12nm, 14nm, 16nm, 18nm, 20nm, etc.

[0081] In some examples, the thickness of the silicon nitride layer 123 is 80nm~100nm, specifically 80nm, 83nm, 86nm, 89nm, 92nm, 95nm, 98nm, etc.

[0082] In some examples, the thickness of the aluminum silicon oxide layer 122 is 2nm to 3nm, specifically 2nm, 2.2nm, 2.4nm, 2.6nm, 2.8nm, 3nm, etc.

[0083] The thickness of each of the above layers can be measured using an ellipsometer.

[0084] In some examples, the Si atom content of the aluminum silicon oxide layer 122 gradually increases from the side closest to the aluminum oxide layer 121 to the side closest to the silicon nitride layer. This allows for a better formation of a gradient band structure, reduces the carrier transport barrier, increases the fixed charge density, and enhances interlayer bonding. In some examples, the Si atom content of the aluminum silicon oxide layer 122 near the aluminum oxide layer 121 is 3%–8%, and the Si atom content of the aluminum silicon oxide layer 122 near the silicon nitride layer 123 is 12%–20%. In some examples, the gradient rate of the Si atom content in the aluminum silicon oxide layer 122 is 2% / nm–5% / nm. These Si atom contents can be measured using atomic absorption spectrometry.

[0085] In some examples, the alumina layer 121, the aluminum silicon oxide layer 122, and the silicon nitride layer 123 are formed by continuous in-situ deposition using atomic layer deposition (ALD) technology, that is, the passivation layer 120 is deposited in the same reaction chamber.

[0086] The aluminum-silicon oxide layer 122 is grown in situ using a pulse sequence of aluminum source, silicon source, and reactive gas, with a process temperature of, for example, 150℃~250℃. The pulse duration is, for example, 30ms~100ms. By adjusting the content of aluminum source and silicon source in the process gas, the atomic ratio of each atom in the aluminum-silicon oxide layer 122 can be adjusted.

[0087] In some examples, the aluminum source includes TMAI (trimethylaluminum iodide), the silicon source includes silane (SiH4), and the oxidant includes O3. Compared to conventional processes that use TMA (trimethylaluminum) as the aluminum source and H2O as the oxidant, the above examples can effectively increase the fixed charge density of the passivation layer, with a fixed charge density of approximately 2 × 10⁻⁶. 12 cm -2 .

[0088] Compared to the traditional method of independently depositing alumina and silicon nitride, the above-mentioned passivation layer 120 fabrication process can avoid interfacial contamination between layers and reduce the risk of particulate contamination, reducing the number of contaminating particles from 50-100 per cm³ in traditional methods. 2 Reduced to 10 / cm 2 Within 2 nm. Furthermore, atomic layer deposition (ALD) processes utilize lower deposition temperatures, between 150°C and 250°C. This low-temperature, one-step deposition environment prevents the collapse of the conical protrusions. The height of the conical protrusions is reduced from over 10 nm using traditional methods to within 2 nm.

[0089] Traditional laser etching methods for fabricating textured surfaces suffer from high surface recombination rates in solar cells. The passivation techniques described above can reduce the surface recombination rate, which can be controlled within the range of 10 cm / s to 30 cm / s.

[0090] Optionally, the textured structure can be formed on one or both sides of the silicon wafer 11. That is, the textured structure can be formed only on the light-receiving side, only on the backlight side, or on both the light-receiving and backlight sides.

[0091] The aforementioned solar cells can be, for example, but not limited to, passivated emitter back contact cells (PERC cells), passivated emitter back contact cells (TOPCon cells), heterojunction cells (HJT cells), and back contact cells (BC cells).

[0092] like Figure 3As shown, the solar cell 200 in Example 1 is a PERC cell, which includes a silicon wafer 210; an emitter 220, a front passivation layer 230, and a front electrode 240 disposed on a first side 211 of the silicon wafer 210; and a back passivation layer 250, a local aluminum back field 260, and a back electrode 270 disposed on a second side 212 of the silicon wafer 210. At least one of the first side 211 and the second side 212 of the silicon wafer 210 is fabricated with the textured structure described above.

[0093] In the above example, the method for fabricating solar cell 200 further includes the following steps:

[0094] An emitter 220 is fabricated on the first side 211 of the silicon wafer 210;

[0095] A front passivation layer 230 is prepared on the emitter 220;

[0096] A front electrode 240 is fabricated on the front passivation layer 230;

[0097] A back passivation layer 250 is prepared on the second side 212 of the silicon wafer 210;

[0098] A local aluminum back field 260 is prepared on the back passivation layer 250;

[0099] A back electrode 270 is fabricated on a local aluminum back field 260.

[0100] like Figure 4 As shown, the solar cell 300 in Example 2 is a TOPCon cell, comprising: a silicon wafer 310; an emitter 320, a front passivation layer 330, and a front electrode 340 disposed on a first side 311 of the silicon wafer 310; and a tunneling layer 350, a doped polycrystalline silicon layer 360, a back passivation layer 370, and a back electrode 380 disposed on a second side 312 of the silicon wafer 310. At least one of the first side 311 and the second side 312 of the silicon wafer 310 is fabricated with the textured structure described above.

[0101] In the above example, the method for fabricating solar cell 300 further includes the following steps:

[0102] An emitter 320 is fabricated on the first side 311 of the silicon wafer 310;

[0103] A front passivation layer 330 is prepared on the emitter 320;

[0104] A front electrode 340 is fabricated on the front passivation layer 330;

[0105] A tunneling layer 350 is fabricated on the second side 312 of the silicon wafer 310;

[0106] A doped polycrystalline silicon layer 360 is prepared on the tunneling layer 350;

[0107] A back passivation layer 370 is prepared on the doped polycrystalline silicon layer 360;

[0108] A back electrode 380 is fabricated on the back passivation layer 370.

[0109] like Figure 5 As shown, the solar cell 400 in Example 3 is an HJT cell, comprising: a silicon wafer 410; a first intrinsic amorphous silicon layer 420, a first doped silicon material layer 430, a first transparent conductive layer 440, and a front electrode 450 disposed on a first side 411 of the silicon wafer 410; and a second intrinsic amorphous silicon layer 460, a second doped silicon material layer 470, a second transparent conductive layer 480, and a back electrode 490 disposed on a second side 412 of the silicon wafer 410. At least one of the first side 411 and the second side 412 of the silicon wafer 410 is fabricated with the textured structure described above.

[0110] In the above example, the method for fabricating solar cell 400 further includes the following steps:

[0111] A first intrinsic amorphous silicon layer 420 is formed on the first side 411 of the silicon wafer 410;

[0112] A first doped silicon material layer 430 is prepared on the first intrinsic amorphous silicon layer 420;

[0113] A first transparent conductive layer 440 is prepared on the first doped silicon material layer 430;

[0114] A front electrode 450 is fabricated on the first transparent conductive layer 440;

[0115] A second intrinsic amorphous silicon layer 460 is prepared on the second side 412 of the silicon wafer 410;

[0116] A second doped silicon material layer 470 is prepared on the second intrinsic amorphous silicon layer 460;

[0117] A second transparent conductive layer 480 is prepared on the second doped silicon material layer 470;

[0118] A back electrode 490 is fabricated on the second transparent conductive layer 480.

[0119] like Figure 6 As shown, the solar cell 500 in Example 4 is a BC cell, comprising: a silicon wafer 510; a front passivation layer 520 disposed on a first side 511 of the silicon wafer 510; an N-type doped layer 530, a P-type doped layer 540, a back passivation layer 550 disposed on a second side 512 of the silicon wafer 510; and a first electrode 560 connected to the N-type doped layer 530 and a second electrode 570 connected to the P-type doped layer 540. At least one of the first side 511 and the second side 512 of the silicon wafer 510 is fabricated with the textured structure described above.

[0120] In the above example, the method for fabricating solar cell 500 further includes the following steps:

[0121] A front passivation layer 520 is prepared on the first side 511 of the silicon wafer 510;

[0122] An N-type doped layer 530 and a P-type doped layer 540 are fabricated on the second side 512 of the silicon wafer 510;

[0123] A back passivation layer 550 is prepared on the N-type doped layer 530 and the P-type doped layer 540;

[0124] A first electrode 560 connected to an N-type doped layer 530 and a second electrode 570 connected to a P-type doped layer 540 are fabricated.

[0125] The trenches formed by this invention suppress Fresnel reflection, the pits enhance wide-angle scattering, and the conical protrusions achieve a gradient refractive index. The multi-level light trap structure results in a significantly lower reflectivity compared to traditional alkaline texturing methods. Furthermore, by combining laser pre-ablation and wet etching to form multiple distributed conical protrusions, light can be guided to the surface of other conical protrusions, extending the light propagation path inside the battery through multiple reflections, thereby effectively reducing the battery surface reflectivity.

[0126] Traditional alkaline texturing is unsuitable for polycrystalline silicon, but femtosecond laser pretreatment breaks through grain boundary limitations. The ultrafast processing characteristics of femtosecond lasers can indiscriminately process anisotropic regions of polycrystalline silicon. Ultraviolet-visible spectroscopy (AM1.5G) testing across the entire wavelength range shows that this invention can reduce reflectivity to below 1.5%, achieving a reflectivity of 1.3% for polycrystalline silicon, significantly lower than the 12.5% ​​of polycrystalline silicon texturized by traditional alkaline methods.

[0127] Traditional black silicon (RIE) technology suffers from chemical contamination risks and complex processes. Black silicon technology requires the use of toxic gases such as SF6, posing a high risk. This invention utilizes laser pre-construction to create micro / nano morphologies, significantly reducing the etching amount in wet etching. It allows for the use of 5%–10% KOH etching solutions for mild etching, minimizing the risk of chemical contamination. Furthermore, this approach eliminates the need for masks and vacuum equipment required by black silicon technology, simplifying the process. QSSPC minority carrier lifetime testing and EL imaging analysis show that, compared to black silicon technology, this invention achieves a significantly lower open-circuit voltage (V0.05). OC It can increase the voltage by 15mV and reduce the surface recombination rate from 50cm / s to 28cm / s.

[0128] Furthermore, the present invention also provides a solar cell, which is prepared by any of the preparation methods described above.

[0129] The aforementioned solar cells can be, for example, but not limited to, PERC cells, TOPCon cells, HJT cells, BC cells, etc.

[0130] like Figure 7 As shown, the present invention also provides a tandem solar cell 600, which includes a bottom cell 610 and a top cell 620 disposed on the bottom cell 610. The bottom cell 610 is a solar cell prepared by any of the methods described above.

[0131] The bottom cell 610 can be, for example, but not limited to, PERC cells, TOPCon cells, HJT cells, BC cells, etc. The top cell 620 can be, for example, but not limited to, perovskite cells, III-V compound cells (III-V compounds such as GaInP, AlGaAs, etc.), cadmium telluride (CdTe) cells, copper indium gallium selenide (CIGS) cells, organic solar cells, etc.

[0132] In some examples, the top cell 620 is a perovskite cell. Further, in some examples, the top cell 620 includes a transparent conductive substrate 621, a hole transport layer 622, a perovskite light-absorbing layer 623, an electron transport layer 624, and a top electrode 625, which are stacked sequentially.

[0133] Furthermore, the present invention also provides a photovoltaic module.

[0134] One embodiment of the photovoltaic module includes a first encapsulation component, a second encapsulation component, and a solar cell disposed between the first encapsulation component and the second encapsulation component. The solar cell is either a solar cell or a tandem solar cell as described above.

[0135] In some examples, the first encapsulation component includes an encapsulation panel and a first adhesive film disposed between the encapsulation panel and the battery cell. The material of the encapsulation panel is, for example, but not limited to, glass, organic polymers, etc. The first adhesive film is, for example, but not limited to, EVA film, POE film, etc.

[0136] In some examples, the second encapsulation component includes an encapsulation backplane and a second encapsulating film disposed between the encapsulation backplane and the battery cell. The material of the encapsulation backplane is, for example, but not limited to, glass, organic polymers, etc. The second encapsulating film is, for example, but not limited to, EVA film, POE film, etc.

[0137] The following specific embodiments further illustrate the present invention. These specific embodiments are provided to better understand the present invention, but are not intended to limit the scope of the invention and do not constitute a limitation on its content or protection.

[0138] Example 1

[0139] The method for fabricating the solar cell (TOPCon cell) provided in this embodiment includes the following steps:

[0140] Step 1: Provide a silicon wafer made of N-type doped monocrystalline silicon. The resistivity of the silicon wafer is approximately 2 Ω·cm, and the thickness is 180 ± 5 μm. After RCA standard cleaning, the silicon wafer is rinsed with a 1% HF solution for 30 seconds to remove the native oxide layer.

[0141] Step 2: A Yb:KGW femtosecond laser (a femtosecond laser with potassium gadolinium tungstate crystal as the gain medium) is used to perform femtosecond laser scanning on the silicon wafer to form trenches. The femtosecond laser has a wavelength of 1030 nm, a pulse width of 350 fs, and an energy density of 1.2 J / cm². 2 The femtosecond laser scanning path is a helical progression. The femtosecond laser radius expansion rate is 18 μm / revolution, the scanning speed is 8 m / s, and the initial radius R0 of the helical path is 25 μm. The overlap ratio of the femtosecond laser is 20%. SEM analysis shows that the distance between the centerlines of adjacent trenches is 380 ± 15 nm, the width is 30 nm ± 5 nm, and the depth is 110 ± 10 nm.

[0142] Step 3: A Q-switched Nd:YAG laser (using Q-switching technology and neodymium-doped yttrium aluminum garnet as the gain medium) is used to perform nanosecond laser scanning on the silicon wafer, forming multiple pits superimposed on the trenches. The nanosecond laser has a wavelength of 355 nm, a pulse width of 12 ns, and an energy density of 2.3 J / cm². 2 The laser's radius expansion rate was 18 μm / revolution, the scanning speed was 8 m / s, and the initial radius R0 of the helical path was 25 μm. SEM analysis showed a pit number density of 6.5 × 10⁻⁶. 4 pcs / cm 2 The pit has an opening width of 3.2±0.3μm and a depth of 1.4±0.2μm.

[0143] Step 4: Wet etching is performed on the surface with grooves and pits using an etching solution containing 7% KOH and 5% IPA for 22 seconds. Figure 8 and Figure 9 As shown, wet etching creates multiple distributed conical bumps, resulting in a textured surface on both sides of the silicon wafer. SEM analysis revealed that the height of the conical bumps is 320±25 nm, the bottom diameter is 65±8 nm, and the top diameter is 14±3 nm. Full-band UV-Vis spectroscopy at AM1.5G conditions yielded a silicon wafer surface reflectance of 1.2%.

[0144] Step 5: Boron diffusion is performed on the front side of the silicon wafer to form an emitter with a thickness of approximately 500 nm.

[0145] Step 6: A tunneling layer with a thickness of 2nm is formed on the back side of the silicon wafer by thermal oxidation.

[0146] Step 7: A phosphorus-doped polycrystalline silicon layer with a thickness of 150 nm is prepared on the tunneling layer using the PECVD process.

[0147] Step 8: A passivation layer is fabricated on the emitter and doped polycrystalline silicon layer using atomic layer deposition (ALD). The passivation layer comprises an aluminum oxide layer, an aluminum silicon oxide layer, and a silicon nitride layer stacked sequentially. The aluminum source is TMAI, the silicon source is silane, the oxidant is O3, and the nitrogen source is NH3. The deposition temperature is 180℃. The Si atom content of the aluminum silicon oxide layer gradually increases from the side closest to the aluminum oxide layer to the side closest to the silicon nitride layer. The Si atom content of the aluminum silicon oxide layer near the aluminum oxide layer is 5%. The Si atom content of the aluminum silicon oxide layer near the silicon nitride layer is 15%. The thickness of the aluminum oxide layer is 12 nm. The thickness of the aluminum silicon oxide layer is 2.4 nm. The thickness of the silicon nitride layer is 92 nm.

[0148] Step 9: Print silver paste on the passivation layer on the back side and sinter to form the back electrode.

[0149] Step 10: Print silver paste on the passivation layer on the front side and sinter to form the front electrode.

[0150] Example 2

[0151] The method for preparing the tandem battery provided in this embodiment includes the following steps:

[0152] Steps 1-9 are the same as steps 1-9 in Example 1, to obtain the bottom cell.

[0153] Step 10: Perform ozone cleaning on the bottom battery for 10 minutes to remove organic residues; then perform UV-ozone treatment for 5 minutes to enhance surface hydrophilicity.

[0154] Step 11: ITO is deposited on the textured surface using magnetron sputtering to form a transparent conductive substrate with a thickness of 80 nm.

[0155] Step 12: A dense nickel oxide layer is deposited on the first conductive layer using magnetron sputtering, and then annealed at 180°C for 30 minutes to form a hole transport layer with a thickness of 15 nm.

[0156] Step 13: Drop the perovskite precursor solution onto the surface of the hole transport layer described above, and spin-coat at 4000 rpm for 3 seconds. The perovskite precursor solution contains the perovskite material FA. 0.8 Cs 0.2 Pb(I 0.8 Br 0.2)3 and a mixed solvent of DMF and DMSO in a volume ratio of 4:1. Annealed at 100°C for 10 min to form a perovskite light-absorbing layer with a thickness of 450 nm.

[0157] Step 14: After forming the perovskite light absorption layer, the device is cooled to room temperature. A PCBM solution with a concentration of 20 mg / mL is coated onto the perovskite light absorption layer. The solution is spin-coated at 1000 rpm for 40 s and annealed at 80 °C for 10 min to form an electron transport layer with a thickness of 40 nm.

[0158] Step 15: ITO is deposited on the electron transport layer using magnetron sputtering to obtain a transparent conductive layer with a thickness of 100 nm.

[0159] Step 16: Silver paste is printed on the transparent conductive layer using screen printing technology, and then sintered to form the front electrode, thus obtaining the tandem battery.

[0160] Comparative Example 1

[0161] The method for preparing the solar cell in this comparative example includes the following steps:

[0162] Step 1 is the same as Step 1 in Example 1.

[0163] Step 2: Wet etching is performed on the surface of the silicon wafer using an etching solution containing 7% KOH and 5% IPA for 30 seconds to form a pyramid textured structure with a base size of 1μm~3μm and a height of 0.8μm~1.8μm.

[0164] Steps 3-8 are the same as steps 5-10 in Example 1.

[0165] Comparative Example 2

[0166] The fabrication method of the tandem solar cell in this comparative example includes the following steps:

[0167] Step 1 is the same as Step 1 in Example 1.

[0168] Step 2: Wet etching is performed on the surface of the silicon wafer using an etching solution containing 7% KOH and 5% IPA for 30 seconds to form a pyramid textured structure with a base size of 1μm~3μm and a height of 0.8μm~1.8μm.

[0169] Steps 3-7 are the same as steps 5-9 in Example 1.

[0170] Steps 8-14 are the same as steps 10-16 in Example 2.

[0171] The performance of the solar cells and tandem cells prepared in the above embodiments and comparative examples was tested, and the test results are shown in Table 1.

[0172] Table 1

[0173]

[0174] In Table 1, in the short-circuit current density results a / b for Example 2 and Comparative Example 2, a represents the contribution value of the top cell, and b represents the contribution value of the top cell.

[0175] As shown in Table 1, Example 1, compared to Comparative Example 1, and Example 2, compared to Comparative Example 2, generally exhibits improved electrical performance parameters such as short-circuit current density, open-circuit voltage, and photoelectric conversion efficiency. This is attributed to the formation of trenches and conical protrusions on the silicon wafer in Examples 1 and 2, creating a micro-nano composite structure that achieves a multi-level light-trapping effect. Compared to Comparative Examples 1 and 2, the textured structures prepared in Examples 1 and 2 can more effectively reduce the light reflectivity of the battery surface, improve light energy utilization, and thus enhance battery performance.

[0176] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0177] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for preparing a solar cell, characterized in that, Includes the following steps: Silicon wafers are supplied; The surface of the silicon wafer is laser-scanned to form multiple trenches spaced apart and multiple pits distributed and superimposed on the trenches; The surface with the grooves and pits is subjected to wet etching to connect adjacent pits, forming multiple distributed conical protrusions to obtain a textured surface.

2. The method for preparing a solar cell as described in claim 1, characterized in that, The trenches were formed using femtosecond laser scanning.

3. The method for preparing a solar cell as described in claim 2, characterized in that, The femtosecond laser has a wavelength of 900 nm to 1100 nm, a pulse width of 150 fs to 500 fs, and an energy density of 0.5 J / cm². 2 ~2J / cm 2 .

4. The method for preparing a solar cell as described in claim 1, characterized in that, The pit was formed using nanosecond laser scanning.

5. The method for preparing a solar cell as described in claim 4, characterized in that, The nanosecond laser has a wavelength of 266nm~532nm, a pulse width of 5ns~20ns, and an energy density of 1J / cm²~3J / cm². 2 .

6. The method for preparing a solar cell as described in claim 4, characterized in that, The groove is formed using femtosecond laser scanning, with the femtosecond laser and the nanosecond laser scanning in a coaxial manner and the scanning path being a spiral progressive path.

7. The method for preparing a solar cell as described in claim 6, characterized in that, The femtosecond laser and the nanosecond laser are triggered alternately by pulses, and at the same position, the femtosecond laser scan is performed first, followed by the nanosecond laser scan.

8. The method for preparing a solar cell according to any one of claims 1 to 7, characterized in that, The method for preparing the solar cell meets at least one of the following characteristics (1) to (3): (1) The distance between the center lines of the adjacent trenches is 300nm~600nm, the width of the trench is 10nm~50nm, and the depth is 50nm~200nm; (2) The opening width of the pit is 2μm~5μm and the depth is 0.5μm~2μm; (3) The number density of the pits is 1×10 4 pcs / cm 2 ~1×10 5 pcs / cm 2 .

9. The method for preparing a solar cell according to any one of claims 1 to 7, characterized in that, The method for preparing the solar cell meets at least one of the following characteristics (1) to (2): (1) The etching solution used in the wet etching process contains at least one alkaline agent selected from potassium hydroxide, sodium hydroxide, tetramethylammonium hydroxide and choline; (2) The wet etching process takes 10s to 30s.

10. The method for preparing a solar cell according to any one of claims 1 to 7, characterized in that, The method for preparing the solar cell meets at least one of the following characteristics (1) to (2): (1) The height of the conical protrusion is 150nm~500nm; (2) The bottom diameter of the conical protrusion is 40nm~100nm and the top diameter is 8nm~20nm.

11. The method for preparing a solar cell according to any one of claims 1 to 7, characterized in that, The preparation method further includes the following steps: A passivation layer is prepared on the textured structure. The passivation layer includes an aluminum oxide layer, an aluminum silicon oxide layer, and a silicon nitride layer stacked sequentially. The aluminum oxide layer is closer to the silicon wafer than the silicon nitride layer.

12. The method for preparing a solar cell as described in claim 11, characterized in that, The method for preparing the solar cell meets at least one of the following characteristics (1) to (2): (1) The proportion of silicon atoms in the aluminum-silicon oxide layer gradually increases from the side closest to the aluminum oxide layer to the side closest to the silicon nitride layer; (2) The thickness of the alumina layer is 5nm~20nm, the thickness of the aluminum silicon oxide layer is 2nm~3nm, and the thickness of the silicon nitride layer is 80nm~100nm.

13. A solar cell, characterized in that, It is prepared by the preparation method according to any one of claims 1 to 12.

14. A stacked battery, characterized in that, It includes a bottom cell and a top cell disposed on the bottom cell, wherein the bottom cell is a solar cell prepared by the preparation method according to any one of claims 1 to 12.

15. A photovoltaic module, characterized in that, It includes a first encapsulation component, a second encapsulation component, and a battery cell disposed between the first encapsulation component and the second encapsulation component, wherein the battery cell is the solar cell of claim 13 or the tandem battery of claim 14.

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