Crystalline silicon solar cell and preparation method thereof

Abstract

The invention discloses a crystalline silicon solar cell and a preparation method thereof. The crystalline silicon solar cell comprises a cell substrate, the back surface of the cell substrate is divided into a plurality of finger-shaped P-type conductive regions and a plurality of finger-shaped N-type conductive regions which are arranged in a finger-crossed manner, and an isolation region is arranged between the adjacent finger-shaped P-type conductive region and the adjacent finger-shaped N-type conductive region; a first seed transport layer disposed on the finger-shaped P-type conductive region; a second seed transport layer disposed on the finger-shaped N-type conductive region; the anti-reflection passivation layer covers the finger-shaped P-type conductive region, the finger-shaped N-type conductive region, the first seed transmission layer, the second seed transmission layer and the isolation region; the first main gate penetrates through the anti-reflection passivation layer and is electrically connected with the first seed transmission layer; and the second main grid penetrates through the anti-reflection passivation layer and is electrically connected with the second seed transmission layer, and the conduction types of the first main grid and the second main grid are opposite. The crystalline silicon solar cell omits insulating glue or an insulating layer, so that the reliability of the crystalline silicon solar cell is effectively improved, and the short-circuit risk of the crystalline silicon solar cell can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to a crystalline silicon solar cell and a preparation method thereof. BACKGROUND

[0002] For the crystalline silicon solar cell with full back electrode structure, the grid lines (fine grid lines and main grid lines) are arranged on the back surface of the crystalline silicon solar cell, which is beneficial to improve the light utilization rate of the crystalline silicon solar cell. Since the positive fine grid lines and the negative fine grid lines are arranged in a finger-crossing manner on the back surface of the crystalline silicon solar cell, an insulating glue or an insulating layer is generally arranged on the electrode grid lines to avoid the contact between the solder strip connected with the positive grid lines and the negative grid lines, and the contact between the solder strip connected with the negative grid lines and the positive grid lines.

[0003] The existing crystalline silicon solar cell with the insulating glue or the insulating layer arranged thereon will cause the contact reliability between the solder strip and the electrode grid lines to be reduced, and the insulating glue or the insulating layer will have a risk of insulation failure, thereby causing the crystalline silicon solar cell to be short-circuited. SUMMARY

[0004] Therefore, the present application provides a crystalline silicon solar cell and a preparation method thereof, which omits the arrangement of the insulating glue or the insulating layer on the electrode grid lines, so as to effectively improve the contact reliability between the solder strip and the electrode grid lines and reduce the short-circuit risk of the crystalline silicon solar cell.

[0005] Specifically, the present application provides the following technical solutions:

[0006] In a first aspect, the present application provides a crystalline silicon solar cell, comprising:

[0007] a cell substrate, wherein the back surface of the cell substrate is divided into a plurality of finger-shaped P-type conductive regions and a plurality of finger-shaped N-type conductive regions arranged in a finger-crossing manner, and an isolation region is arranged between adjacent finger-shaped P-type conductive regions and finger-shaped N-type conductive regions;

[0008] a first seed transport layer arranged on each of the finger-shaped P-type conductive regions;

[0009] a second seed transport layer arranged on each of the finger-shaped N-type conductive regions;

[0010] an anti-reflection passivation layer covering the finger-shaped P-type conductive regions, the finger-shaped N-type conductive regions, the first seed transport layer and the second seed transport layer;

[0011] The main grid comprises: a first main grid arranged on the anti-reflection passivation layer and electrically connected with the first seed transport layer through the anti-reflection passivation layer in the thickness direction; and a second main grid arranged on the anti-reflection passivation layer and electrically connected with the second seed transport layer through the anti-reflection passivation layer in the thickness direction, the first main grid and the second main grid being opposite in conductive type.

[0012] In a second aspect, the embodiment of the present application provides a preparation method of a crystalline silicon solar cell, comprising:

[0013] Step 1: providing a cell substrate, wherein the back surface of the cell substrate is divided into a plurality of finger-shaped P-type conductive regions and a plurality of finger-shaped N-type conductive regions arranged in a finger cross pattern;

[0014] Step 2: forming a first seed transport layer in each of the finger-shaped P-type conductive regions and a second seed transport layer in each of the finger-shaped N-type conductive regions;

[0015] Step 3: forming an anti-reflection passivation layer outside the finger-shaped P-type conductive regions, the finger-shaped N-type conductive regions, the first seed transport layer and the second seed transport layer;

[0016] Step 4: printing a burn-through type main grid paste corresponding to the first seed transport layer and the second seed transport layer respectively outside the anti-reflection passivation layer, and sintering to form a first main grid penetrating through the anti-reflection passivation layer and electrically connected with the first seed transport layer, and a second main grid penetrating through the anti-reflection passivation layer and electrically connected with the second seed transport layer.

[0017] The technical solution of the first aspect of the above-mentioned application has the following advantages or beneficial effects:

[0018] The crystalline silicon solar cell provided by the embodiment of the present application covers the finger-shaped P-type conductive regions, the finger-shaped N-type conductive regions, the first seed transport layer and the second seed transport layer by the anti-reflection passivation layer, the first seed transport layer and the second seed transport layer are arranged below the anti-reflection passivation layer, and then the burn-through type main grid is arranged above the anti-reflection passivation layer, so that the anti-reflection passivation layer can isolate the second seed transport layer from the first main grid electrically connected with the first seed transport layer, and the anti-reflection passivation layer can also isolate the first seed transport layer from the second main grid electrically connected with the second seed transport layer, thereby avoiding the isolation of the main grid and the fine grid without the anti-reflection passivation film in the prior art, and the need to set the insulating glue or insulating layer at the end of the fine grid line when connecting, so as to avoid the influence of the insulating glue or insulating layer on the electrical connection between the solder strip and the main grid line, thereby effectively improving the contact reliability of the solder strip and the electrode grid line, and reducing the short circuit risk of the crystalline silicon solar cell due to the aging of the insulating glue or insulating layer.

[0019] Further, compared with the existing crystalline silicon solar cell, the crystalline silicon solar cell provided by the embodiment of the present application can make the structure of the crystalline silicon solar cell simpler by omitting the insulating glue or the insulating layer, facilitate industrialized production, and effectively reduce the cost of the crystalline silicon solar cell. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 is a back structure schematic diagram of a crystalline silicon solar cell according to the prior art;

[0021] Figure 2 is a partial section structure schematic diagram of a crystalline silicon solar cell according to the prior art;

[0022] Figure 3A is a back structure schematic diagram of a first structure of a crystalline silicon solar cell provided by the embodiment of the present application;

[0023] Figure 3B is a back structure schematic diagram of a second structure of a crystalline silicon solar cell provided by the embodiment of the present application;

[0024] Figure 4A is a partial structure schematic diagram of a B-B section of the first structure of the crystalline silicon solar cell provided by the embodiment of the present application corresponding to Figure 3A ;

[0025] Figure 4B is a partial structure schematic diagram of a B'-B' section of the first structure of the crystalline silicon solar cell provided by the embodiment of the present application corresponding to Figure 3B ;

[0026] Figure 5 is a partial structure schematic diagram of a C-C section of the first structure of the crystalline silicon solar cell provided by the embodiment of the present application corresponding to Figure 3A or a C'-C' section of the second structure of the crystalline silicon solar cell provided by the embodiment of the present application corresponding to Figure 3B ;

[0027] Figure 6 is a partial structure schematic diagram of a D-D section of the first structure of the crystalline silicon solar cell provided by the embodiment of the present application corresponding to Figure 3A or a D'-D' section of the second structure of the crystalline silicon solar cell provided by the embodiment of the present application corresponding to Figure 3B ;

[0028] Figure 7 is a back structure schematic diagram of the crystalline silicon solar cell before a reflection-reducing layer 30 is arranged in the crystalline silicon solar cell provided by the embodiment of the present application;

[0029] Figure 8 is a main flow schematic diagram of a preparation method of the crystalline silicon solar cell provided by the embodiment of the present application;

[0030] Figure 9 is a structural change schematic diagram corresponding to steps SP1 to SP5 in the first preparation method of the crystalline silicon solar cell provided by the embodiment of the present application;

[0031] Figure 10 is a structural change schematic diagram corresponding to steps SP6 to SP8 in the first preparation method of the crystalline silicon solar cell provided by the embodiment of the present application;

[0032] Figure 11 is a structural change schematic diagram corresponding to steps SP9 to SP11 in the first preparation method of the crystalline silicon solar cell provided by the embodiment of the present application;

[0033] Figure 12 is a structural change schematic diagram corresponding to steps SP12 to SP14 in the first preparation method of the crystalline silicon solar cell provided by the embodiment of the present application;

[0034] Figure 13 is a structural change schematic diagram corresponding to steps SP15 and SP16 in the first preparation method of the crystalline silicon solar cell provided by the embodiment of the present application;

[0035] Figure 14 is a structural change schematic diagram corresponding to step SP17 in the first preparation method of the crystalline silicon solar cell provided by the embodiment of the present application;

[0036] Figure 15 is a structural change schematic diagram corresponding to step SP18 in the first preparation method of the crystalline silicon solar cell provided by the embodiment of the present application;

[0037] Figure 16 is a structural change schematic diagram corresponding to steps SP12' to SP16' in the second preparation method of the crystalline silicon solar cell provided by the embodiment of the present application.

[0038] The reference signs are as follows:

[0039] 10 - cell substrate; 11 - P-type finger conductive region; 111 - first edge; 12 - N-type finger conductive region; 121 - second edge; 13 - isolation region; 14 - crystalline silicon substrate; 15 - first carrier collecting layer; 151 - P-type doped diffusion layer; 151' - first wrap-around layer; 152 - second tunneling passivation layer; 153 - P-type doped polysilicon layer; 154 - first borosilicate glass layer; 154' - second wrap-around layer; 155 - second borosilicate glass layer; 155' - fifth wrap-around layer; 155'' - borophosphosilicate glass layer; 155''' - seventh wrap-around layer; 16 - second carrier collecting layer; 161 - third tunneling passivation layer; 162 - N-type doped polysilicon layer; 162' - phosphosilicate glass layer; 17 - tunneling passivation layer; 17' - third wrap-around layer; 18 - intrinsic polysilicon layer; 18' - fourth wrap-around layer; 18'' - sixth wrap-around layer; 19 - silicon nitride mask; 21 - first seed transport layer; 211 - first branch seed layer; 212 - first busbar seed layer; 21' - positive electrode fine grid line; 22 - second seed transport layer; 22' - negative electrode fine grid line; 221 - second branch seed layer; 222 - second busbar seed layer; 30 - anti-reflective passivation layer; 41 - first main grid; 41' - positive electrode main grid; 42 - second main grid; 42' - negative electrode main grid; 50 - extended grid line segment; 60 - soldering point; 70 - front passivation layer; 80 - insulating glue; 90 - mask. DETAILED DESCRIPTION

[0040] It is found that, for the existing crystalline silicon solar cell with full back electrode structure, for example, in the existing crystalline silicon solar cell, as shown in Figure 1 and Figure 2 , generally, a P-type finger conductive region 11 and an N-type finger conductive region 12 are formed on a crystalline silicon substrate 14, the P-type finger conductive region 11 and the N-type finger conductive region 12 can be used for collecting carriers, and the structure thereof can be different according to different cell types. For example, as shown in Figure 2 , it corresponds to Figure 1The cross-sectional structure diagram of A-A of the structure. Exemplarily, for the back junction passivated contact solar cell of N-type crystalline silicon substrate, the finger-shaped P-type conductive region 11 can be stacked with the P-type doped diffusion layer 151 and the anti-reflection passivation layer 30 from inside to outside; the finger-shaped N-type conductive region 12 can be stacked with the third tunneling passivation layer 161, the N-type doped polysilicon layer 162 and the anti-reflection passivation layer 30 from inside to outside, the positive fine grid line 21' is electrically connected with the P-type doped diffusion layer 151 after burning through the anti-reflection passivation layer 30, the negative fine grid line 22' is electrically connected with the N-type doped polysilicon layer 162 after burning through the anti-reflection passivation layer 30, and a front passivation layer can be formed on the front of the cell. Even if the sintering process is accurately controlled, the positive fine grid line 21' and the negative fine grid line 22' form stable contact with the doped layer, and the positive fine grid line 21' and the negative fine grid line 22' will have the problem of high contact resistance. In addition, the positive main grid 41' and the negative main grid 42' are formed by printing and curing non-burn-through type paste, the contact area of the positive main grid 41' with the positive fine grid line 21' and the contact area of the negative main grid 42' with the negative fine grid line 22' are small, resulting in poor tension between the positive main grid 41' and the positive fine grid line 21' and between the negative main grid 42' and the negative fine grid line 22', which easily causes the positive main grid 41' and the negative main grid 42' to fall off. On the other hand, since the positive fine grid line 21' and the negative fine grid line 22' are arranged in a finger cross manner on the back of the crystalline silicon solar cell, it is generally necessary to provide an insulating glue 80 or an insulating layer at the end of the electrode grid line (positive fine grid line 21' and negative fine grid line 22') to avoid the contact between the solder strip connected with the positive main grid 41' and the negative fine grid line 22', and to avoid the contact between the solder strip connected with the negative main grid 42' and the positive fine grid line 21'. The setting of the insulating glue 80 or the insulating layer not only increases the preparation process of the full-back electrode structure crystalline silicon solar cell, resulting in complex production process of the crystalline silicon solar cell and high cost, but also reduces the contact reliability of the solder strip welded with the grid line (positive main grid 41' or negative main grid 42') at the welding point 60 of the positive main grid 41' and the negative main grid 42', and the insulating glue 80 or the insulating layer has the risk of insulation failure, resulting in short circuit of the crystalline silicon solar cell. It is worth noting that, in the prior art, the positive main grid 41' and the negative main grid 42' are formed by printing and curing non-burn-through type paste, and the positive main grid 41' and the negative main grid 42' are not connected with the positive fine grid line 21' and the negative fine grid line 22' respectively, which is not conducive to the stable connection between the positive main grid 41' and the positive fine grid line 21' and between the negative main grid 42' and the negative fine grid line 22'. Figure 1Among them, multiple negative fine grid lines 22' and a negative main grid 42' connecting the multiple negative fine grid lines 22' are marked with red line segments, and multiple positive fine grid lines 21' and a positive main grid 41' connecting the multiple positive fine grid lines 21' are marked with black line segments. Each finger-shaped P-type conductive region 11 is provided with multiple parallel positive fine grid lines 21' and a positive main grid 41', and each finger-shaped N-type conductive region 12 is provided with multiple parallel negative fine grid lines 22' and a negative main grid 42'. On both sides of a negative main grid 42' or a negative fine grid line 22', N-type conductive regions and P-type conductive regions are arranged alternately, where the N-type conductive region is a part of the finger-shaped N-type conductive region 12, and the P-type conductive region is a part of the finger-shaped P-type conductive region 11. Additionally, Figure 1 the dashed line in marks the isolation region 13, that is, the region outlined by the dashed line and similar to the "丰" structure or similar to the "" structure or similar to the

[0041] "" structure is the finger-shaped N-type conductive region 12 or the finger-shaped P-type conductive region 11.

[0041] To solve the above problems existing in the existing crystalline silicon solar cell with a full back electrode structure, an embodiment of the present invention provides a crystalline silicon solar cell with a novel structure and a preparation method thereof. In particular, the crystalline silicon solar cell is a crystalline silicon solar cell with a full back electrode structure.

[0042] It should be noted that the full back electrode structure involved in the embodiment of the present invention generally means that all the electrodes of the crystalline silicon solar cell are disposed on the back of the crystalline silicon solar cell, and there is no electrode shielding on the front of the crystalline silicon solar cell.

[0043] It should be noted that terms such as "first", "second", etc. are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "multiple" means two or more, unless otherwise specifically and clearly defined.

[0044] That one structure is disposed on another structure involved in the embodiment of the present invention generally means that when the one structure faces upward, at least part of the region of the other structure is located above the one structure. Exemplarily, the first main grid 41 disposed on the anti-reflection passivation layer 30 means that when the anti-reflection passivation layer 30 faces upward, at least part of the region of the first main grid 41 is located above the anti-reflection passivation layer 30. Another example is that the extended grid line segment 50 disposed on the anti-reflection passivation layer 30 means that when the anti-reflection passivation layer 30 faces upward, at least part of the region of the extended grid line segment 50 is located above the anti-reflection passivation layer 30.

[0045] This invention provides a crystalline silicon solar cell. Figures 3A to 7 A partial structural schematic diagram of a crystalline silicon solar cell provided in an embodiment of the present invention is shown. Figure 3A and Figure 3B These are schematic diagrams of the back structure of two types of crystalline silicon solar cells provided in the embodiments of the present invention; Figure 4A This is provided by the embodiments of the present invention. Figure 3A A partial structural schematic diagram of the BB cross-section of a crystalline silicon solar cell; Figure 4B This is provided by the embodiments of the present invention. Figure 3B A partial structural schematic diagram of the B'-B' cross-section of a crystalline silicon solar cell; Figure 5 This is provided by the embodiments of the present invention. Figure 3A CC profile of crystalline silicon solar cells or Figure 3B A partial structural schematic diagram of the C'-C' cross-section of a crystalline silicon solar cell; Figure 6 This is provided by the embodiments of the present invention. Figure 3A DD profile of crystalline silicon solar cells or Figure 3B A partial structural schematic diagram of the D'-D' cross-section of a crystalline silicon solar cell; Figure 7 This is a schematic diagram of the back structure of a crystalline silicon solar cell before the antireflection layer 30 is applied, as provided in an embodiment of the present invention.

[0046] Specifically, such as Figures 3A to 7 As shown, the crystalline silicon solar cell may include: a cell substrate 10, wherein the back surface of the cell substrate 10 is divided into a plurality of finger-shaped P-type conductive regions 11 and a plurality of finger-shaped N-type conductive regions 12 arranged in an interlaced pattern, and an isolation region 13 is provided between adjacent finger-shaped P-type conductive regions 11 and finger-shaped N-type conductive regions 12; a first seed transport layer 21 disposed on each finger-shaped P-type conductive region 11; a second seed transport layer 22 disposed on each finger-shaped N-type conductive region 12; and a layer covering the finger-shaped P-type conductive regions 11 and finger-shaped N-type conductive regions 12. The structure includes an anti-reflection passivation layer 30 for the electric region 12, the first seed transport layer 21, and the second seed transport layer 22; a main gate, comprising: a first main gate 41 disposed on the anti-reflection passivation layer and electrically connected to the first seed transport layer 21 through the anti-reflection passivation layer 30 in the thickness direction of the crystalline silicon solar cell; and a second main gate 42 disposed on the anti-reflection passivation layer and electrically connected to the second seed transport layer 22 through the anti-reflection passivation layer 30 in the thickness direction of the crystalline silicon solar cell, wherein the first main gate 41 and the second main gate 42 have opposite conductivity types.

[0047] The anti-reflection passivation layer 30 is generally formed of an insulating material, which can prevent electrical contact between the first main gate 41 and the second seed transport layer 22, and between the second main gate 42 and the first seed transport layer 21. The anti-reflection passivation layer 30 can be configured as follows: Figure 3B and Figure 4BAs shown, the anti-reflective passivation layer 30 can only cover the finger-shaped P-type conductive region 11, the finger-shaped N-type conductive region 12, the first seed transport layer 21 and the second seed transport layer 22, and does not cover the isolation region 13. Figure 3B As shown, the anti-reflective passivation layer 30 can only cover the finger-shaped P-type conductive region 11, the finger-shaped N-type conductive region 12, the first seed transport layer 21 and the second seed transport layer 22, and does not cover the isolation region 13. Figure 3A As shown, the anti-reflective passivation layer 30 can only cover the finger-shaped P-type conductive region 11, the finger-shaped N-type conductive region 12, the first seed transport layer 21 and the second seed transport layer 22, and does not cover the isolation region 13. Figure 4A As shown, the anti-reflective passivation layer 30 not only covers the finger-shaped P-type conductive region 11, the finger-shaped N-type conductive region 12, the first seed transport layer 21 and the second seed transport layer 22, but also covers the isolation region 13. By covering the isolation region 13 with the anti-reflective passivation layer 30, on the one hand, the silicon substrate 14 of the isolation region 13 can be protected from being exposed, thereby reducing the risk of the silicon substrate 14 of the isolation region 13 being scratched; on the other hand, the light reflection of the isolation region 13 can be reduced, and the light utilization rate of the crystalline silicon solar cell can be improved. In addition, by covering the isolation region 13 with the anti-reflective passivation layer 30, the appearance of the back surface of the crystalline silicon solar cell can be consistent and aesthetically pleasing.

[0048] It is worth noting that, for the structure of the anti-reflective passivation layer 30 covering the isolation region 13 as shown in Figure 3A and the structure of the anti-reflective passivation layer 30 not covering the isolation region 13 as shown in Figure 3B , the cross-sectional structure along the direction of the second main grid 42 (the cross-section of C-C as shown in Figure 3A and the cross-section of C'-C' as shown in Figure 3B ) is the same (as shown in Figure 5 ), and the cross-sectional structure along the direction of the first main grid 41 (the cross-section of D-D as shown in Figure 3A and the cross-section of D'-D' as shown in Figure 3B ) is the same (as shown in Figure 6 ).

[0049] For the crystalline silicon solar cell provided in the above embodiments, by covering the finger-shaped P-type conductive region 11, the finger-shaped N-type conductive region 12, the first seed transport layer 21 and the second seed transport layer 22 with the anti-reflective passivation layer 30, the anti-reflective passivation layer 30 can isolate the second seed transport layer 22 from the first main grid 41 electrically connected to the first seed transport layer 21, and the anti-reflective passivation layer 30 can also isolate the first seed transport layer 21 from the second main grid 42 electrically connected to the second seed transport layer 22, thereby avoiding the need to set an insulating glue or an insulating layer at the end of the fine grid line, so that the insulating glue or the insulating layer can not affect the electrical connection between the solder strip and the main grid line, thereby effectively improving the contact reliability between the solder strip and the electrode grid line, and reducing the short circuit risk of the crystalline silicon solar cell due to the aging of the insulating glue or the insulating layer.

[0050] Further, compared with the existing crystalline silicon solar cell, the crystalline silicon solar cell provided by the embodiment of the present application can make the structure of the crystalline silicon solar cell simpler by omitting the insulating glue or the insulating layer, facilitate industrialized production, and effectively reduce the cost of the crystalline silicon solar cell.

[0051] The following will describe the various functional structures of the crystalline silicon solar cell.

[0052] For the isolation region 13, it is not only used for isolating the adjacent finger-shaped P-type conductive region 11 and the finger-shaped N-type conductive region 12, but also used for isolating the adjacent first seed transport layer 21 and the second seed transport layer 22. Based on the isolation region 13, the electrical contact between the adjacent first seed transport layer 21 and the second seed transport layer 22 is avoided, so as to further improve the electrical isolation between the positive electrode and the negative electrode of the crystalline silicon solar cell, and reduce the risk of short circuit of the crystalline silicon solar cell. Further, in order to improve the isolation effect of the isolation region 13 and avoid the influence of the isolation region 13 on the effective area of the cell, the width of the isolation region 13 is generally 0.03 μm to 500 μm. For example, the width of the isolation region can be 0.03 μm, 1 μm, 5 μm, 10 μm, 50 μm, 100 μm, 200 μm, 250 μm, 300 μm, 360 μm, 400 μm or 500 μm, etc.

[0053] Further, for the cell substrate 10, it can include a crystalline silicon substrate 14, a first carrier collection layer 15 arranged on the back surface of the crystalline silicon substrate 14 and located in the finger-shaped P-type conductive region 11, and the first carrier collection layer 15 is electrically connected with the first seed transport layer 21, and a second carrier collection layer 16 arranged on the back surface of the crystalline silicon substrate 14 and located in the finger-shaped N-type conductive region 12, and the second carrier collection layer 16 is electrically connected with the second seed transport layer 22.

[0054] The crystalline silicon substrate 14 can be an N-type crystalline silicon substrate or a P-type crystalline silicon substrate. Optionally, the crystalline silicon substrate 14 is an N-type crystalline silicon substrate. The following will take the N-type crystalline silicon substrate as an example.

[0055] It can be understood that the conductive types of the finger-shaped P-type conductive region 11 and the finger-shaped N-type conductive region 12 are opposite, the finger-shaped P-type conductive region 11 is used for collecting and transporting hole carriers, and the finger-shaped N-type conductive region 12 is used for collecting and transporting electron carriers. The conductive type of the finger-shaped P-type conductive region 11 is determined by the first carrier collection layer 15 doped with P-type doping atoms (such as boron atoms, aluminum atoms or gallium atoms), and the conductive type of the finger-shaped N-type conductive region 12 is determined by the second carrier collection layer 16 doped with N-type doping atoms (such as phosphorus atoms, arsenic atoms or antimony atoms).

[0056] More specifically, the first carrier collection layer 15 can have various structures.

[0057] The first structure of the first carrier collection layer 15 can include a first tunneling passivation layer and a P-type doped polysilicon layer stacked outside the first tunneling passivation layer. That is, the first structure of the first carrier collection layer 15 can be a tunneling passivation structure.

[0058] The second structure of the first carrier collection layer 15 can include a P-type doped diffusion layer formed on the back surface of the crystalline silicon substrate 14.

[0059] As shown in Figure 4A , Figure 4B and Figure 6 , the third structure of the first carrier collection layer 15 can include a P-type doped diffusion layer 151 formed on the back surface of the crystalline silicon substrate 14, a second tunneling passivation layer 152 stacked outside the P-type doped diffusion layer 151, and a P-type doped polysilicon layer 153 stacked outside the second tunneling passivation layer 152.

[0060] In addition, the second carrier collection layer 16 can also have multiple structures.

[0061] Specifically, as shown in Figure 4A , Figure 4B and Figure 5 , the first structure of the second carrier collection layer 16 can include a third tunneling passivation layer 161 and an N-type doped polysilicon layer 162 stacked outside the third tunneling passivation layer 161.

[0062] The second structure of the second carrier collection layer 16 can include an N-type doped diffusion layer formed on the back surface of the crystalline silicon substrate 14.

[0063] The third structure of the second carrier collection layer 16 can include an N-type doped diffusion layer formed on the back surface of the crystalline silicon substrate 14, a fourth tunneling passivation layer stacked outside the N-type doped diffusion layer, and an N-type doped polysilicon layer stacked outside the fourth tunneling passivation layer.

[0064] The three structures of the first carrier collection layer 15 and the three structures of the second carrier collection layer 16 can be combined in any manner.

[0065] Therefore, the structure of the crystalline silicon solar cell provided by the embodiments of the present application has a wide range of application scenarios, and the structure of the crystalline silicon solar cell has practicality and generalizability.

[0066] Preferably, as shown in Figures 4A to 6 , the third structure of the first carrier collection layer 15 cooperates with the first structure of the second carrier collection layer 16 to effectively improve the photoelectric conversion efficiency and carrier collection capability of the crystalline silicon solar cell.

[0067] Further, the width of the first seed transport layer 21 can be 0.1 μm to 10 μm; for example, the width of the first seed transport layer 21 can be 0.1 μm, 1 μm, 2 μm, 5 μm, 8 μm, or 10 μm, etc. By limiting the width of the first seed transport layer 21, it can be ensured that the first seed transport layer 21 can form a stable and reliable electrical connection with the first carrier collection layer 15, and ensure the carrier transport capability of the first seed transport layer 21.

[0068] In addition, the thickness of the first seed transport layer 21 is generally 0.02 μm to 1 μm; for example, the thickness of the first seed transport layer 21 can be 0.02 μm, 0.05 μm, 0.08 μm, 0.1 μm, 0.5 μm, 0.8 μm, or 1 μm, etc. By controlling the thickness of the first seed transport layer 21, it can be ensured that the first seed transport layer 21 forms a stable and reliable electrical connection with the first main grid 41.

[0069] Further, the width of the second seed transport layer 22 can be 0.1 μm to 10 μm; for example, the width of the second seed transport layer 22 can be 0.1 μm, 1 μm, 2 μm, 5 μm, 8 μm, or 10 μm, etc. By limiting the width of the second seed transport layer 22, it can be ensured that the second seed transport layer 22 can form a stable and reliable electrical connection with the second carrier collection layer 16, and ensure the carrier transport capability of the second seed transport layer 22.

[0070] In addition, the thickness of the second seed transport layer 22 can be 0.02 μm to 1 μm; for example, the thickness of the second seed transport layer 22 can be 0.02 μm, 0.05 μm, 0.08 μm, 0.1 μm, 0.5 μm, 0.8 μm, or 1 μm, etc. By controlling the thickness of the second seed transport layer 22, it can be ensured that the second seed transport layer 22 forms a stable and reliable electrical connection with the second main grid 42.

[0071] The first seed transport layer 21 and the second seed transport layer 22 can comprise one or more of the following metals: silver, nickel, copper, and aluminum; it should be noted that the metals contained in the first seed transport layer 21 and the second seed transport layer 22 can be the same or different. The first seed transport layer 21 and the second seed transport layer 22 can select multiple types of metals, effectively reducing silver paste consumption, and further reducing the cost of crystalline silicon solar cells.

[0072] The first seed transport layer 21 and the second seed transport layer 22 are formed by electroplating or printing. In addition, the first seed transport layer 21 and the second seed transport layer 22 can be formed without a sintering process.

[0073] The first seed transfer layer 21 and the second seed transfer layer 22 are generally prepared by using non-burn-through paste. The non-burn-through paste generally refers to a paste that does not burn through the film layer covered thereby under high temperature condition. That is, even if the first main grid 41 and the second main grid 42 are prepared by subsequent sintering process, the first seed transfer layer 21 and the second seed transfer layer 22 will not burn through the anti-reflective passivation layer 30 covered thereby due to the selection of non-burn-through paste.

[0074] Further, the first seed transfer layer 21 and the second seed transfer layer 22 can have two structures respectively.

[0075] Specifically, as shown in Figure 6 and Figure 7 , the first structure of the first seed transfer layer 21 can include a plurality of first branch seed layers 211 arranged at intervals along a first direction (the first direction is the direction D1 shown in Figure 3A , Figure 3B and Figure 7 , which is consistent with the extension direction of the first main grid 41) and a first bus seed layer 212 connected in series with the plurality of first branch seed layers 211 and extending along the first direction; the first structure of the second seed transfer layer 22 can include a plurality of second branch seed layers 221 arranged at intervals along a first direction (the first direction is the direction D1 shown in Figure 3A , Figure 3B and Figure 7 , which is consistent with the extension direction of the first main grid 41) and a second bus seed layer 222 connected in series with the plurality of second branch seed layers 221 and extending along the first direction; the first direction is perpendicular to the extension direction of the second branch seed layer 221 and the extension direction of the first branch seed layer 211. Wherein, the extension direction of the second branch seed layer 221 and the extension direction of the first branch seed layer 211 are both the direction D2 shown in Figure 3A , Figure 3B and Figure 7 . The first main grid 41 extends along the first direction and is electrically connected to the first bus seed layer 212 of the first seed transfer layer 21 correspondingly; the second main grid 42 extends along the first direction and is electrically connected to the second bus seed layer 222 of the second seed transfer layer 22 correspondingly.

[0076] It can be understood that the finger-shaped N-type conductive region 12 and the finger-shaped P-type conductive region 11 are cross-shaped and are electrically isolated by the isolation region 13. In Figure 7Among them, multiple first branch seed layers 211 are marked with red line segments, and a first converging seed layer 212 connecting multiple first branch seed layers 211 in series is marked with a red line segment. Multiple second branch seed layers 221 are marked with black line segments, and a second converging seed layer 222 connecting multiple second branch seed layers 221 in series and extending along the first direction is marked with a black line segment. Each finger-shaped P-type conductive region 11 is provided with multiple parallel first branch seed layers 211 and a first converging seed layer 212, and each finger-shaped N-type conductive region 12 is provided with multiple parallel second branch seed layers 221 and a second converging seed layer 222. On both sides of a second converging seed layer 222 or a first converging seed layer 212, N-type conductive regions and P-type conductive regions are alternately arranged. Among them, the N-type conductive region is a part of the finger-shaped N-type conductive region 12, and the P-type conductive region is a part of the finger-shaped P-type conductive region 11. In addition, Figure 7 the dotted line in marks the isolation region 13, that is, the region similar to the "丰" - shaped structure or similar to the "型" structure or similar to the

[0077] "型" structure surrounded by the dotted line is the finger-shaped N-type conductive region 12 or the finger-shaped P-type conductive region 11. The first converging seed layer 212 and the second converging seed layer 222 are alternately arranged at intervals along a direction perpendicular to the first direction. The first branch seed layer 211 is vertically connected to one side or both sides of the first converging seed layer 212, and the second branch seed layer 221 is vertically connected to one side or both sides of the second converging seed layer 222, so that multiple first branch seed layers 211 vertically connected to the side of the first converging seed layer 212 close to the second converging seed layer 222 and multiple second branch seed layers 221 vertically connected to the side of the second converging seed layer 222 close to the first converging seed layer 212 are alternately arranged at intervals along the first direction, realizing the finger-shaped cross arrangement of the finger-shaped P-type conductive region 11 and the finger-shaped N-type conductive region 12.

[0078] In addition, the second structure of the first seed transmission layer 21 (not shown in the figure) can be composed of multiple first branch seed layers 211 arranged at intervals along the first direction (this first direction is Figure 3A 、 Figure 3B and Figure 7 the direction D1 shown, and this direction D1 is consistent with the extension direction of the first main grid 41); the second structure of the second seed transmission layer 22 (not shown in the figure) can be composed of multiple first branch seed layers 211 arranged at intervals along the first direction (this first direction is Figure 3A 、Figure 3B and Figure 7 The second seed layer 221 is arranged in a plurality of second branch seed layers 221 spaced apart in the direction D1 consistent with the extension direction of the first main grid 41 as shown in the figure, that is, compared with the first structure of the first seed transport layer 21, the second structure of the first seed transport layer 21 omits the first busbar seed layer 212; compared with the first structure of the second seed transport layer 22, the second structure of the second seed transport layer 22 omits the second busbar seed layer 222.

[0079] Generally, the first structure of the first seed transport layer 21 cooperates with the first structure of the second seed transport layer 22, and the second structure of the first seed transport layer 21 cooperates with the second structure of the second seed transport layer 22, to facilitate industrial production and ensure the balance of carrier transport of opposite types.

[0080] The first seed transport layer 21 and the second seed transport layer 22 can replace the positive fine grid lines 21' and the negative fine grid lines 22' of the existing crystalline silicon solar cell, omit the sintering process, and can be made thinner, finer and denser than the positive fine grid lines 21' and the negative fine grid lines 22' of the prior art, which can reduce the amount of electrode metal, and also can be beneficial to improve the efficiency and double-sided rate of the battery. In addition, the first seed transport layer 21 and the second seed transport layer 22 of the present application are located inside the anti-reflection passivation layer 30 (i.e. the first seed transport layer 21 and the second seed transport layer 22 are formed before the anti-reflection passivation layer 30, and the anti-reflection passivation layer 30 is not damaged), compared with the positive fine grid lines 21' and the negative fine grid lines 22' of the prior art located on the anti-reflection passivation layer 30, which need to pass through the anti-reflection passivation layer 30 to form silver-silicon alloy with the conductive area inside the anti-reflection passivation layer 30, the structure provided by the embodiment of the present application not only directly contacts the corresponding conductive area to form alloy, reduces the contact resistance, but also can improve the corrosion resistance of the battery and improve the reliability of the battery.

[0081] In particular, for the first structure of the first seed transport layer 21, the first busbar seed layer 212 included therein is in full contact with the first main busbar 41 included in the main busbar, so that the first busbar seed layer 212 has a relatively large contact area with the first main busbar 41, ensuring good electrical contact while allowing the first seed transport layer 21 and the first main busbar 41 to have a relatively strong pulling force, thereby reducing the risk of the first main busbar 41 falling off. Similarly, for the first structure of the second seed transport layer 22, the second busbar seed layer 222 included therein is in full contact with the second main busbar 42 included in the main busbar, so that the second busbar seed layer 222 has a relatively large contact area with the second main busbar 42, ensuring good electrical contact while allowing the second seed transport layer 22 and the second main busbar 42 to have a relatively strong pulling force, thereby reducing the risk of the second main busbar 42 falling off and improving the reliability of the crystalline silicon solar cell.

[0082] Further, since the first main busbar 41 and the second main busbar 42 pass through the anti-reflective passivation layer 30, the anti-reflective passivation layer 30 further stabilizes the first main busbar 41 and the second main busbar 42, further reducing the risk of the first main busbar 41 and the second main busbar 42 falling off, and further improving the corrosion resistance and reliability of the crystalline silicon solar cell.

[0083] Further, the anti-reflective passivation layer 30 can be a single layer or a stacked film layer including one or more of aluminum oxide, aluminum nitride, silicon nitride, and silicon oxynitride.

[0084] Further, as shown in Figure 3A and Figure 3B , the above-mentioned crystalline silicon solar cell can further include a plurality of extension busbar segments 50 disposed on the anti-reflective passivation layer 30. Among them, the plurality of extension busbar segments 50 are distributed between the edge main busbar and the main busbar adjacent to the edge main busbar, and are located on the anti-reflective passivation layer 30. The main busbar includes the edge main busbar located at the edge of the cell and the intermediate main busbar located in the middle of the cell, and the edge main busbar is the first main busbar 41 or the second main busbar 42, and the intermediate main busbar is the first main busbar 41 or the second main busbar 42. The edge main busbar and the adjacent intermediate main busbar have opposite conductivity types; one end of each extension busbar segment 50 is electrically connected to the adjacent edge main busbar; the other end of each extension busbar segment 50 extends vertically to the side of the adjacent intermediate main busbar of the edge main busbar, and the other end of each extension busbar segment 50 is electrically isolated from the adjacent intermediate main busbar of the edge main busbar, that is, the other end of each extension busbar segment 50 is located between the edge main busbar and the adjacent intermediate main busbar. Exemplarily, as shown in Figure 3A and Figure 3BAs shown, for the edge main grid being the first main grid 41, the middle main grid adjacent to the edge main grid is the second main grid 42, the plurality of extension grid line segments 50 are distributed between the first main grid 41 of the edge and the second main grid 42 adjacent to the first main grid 41 of the edge, and one end of the plurality of extension grid line segments 50 is electrically connected with the first main grid 41 of the edge and the other end is electrically isolated from the second main grid 42 adjacent to the first main grid 41 of the edge. For the edge main grid being the second main grid 42, the main grid adjacent to the edge main grid is the first main grid 41, the plurality of extension grid line segments 50 are distributed between the second main grid 42 of the edge and the first main grid 41 adjacent to the second main grid 42 of the edge, and one end of the plurality of extension grid line segments 50 is electrically connected with the second main grid 42 of the edge and the other end is electrically isolated from the first main grid 41 adjacent to the second main grid 42 of the edge. Wherein, the extension direction of the extension grid line segment 50 is perpendicular to the extension direction of the edge main grid; that is, the extension direction of the extension grid line segment 50 is the direction D2 perpendicular to the extension direction of the first main grid 41 and the second main grid 42. It is worth noting that the extension grid line segment 50 is located outside the anti-reflection passivation layer 30, that is, the extension grid line segment 50 does not contact the first seed transport layer 21 and the second seed transport layer 22, and the extension grid line segment 50 also does not contact the first carrier collection layer 15 and the second carrier collection layer 16 of the cell base body 10.

[0085] By arranging the plurality of extension grid line segments 50, in the subsequent soldering of the solder ribbon, the solder ribbon can be soldered with the plurality of extension grid line segments 50 to realize the electrical connection of the solder ribbon with the edge main grid (the first main grid 41 or the second main grid 42), and ensure that the solder ribbon and the edge main grid form a stable and reliable electrical connection.

[0086] Further, as shown in Figure 3A and Figure 3B , the other end of the extension grid line segment 50 away from the edge main grid is provided with a soldering point 60. Through the soldering point 60, the solder ribbon and the extension grid line segment 50 form a stable and reliable electrical connection.

[0087] In the embodiment of the present application, for the first main grid 41 and the second main grid 42, as shown in Figure 3A and Figure 3B , the first main grid 41 and the second main grid 42 are both a plurality of; the plurality of first main grids 41 and the plurality of second main grids 42 are alternately and spaced arranged to ensure the carrier transport capability of the crystalline silicon solar cell.

[0088] Further, in the embodiment of the present application, as shown in Figure 3A and Figure 3B , the first main grid 41 and the second main grid 42 are both spaced distributed with a soldering point 60. Through the soldering point 60, the solder ribbon and the first main grid 41 and the second main grid 42 form a stable and reliable electrical connection.

[0089] In addition, as shown in Figures 4A to 6As shown, the crystalline silicon solar cell provided by any of the above embodiments can further include a front passivation layer 70 disposed on the front surface of the cell substrate 10.

[0090] Further, the present application also provides a preparation method of the crystalline silicon solar cell. Specifically, as shown, the preparation method of the crystalline silicon solar cell can include the following steps: Figure 8

[0091] Step S801: providing a cell substrate 10, wherein the back surface of the cell substrate 10 is divided into a plurality of finger-shaped P-type conductive regions 11 and a plurality of finger-shaped N-type conductive regions 12 arranged in a cross pattern.

[0092] Specifically, there can be two kinds of structures for the back surface of the cell substrate 10. The first structure of the back surface of the cell substrate 10 is that the side surfaces of adjacent finger-shaped P-type conductive regions 11 and finger-shaped N-type conductive regions 12 are in contact (i.e., the back surface of the cell substrate 10 does not have an isolation region 13). The second structure of the back surface of the cell substrate 10 can also include an isolation region 13 disposed between adjacent finger-shaped P-type conductive regions 11 and finger-shaped N-type conductive regions 12. That is, for the first structure of the back surface of the cell substrate 10, it does not have an isolation region 13, and the isolation region 13 needs to be formed in the subsequent step. For the second structure of the back surface of the cell substrate 10, it itself contains an isolation region 13, and the subsequent step can omit the process of forming the isolation region 13.

[0093] Wherein, no matter the first structure of the back surface of the cell substrate 10 or the second structure of the back surface of the cell substrate 10, the cell substrate 10 can include a crystalline silicon substrate 14, a first carrier collection layer 15 disposed on the back surface of the crystalline silicon substrate 14 and located in the finger-shaped P-type conductive region 11, and a second carrier collection layer 16 disposed on the back surface of the crystalline silicon substrate 14 and located in the finger-shaped N-type conductive region 12. The crystalline silicon substrate 14 can be an N-type crystalline silicon substrate or a P-type crystalline silicon substrate. Preferably, the crystalline silicon substrate 14 is an N-type crystalline silicon substrate.

[0094] Wherein, the first carrier collection layer 15 can include a first tunneling passivation layer and a P-type doped polysilicon layer stacked outside the first tunneling passivation layer; or the first carrier collection layer 15 can include a P-type doped diffusion layer formed on the back surface of the crystalline silicon substrate 14; or the first carrier collection layer 15 includes a P-type doped diffusion layer 151 formed on the back surface of the crystalline silicon substrate 14, a second tunneling passivation layer 152 stacked outside the P-type doped diffusion layer 151, and a P-type doped polysilicon layer 153 stacked outside the second tunneling passivation layer 152.

[0095] ​The second carrier collection layer 16 can include a third tunneling passivation layer 161 and an N-type doped polysilicon layer 162 stacked outside the third tunneling passivation layer 161, or the second carrier collection layer 16 can include an N-type doped diffusion layer formed on the back surface of the crystalline silicon substrate 14, or the second carrier collection layer 16 can include an N-type doped diffusion layer formed on the back surface of the crystalline silicon substrate 14, a fourth tunneling passivation layer stacked outside the N-type doped diffusion layer, and an N-type doped polysilicon layer stacked outside the fourth tunneling passivation layer.

[0096] The first carrier collection layer 15 and the second carrier collection layer 16 can be formed by chemical vapor deposition such as low-temperature plasma chemical vapor deposition, wet etching (such as acid etching, alkali etching), and laser etching.

[0097] Step S802: Form a first seed transport layer 21 on each of the finger-shaped P-type conductive regions 11 and a second seed transport layer 22 on each of the finger-shaped N-type conductive regions 12.

[0098] Specifically, the first specific implementation of the step S802 can include:

[0099] Step S8021: Print a plurality of first branch seed layers 211 on the finger-shaped P-type conductive regions 11 in a first direction, and print a plurality of second branch seed layers 221 on the finger-shaped N-type conductive regions 12 in the first direction.

[0100] It is worth noting that for the first structure in which the back surface of the battery substrate 10 does not have a separation region between the finger-shaped P-type conductive regions 11 and the finger-shaped N-type conductive regions 12, as shown in FIG. 1A, the plurality of first branch seed layers 211 do not extend to the edge regions of the finger-shaped P-type conductive regions 11 in the width direction, and the plurality of second branch seed layers 221 do not extend to the edge regions of the finger-shaped N-type conductive regions 12 in the width direction. Figure 12 Figure 3A Figure 3B Figure 7

[0101] ​​​​Step S8022: printing the first busbar seed layer 212 which is composed of a plurality of first branch seed layers 211 and extends along the first direction on the finger-shaped P-type conductive region 11, and printing the second busbar seed layer 222 which is composed of a plurality of second branch seed layers 221 and extends along the first direction on the finger-shaped N-type conductive region 12, wherein the first direction is perpendicular to the extending direction of the second branch seed layer 221 and the extending direction of the first branch seed layer 211. Wherein the plurality of first branch seed layers 211 and the first busbar seed layer 212 constitute the first seed transport layer 21, and the plurality of second branch seed layers 221 and the second busbar seed layer 222 constitute the second seed transport layer 22.

[0102] The second specific embodiment of the step S802 can only print a plurality of first branch seed layers 211 which are arranged at intervals along the first direction on the finger-shaped P-type conductive region 11 and a plurality of second branch seed layers 221 which are arranged at intervals along the first direction on the finger-shaped N-type conductive region 12 by the above-mentioned step S8021, to obtain the first seed transport layer 21 and the second seed transport layer 22. That is, the plurality of first branch seed layers 211 constitute the first seed transport layer 21, and the plurality of second branch seed layers 221 constitute the second seed transport layer 22. For the first structure in which the battery substrate 10 does not have an isolation region between the finger-shaped P-type conductive region 11 and the finger-shaped N-type conductive region 12 on the back surface, in the second specific embodiment of the step S802, none of the plurality of first branch seed layers 211 extends to the edge region of the finger-shaped P-type conductive region 11 in the width direction; none of the plurality of second branch seed layers 221 extends to the edge region of the finger-shaped N-type conductive region 12 in the width direction. Wherein the width direction of the finger-shaped P-type conductive region 11 and the width direction of the finger-shaped N-type conductive region 12 are consistent with the D2 direction shown in FIG. 1. Figure 3A 、 Figure 3B and Figure 7

[0103] Step S803: forming the anti-reflection passivation layer 30 outside the finger-shaped P-type conductive region 11, the finger-shaped N-type conductive region 12, the first seed transport layer 21 and the second seed transport layer 22.

[0104] The step S803 can be prepared by chemical vapor deposition of a single layer or a laminated film layer containing one or more of aluminum oxide, aluminum nitride, silicon nitride, silicon oxynitride to obtain the anti-reflection passivation layer 30.

[0105] ​It is worth mentioning that for the first structure that the battery substrate 10 back surface between the finger-shaped P-type conductive area 11 and the finger-shaped N-type conductive area 12 does not have an isolation area, after the step S803, before the step S804, it can further include: a step S803' (not shown in the figure): setting a mask 90 outside the anti-reflective passivation layer 30, wherein the mask 90 does not cover the first edge 111 of the finger-shaped P-type conductive area 11 close to the finger-shaped N-type conductive area 12 and / or the mask 90 does not cover the second edge 121 of the finger-shaped N-type conductive area 12 close to the finger-shaped P-type conductive area 11; by a wet etching process, the first edge 111 not covered by the mask 90 and / or the second edge 121 not covered by the mask 90 are removed, the crystalline silicon substrate 14 corresponding to the first edge 111 and / or the second edge 121 is exposed, an isolation area 13 is formed, and the mask 90 is removed. Further, after the step S803', before the step S804, it can further include: forming an anti-reflective passivation layer 30 on the surface of the crystalline silicon substrate 14 exposed by the isolation area 13. Understandably, during the process of forming the anti-reflective passivation layer 30 on the surface of the crystalline silicon substrate 14 exposed by the isolation area 13, the anti-reflective passivation layer 30 outside the anti-reflective passivation layer 30 already formed in the step S803 can be continuously formed synchronously, so that the anti-reflective passivation layer 30 corresponding to the finger-shaped P-type conductive area 11 and the finger-shaped N-type conductive area 12 is a laminated structure.

[0106] For the second structure that the battery substrate 10 back surface between the finger-shaped P-type conductive area 11 and the finger-shaped N-type conductive area 12 has an isolation area, the anti-reflective passivation layer 30 formed in the step S803 covers the isolation area 13. That is, the step S803 further includes forming the anti-reflective passivation layer 30 covering the isolation area 13, wherein the anti-reflective passivation layer 30 covering the isolation area 13 can be formed synchronously with the anti-reflective passivation layer 30 covering the first seed transport layer 21 and the second seed transport layer 22.

[0107] Step S804: printing and sintering a burn-through type main grid paste outside the anti-reflective passivation layer 30 corresponding to the first seed transport layer 21 and the second seed transport layer 22 respectively, to form a first main grid 41 penetrating through the anti-reflective passivation layer 30 and electrically connected to the first seed transport layer 21 and a second main grid 42 penetrating through the anti-reflective passivation layer 30 and electrically connected to the second seed transport layer 22.

[0108] Further, the step S804 can further include: printing non-penetrating main grid paste on the anti-reflective passivation layer 30, the edge main grid and the main grid adjacent to the edge main grid, and curing to form a plurality of extended grid line segments 50, wherein each of the extended grid line segments 50 does not penetrate the anti-reflective passivation layer 30, one end of each of the extended grid line segments 50 is electrically connected to the edge main grid adjacent thereto, and the extended grid line segment 50 is electrically isolated from the main grid adjacent to the edge main grid. By selecting the non-penetrating main grid paste to cure the plurality of extended grid line segments 50, the extended grid line segments 50 are electrically isolated from the finger-shaped P-type conductive regions 11 and the finger-shaped N-type conductive regions 12, and in addition, the cost of the extended grid line segments 50 is reduced, thereby reducing the production cost of the crystalline silicon solar cell.

[0109] The preparation method of the crystalline silicon solar cell forms stable and reliable electrical contact between the first main grid 41 and the first seed transport layer 21, and between the second main grid 42 and the second seed transport layer 22, and avoids the first seed transport layer 21 penetrating the first carrier collection layer 15 and the second seed transport layer 22 penetrating the second carrier collection layer 16, thereby reducing the risk of short circuit of the prepared crystalline silicon solar cell and improving the reliability of the crystalline silicon solar cell. Further, the preparation method omits the process of arranging the insulating glue or insulating layer, effectively simplifies the preparation process of the crystalline silicon solar cell, and reduces the cost of the crystalline silicon solar cell.

[0110] Further, the first main grid 41 and the second main grid 42 penetrate the anti-reflective passivation layer 30, which further stabilizes the first main grid 41 and the second main grid 42, reduces the risk of the first main grid 41 and the second main grid 42 falling off, and further improves the reliability of the crystalline silicon solar cell.

[0111] Further, the preparation method provided by the embodiment of the present application can further include: a preparation process of the cell substrate 10, specifically, a process of preparing the cell substrate 10 based on the crystalline silicon substrate 14.

[0112] The following takes the first structure of the cell substrate 10 with an N-type crystalline silicon substrate, a P-type doped diffusion layer 151 formed in the finger-shaped P-type conductive region 11, a second tunneling passivation layer 152 laminated on the outer side of the P-type doped diffusion layer 151, a P-type doped polysilicon layer 153 laminated on the outer side of the second tunneling passivation layer 152, a third tunneling passivation layer 161 formed in the finger-shaped N-type conductive region 12, and an N-type doped polysilicon layer 162 laminated on the outer side of the third tunneling passivation layer 161, and without the isolation region 13, as an example, to specifically describe the preparation method of the crystalline silicon solar cell provided by the embodiment of the present application. The preparation method of the crystalline silicon solar cell can include the following steps:

[0113] SP1: removing surface damage and dirt of the N-type crystalline silicon substrate 14 with strong acid and strong base.

[0114] SP2: boron diffusion process, boron diffusion is performed in a boron diffusion furnace, a P-type doped diffusion layer 151 and a first borosilicate glass layer 154 are sequentially laminated on the back surface of the crystalline silicon substrate 14, and a first plating layer 151' corresponding to the P-type doped diffusion layer 151 and a second plating layer 154' corresponding to the first borosilicate glass layer 154 laminated on the outer side of the first plating layer 151' are formed on the front surface of the crystalline silicon substrate 14.

[0115] SP3: using laser etching to form a patterned boron diffusion region on the back surface of the crystalline silicon substrate 14, the boron diffusion region corresponding to the finger-shaped P-type conductive region 11.

[0116] SP4: using strong acid to remove the first borosilicate glass layer 154 and the second plating layer 154'.

[0117] SP5: using low-temperature chemical vapor deposition (LPCVD) to form a tunneling passivation layer 17 on the back surface of the crystalline silicon substrate 14, and an intrinsic polysilicon layer 18 is prepared on the outer side of the tunneling passivation layer 17, and a third plating layer 17' corresponding to the tunneling passivation layer 17 and a fourth plating layer 18' corresponding to the intrinsic polysilicon layer 18 are formed on the front surface of the crystalline silicon substrate 14.

[0118] Wherein, the structural changes corresponding to the above steps SP1 to SP5 are as shown in Figure 9 .

[0119] SP6: using plasma chemical vapor deposition (PECVD) to form a silicon nitride mask 19 on the outer side of the intrinsic polysilicon layer 18.

[0120] SP7: using laser to pattern the silicon nitride mask 19, the patterned silicon nitride mask 19 corresponding to the finger-shaped N-type conductive region 12.

[0121] SP8: using a boron diffusion furnace to convert the intrinsic polysilicon layer 18 in the region where the silicon nitride mask 19 is not provided into a P-type doped polysilicon layer 153, the fourth plating layer 18' into a boron-containing sixth plating layer 18'', and a second borosilicate glass layer 155 is formed on the outer side of the P-type doped polysilicon layer 153, and a fifth plating layer 155' corresponding to the second borosilicate glass layer 155 is formed on the outer side of the boron-containing sixth plating layer 18''.

[0122] Wherein, the structural changes corresponding to the above steps SP6 to SP8 are as shown in Figure 10 .

[0123] SP9: using laser to remove the residual silicon nitride mask 19 on the back surface.

[0124] SP10: using a phosphorus diffusion furnace to convert the remaining intrinsic polysilicon layer 18 on the back surface into an N-type doped polysilicon layer 162, and form a phosphorus-silicon glass layer 162' outside the N-type doped polysilicon layer 162, the second boron-silicon glass layer 155 is converted into a boron-phosphorus glass layer 155'', and the fifth wrap-around layer 155' is converted into a seventh wrap-around layer 155''' containing phosphorus and boron.

[0125] SP11: using an HF solution to remove the boron-phosphorus glass layer 155'', the seventh wrap-around layer 155''' containing phosphorus and boron, and the phosphorus-silicon glass layer 162'.

[0126] Wherein, the structural changes corresponding to the above steps SP9 to SP11 are shown as Figure 11

[0127] SP12: using a patterned deposition device to prepare a second seed transport layer 22 on the back surface of the cell according to Figure 12 The first seed transport layer 21 is formed outside the P-type doped polysilicon layer 153.

[0128] SP13: using PECVD to form an anti-reflection passivation layer 30 on the back surface of the cell.

[0129] SP14: using screen printing to print a mask 90 on the back surface of the cell to protect the area that does not need to be removed.

[0130] The mask 90 can be formed by paraffin.

[0131] Wherein, the structural changes corresponding to the above steps SP12 to SP14 are shown as Figure 12

[0132] Wherein, for SP14, Figure 12 Exemplarily, the area not covered by the mask 90 is the first edge 111 of the finger-shaped P-type conductive region 11 close to the finger-shaped N-type conductive region 12 and the second edge 121 of the finger-shaped N-type conductive region 12 close to the finger-shaped P-type conductive region 11. That is, the area not covered by the mask 90 is the first edge 111 of the finger-shaped P-type conductive region 11 close to the finger-shaped N-type conductive region 12 and the second edge 121 of the finger-shaped N-type conductive region 12 close to the finger-shaped P-type conductive region 11, after removing each functional layer in S15, the isolation region 13 is formed.

[0133] ​​SP15: using wet chemical equipment to remove the battery front and all film layers (the sixth boron-containing plating layer 18" of the battery front, the third plating layer 17' and the first plating layer 151' of the battery front, the anti-reflective passivation layer 30 corresponding to the isolation region 13, the N-type doped polysilicon layer 162, the P-type doped polysilicon layer 153 and the tunneling passivation layer 17) not covered by the mask 90, exposing the battery front and the isolation region 13 to the crystalline silicon substrate 14, and texturing the surface to reduce reflectivity, forming the isolation region 13 to separate the tunneling passivation layer 17 into the second tunneling passivation layer 152 and the third tunneling passivation layer 161, and removing the mask 90.

[0134] After this processing, the anti-reflective passivation layer 30 corresponding to the finger-shaped P-type conductive region 11 and the finger-shaped N-type conductive region 12 is a laminated structure.

[0135] In addition, this step can also be replaced by forming a silicon nitride passivation anti-reflective film on the battery front as the front passivation layer 70, while the crystalline silicon substrate 14 exposed by the isolation region 13 remains exposed.

[0136] In this embodiment, the battery front is generally textured.

[0137] In this embodiment, the structure corresponding to the above steps SP15 and SP16 is shown in FIG. 6. Figure 13

[0138] SP17: using screen printing and drying equipment to print a burn-through type main grid silver electrode on the battery back, obtaining the first main grid 41 and the second main grid 42.

[0139] In this embodiment, the structure corresponding to the above step SP17 is shown in FIG. 7. Figure 14

[0140] SP18: using screen printing and drying sintering equipment to print a non-burn-through type extension grid line segment 50 and a soldering point 60 on the battery back, and then drying and sintering, obtaining the crystalline silicon solar cell provided in the above embodiments of the present application.

[0141] In this embodiment, the structure corresponding to the above step SP18 is shown in FIG. 8. Figure 15

[0142] ​​​The following takes the N-type silicon substrate as an example, forms a P-type doped diffusion layer 151 in the finger-shaped P-type conductive region 11, a second tunneling passivation layer 152 laminated on the outer side of the P-type doped diffusion layer 151, a P-type doped polysilicon layer 153 laminated on the outer side of the second tunneling passivation layer 152, and a third tunneling passivation layer 161 and an N-type doped polysilicon layer 162 laminated on the outer side of the third tunneling passivation layer 161 in the finger-shaped N-type conductive region 12, and takes the second structure of the cell substrate 10 with the isolation region 13 as an example to describe the preparation method of the crystalline silicon solar cell provided by the embodiment of the present application. The preparation method of the crystalline silicon solar cell can include the following steps, SP1' to SP11' are the same as SP1 to SP11 described above, and the corresponding structural changes are shown in the following table, and the details are not described herein again. Figures 9 to 11

[0143] After SP11', the following steps are sequentially performed:

[0144] SP12': screen printing a mask 90 on the back surface of the cell to protect the areas that do not need to be removed.

[0145] The mask 90 can be formed by paraffin wax. In SP12', the areas not covered by the mask 90 are the first edge 111 of the finger-shaped P-type conductive region 11 close to the finger-shaped N-type conductive region 12 and the second edge 121 of the finger-shaped N-type conductive region 12 close to the finger-shaped P-type conductive region 11. Figure 16 Exemplarily, the areas not covered by the mask 90 are the first edge 111 of the finger-shaped P-type conductive region 11 close to the finger-shaped N-type conductive region 12 and the second edge 121 of the finger-shaped N-type conductive region 12 close to the finger-shaped P-type conductive region 11. After SP13' removes each functional layer, the isolation region 13 is formed.

[0146] SP13': using a wet chemical device to remove all the film layers on the front surface of the cell and the areas not covered by the mask 90 (the sixth boron-containing plating layer 18'' on the front surface of the cell, the third plating layer 17' and the first plating layer 151' of the cell, the anti-reflection passivation layer 30, the N-type doped polysilicon layer 162, the P-type doped polysilicon layer 153 and the tunneling passivation layer 17 corresponding to the isolation region 13), so that the front surface of the cell and the isolation region 13 expose the crystalline silicon substrate 14, and the surface is textured to reduce the reflectivity, the isolation region 13 separates the tunneling passivation layer 17 into the second tunneling passivation layer 152 and the third tunneling passivation layer 161, and the mask 90 is removed.

[0147] The front surface of the cell is generally a textured structure.

[0148] SP14': using PECVD to form a silicon nitride passivation anti-reflection film as the front passivation layer 70 on the front surface of the cell.

[0149] SP15': using a patterned deposition device to form a P-type doped diffusion layer 151' on the front surface of the cell according to the shape of the isolation region 13.​Figure 16 A second seed transport layer 22 is formed on the N-type doped polysilicon layer 162, and a first seed transport layer 21 is formed outside the P-type doped polysilicon layer 153.

[0150] SP16': Forming an anti-reflective passivation layer 30 on the back of the cell using PECVD.

[0151] In the above, the corresponding structural changes of SP12' to SP16' are shown in Figure 16 .

[0152] In the above, the corresponding structural changes of SP12' to SP16' are shown in Figure 16 .

[0153] Regardless of the execution order of steps SP14', SP15' and SP16', after the steps SP14', SP15' and SP16' are executed, the structure obtained is the same as the structure obtained after step SP16', that is, the anti-reflective passivation layer 30 will also be formed in the isolation region 13.

[0154] After SP16', steps SP17' and SP18' are further included, which are the same as SP17 and SP18 respectively, and the corresponding structures of SP17' and SP18' are also the same as Figure 14 and Figure 15 , which will not be described here.

[0155] The above steps are provided for the purpose of understanding the method, structure and core idea of the present application. For those skilled in the art, without departing from the principles of the present application, the present application can also be improved and modified in several ways, and these improvements and modifications also belong to the scope of protection of the present application.

Claims

1. A crystalline silicon solar cell, characterized in that, include: The battery substrate (10) has a back surface divided into a plurality of finger-shaped P-type conductive regions (11) and a plurality of finger-shaped N-type conductive regions (12) arranged in an interlaced pattern, and an isolation region (13) is provided between adjacent finger-shaped P-type conductive regions (11) and finger-shaped N-type conductive regions (12). A first seed transport layer (21) is disposed on each of the finger-shaped P-type conductive regions (11). A second seed transport layer (22) is disposed on each of the finger-shaped N-type conductive regions (12). Anti-reflection passivation layer (30) covering the finger-shaped P-type conductive region (11), the finger-shaped N-type conductive region (12), the first seed transport layer (21) and the second seed transport layer (22); The main gate includes: a first main gate (41) disposed on the anti-reflection passivation layer (30) and electrically connected to the first seed transport layer (21) through the anti-reflection passivation layer (30) in the thickness direction; and a second main gate (42) disposed on the anti-reflection passivation layer (30) and electrically connected to the second seed transport layer (22) through the anti-reflection passivation layer (30) in the thickness direction, wherein the first main gate (41) and the second main gate (42) have opposite conductivity types.

2. The crystalline silicon solar cell according to claim 1, characterized in that, Also includes: Multiple extended gate segments (50) are disposed on the anti-reflection passivation layer (30); One end of each of the extended grid line segments (50) is electrically connected to the edge grid of the main grid located at the edge of the cell substrate (10); The other end of each of the extended gate segments (50) extends vertically toward the intermediate gate side adjacent to the edge gate and is electrically isolated from the intermediate gate adjacent to the edge gate.

3. The crystalline silicon solar cell according to claim 2, characterized in that, Both the first main gate (41) and the second main gate (42) have multiple bars; Multiple first main gates (41) and multiple second main gates (42) are arranged alternately and at intervals; And / or, Both the first main gate (41) and the second main gate (42) have welding points (60) distributed at intervals. And / or, The other end of the extended grid line segment (50) is provided with a welding point (60).

4. The crystalline silicon solar cell according to any one of claims 1 to 3, characterized in that, The first seed transmission layer (21) includes: a plurality of first branch seed layers (211) arranged at intervals along a first direction and a first confluence seed layer (212) that connects the plurality of first branch seed layers (211) in series and extends along the first direction. The second seed transmission layer (22) includes: a plurality of second branch seed layers (221) arranged at intervals along a first direction and a second confluence seed layer (222) that connects the plurality of second branch seed layers (221) in series and extends along the first direction. Wherein, the first direction is perpendicular to the extension direction of the second branch seed layer (221) and the extension direction of the first branch seed layer (211); And / or, The first main gate (41) extends along the first direction and is electrically connected to the first bus seed layer (212) of the first seed transmission layer (21); The second main gate (42) extends along the first direction and is electrically connected to the second bus seed layer (222) of the second seed transmission layer (22); And / or, The anti-reflection passivation layer (30) also covers the isolation area (13).

5. The crystalline silicon solar cell according to claim 1, characterized in that, The width of the first seed transport layer (21) is 0.1 μm to 10 μm; And / or, The width of the second seed transport layer (22) is 0.1 μm to 10 μm; And / or, The first seed transport layer (21) and the second seed transport layer (22) contain one or more of the following metals: silver, nickel, copper and aluminum; And / or, The width of the isolation zone (13) is 0.03μm~500μm; And / or, The anti-reflection passivation layer (30) is a single-layer or stacked film layer comprising one or more of aluminum oxide, aluminum nitride, silicon nitride, and silicon oxynitride. And / or, The crystalline silicon solar cell further includes a front passivation layer (70) disposed on the front side of the cell substrate (10).

6. The crystalline silicon solar cell according to claim 1, characterized in that, The battery substrate (10) includes: Crystalline silicon substrate (14); The first carrier collection layer (15) is located in the finger-shaped P-type conductive region (11) and is electrically connected to the first seed transport layer (21). The second carrier collection layer (16) is located in the finger-shaped N-type conductive region (12) and is electrically connected to the second seed transport layer (22).

7. The crystalline silicon solar cell according to claim 6, characterized in that, The first carrier collection layer (15) includes: A first tunneling passivation layer and a P-type doped polysilicon layer stacked on the outside of the first tunneling passivation layer; or, A P-type doped diffusion layer is formed on the back side of the crystalline silicon substrate (14); or, A P-type doped diffusion layer (151) is formed on the back side of the crystalline silicon substrate (14), a second tunneling passivation layer (152) is stacked on the outside of the P-type doped diffusion layer (151), and a P-type doped polycrystalline silicon layer (153) is stacked on the outside of the second tunneling passivation layer (152).

8. The crystalline silicon solar cell according to claim 6 or 7, characterized in that, The second carrier collection layer (16) includes: The third tunneling passivation layer (161) and the N-type doped polysilicon layer (162) stacked on the outside of the third tunneling passivation layer (161). or, An N-type doped diffusion layer is formed on the back side of the crystalline silicon substrate (14); or, An N-type doped diffusion layer is formed on the back side of the crystalline silicon substrate (14), a fourth tunneling passivation layer is stacked on the outside of the N-type doped diffusion layer, and an N-type doped polycrystalline silicon layer is stacked on the outside of the fourth tunneling passivation layer.

9. A method for preparing a crystalline silicon solar cell according to any one of claims 1-8, characterized in that, include: Step 1: Provide a battery substrate (10), wherein the back side of the battery substrate (10) is divided into a plurality of finger-shaped P-type conductive regions (11) and a plurality of finger-shaped N-type conductive regions (12) arranged in an interlaced pattern. Step 2: Form a first seed transport layer (21) in each of the finger-shaped P-type conductive regions (11) and form a second seed transport layer (22) in each of the finger-shaped N-type conductive regions (12). Step 3: An anti-reflection passivation layer (30) is formed on the outside of the finger-shaped P-type conductive region (11), the finger-shaped N-type conductive region (12), the first seed transport layer (21), and the second seed transport layer (22). Step 4: Print burn-through type main gate paste on the outside of the anti-reflection passivation layer (30) at intervals corresponding to the first seed transport layer (21) and the second seed transport layer (22), and sinter to form a first main gate (41) that penetrates the anti-reflection passivation layer (30) and is electrically connected to the first seed transport layer (21) and a second main gate (42) that penetrates the anti-reflection passivation layer (30) and is electrically connected to the second seed transport layer (22).

10. The method for preparing a crystalline silicon solar cell according to claim 9, characterized in that, The back side of the battery substrate (10) also includes an isolation region (13) disposed between adjacent finger-shaped P-type conductive regions (11) and finger-shaped N-type conductive regions (12). Step 3 of the method further includes forming the anti-reflection passivation layer (30) covering the isolation area (13). or, The sides of the finger-shaped P-type conductive region (11) and the side of the finger-shaped N-type conductive region (12) adjacent to each other on the back of the battery substrate (10) are in contact. The method further includes the following steps after step 3 and before step 4: Step 3': A mask (90) is provided on the outside of the anti-reflection passivation layer (30), wherein the mask (90) does not cover the first edge (111) of the finger-shaped P-type conductive region (11) near the finger-shaped N-type conductive region (12) and / or the mask (90) does not cover the second edge (121) of the finger-shaped N-type conductive region (12) near the finger-shaped P-type conductive region (11); the first edge (111) and / or the second edge (121) not covered by the mask (90) are removed by a wet etching process, so that the silicon substrate (14) corresponding to the first edge (111) and / or the second edge (121) is exposed to form an isolation region (13), and the mask (90) is removed.

11. The method for preparing a crystalline silicon solar cell according to claim 10, characterized in that, Step 4 also includes: On the anti-reflection passivation layer (30), a non-burn-through main gate paste is printed between the edge main gate and the intermediate main gate adjacent to the edge main gate, and after curing, multiple extended gate line segments (50) are formed. Each of the extended gate line segments (50) does not burn through the anti-reflection passivation layer (30). One end of each extended gate line segment (50) is electrically connected to the edge main gate that is close to it, and the other end of the extended gate line segment (50) extends vertically toward the intermediate main gate side adjacent to the edge main gate and is electrically isolated from the intermediate main gate adjacent to the edge main gate. And / or, Step 2 includes: Step 21: Print a plurality of first branch seed layers (211) spaced apart along the first direction in the finger-shaped P-type conductive region (11), and print a plurality of second branch seed layers (221) spaced apart along the first direction in the finger-shaped N-type conductive region (12). Step 22: Print a first bus seed layer (212) with multiple first branch seed layers (211) connected in series and extending along the first direction in the finger-shaped P-type conductive region (11), and print a second bus seed layer (222) with multiple second branch seed layers (221) connected in series and extending along the first direction in the finger-shaped N-type conductive region (12), wherein the first direction is perpendicular to the extension direction of the second branch seed layer (221) and the extension direction of the first branch seed layer (211).

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