Photovoltaic cell and preparation method thereof

Abstract

The invention relates to the technical field of photovoltaic cells, in particular to a photovoltaic cell and a preparation method thereof. The photovoltaic cell comprises a transparent conducting layer, a dielectric film layer and a metal electrode, the metal electrode comprises an electrode seed layer, an electrode connecting layer and an electrode conducting layer, the electrode seed layer is a low-temperature metal slurry electrode and is located on the outer side of the transparent conducting layer, and the dielectric film layer covers the outer side of the transparent conducting layer and the outer side of the electrode seed layer. And the electrode connecting layer penetrates through the cracks of the dielectric film layer and is connected with the electrode conducting layer and the electrode seed layer. The preparation method of the photovoltaic cell comprises the following steps: printing and drying low-temperature metal slurry to form an electrode seed layer after preparing the transparent conductive layer; depositing a dielectric film layer; forming an electrode connection layer through the cracks in an electroplating mode; and preparing an electrode conducting layer. The method has the beneficial effects that the consumption of a transparent conductive material, especially ITO, is reduced; the antireflection effect of the photovoltaic cell is enhanced; the electrode connection layer can improve contact between the electrode seed layer and the electrode conductive layer.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic cell technology, and in particular to a photovoltaic cell and its preparation method. Background Technology

[0002] Heterojunction (HJT) photovoltaic cells are currently the most efficient photovoltaic technology, with broad development prospects. In recent years, the production capacity and output of HJT photovoltaic cells have grown rapidly. At the same time, how to achieve "low-indium" target materials has become one of the key issues in HJT technology.

[0003] Indium is currently the main component of ITO sputtering targets for heterojunction photovoltaic cells. Its resources are scarce and scattered, leading to high production costs for refined indium. Therefore, the high price of existing ITO sputtering targets hinders cost reduction in heterojunction photovoltaic cells. Furthermore, with the surge in heterojunction photovoltaic cell production capacity, a "bottleneck" problem of insufficient indium supply is likely to emerge in the future.

[0004] Aluminum-doped zinc oxide (AZO) films are another commonly used transparent conductive (TCO) films. Because their main components are Zn and Al, their cost is only about 1 / 10 that of ITO films. In existing technologies, to reduce costs, some schemes use low-cost AZO films to replace ITO films. However, heterojunction photovoltaic cells prepared using AZO films as TCO films have low efficiency and suffer from severe cell degradation problems.

[0005] Chinese patent document CN113745358A proposes a composite transparent conductive layer structure using ITO and AGZO thin films as contact layers with doped amorphous silicon, with AGZO thin film as the conductive layer and ITO thin film as the protective layer. The structure controls the thickness of the ITO thin film in the composite layer to be less than the thickness of the AGZO thin film, thus saving ITO usage and avoiding the severe battery degradation problem caused by using only AGZO thin film. However, this method requires additional sputtering chambers and target sites, increasing equipment investment and maintenance costs. Furthermore, when used in outdoor photovoltaic systems, the AGZO / ITO composite film layer still faces significant risks of reliability issues due to moisture, acetic acid, and sodium ions. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a photovoltaic cell and its preparation method that can reduce the amount of transparent conductive materials, especially ITO, without sacrificing cell efficiency and reliability.

[0007] The technical solution adopted by the present invention to solve its technical problem is as follows: a photovoltaic cell, comprising a transparent conductive layer, a dielectric film layer and a metal electrode, wherein the metal electrode comprises an electrode seed layer, an electrode connection layer and an electrode conductive layer, the electrode seed layer is a low-temperature metal paste electrode, the electrode seed layer is located outside the transparent conductive layer, the dielectric film layer covers the outside of the transparent conductive layer and the electrode seed layer, the area of ​​the dielectric film layer covering the outside of the electrode seed layer is a cracked area of ​​the dielectric film layer, the electrode connection layer is located outside the electrode seed layer, the electrode conductive layer is located outside the electrode connection layer, the electrode connection layer penetrates the cracks in the cracked area of ​​the dielectric film layer, and is used to connect the electrode conductive layer and the electrode seed layer.

[0008] In some embodiments, optionally, the photovoltaic cell is a heterojunction photovoltaic cell, which further includes a silicon wafer substrate, an intrinsic amorphous silicon layer, and a doped amorphous silicon layer. The silicon wafer substrate has an intrinsic amorphous silicon layer, a doped amorphous silicon layer, a transparent conductive layer, a dielectric film layer, and a metal electrode on both the front and back sides. The intrinsic amorphous silicon layer, the doped amorphous silicon layer, the transparent conductive layer, and the dielectric film layer on the front and back sides of the silicon wafer substrate are arranged sequentially from the inside to the outside. The conductivity types of the doped amorphous silicon layers on the front and back sides of the silicon wafer substrate are opposite.

[0009] In some embodiments, the material of the transparent conductive layer is optionally one or a combination of indium oxide, tin oxide, and zinc oxide-based transparent conductive materials, and the thickness is controlled to be within 50 nm.

[0010] Preferably, the thickness of the transparent conductive layer is 10–30 nm.

[0011] In some embodiments, the dielectric film may be made of one or a combination of SiNx, SiNxOy, and SiOx, and the thickness of the dielectric film may be 70–120 nm.

[0012] In some embodiments, the electrode seed layer may be a low-temperature silver paste electrode, a low-temperature silver-coated copper paste electrode, or a low-temperature copper paste electrode.

[0013] In some embodiments, the material of the electrode connection layer may be one or a combination of Cu, Ni, and Sn;

[0014] The electrode conductive layer is made of one or a combination of Cu, Ni, and Sn; or the electrode conductive layer is a low-temperature silver paste electrode, a low-temperature silver-coated copper paste electrode, or a low-temperature copper paste electrode.

[0015] A method for preparing the above-mentioned photovoltaic cell involves preparing a transparent conductive layer, then printing and drying a low-temperature metal paste on the surface of the transparent conductive layer to form an electrode seed layer; then depositing a dielectric film layer; forming an electrode connection layer on the surface of the electrode seed layer through electroplating via cracks in the dielectric film layer; and finally preparing an electrode conductive layer.

[0016] In some embodiments, optionally, the photovoltaic cell is a heterojunction photovoltaic cell, specifically including the following steps:

[0017] 1) Texturing and cleaning the silicon wafer substrate;

[0018] 2) An intrinsic amorphous silicon layer and a doped amorphous silicon layer are deposited sequentially on both the front and back sides of the silicon wafer substrate;

[0019] 3) A transparent conductive layer is deposited on the surface of the doped amorphous silicon layer on both the front and back sides of the silicon wafer substrate;

[0020] 4) Low-temperature metal paste is printed on the surface of the transparent conductive layer on both the front and back sides of the silicon wafer substrate and then dried to form an electrode seed layer;

[0021] 5) Dielectric films are deposited on both the front and back sides of the silicon wafer substrate;

[0022] 6) Through the cracks in the dielectric film, an electrode connection layer is formed on the surface of the electrode seed layer by electroplating;

[0023] 7) The electrode conductive layer is prepared by electroplating or by printing a low-temperature metal paste and then drying it.

[0024] In some embodiments, the dielectric film may be made of one or a combination of SiNx, SiNxOy, and SiOx, and deposited using a low-temperature PECVD deposition method at a deposition temperature of 150–250°C and a thickness of 70–120 nm. The morphology of the electrode seed layer causes stress in the dielectric film, which in turn causes cracks to form in the area of ​​the dielectric film covering the outer side of the electrode seed layer.

[0025] The beneficial effects of this invention are: by adding a dielectric film layer, the thickness of the transparent conductive layer can be reduced, thereby reducing the consumption of transparent conductive materials, especially ITO.

[0026] Meanwhile, the electrode can be fabricated by utilizing the cracks in the dielectric film, without the need to cut grooves on the dielectric film, which simplifies the fabrication method.

[0027] Dielectric films can enhance the anti-reflection effect of photovoltaic cells, improve short-circuit current and cell efficiency;

[0028] Electroplating can improve the contact between the electrode seed layer and the electrode conductive layer, reduce series resistance, and improve the battery fill factor and efficiency.

[0029] The dielectric film can protect transparent conductive materials from moisture, acetic acid, and sodium ions, thereby improving the reliability of the components. Attached Figure Description

[0030] The present invention will be further described below with reference to the accompanying drawings and embodiments;

[0031] Figure 1 This is a flowchart illustrating the fabrication process of the heterojunction photovoltaic cells in Examples 1 and 2 of the present invention.

[0032] Figure 2 These are schematic diagrams of the heterojunction photovoltaic cells of Embodiments 1 and 2 of the present invention;

[0033] Figure 3 This is a schematic diagram of the perovskite / heterojunction tandem solar cell of Embodiment 3 of the present invention;

[0034] In the figure, 0-1. Silicon substrate, 1-1. First intrinsic amorphous silicon layer, 1-2. First doped amorphous silicon layer, 1-3. First transparent conductive layer, 1-4. First electrode seed layer, 1-5. First dielectric film layer, 1-6. First electrode connection layer, 1-7. First electrode conductive layer, 1-8. Intermediate layer, 1-9. Hole transport layer, 1-10. Perovskite light absorption layer, 1-11. First electron transport layer, 2-1. Second intrinsic amorphous silicon layer, 2-2. Second doped amorphous silicon layer, 2-3. Second transparent conductive layer, 2-4. Second electrode seed layer, 2-5. Second dielectric film layer, 2-6. Second electrode connection layer, 2-7. Second electrode conductive layer. Detailed Implementation

[0035] like Figure 2 As shown, a photovoltaic cell includes a transparent conductive layer, a dielectric film layer, and a metal electrode. The metal electrode includes an electrode seed layer, an electrode connection layer, and an electrode conductive layer. The electrode seed layer is a low-temperature metal paste electrode located outside the transparent conductive layer. The dielectric film layer covers the outside of the transparent conductive layer and the electrode seed layer. The area of ​​the dielectric film layer covering the outside of the electrode seed layer is a cracked area of ​​the dielectric film layer. The electrode connection layer is located outside the electrode seed layer, and the electrode conductive layer is located outside the electrode connection layer. The electrode connection layer penetrates the cracks in the cracked area of ​​the dielectric film layer and is used to connect the electrode conductive layer and the electrode seed layer.

[0036] The method for preparing this photovoltaic cell is as follows: after preparing a transparent conductive layer, a low-temperature metal paste is printed and dried on the surface of the transparent conductive layer to form an electrode seed layer; then a dielectric film layer is deposited; through the cracks in the dielectric film layer, an electrode connection layer is formed on the surface of the electrode seed layer by electroplating; and finally, an electrode conductive layer is prepared.

[0037] When the photovoltaic cell in this scheme is a heterojunction photovoltaic cell, in addition to the transparent conductive layer, dielectric film layer and metal electrode, it also includes a silicon wafer substrate 0-1, an intrinsic amorphous silicon layer and a doped amorphous silicon layer. The silicon wafer substrate 0-1 has an intrinsic amorphous silicon layer, a doped amorphous silicon layer, a transparent conductive layer, a dielectric film layer and a metal electrode on both the front and back sides. The intrinsic amorphous silicon layer, doped amorphous silicon layer, transparent conductive layer and dielectric film layer on the front and back sides of the silicon wafer substrate 0-1 are arranged sequentially from the inside to the outside. The conductivity types of the doped amorphous silicon layers on the front and back sides of the silicon wafer substrate 0-1 are opposite.

[0038] The intrinsic amorphous silicon layer, doped amorphous silicon layer, transparent conductive layer, dielectric film layer, and metal electrode on the front side of silicon wafer substrate 0-1 are respectively the first intrinsic amorphous silicon layer 1-1, the first doped amorphous silicon layer 1-2, the first transparent conductive layer 1-3, the first dielectric film layer 1-5, and the first metal electrode. The electrode seed layer, electrode connection layer, and electrode conductive layer of the first metal electrode are respectively the first electrode seed layer 1-4, the first electrode connection layer 1-6, and the first electrode conductive layer 1-7. The intrinsic amorphous silicon layer, doped amorphous silicon layer, transparent conductive layer, dielectric film layer, and metal electrode on the back side of silicon wafer substrate 0-1 are respectively the second intrinsic amorphous silicon layer 2-1, the second... The silicon wafer substrate 0-1 has a doped amorphous silicon layer 2-2, a second transparent conductive layer 2-3, a second dielectric film layer 2-5, and a second metal electrode. The second metal electrode has an electrode seed layer 2-4, an electrode connection layer 2-6, and an electrode conductive layer 2-7, respectively. The first intrinsic amorphous silicon layer 1-1, the first doped amorphous silicon layer 1-2, the first transparent conductive layer 1-3, and the first dielectric film layer 1-5 are arranged from bottom to top on the front side of the silicon wafer substrate 0-1. The second intrinsic amorphous silicon layer 2-1, the second doped amorphous silicon layer 2-2, the second transparent conductive layer 2-3, and the second dielectric film layer 2-5 are arranged from top to bottom on the back side of the silicon wafer.

[0039] The silicon substrate 0-1 is a p-type or n-type monocrystalline silicon wafer.

[0040] The doped amorphous silicon in the first doped amorphous silicon layer 1-2 and the second doped amorphous silicon layer 2-2 is phosphorus-doped n-type amorphous silicon or boron-doped p-type amorphous silicon; the material of the doped amorphous silicon is one or a combination of two of a-Si:H, a-SiOx:H, and a-SiCx:H, with a thickness of 5 to 20 nm; the doped amorphous silicon can be doped amorphous silicon or microcrystalline silicon.

[0041] The intrinsic amorphous silicon of the first intrinsic amorphous silicon layer 1-1 and the second intrinsic amorphous silicon layer 2-1 is usually one or a combination of two undoped a-Si:H and a-SiOx, with a thickness of 3 to 8 nm.

[0042] The materials of the first transparent conductive layer 1-3 and the second transparent conductive layer 2-3 are one or a combination of indium oxide, tin oxide and zinc oxide-based transparent conductive materials, and the thickness is controlled within 50 nm, preferably within 10 to 30 nm.

[0043] The materials of the first dielectric film layer 1-5 and the second dielectric film layer 2-5 are one or a combination of SiNx, SiNxOy, and SiOx, with a comprehensive refractive index of 1.9 to 2.05 and a dielectric film thickness of 70 to 120 nm.

[0044] The first electrode seed layer 1-4 and the second electrode seed layer 2-4 are low-temperature metal paste electrodes formed by printing and drying low-temperature metal paste. The low-temperature metal paste is low-temperature silver paste, low-temperature silver-coated copper (Ag@Cu) paste or low-temperature copper paste. The low-temperature metal paste electrode is a low-temperature silver paste electrode, a low-temperature silver-coated copper paste electrode or a low-temperature copper paste electrode.

[0045] The materials of the first electrode connecting layer 1-6 and the second electrode connecting layer 2-6 are one or a combination of Cu, Ni, and Sn.

[0046] The materials of the first electrode conductive layer 1-7 and the second electrode conductive layer 2-7 are one or a combination of Cu, Ni, and Sn. Alternatively, the first electrode conductive layer 1-7 and the second electrode conductive layer 2-7 are low-temperature metal paste electrodes formed by printing and drying low-temperature metal paste. The low-temperature metal paste is low-temperature silver paste, low-temperature silver-coated copper (Ag@Cu) paste, or low-temperature copper paste. The low-temperature metal paste electrode is a low-temperature silver paste electrode, a low-temperature silver-coated copper paste electrode, or a low-temperature copper paste electrode.

[0047] like Figure 1 As shown, the fabrication method of the heterojunction photovoltaic cell in this scheme specifically includes the following steps:

[0048] 1) Texturing and cleaning of silicon wafer substrate 0-1.

[0049] In step 1, the silicon substrate 0-1 is a p-type or n-type monocrystalline silicon wafer. An anisotropic etching process can be used to prepare a pyramidal textured surface on the monocrystalline silicon wafer using an alkaline solution. Then, the surface of the textured monocrystalline silicon wafer is cleaned. The alkaline solution is usually a mixed solution containing KOH or NaOH, deionized water, and texturing additives.

[0050] 2) A first intrinsic amorphous silicon layer 1-1 and a first doped amorphous silicon layer 1-2 are sequentially deposited on the front side of the silicon substrate 0-1, and a second intrinsic amorphous silicon layer 2-1 and a second doped amorphous silicon layer 2-2 are sequentially deposited on the back side of the silicon substrate 0-1.

[0051] In step 2, PECVD and HWCVD are typically used to deposit intrinsic amorphous silicon layers and doped amorphous silicon layers.

[0052] 3) Deposit a first transparent conductive layer 1-3 on the surface of the first doped amorphous silicon layer 1-2, and deposit a second transparent conductive layer 2-3 on the surface of the second doped amorphous silicon layer 2-2.

[0053] In step 3, the transparent conductive layer is deposited using magnetron sputtering and RPD.

[0054] 4) Low-temperature metal paste is printed on the surfaces of the first transparent conductive layer 1-3 and the second transparent conductive layer 2-3 respectively and then dried to form the first electrode seed layer 1-4 and the second electrode seed layer 2-4. An ohmic contact is formed between the electrode seed layer and the transparent conductive layer.

[0055] 5) Deposit a first dielectric film layer 1-5 and a second dielectric film layer 2-5 on the front and back sides of the silicon wafer substrate 0-1.

[0056] In step 5, the dielectric film is deposited using a low-temperature PECVD deposition method at a deposition temperature of 150–250°C. The morphology of the electrode seed layer causes stress in the dielectric film, which in turn causes cracks to form in the area of ​​the dielectric film covering the outer side of the electrode seed layer.

[0057] 6) Through the cracks in the first dielectric film layer 1-5 and the second dielectric film layer 2-5, an electrode connection layer is formed on the surface of the electrode seed layer by electroplating.

[0058] In step 6, during the electroplating process, metal ions penetrate the cracks in the dielectric film and deposit and grow on the surface of the electrode seed layer until they penetrate the cracks in the dielectric film.

[0059] 7) The electrode conductive layer is prepared by electroplating or by printing a low-temperature metal paste and then drying it.

[0060] The present solution will be further illustrated below with several embodiments.

[0061] Example 1: A method for preparing a heterojunction photovoltaic cell, comprising the following steps:

[0062] 1) The surface of the silicon wafer substrate 0-1 is texturized and cleaned.

[0063] In step 1, the silicon substrate 0-1 is an n-type monocrystalline silicon wafer. An anisotropic etching process is used to prepare a pyramidal textured surface on the monocrystalline silicon wafer using an alkaline solution. Then, the surface of the textured monocrystalline silicon wafer is cleaned. The alkaline solution is usually a mixed solution containing KOH or NaOH, deionized water, and texturing additives.

[0064] 2) A first intrinsic amorphous silicon layer 1-1 and a first doped amorphous silicon layer 1-2 are sequentially deposited on the front side of the silicon substrate 0-1, and a second intrinsic amorphous silicon layer 2-1 and a second doped amorphous silicon layer 2-2 are sequentially deposited on the back side of the silicon substrate 0-1.

[0065] In step 2, the first doped amorphous silicon layer 1-2 is an n-type doped amorphous silicon layer, and the second doped amorphous silicon layer 2-2 is a p-type doped amorphous silicon layer. The intrinsic amorphous silicon layer and the doped amorphous silicon layer are deposited by PECVD. The first intrinsic amorphous silicon layer 1-1 and the second intrinsic amorphous silicon layer 2-1 are both undoped a-Si:H with a thickness of 4-6 nm. The first doped amorphous silicon layer 1-2 is phosphorus-doped n-type microcrystalline silicon oxide (n-uc-SiOx:H) and the first doped amorphous silicon layer 1-2 is boron-doped p-type microcrystalline silicon (p-uc-Si:H) with a doping layer thickness of 10-20 nm.

[0066] 3) Deposit a first transparent conductive layer 1-3 on the surface of the first doped amorphous silicon layer 1-2, and deposit a second transparent conductive layer 2-3 on the surface of the second doped amorphous silicon layer 2-2.

[0067] In step 3, both the first transparent conductive layer 1-3 and the second transparent conductive layer 2-3 are made of indium tin oxide (ITO) and are deposited using magnetron sputtering with a target composition of 97 / 3 (In₂O₃ / SnO₂). The thickness of both the first transparent conductive layer 1-3 and the second transparent conductive layer 2-3 is 20–30 nm; the carrier concentration is 2.5 x 10⁻⁶. 20 cm -3 .

[0068] 4) Low-temperature silver paste is printed on the surfaces of the first transparent conductive layer 1-3 and the second transparent conductive layer 2-3 respectively and then dried to form the first electrode seed layer 1-4 and the second electrode seed layer 2-4. An ohmic contact is formed between the electrode seed layer and the transparent conductive layer, and the contact resistance is 0.5 to 1.0 mΩcm2.

[0069] 5) Deposit a first dielectric film layer 1-5 and a second dielectric film layer 2-5 on the front and back sides of the silicon wafer substrate 0-1.

[0070] In step 5, the dielectric film is a composite film composed of SiNx / SiNxOy / SiOx. The dielectric film is deposited using a low-temperature PECVD deposition method at a deposition temperature of 180℃ and a thickness of 70-110nm. The protruding morphology of the electrode seed layer causes stress in the dielectric film, which in turn causes cracks to form in the area of ​​the dielectric film covering the outer side of the electrode seed layer.

[0071] 6) Through the cracks in the first dielectric film layer 1-5 and the second dielectric film layer 2-5, an electrode connection layer is formed on the surface of the electrode seed layer by electroplating.

[0072] In step 6, during the electroplating process, metal ions penetrate the cracks in the dielectric film and deposit and grow on the surface of the electrode seed layer until they penetrate the cracks in the dielectric film.

[0073] 7) The electrode conductive layer is prepared by printing low-temperature silver-coated copper paste and then drying it.

[0074] In step 7, the low-temperature silver-coated copper paste is aligned and printed with the electrode seed layer. The electrode connection layer penetrates the cracks in the dielectric film layer and connects with the electrode seed layer and the electrode conductive layer, which can effectively reduce the contact resistance.

[0075] The heterojunction photovoltaic cell prepared by the preparation method of this embodiment 1 includes a silicon wafer substrate 0-1, which is an n-type monocrystalline silicon wafer after texturing and cleaning. The front side of the silicon wafer substrate 0-1 is sequentially provided with a first intrinsic amorphous silicon layer 1-1, a first doped amorphous silicon layer 1-2, a first transparent conductive layer 1-3, a first dielectric film layer 1-5, and a first metal electrode that penetrates the first dielectric film layer 1-5 and contacts the first transparent conductive layer 1-3. The back side of the silicon wafer substrate 0-1 is sequentially provided with a second intrinsic amorphous silicon layer 2-1, a second doped amorphous silicon layer 2-2, a second transparent conductive layer 2-3, a second dielectric film layer 2-5, and a second metal electrode that penetrates the second dielectric film layer 2-5 and contacts the second transparent conductive layer 2-3.

[0076] Example 2: A method for preparing a heterojunction photovoltaic cell, wherein steps 1 to 6 are basically the same as in Example 1, except that in step 7, metal is deposited by electroplating to obtain an electrode conductive layer. The electrode conductive layer is made of Cu / Sn composite metal with a thickness of 10 to 20 μm, preferably 15 μm.

[0077] In addition to heterojunction photovoltaic cells, the technical solution of this invention can also be used in other types of photovoltaic cells that require current collection through a transparent conductive layer and a metal electrode in contact with the transparent conductive layer, achieving the same technical effect, such as perovskite / heterojunction tandem cells.

[0078] Example 3, as Figure 3 As shown, a method for fabricating a perovskite / heterojunction tandem solar cell includes the following steps:

[0079] 1) The surface of the silicon wafer substrate 0-1 is texturized and cleaned.

[0080] 2) A first intrinsic amorphous silicon layer 1-1 and a first doped amorphous silicon layer 1-2 are sequentially deposited on the front side of the silicon substrate 0-1, and a second intrinsic amorphous silicon layer 2-1 and a second doped amorphous silicon layer 2-2 are sequentially deposited on the back side of the silicon substrate 0-1.

[0081] 3) Deposit an intermediate layer 1-8 on the surface of the first doped amorphous silicon layer 1-2, and deposit a second transparent conductive layer 2-3 on the surface of the second doped amorphous silicon layer 2-2.

[0082] 4) Deposit hole transport layers 1-9 on the surface of intermediate layers 1-8.

[0083] In step 4, hole transport layers 1-9 are composite layers of NiOx and 2PACz. The NiOx deposition process is as follows: RF sputtering is used with a NiOx target of 99.99% purity, the sputtering atmosphere is pure Ar, and the NiOx thickness is 20nm. 2PACz is deposited on the NiOx surface. The 2PACz deposition process is as follows: first, an ethanol solution of 1mg / mL 2PACz is used, and spin-coating is performed continuously at a speed of 4000 rpm for 30s, and then dried at 100℃ for 10min.

[0084] 5) Deposit perovskite light absorption layers 1-10 on the surface of hole transport layers 1-9.

[0085] In step 5, the process for depositing the perovskite light-absorbing layers 1-10 is as follows: a perovskite precursor solution is deposited using a spin-coating process. The perovskite precursor solution is a mixed solution of DMF and DMSO with a composition of 1.7M Cs0.05FA0.8MA0.15Pb(I0.755Br0.255)3 (volume ratio 4:1). The spin-coating speed is 2500 rpm, the continuous spin-coating time is 40 s, and then the spin-coating speed is 5000 rpm for 10 s. Finally, the perovskite is dried at 100℃ / N2 for 30 min. The resulting perovskite has a band gap of 1.69 eV and a thickness of 0.7-0.9 μm.

[0086] 6) Deposit electron transport layer 1-11 on the surface of perovskite light absorption layer 1-10.

[0087] In step 6, the electron transport layer 1-11 is a composite layer of LiF / C60 / SnO2. The process for depositing the electron transport layer 1-11 is as follows: using evaporation, 1 nm of LiF is thermally evaporated and deposited on the PVK surface, and then 18 nm of C60 is thermally evaporated and deposited on the LiF surface; using ALD process, with TDMASn and H2O as reaction gases, N2 as carrier gas, and a deposition temperature of 80℃, 20 nm of SnO2 is deposited on the C60 surface.

[0088] 7) Deposit a first transparent conductive layer 1-3 on the surface of electron transport layer 1-11.

[0089] The first transparent conductive layer 1-3 and the second transparent conductive layer 2-3 are both made of indium tin oxide (ITO) and deposited by magnetron sputtering. The target composition is 97 / 3 (In₂O₃ / SnO₂). The thickness of both the first transparent conductive layer 1-3 and the second transparent conductive layer 2-3 is 20–30 nm. The carrier concentration is 2.5 x 10⁻⁶. 20 cm -3 .

[0090] 8) Low-temperature silver paste is printed on the surfaces of the first transparent conductive layer 1-3 and the second transparent conductive layer 2-3, and then dried to form the first electrode seed layer 1-4 and the second electrode seed layer 2-4. An ohmic contact is formed between the electrode seed layer and the transparent conductive layer, with a contact resistance of 0.5 to 1.0 mΩcm. 2 .

[0091] 9) Deposit the first dielectric film layer 1-5 and the second dielectric film layer 2-5 on the surface of the first transparent conductive layer 1-3 and the second transparent conductive layer 2-3, respectively.

[0092] 10) Through the cracks in the first dielectric film layer 1-5 and the second dielectric film layer 2-5, the first electrode connection layer 1-6 and the second electrode connection layer 2-6 are formed on the surface of the electrode seed layer by electroplating.

[0093] 11) The first electrode conductive layer 1-7 and the second electrode conductive layer 2-7 are prepared by printing low-temperature silver-coated copper paste and then drying it.

[0094] In step 11, the low-temperature silver-coated copper paste is aligned and printed with the electrode seed layer. The electrode connection layer penetrates the cracks in the dielectric film layer and is connected to the electrode seed layer and the electrode conductive layer, which can effectively reduce the contact resistance.

[0095] The perovskite / heterojunction tandem solar cell prepared in Example 3 includes a silicon substrate 0-1, which is an n-type monocrystalline silicon wafer after texturing and cleaning. On the front side of the silicon substrate 0-1, a first intrinsic amorphous silicon layer 1-1, a first doped amorphous silicon layer 1-2, an intermediate layer 1-8, a hole transport layer 1-9, a perovskite light absorption layer 1-10, an electron transport layer 1-11, a first transparent conductive layer 1-3, a first dielectric film layer 1-5, and a first metal electrode that penetrates the first dielectric film layer 1-5 and contacts the first transparent conductive layer 1-3 are arranged sequentially. On the back side of the silicon substrate 0-1, a second intrinsic amorphous silicon layer 2-1, a second doped amorphous silicon layer 2-2, a second transparent conductive layer 2-3, a second dielectric film layer 2-5, and a second metal electrode that penetrates the second dielectric film layer 2-5 and contacts the second transparent conductive layer 2-3 are arranged sequentially.

Claims

1. A photovoltaic cell characterized by: The transparent conductive layer, the dielectric film layer and the metal electrode are included, the metal electrode includes an electrode seed layer, an electrode connecting layer and an electrode conductive layer, the electrode seed layer is a low-temperature metal paste electrode, the electrode seed layer is located on the outside of the transparent conductive layer, the dielectric film layer is covered on the outside of the transparent conductive layer and the electrode seed layer, the area of the dielectric film layer covered on the outside of the electrode seed layer is a dielectric film layer crack zone with cracks, the electrode connecting layer is located on the outside of the electrode seed layer, the electrode conductive layer is located on the outside of the electrode connecting layer, and the electrode connecting layer penetrates through the cracks of the dielectric film layer crack zone to connect the electrode conductive layer and the electrode seed layer.

2. A photovoltaic cell according to claim 1, characterised in that: The heterojunction photovoltaic cell further includes a silicon wafer substrate, an intrinsic amorphous silicon layer and a doped amorphous silicon layer, and the intrinsic amorphous silicon layer and the doped amorphous silicon layer are arranged on the front and back surfaces of the silicon wafer substrate, the transparent conductive layer, the dielectric film layer and the metal electrode are arranged on the front and back surfaces of the silicon wafer substrate, and the conductive types of the doped amorphous silicon layers on the front and back surfaces of the silicon wafer substrate are opposite.

3. The photovoltaic cell of claim 1, wherein: The material of the transparent conductive layer is one or a combination of several of indium oxide, tin oxide and zinc oxide-based transparent conductive materials, and the thickness is controlled within 50 nm.

4. A photovoltaic cell according to claim 3, characterised in that: The thickness of the transparent conductive layer is 10-30 nm.

5. The photovoltaic cell of claim 1, wherein: The material of the dielectric film layer is one or a combination of several of SiNx, SiNxOy and SiOx, and the thickness of the dielectric film layer is 70-120 nm.

6. The photovoltaic cell of claim 1, wherein: The electrode seed layer is a low-temperature silver paste electrode, a low-temperature silver-coated copper paste electrode or a low-temperature copper paste electrode.

7. The photovoltaic cell of claim 1, wherein: The material of the electrode connecting layer is one or a combination of several of Cu, Ni and Sn. The material of the electrode conductive layer is one or a combination of several of Cu, Ni and Sn, or the electrode conductive layer is a low-temperature silver paste electrode, a low-temperature silver-coated copper paste electrode or a low-temperature copper paste electrode.

8. A method of producing a photovoltaic cell as claimed in claim 1, characterized in that the step of depositing a layer of a material having a band gap of 1.7 eV or less is performed by a method selected from the group consisting of sputtering, evaporation, and chemical vapor deposition. After the transparent conductive layer is prepared, a low-temperature metal paste is printed and dried on the surface of the transparent conductive layer to form the electrode seed layer. Then, the dielectric film layer is deposited. The electrode connecting layer is formed on the surface of the electrode seed layer through electroplating through the cracks of the dielectric film layer. The electrode conductive layer is prepared.

9. The method of claim 8, wherein the method further comprises: The photovoltaic cell is a heterojunction photovoltaic cell, and the specific steps are as follows: 1) The silicon wafer substrate is etched and cleaned; 2) The intrinsic amorphous silicon layer and the doped amorphous silicon layer are sequentially deposited on the front and back surfaces of the silicon wafer substrate; 3) The transparent conductive layer is deposited on the surface of the doped amorphous silicon layer on the front and back surfaces of the silicon wafer substrate; 4) The low-temperature metal paste is printed and then dried on the surface of the transparent conductive layer on the front and back surfaces of the silicon wafer substrate to form the electrode seed layer; 5) The dielectric film layer is deposited on the front and back surfaces of the silicon wafer substrate; 6) The electrode connecting layer is formed on the surface of the electrode seed layer through electroplating through the cracks of the dielectric film layer; 7) The electrode conductive layer is prepared through electroplating or by printing and drying a low-temperature metal paste.

10. The method of claim 8, wherein the method further comprises: The material of the dielectric film layer is one or a combination of several of SiNx, SiNxOy and SiOx, and the dielectric film layer is deposited by low-temperature PECVD deposition method at a deposition temperature of 150-250 ℃ and a thickness of 70-120 nm. The dielectric film layer has stress due to the morphology of the electrode seed layer, so that cracks are formed in the area of the dielectric film layer covering the outside of the electrode seed layer.

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