Photovoltaic cell and preparation method thereof

Abstract

The invention provides a photovoltaic cell and a preparation method thereof, relates to the technical field of photovoltaics, and aims to solve the technical problem of low photoelectric conversion efficiency of the photovoltaic cell. The photovoltaic cell comprises a substrate, the substrate is provided with a first surface, the first surface comprises a first area and a second area which form a stepped surface, the substrate is further provided with a groove formed in the stepped surface, and the first area is lower than the second area; a tunneling oxide layer and a first doping layer are sequentially stacked on the first region from inside to outside; the second region is provided with a second doping layer, and the doping type of the second doping layer is opposite to that of the first doping layer; and the side wall surface, close to the second doping layer, of the groove is higher than the surface, away from the substrate, of the first doping layer. The photovoltaic cell can improve the photoelectric conversion efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of photovoltaic, in particular to a photovoltaic cell and a preparation method thereof. BACKGROUND

[0002] The statements in this section merely provide background information related to the present application and do not necessarily constitute the prior art.

[0003] In recent years, the back contact (BC) cell technology is used to improve the photoelectric conversion performance of photovoltaic cells. On the basis of the interdigitated back contact (IBC) photovoltaic cell, a new type of photovoltaic cell is formed by using structures such as tunnel oxide passivated contact (TOPCon), for example, tunneling oxide passivated contact back contact (TBC). How to improve the photoelectric conversion efficiency of photovoltaic cells is the continuous work of developers. SUMMARY

[0004] The purpose of the present application is to provide a photovoltaic cell and a preparation method thereof, to solve the technical problem of low photoelectric conversion efficiency of photovoltaic cells.

[0005] In order to achieve the above-mentioned purpose, the present application provides the following technical scheme:

[0006] In a first aspect, the present application provides a photovoltaic cell, comprising a substrate, the substrate has a first surface, the first surface comprises a first region and a second region forming a stepped surface, and the substrate further has a groove formed on the stepped surface, wherein the first region is lower than the second region;

[0007] The tunneling oxide layer and the first doped layer are sequentially stacked from inside to outside on the first region;

[0008] The second region has a second doped layer, wherein the doping type of the second doped layer is opposite to that of the first doped layer;

[0009] The side wall surface of the groove close to the second doped layer is higher than the surface of the first doped layer away from the substrate.

[0010] According to at least one embodiment of the present application, the distance between the side wall surface of the groove away from the second doped layer and the surface of the first doped layer away from the substrate is in the range of 0.1 μm to 5 μm; and / or,

[0011] A distance between a side wall surface of the trench away from the second doped layer and a surface of the second doped layer away from the substrate ranges from 0.5 μm to 10 μm.

[0012] According to at least one of the embodiments of the present application, a depth of the trench ranges from 30 μm to 100 μm, and the depth direction of the trench is perpendicular to a thickness direction of the substrate; and / or,

[0013] A width of the trench ranges from 1 μm to 5 μm, and the width direction of the trench is parallel to the thickness direction of the substrate.

[0014] According to at least one of the embodiments of the present application, a first rough structure is formed on an inner wall surface of the trench.

[0015] According to at least one of the embodiments of the present application, the first rough structure includes a pyramid structure protruding from the inner wall surface, and a protruding height of the pyramid structure ranges from 0.5 μm to 1 μm; and / or,

[0016] A top angle of the pyramid structure ranges from 60° to 120°.

[0017] According to at least one of the embodiments of the present application, a part of the trench is formed on the second doped layer.

[0018] According to at least one of the embodiments of the present application, the second doped layer is an emitter layer formed on the substrate.

[0019] According to at least one of the embodiments of the present application, the substrate is one of an N-type substrate or a P-type substrate.

[0020] When the substrate is an N-type substrate, the emitter layer has P-type doped ions.

[0021] According to at least one of the embodiments of the present application, a doped depth of the doped ions of the emitter layer in the substrate ranges from 0.5 μm to 2 μm; and / or,

[0022] A doped concentration of the doped ions of the emitter layer ranges from 2×10 18 atoms / cm 3 to 1×10 19 atoms / cm 3 .

[0023] According to at least one of the embodiments of the present application, a thickness of the first doped layer ranges from 100 nm to 300 nm; and / or,

[0024] The doping concentration of the doping ions of the first doped layer ranges from 3×10 20 atoms / cm 3 to 1×10 21 atoms / cm 3 .

[0025] According to at least one embodiment of the present application, the substrate further has a second surface opposite to the first surface, and the second surface is formed with a second textured structure; and / or,

[0026] The area of the first region is greater than the area of the second region.

[0027] According to at least one embodiment of the present application, the photovoltaic cell further comprises a passivation anti-reflection layer stacked on the first doped layer, the second doped layer, the first textured structure and the second textured structure.

[0028] In a second aspect, the present application further provides a method for preparing a photovoltaic cell, comprising:

[0029] providing a substrate, the substrate having a first surface, the first surface comprising a first region and a second region;

[0030] forming a second doped layer on the first surface;

[0031] removing the second doped layer on the first region to form a stepped surface between the first region and the second region, and forming a trench on the stepped surface;

[0032] stacking a tunneling oxide layer and a first doped layer on the first region after removing the second doped layer, wherein the first doped layer is formed by physical vapor deposition, the doping type of the second doped layer is opposite to that of the first doped layer, and the sidewall surface of the trench close to the second doped layer is higher than the surface of the first doped layer away from the substrate.

[0033] According to at least one embodiment of the present application, after forming the second doped layer on the first surface, and before removing the second doped layer on the first region, the method for preparing a photovoltaic cell further comprises:

[0034] stacking a mask layer on the second doped layer, and removing the part of the mask layer on the first region.

[0035] According to at least one embodiment of the present application, removing the second doped layer on the first region comprises:

[0036] removing the second doped layer on the first region by chemical etching to expose the substrate to form the stepped surface, and forming the trench on the stepped surface.

[0037] According to at least one embodiment of the present application, the chemical corrosion includes alkaline corrosion, and the alkaline solution includes one or more of potassium hydroxide and sodium hydroxide.

[0038] According to at least one embodiment of the present application, the mass concentration of the alkaline solution ranges from 1% to 10%; and / or,

[0039] The time of the alkaline corrosion ranges from 100s to 350s.

[0040] According to at least one embodiment of the present application, the material of the mask layer includes at least one of silicon nitride and silicon carbide.

[0041] According to at least one embodiment of the present application, the tunneling oxide layer and the first doped layer are stacked on the first region of the second doped layer, including:

[0042] The tunneling oxide layer, the first doped layer and the first glass layer are stacked on the mask layer of the second region and the exposed substrate of the first region;

[0043] The first glass layer on the second region is removed by laser etching;

[0044] The first doped layer, the tunneling oxide layer and the mask layer on the second region and the first glass layer on the first region are removed by chemical corrosion, and a first textured structure is formed on the inner wall surface of the trench and a second textured structure is formed on the second surface of the substrate, wherein the second surface is opposite to the first surface.

[0045] According to at least one embodiment of the present application, the first doped layer, the tunneling oxide layer and the mask layer on the second region and the first glass layer on the first region are removed by chemical corrosion, including:

[0046] The first doped layer and the tunneling oxide layer on the second region are removed by alkaline corrosion, and a first textured structure is formed on the inner wall surface of the trench and a second textured structure is formed on the second surface of the substrate, wherein the alkaline solution includes one or more of potassium hydroxide and sodium hydroxide.

[0047] The mask layer on the second region and the first glass layer on the first region are removed by acid corrosion, wherein the acid solution includes hydrofluoric acid.

[0048] According to at least one embodiment of the present application, the power of the laser etching ranges from 5W to 20W.

[0049] One or more of the technical solutions provided in the exemplary embodiments of the present application can at least achieve one of the following beneficial effects.

[0050] The photovoltaic cell of the exemplary embodiments of the present application comprises a substrate, the substrate has a first surface, the first surface comprises a first region and a second region forming a stepped surface, and the substrate further has a groove formed in the stepped surface, wherein the first region is lower than the second region, that is, the first region and the second region have a height difference. When a tunneling oxide layer and a first doped layer are stacked on the first region, a second doped layer is formed on the second region, and the doping type of the second doped layer is opposite to that of the first doped layer, one of the first region and the second region forms a P region, and the other forms an N region. Specifically, when the sidewall surface of the groove close to the second doped layer is higher than the surface of the first doped layer away from the substrate, the functional layer of the first region and the functional layer of the second region are physically separated by the groove, thereby forming electrical isolation, that is, the groove forms a spacing region between the N region and the P region in the related art photovoltaic cell.

[0051] The photovoltaic cell structure of the exemplary embodiments of the present application can use physical vapor deposition to deposit the first doped layer on the first region when the first doped layer is stacked, and the groove is shielded by the second region, so that the first doped layer (also forming a first glass layer) is prevented from being formed on the inner wall of the groove, thereby avoiding the need to use laser etching to remove the first glass layer in the groove in subsequent processes. In the related art photovoltaic cell structure, the first doped layer (including the first glass layer) is formed on the first region, the spacing region, and the second region in sequence, and when laser etching is used to remove the first glass layer on the second region and the spacing region at the same time, the polishing surface of the spacing region itself reflects the laser, and a high laser power is required to etch the first glass layer of the spacing region. However, high-power laser can damage the functional layer such as the second doped layer in the second region, and seriously affect the passivation effect of the passivation and anti-reflection film subsequently arranged in the second region. Based on this, the spacing region in the form of the groove in the photovoltaic cell structure of the exemplary embodiments of the present application does not need to be subjected to laser etching at the same time as the second region to remove the first glass layer, so that a lower laser power can be used to etch the second region, reducing the influence on the passivation of the second region, thereby improving the photoelectric conversion efficiency of the photovoltaic cell. BRIEF DESCRIPTION OF DRAWINGS

[0052] The accompanying drawings illustrate exemplary embodiments of the present application and together with the general description of the application given above and the detailed description of the application given below, serve to explain the principles of the present application. These drawings are included herewith and constitute a part of this specification;

[0053] Figures 1 to 5 are respectively process structure cross-sectional schematic diagrams corresponding to the respective steps in the photovoltaic cell preparation method according to the embodiments of the present application after the respective steps are completed;

[0054] Figure 6 This is a schematic cross-sectional view of a photovoltaic cell according to an embodiment of the present invention;

[0055] Figure 7 This is a schematic diagram of the trench structure of a photovoltaic cell according to an embodiment of the present invention;

[0056] Figure 8 This is a schematic diagram of the photovoltaic cell preparation method according to an embodiment of the present invention.

[0057] Figure label:

[0058] 10. Substrate; 12. Second surface;

[0059] 21. Tunneling oxide layer; 22. First doped layer; 23. First glass layer;

[0060] 31. Second doped layer; 32. Mask layer;

[0061] 40. Trench;

[0062] 50. Passivation anti-reflection layer;

[0063] 61. First electrode; 62. Second electrode;

[0064] 71. First nap structure; 72. Second nap structure; 73. Third nap structure. Detailed Implementation

[0065] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0066] Figure 6 This is a schematic cross-sectional view of a photovoltaic cell according to an embodiment of the present invention. Figure 6As shown, the photovoltaic cell provided by the exemplary embodiment of the present application comprises a substrate 10 having a first surface, the first surface comprising a first region and a second region forming a stepped surface, and a trench 40 formed on the stepped surface, the trench 40 forming a spacing region at which the first region is lower than the second region; a tunneling oxide layer 21 and a first doped layer 22 are sequentially stacked from inside to outside on the first region; the second region has a second doped layer 31, wherein the second doped layer 31 is opposite in doping type to the first doped layer 22; the sidewall surface of the trench 40 close to the second doped layer 31 is higher than the surface of the first doped layer 22 away from the substrate 10. It should be noted that the first region is lower than the second region, which forms a stepped surface between the first region and the second region, and the trench is formed on the stepped surface to isolate the first region and the second region. The sidewall surface of the trench 40 close to the second doped layer 31 is higher than the surface of the first doped layer 22 away from the substrate 10, that is, the sidewall of the trench 40 protrudes downward from the surface of the first doped layer 22 away from the substrate 10.

[0067] Exemplarily, the substrate 10 can be a silicon base, for example, a P-type silicon base or an N-type silicon base. Hereinafter, the N-type silicon base is taken as an example, and the first doped layer 22 is taken as an example of N-type doped elements. Exemplarily, the doped elements of the first doped layer 22 can be phosphorus, arsenic, etc., and hereinafter, the phosphorus is taken as an example, and the doped elements of the second doped layer 31 are boron.

[0068] Exemplarily, the substrate 10 is a phosphorus-doped single crystal silicon wafer, the resistivity is 0.1 Ωcm-100 Ωcm, and the thickness is 100 μm-500 μm. The front surface (light receiving surface) of the substrate 10 is the second surface 12, and the back surface is the first surface.

[0069] It should be noted that the first surface of the substrate 10 has not only one set of the first region, the second region, and the spacing region formed by the trench 40, but also can have multiple sets of the above regions.

[0070] For example, the tunneling oxide layer 21 and the first doped layer 22 on the first region form an N-region, and the second doped layer 31 on the second region forms a P-region. A trench 40 is formed on the stepped surface between the first region and the second region. The sidewall of the trench 40 near the second doped layer 31 is higher than the surface of the first doped layer 22 away from the substrate 10. That is, the first doped layer 22 and the second region are physically isolated by the trench 40, thereby forming an electrically isolated region between the N-region and the P-region. From another perspective, when using unidirectional deposition (physical vapor deposition), for example, depositing the first doped layer 22 perpendicular to the first surface, the trench 40 is partially blocked by the second region. This makes it difficult for the first doped layer 22 and the inevitably formed phosphosilicate glass (PSG) layer to form on the inner wall of the trench 40, thus avoiding subsequent laser etching of the trench 40, i.e., the PSG layer formed on the spacer region. In related technologies, laser etching of the spacer region requires high laser power to remove the PSG layer in the spacer region and the second region. This inevitably damages the second doped layer 31 and / or other functional layers in the second region, thus failing to ensure the passivation effect of the second region during subsequent passivation. The trench 40 of the exemplary embodiment of the present invention does not require laser etching. Laser etching can be performed only on the PSG layer in the second region, using lower laser power to reduce damage to the second doped layer 31 and / or other functional layers in the second region, ensuring the passivation effect of the second region in the later stage, and thus improving the photoelectric conversion efficiency of the photovoltaic cell.

[0071] like Figure 2 As shown, Figure 2 This is a schematic diagram of a photovoltaic cell when trench 40 is formed, before the first textured structure 71 is formed on trench 40. Trench 40 has a sidewall (first sidewall) away from the second doped layer 31, a sidewall (second sidewall) close to the second doped layer 31, and a bottom wall opposite to the side of the first doped layer 22. That is, the cross-section of trench 40 is approximately U-shaped. The trench opening is formed on a stepped surface. For example, the cross-section of trench 40 is roughly circular or arc-shaped. Trench 40 is formed by recessing from the stepped surface in a direction away from the first region. Trench 40 is formed by recessing from the stepped surface in a direction away from the first region and parallel to the surface of substrate 10.

[0072] For example, see [link to previous article] Figure 2The distance d2 between the first sidewall of the trench 40 and the surface of the second doped layer 31 away from the substrate 10 is in the range of 0.5-10 μm, for example, 1 μm, 2 μm, 3 μm, 5 μm, 7 μm, 9 μm, etc. That is, d2 is the maximum vertical distance between the trench 40 and the surface of the second doped layer 31 away from the substrate 10, which is in the direction perpendicular to the substrate 10.

[0073] As shown in the example, Figure 3 The distance d1 between the first sidewall of the trench 40 and the surface of the first doped layer 22 away from the substrate 10 is in the range of 0.1-5 μm, for example, 1 μm, 2 μm, 3 μm, 4 μm, etc. When the distance between the first sidewall of the trench 40 and the first doped layer 22 and the second doped layer 31 is in the above range, the carrier transport path is short and the transport loss is small, so that the collection efficiency of the carriers is high and the battery efficiency is improved.

[0074] As shown in the example, the depth of the trench 40, that is, the distance d3 between the bottom wall and the stepped surface, is in the range of 30-100 μm, for example, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, etc. Alternatively, the distance between the bottom wall of the trench 40 and the first region is the depth of the trench 40. When the depth of the trench 40 is in the above range, the carrier transport loss is small on the basis of ensuring electrical isolation, and the battery efficiency is improved.

[0075] As shown in the example, the width of the trench 40 is in the range of 1-5 μm, that is, the distance between the first sidewall and the second sidewall of the trench 40 is 1-5 μm, or the opening width of the trench 40, for example, 1 μm, 2 μm, 3 μm, 4 μm, etc., wherein the width direction of the trench 40 is parallel to the thickness direction of the substrate 10. When the width of the trench 40 is in the above range, the first region and the second region can be effectively isolated, and the functional layer on the first region and the second region can collect carriers to the greatest extent, thereby improving the photoelectric conversion efficiency.

[0076] In some embodiments, the trench 40 can be formed entirely on the substrate 10, or partially on the substrate 10 and partially on the second doped layer 31, that is, a part of the second sidewall of the trench 40 extends and is formed on the second doped layer 31. The etching depth and opening width of the trench 40 are related to the concentration of the etching liquid and the etching time.

[0077] As shown in the example, Figure 4 and Figure 7 The first textured structure 71 is further formed on the inner wall of the trench 40, wherein, Figure 7This is a schematic diagram of the trench structure of a photovoltaic cell according to an embodiment of the present invention.

[0078] For example, the first velvet structure 71 includes a pyramid structure protruding from the inner wall surface, wherein the protrusion height h of the pyramid structure ranges from 0.5μm to 1μm, for example, h can be 0.6μm, 0.7μm, 0.8μm, 0.9μm, etc.

[0079] For example, the value of the apex angle α of the pyramid structure ranges from 60° to 120°, such as α being 75°, 90°, 105°, etc.

[0080] In some implementations, such as Figure 1 As shown, the second doped layer 31 is an emitter layer formed on the substrate 10. When the substrate 10 is phosphorus-doped single-crystal silicon, the emitter layer is a boron-doped single-crystal silicon layer formed by boron diffusion on the first surface of the substrate 10.

[0081] For example, the doping depth of the doped ions in the emitter layer on the substrate 10 ranges from 0.5 μm to 2 μm, that is, the thickness of the emitter layer can be 0.7 μm, 0.9 μm, 1.1 μm, 1.3 μm, 1.5 μm, 1.7 μm, or 1.9 μm.

[0082] For example, the doping concentration of boron ions in the emitter layer ranges from 2 × 10⁻⁶. 18 atoms / cm 3 ~1×10 19 atoms / cm 3 For example, it can be 2×10 18 atoms / cm 3 3×10 18 atoms / cm 3 4×10 18 atoms / cm 3 5×10 18 atoms / cm 3 6×10 18 atoms / cm 3 7×10 18 atoms / cm 3 8×10 18 atoms / cm 3 9×10 18 atoms / cm 3 .

[0083] Exemplarily, the thickness of the first doped layer 22 ranges from 100 nm to 300 nm, for example, can be 120 nm, 150 nm, 170 nm, 200 nm, 230 nm, 270 nm, 290 nm.

[0084] Exemplarily, the doping concentration of the phosphorus ions in the first doped layer 22 ranges from 3 x 1018 atoms / cm3 to 1 x 1020 atoms / cm3. 20 atoms / cm3 3 21 atoms / cm3 3 For example, can be 4 x 1018 atoms / cm3, 5 x 1018 atoms / cm3, 6 x 1018 atoms / cm3, 7 x 1018 atoms / cm3, 8 x 1018 atoms / cm3, 9 x 1018 atoms / cm3, or 1 x 1019 atoms / cm3. 20 atoms / cm3 3 20 atoms / cm3 3 20 atoms / cm3 3 20 atoms / cm3 3 20 atoms / cm3 3 20 atoms / cm3 3 .

[0085] Exemplarily, the tunneling oxide layer 21 can be a silicon oxide layer, and the thickness thereof can range from 0.5 nm to 3.0 nm, for example, can be 0.7 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, etc. By reasonably controlling the thickness of the tunneling oxide layer 21, the collection probability of majority carriers can be increased, and thus the photoelectric conversion efficiency of the battery can be improved.

[0086] In some embodiments, the area of the first region is greater than the area of the second region, for example, the area of the first region accounts for 40% to 60% of the area of the first surface, for example, can be 40%, 45%, 50%, 55%, or 60%, etc., and the area of the second region accounts for 30% to 50% of the area of the first surface, for example, can be 30%, 35%, 40%, 45%, or 50%, etc., so as to ensure the total amount of photo-generated carriers.

[0087] In some embodiments, as shown in FIG. 1, the substrate 10 further has a second surface 12 opposite to the first surface, and a second textured structure 72 is formed on the second surface 12. Figure 4

[0088] In some embodiments, as shown in FIG. 1, the substrate 10 further has a second surface 12 opposite to the first surface, and a second textured structure 72 is formed on the second surface 12. Figure 5 ​​​​​​​As shown, the photovoltaic cell further comprises a passivation anti-reflection layer 50 stacked on the first doped layer 22, the second doped layer 31, the first textured structure 71 and the second textured structure 72.

[0089] Specifically, the passivation anti-reflection layer 50 comprises a passivation layer and an anti-reflection layer, wherein the material of the passivation layer can be silicon nitride. The material of the anti-reflection layer can comprise at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride, aluminum oxynitride, magnesium fluoride, lithium fluoride, ITO, zinc oxide.

[0090] In some embodiments, as shown, a corresponding metal electrode is prepared on the first region and the second region. For example, the first electrode 61 is located outside the passivation anti-reflection layer 50 at one end and connected with the first doped layer 22 at the other end; the second electrode 62 is located outside the passivation anti-reflection layer 50 at one end and connected with the second doped layer 31 at the other end, thereby forming a photovoltaic cell. Figure 6

[0091] In some embodiments, the first electrode 61 is a negative electrode, and correspondingly, the second electrode 62 is a positive electrode.

[0092] Exemplarily, the first electrode 61 and the second electrode 62 can be one or several stacked layers of a silver electrode, a silver alloy electrode, a copper electrode, a copper alloy electrode, a nickel / copper / silver multilayer electrode.

[0093] Figure 8 is a flowchart of a preparation method of a photovoltaic cell according to an embodiment of the present application. As shown, Figure 8 The present exemplary embodiment further provides a preparation method of a photovoltaic cell, comprising the following steps:

[0094] Step 801: providing a substrate 10 having a first surface comprising a first region and a second region. The substrate 10 can be an N-type substrate.

[0095] Step 802: forming a second doped layer 31 on the first surface.

[0096] Step 8021: forming a third textured structure 73 on the opposite first surface and second surface 12 of the N-type substrate 10 by a texturing treatment. The texturing liquid can be an alkali solution, such as potassium hydroxide, sodium hydroxide, etc.

[0097] Step 8022: forming a P+ emitter layer (the second doped layer 31) and a borosilicate glass layer on the two surfaces after the treatment in step 8021 by a boron diffusion process.

[0098] Step 8023: removing the borosilicate glass layer on the surface of the substrate 10 using an acid solution, wherein the acid solution can be HF with a mass concentration of 5% to 15%. ​

[0099] Step 803: removing the second doped layer 31 on the first region to form a step surface between the first region and the second region, and forming a trench 40 on the step surface.

[0100] Step 8031: stacking a mask layer 32 on the second doped layer 31 of the first surface, removing the mask layer 32 on the first region to form a structure as shown in Figure 1 .

[0101] Specifically, a deposition process is used to deposit silicon nitride, silicon carbide, or the like as the mask layer 32 on the second doped layer 31 of the first surface.

[0102] Exemplarily, the thickness of the mask layer 32 is 10 nm to 200 nm, for example, can be 20 nm, 50 nm, 60 nm, 70 nm, 80 nm, 100 nm, 150 nm, etc.

[0103] The deposition process can use any one of vacuum evaporation, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), or a combination of multiple deposition methods in sequence.

[0104] Step 8032: removing the mask layer 32 on the first region by laser etching, and retaining the mask layer 32 on the second region to form a structure as shown in Figure 1 .

[0105] Exemplarily, the laser power of the above laser etching is 0.1 W to 100 W, for example, can be 0.1 W, 10 W, 20 W, 30 W, 50 W, 70 W, or 90 W, etc.

[0106] Step 8033: removing the second doped layer 31 on the first region by chemical etching to expose the substrate 10 to form a step surface, and forming a trench 40 on the step surface to form a structure as shown in Figure 2 .

[0107] Specifically, the second doped layer 31 and the third textured structure 73 on the second surface 12 are removed by a polishing process (alkali etching) to form a polished surface, the second doped layer 31 on the first region is also removed by the alkali etching to form the polished surface, and the second region is not etched due to the protection of the mask layer 32, so that the height of the first region is reduced, a stepped surface is formed between the first region and the second region, and the alkali etches to the deep of the stepped surface to form a U-shaped trench 40, such as a circular or arc-shaped structure, which can be used as a separation region of the N region on the first region and the P region on the second region to form an electrical isolation region of the N region and the P region.

[0108] Exemplarily, the alkali solution for polishing can be potassium hydroxide, sodium hydroxide, etc., and the mass concentration of the alkali solution can be 1% to 10%, for example, 2%, 4%, 5%, 6%, 7%, 9%, etc.

[0109] Exemplarily, the time of alkali etching can be 100s to 350s, for example, 150s, 200s, 250s, 300s, 330s, etc.

[0110] Within the concentration range and the etching time range of the alkali solution, the size of the trench 40 required by the electrical isolation region can be obtained, for example, the depth d3 of the trench 40 is 30μm to 100μm, and the width of the trench 40 is 1μm to 5μm, that is, the distance between the first sidewall and the second sidewall of the trench 40 is 1μm to 5μm.

[0111] Step 804: stack a tunneling oxide layer 21 and a first doped layer 22 on the first region where the second doped layer 31 is removed, wherein the first doped layer 22 is formed by a unidirectional deposition method, the doping type of the second doped layer 31 is opposite to that of the first doped layer 22, and the sidewall surface of the trench 40 close to the second doped layer 31 is higher than the surface of the first doped layer 22 away from the substrate 10.

[0112] Step 8041: deposit a tunneling oxide layer 21 on the entire first surface of the battery structure formed in step 803 by a deposition method, for example, any one of LPCVD, PECVD, PVD or ALD deposition method or a combination of multiple deposition methods.

[0113] Exemplarily, the tunneling oxide layer 21 can be a silicon oxide layer, and the thickness thereof can be 0.5nn to 3.0nm.

[0114] Step 8042: deposit a first doped layer 22 on the tunneling oxide layer 21 of the first surface by a unidirectional deposition method, for example, PVD, which is unidirectionally deposited in a direction perpendicular to the first surface.

[0115] In some embodiments, the material of the first doped layer 22 after deposition is phosphorus-doped amorphous silicon, and then an annealing process is performed to convert the amorphous silicon into polycrystalline silicon, so that the material of the final first doped layer 22 is phosphorus-doped polycrystalline silicon, and a PSG layer (the first glass layer 23) is inevitably formed on the surface of the first doped layer 22, forming a structure as shown in Figure 3 .

[0116] Exemplarily, the annealing temperature of the above-mentioned annealing process is 700-1100°C, for example, it can be 750°C, 800°C, 850°C, 900°C, 950°C, 1000°C, or 1050°C.

[0117] Exemplarily, the thickness of the first doped layer 22 ranges from 100 nm to 300 nm.

[0118] Step 8043: removing the first glass layer 23 on the second region by laser etching, and retaining the first glass layer 23 on the first region.

[0119] Exemplarily, the laser power for removing the PSG layer by laser etching ranges from 5 W to 20 W, for example, it can be 7 W, 9 W, 11 W, 13 W, 15 W, 17 W, or 19 W, etc.

[0120] Due to the shielding of the second region to the trench 40 in the deposition direction, the first doped layer 22 and the PSG layer are stacked on the first region and the second region, and the trench 40 is avoided from being deposited with the first doped layer 22 and the PSG layer. In the prior art, there is a spacing region between the N region and the P region (consistent with the electrical isolation effect of the trench 40), which is inevitably deposited in the spacing region when the first doped layer 22 and the PSG layer are deposited. Subsequent processes need to retain only the first doped layer 22 of the N region, and need to use laser etching to remove the PSG layer of the P region and the spacing region at the same time. However, the spacing region has a polished surface, which reflects laser, so high-power laser is needed to remove the PSG layer of the spacing region and the P region at the same time. High-power laser will damage other functional layers of the P region, thereby affecting the passivation effect of the P region, resulting in a decrease in the photoelectric conversion efficiency of the battery. In the exemplary embodiments of the present application, the trench 40 is not deposited with the first doped layer 22, and in the process of removing the PSG layer, laser etching is only performed on the P region of the second region, so low-power laser can be used, thereby minimizing the influence on the passivation effect of the P region, and the photoelectric conversion efficiency of the battery can be improved.

[0121] Step 8044: removing the first doped layer 22, the tunneling oxide layer 21 on the second region by a chemical etching liquid, and forming the first rough structure 71 on the inner wall surface of the trench 40 and the second rough structure 72 on the second surface 12 of the substrate 10. The chemical etching liquid includes an alkali solution, and the alkali solution includes one or more of potassium hydroxide and sodium hydroxide. The alkali solution can remove the first doped layer 22 and react with the second surface 12 of the substrate 10 and the trench 40 to form a rough surface, and can also remove the tunneling oxide layer 21.

[0122] For example, the mass concentration of the alkali solution is in the range of 1% to 10%, for example, the mass concentration can be 2%, 4%, 5%, 6%, 7%, 9%, etc.

[0123] For example, as shown in Figure 7 The first rough structure 71 includes a pyramid structure protruding from the inner wall surface, and the protruding height h of the pyramid structure is in the range of 0.5 μm to 1 μm, for example, h can be 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, etc. The apex angle a of the pyramid structure is in the range of 60° to 120°, for example, a can be 75°, 90°, 105°, etc.

[0124] In some embodiments, the second rough structure 72 has the same or similar size and shape as the first rough structure 71.

[0125] Step 8045: removing the mask layer 32 on the second region and the first glass layer 23 on the first region by acid etching, forming a structure as shown in Figure 4 .

[0126] Step 805: depositing a passivation and anti-reflection layer 50 on the structure formed after step 8045 of the first surface and the second surface 12 of the substrate 10, forming a structure as shown in Figure 5 .

[0127] For example, using multi-directional deposition methods such as ALD and PECVD, the passivation and anti-reflection layer 50 is formed on the second surface 12, the inner wall surface of the trench 40, the first doped layer 22 of the first region, and the second doped layer 31 of the second region.

[0128] For example, the passivation and anti-reflection layer 50 includes a passivation layer and an anti-reflection layer, and the material of the passivation layer can be silicon nitride. The material of the anti-reflection layer can include at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride, aluminum oxynitride, magnesium fluoride, lithium fluoride, ITO, and zinc oxide.

[0129] Step 806: The first electrode 61 and the second electrode 62 are prepared by sintering at high temperature on the first region and the second region of the passivation anti-reflection layer 50 on the back of the silicon wafer respectively by screen printing, and a structure as shown in FIG. 8 is formed. Figure 6

[0130] For example, one end of the first electrode 61 is located outside the passivation anti-reflection layer 50, and the other end is connected with the first doped layer 22; one end of the second electrode 62 is located outside the passivation anti-reflection layer 50, and the other end is connected with the second doped layer 31, so as to form a photovoltaic cell.

[0131] For example, the first electrode 61 and the second electrode 62 can be one or several laminated layers of silver electrode, silver alloy electrode, copper electrode, copper alloy electrode, nickel / copper / silver multilayer electrode.

[0132] As can be seen from the above, the photovoltaic cell preparation method provided by the example embodiment of the present application has simple process, avoids the problem of weakening of passivation effect caused by laser etching in the conventional process route, and is highly compatible with the existing TOPCon factory layout, and has low modification cost.

[0133] Embodiment 1

[0134] The preparation method of the photovoltaic cell comprises the following steps:

[0135] (1) The N-type silicon wafer with a resistivity of 20Ωcm and a thickness of 150μm is etched to form a third texturing structure.

[0136] The boron diffusion process is performed by LPCVD with boron source to form P + emitter layer / boron-silicate glass (BSG) on both surfaces (the first surface and the second surface) of the substrate.

[0137] After the BSG layer is removed by HF, a 50nm silicon nitride layer (mask layer) is deposited on both surfaces, and the silicon nitride layer on the first region of the first surface is etched away by a 35W laser (green picosecond laser).

[0138] (2) Polishing is performed in KOH solution, and a polished surface is formed on the first region and the second surface, and a groove is formed on the stepped surface formed on the first region and the second region due to etching by alkali, wherein the mass concentration of KOH is 5%, and the etching time is 200s.

[0139] (3) A 1.5nm tunneling oxide layer is formed on the first surface of the silicon wafer.

[0140] The dried silicon wafer is placed in a PVD device, and phosphorus-doped amorphous silicon is deposited on the first region and the second region.

[0141] ​Subsequently, annealing treatment at 900℃ is performed to convert the phosphorus-doped amorphous silicon into phosphorus-doped polysilicon, wherein a PSG layer with a thickness of about 30nm is formed on the surface of the phosphorus-doped polysilicon.

[0142] (4) The PSG on the surface of the second region is removed by using a 15W green picosecond laser to etch, and the trench and the first region are not etched by the laser;

[0143] (5) A texturing process is performed by using a KOH solution with a mass concentration of 5% to form a second texturing structure on the second surface, and a first texturing structure is formed on the inner wall of the trench; at the same time, the tunneling oxide layer and the phosphorus-doped polysilicon layer on the second region are removed;

[0144] The PSG on the surface of the first region and the silicon nitride (mask layer) on the surface of the second region are removed by using a HF solution with a mass concentration of 10%.

[0145] (6) A 6nm-thick Al2O3 layer is grown on the first surface and the second surface by using a PECVD device at 250℃, and by introducing trimethylaluminum and water;

[0146] Then, a 75nm-thick silicon nitride layer is deposited on the Al2O3 layer by using a PECVD device at 540℃, and by introducing silane and ammonia.

[0147] (7) Silver paste is screen-printed on the first region and the second region, respectively, and positive and negative electrodes are formed after high-temperature sintering.

[0148] Comparative Example 1

[0149] The difference between this comparative example and Example 1 is only that:

[0150] In step (2), the etching time of the KOH solution is 400s.

[0151] Comparative Example 2

[0152] The difference between this comparative example and Example 1 is only that:

[0153] In step (2), the mass concentration of the KOH solution is 12%.

[0154] Comparative Example 3

[0155] (1) An N-type silicon wafer with a resistivity of 20Ωcm and a thickness of 150μm is textured to form a third texturing structure.

[0156] Boron diffusion is performed by using LPCVD to introduce a boron source to form a P + emitter layer / Boron-Silicate Glass (BSG) layer on both surfaces (the first surface and the second surface) of the substrate.

[0157] The BSG on the first region and the interval region on the first surface is etched away by a 45W laser (green picosecond laser).

[0158] (2) A polishing process is performed in a KOH solution, the first region, the interval region and the second surface form a polished surface, a stepped surface is formed on the first region and the interval region, but no trench is formed, wherein the mass concentration of KOH is 5%, and the etching time is 200s.

[0159] (3) A 1.5nm tunneling oxide layer is formed on the first surface of the silicon wafer;

[0160] The dry silicon wafer is placed in a PVD device, and phosphorus-doped amorphous silicon is deposited on the first region, the interval region and the second region;

[0161] Subsequently, an annealing process at 900℃ is performed, so that the phosphorus-doped amorphous silicon is converted into phosphorus-doped polysilicon, and a PSG of about 30nm is formed on the surface of the phosphorus-doped polysilicon.

[0162] (4) The PSG on the surface of the second region and the interval region is removed by etching with a 30W green picosecond laser.

[0163] (5) A texturing process is performed using a KOH solution with a mass concentration of 5%, a second textured structure is formed on the second surface, a first textured structure is formed on the interval region, and the tunneling oxide layer and the phosphorus-doped polysilicon layer on the second region are removed at the same time;

[0164] HF with a mass concentration of 10% is used to remove the PSG on the surface of the first region and the BSG on the surface of the second region.

[0165] (6) A 6nm thick Al2O3 layer is grown on the first surface and the second surface by using a PECVD device at 250℃, and introducing trimethylaluminum and water;

[0166] Then, a 75nm thick silicon nitride layer is deposited on the Al2O3 layer by using a PECVD device at 540℃, and introducing silane and ammonia.

[0167] (7) Silver paste is screen printed on the first region and the second region respectively, and positive and negative electrodes are formed after high-temperature sintering.

[0168] Table 1: Electrical performance test results of each example and comparative example

[0169] EFF (%) Voc (mV) Isc (A) FF (%) Example 1 26.49 740.0 14.60 81.21 Comparative Example 1 26.19 739.9 14.59 80.05 Comparative Example 2 26.35 739.8 14.60 80.50 Comparative Example 3 Comparative Example 4 24.79 725.2 14.45 78.35

[0170] As shown in Table 1, the comparative example 3 is a preparation method of forming a spacing area in the prior art process route, since the polished surface of the spacing area reflects more laser, a higher laser power 30W (relative to the laser power 15W of etching the PSG layer on the second area in the example 1) is needed to etch the PSG on the surface of the spacing area, which affects the passivation effect of the second area in step (4), thereby causing the current density (14.60A) and the fill factor (81.21%) to be reduced relative to the example 1, while the carrier recombination is increased.

[0171] The trench depth d3 formed after step (2) of the example 1 is 60μm, and the width (the distance between the first sidewall and the second sidewall) is 2μm; the distance d2 between the first sidewall of the trench after step (5) and the second doped layer is 5μm, and the distance d1 between the first sidewall and the first doped layer is 2μm.

[0172] The trench depth d3 formed after step (2) of the comparative example 1 is 70μm, and the width is 5μm; the distance d2 between the first sidewall of the trench after step (5) and the second doped layer is 8μm, and the distance d1 between the first sidewall and the first doped layer is 5μm.

[0173] The trench depth d3 formed after step (2) of the comparative example 2 is 100μm, and the width is 4μm; the distance d2 between the first sidewall of the trench after step (5) and the second doped layer is 7μm, and the distance d1 between the first sidewall and the first doped layer is 4μm.

[0174] As shown in Table 1, relative to the example 1, in the polishing process of the comparative examples 1 and 2, a higher concentration of KOH solution is used or the etching time of polishing is increased, so that the height difference between the first area and the second area is larger, the distance between the first sidewall of the trench and the first doped layer and the second doped layer is increased, the carrier path is lengthened, which is not conducive to the transmission of the carrier (the transmission loss is large), and the fill factor of the battery is reduced. It shows that the efficiency of the photovoltaic cell prepared by the photovoltaic cell preparation method of the example embodiment of the present application is higher.

[0175] The example embodiment of the present application also provides the following technical solutions:

[0176] Technical solution 1. A photovoltaic cell, comprising a substrate, the substrate has a first surface, the first surface comprises a first area and a second area forming a stepped surface, and the substrate further has a trench formed in the stepped surface, wherein the first area is lower than the second area;

[0177] The first area has a tunneling oxide layer and a first doped layer stacked in sequence from inside to outside;

[0178] The second area has a second doped layer, wherein the doping type of the second doped layer is opposite to that of the first doped layer.

[0179] The side wall surface of the trench close to the second doped layer is higher than the surface of the first doped layer away from the substrate.

[0180] Technical solution 2. The photovoltaic cell according to technical solution 1, wherein the distance between the side wall surface of the trench away from the second doped layer and the surface of the first doped layer away from the substrate ranges from 0.1 μm to 5 μm; and / or,

[0181] The distance between the side wall surface of the trench away from the second doped layer and the surface of the second doped layer away from the substrate ranges from 0.5 μm to 10 μm.

[0182] Technical solution 3. The photovoltaic cell according to technical solution 1, wherein the depth of the trench ranges from 30 μm to 100 μm, and the depth direction of the trench is perpendicular to the thickness direction of the substrate; and / or,

[0183] The width of the trench ranges from 1 μm to 5 μm, wherein the width direction of the trench is parallel to the thickness direction of the substrate.

[0184] Technical solution 4. The photovoltaic cell according to technical solution 1, wherein a first textured structure is formed on the inner wall surface of the trench.

[0185] Technical solution 5. The photovoltaic cell according to technical solution 4, wherein the first textured structure comprises a pyramid structure protruding from the inner wall surface, and the protruding height of the pyramid structure ranges from 0.5 μm to 1 μm; and / or,

[0186] The size of the top angle of the pyramid structure ranges from 60° to 120°.

[0187] Technical solution 6. The photovoltaic cell according to any one of technical solutions 1-5, wherein part of the trench is formed on the second doped layer.

[0188] Technical solution 7. The photovoltaic cell according to any one of technical solutions 1-5, wherein the second doped layer is an emitter layer formed on the substrate.

[0189] Technical solution 8. The photovoltaic cell according to technical solution 7, wherein the substrate is one of an N-type substrate or a P-type substrate.

[0190] When the substrate is an N-type substrate, the emitter layer has P-type doped ions.

[0191] Technical solution 9. The photovoltaic cell according to technical solution 7, wherein the doped ions of the emitter layer have a doped depth ranging from 0.5 μm to 2 μm on the substrate; and / or,

[0192] The doping concentration of the doping ions of the emitter layer ranges from 2x10 18 atoms / cm 3 19 atoms / cm 3 .

[0193] Technical solution 10. The photovoltaic cell according to technical solution 9, wherein the thickness of the first doped layer ranges from 100 nm to 300 nm; and / or,

[0194] The doping concentration of the doping ions of the first doped layer ranges from 3x10 20 atoms / cm 3 21 atoms / cm 3 .

[0195] Technical solution 11. The photovoltaic cell according to technical solution 4 or 5, wherein the substrate further has a second surface opposite to the first surface, and a second textured structure is formed on the second surface; and / or,

[0196] The area of the first region is greater than the area of the second region.

[0197] Technical solution 12. The photovoltaic cell according to technical solution 11, wherein the photovoltaic cell further comprises a passivation anti-reflection layer stacked on the first doped layer, the second doped layer, the first textured structure and the second textured structure.

[0198] Technical solution 13. A method for preparing a photovoltaic cell, comprising:

[0199] providing a substrate, wherein the substrate has a first surface, and the first surface comprises a first region and a second region;

[0200] forming a second doped layer on the first surface;

[0201] removing the second doped layer on the first region to form a stepped surface between the first region and the second region, and forming a trench on the stepped surface;

[0202] stacking a tunneling oxide layer and a first doped layer on the first region after removing the second doped layer, wherein the first doped layer is formed by physical vapor deposition, the doping type of the second doped layer is opposite to that of the first doped layer, and the sidewall surface of the trench close to the second doped layer is higher than the surface of the first doped layer away from the substrate.

[0203] ​​Technical solution 14. The preparation method according to technical solution 13, after forming the second doped layer on the first surface, before removing the second doped layer on the first region, the preparation method further comprises:

[0204] stacking a mask layer on the second doped layer, and removing a part of the mask layer on the first region.

[0205] Technical solution 15. The preparation method according to technical solution 14, removing the second doped layer on the first region comprises:

[0206] removing the second doped layer on the first region by chemical etching to expose the substrate to form the stepped surface, and forming the trench on the stepped surface.

[0207] Technical solution 16. The preparation method according to technical solution 15, the chemical etching comprises alkali etching, and the alkali solution comprises one or more of potassium hydroxide and sodium hydroxide.

[0208] Technical solution 17. The preparation method according to technical solution 16, the mass concentration of the alkali solution ranges from 1% to 10%; and / or,

[0209] the time of the alkali etching ranges from 100s to 350s.

[0210] Technical solution 18. The preparation method according to any one of technical solutions 14-17, the material of the mask layer comprises at least one of silicon nitride and silicon carbide.

[0211] Technical solution 19. The preparation method according to technical solution 15, after removing the second doped layer, stacking a tunneling oxide layer and a first doped layer on the first region comprises:

[0212] stacking the tunneling oxide layer, the first doped layer and a first glass layer on the mask layer of the second region and the exposed substrate of the first region;

[0213] removing the first glass layer on the second region by laser etching;

[0214] removing the first doped layer, the tunneling oxide layer and the mask layer on the second region and the first glass layer on the first region by chemical etching, and forming a first textured structure on the inner wall surface of the trench and a second textured structure on the second surface of the substrate, wherein the second surface is opposite to the first surface.

[0215] Technical solution 20. The preparation method according to technical solution 19, wherein the first doped layer, the tunneling oxide layer and the mask layer on the second region, and the first glass layer on the first region are removed by chemical etching, comprising:

[0216] The first doped layer and the tunneling oxide layer on the second region are removed by alkaline etching, and a first rough structure is formed on the inner wall surface of the trench and a second rough structure is formed on the second surface of the substrate, wherein the alkaline solution comprises one or more of potassium hydroxide and sodium hydroxide.

[0217] The mask layer on the second region and the first glass layer on the first region are removed by acid etching, wherein the acid solution comprises hydrofluoric acid.

[0218] Technical solution 21. The preparation method according to technical solution 19 or 20, wherein the power of the laser etching ranges from 5 W to 20 W.

[0219] Those skilled in the art should understand that the above embodiments are only for clearly illustrating the present application, and are not intended to limit the scope of the present application. Based on the above disclosure, other changes or modifications can also be made by those skilled in the art, and these changes or modifications are still within the scope of the present application.

Claims

1. A photovoltaic cell, characterized by, The substrate has a first surface, the first surface includes a first region and a second region forming a step surface, and the substrate further has a trench formed on the step surface, wherein the first region is lower than the second region; A tunneling oxide layer and a first doped layer are sequentially stacked from inside to outside on the first region; The second region has a second doped layer, wherein the second doped layer is opposite to the first doped layer in doping type; The sidewall surface of the trench close to the second doped layer is higher than the surface of the first doped layer away from the substrate.

2. The photovoltaic cell of claim 1, wherein, The distance between the sidewall surface of the trench away from the second doped layer and the surface of the first doped layer away from the substrate ranges from 0.1 μm to 5 μm; And / or, The distance between the sidewall surface of the trench away from the second doped layer and the surface of the second doped layer away from the substrate ranges from 0.5 μm to 10 μm.

3. The photovoltaic cell of claim 1, wherein, The depth of the trench ranges from 30 μm to 100 μm, and the depth direction of the trench is perpendicular to the thickness direction of the substrate; and / or, The width of the trench ranges from 1 μm to 5 μm, and the width direction of the trench is parallel to the thickness direction of the substrate.

4. The photovoltaic cell of claim 1, wherein, A first textured structure is formed on the inner wall surface of the trench.

5. The photovoltaic cell of claim 4, wherein, The first textured structure includes a pyramid structure protruding from the inner wall surface, wherein the protruding height of the pyramid structure ranges from 0.5 μm to 1 μm; and / or, The top angle of the pyramid structure ranges from 60° to 120°.

6. Photovoltaic cell according to any of claims 1 to 5, characterized in that Part of the trench is formed on the second doped layer.

7. Photovoltaic cell according to any of claims 1 to 5, characterized in that The second doped layer is an emitter layer formed on the substrate; Preferably, the substrate is one of an N-type substrate or a P-type substrate; When the substrate is an N-type substrate, the emitter layer has P-type doping ions; Preferably, the doping depth of the emitter layer ranges from 0.5 μm to 2 μm; and / or, The doping concentration of the doping ions of the emitter layer ranges from 2 x 1018 atoms / cm3 to 1 x 1021 atoms / cm3. 18 atoms / cm3 3 atoms / cm3 19 atoms / cm3 3 ; Preferably, the thickness of the first doped layer ranges from 100 nm to 300 nm; and / or, The doping concentration of the doping ions of the first doped layer ranges from 3 x 1010atoms / cm3to 1 x 1012atoms / cm3. 20 atoms / cm3 3 . 21 atoms / cm3 3 .

8. Photovoltaic cell according to claim 4 or 5, characterized in that The substrate further has a second surface opposite to the first surface, and a second textured structure is formed on the second surface; and / or, The area of the first region is greater than the area of the second region; Preferably, the photovoltaic cell further includes a passivation anti-reflection layer stacked on the first doped layer, the second doped layer, the first textured structure, and the second textured structure.

9. A method of producing a photovoltaic cell, characterized by, The method includes: providing a substrate, the substrate has a first surface, the first surface includes a first region and a second region; forming a second doped layer on the first surface; removing the second doped layer on the first region to form a step surface between the first region and the second region, and form a trench on the step surface; stacking a tunneling oxide layer and a first doped layer on the first region after removing the second doped layer, wherein the first doped layer is formed by a physical vapor deposition method, the second doped layer is opposite to the first doped layer in doping type, and the sidewall surface of the trench near the second doped layer is higher than the surface of the first doped layer away from the substrate.

10. The method of claim 9, wherein, After forming the second doped layer on the first surface and before removing the second doped layer on the first region, the preparation method further comprises: stacking a mask layer on the second doped layer, and removing the part of the mask layer on the first region; Preferably, removing the second doped layer on the first region comprises: removing the second doped layer on the first region by chemical etching to expose the substrate to form the stepped surface and form the trench on the stepped surface; Preferably, the chemical etching comprises alkaline etching, and the alkaline solution comprises one or more of potassium hydroxide and sodium hydroxide; Preferably, the mass concentration of the alkaline solution ranges from 1% to 10%; and / or, the time of the alkaline etching ranges from 100s to 350s; Preferably, the material of the mask layer comprises at least one of silicon nitride and silicon carbide; Preferably, stacking the tunneling oxide layer and the first doped layer on the first region after removing the second doped layer comprises: stacking the tunneling oxide layer, the first doped layer and a first glass layer on the mask layer of the second region and the exposed substrate of the first region; removing the first glass layer on the second region by laser etching; removing the first doped layer, the tunneling oxide layer and the mask layer on the second region and the first glass layer on the first region by chemical etching, and forming a first textured structure on the inner wall surface of the trench and a second textured structure on the second surface of the substrate, wherein the second surface is opposite to the first surface; Preferably, removing the first doped layer, the tunneling oxide layer and the mask layer on the second region and the first glass layer on the first region by chemical etching comprises: alkaline etching to remove the first doped layer and the tunneling oxide layer on the second region, and forming a first textured structure on the inner wall surface of the trench and a second textured structure on the second surface of the substrate, wherein the alkaline solution comprises one or more of potassium hydroxide and sodium hydroxide; acid etching to remove the mask layer on the second region and the first glass layer on the first region, wherein the acid solution comprises hydrofluoric acid; Preferably, the power of the laser etching ranges from 5W to 20W.

Images