Charge storage type synaptic device for deep neural network training and driving method thereof

Abstract

The invention relates to a charge storage type synaptic device for deep neural network training and a driving method thereof. The synaptic device disclosed by the invention comprises a weighting capacitor which is provided with a first terminal and a second terminal and is used for storing a voltage corresponding to a weighting value; the four control transistors are used for changing the voltage or the weighted value of the capacitor; a first output transistor including a first gate terminal coupled to a first terminal of the capacitor and outputting a first drain current in accordance with a voltage applied to the first gate terminal; and a second output transistor including a second gate terminal coupled to a second terminal of the capacitor and outputting a second drain current in accordance with a voltage applied to the second gate terminal, the weighting value being dependent on a difference between the first drain current and the second drain current.

Description

Technical Field

[0001] This invention relates to synaptic devices and their driving methods, and more specifically, to charge storage type synaptic devices and their driving methods for training deep neural networks. Background Technology

[0002] Recently, with the gradual development of artificial intelligence applications based on artificial neural networks, computational structures most suitable for artificial neural network operations have been widely proposed. In particular, low-power and high-efficiency deep neural network computation can be achieved through hardware structures that can maximize the efficiency of large-scale parallel multiply-and-accumulate (MAC) operations. Using this structure, the crossbar array structure of the analog resistive processing unit (RPU) is known. In this RPU architecture, the unit cell adjusts the weighted connection strength of the artificial neural network synapses by changing the conductivity or the amount of stored charge according to the input pulse signal. This allows the artificial neural network synapses to simultaneously perform multiply-and-accumulate operations and weighted value storage.

[0003] Furthermore, artificial neural network synapses have different requirements for learning and inference tasks. Devices used for learning prioritize computational accuracy over non-volatility. Conversely, devices used for inference prioritize storing learned weighted values. This shift in device requirements based on computational function execution is similarly reflected in the storage devices of the widely used von Neumann computing architecture. While Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM), which retrieves programs from auxiliary storage and uses them as primary storage, are volatile, they possess high speed and wide bandwidth. Conversely, auxiliary storage focuses on storing completed computation data and large data volumes. Similarly, current storage devices also have different requirements and hierarchical structures to interact with computing devices.

[0004] On the other hand, the number of devices connected to the next-generation Internet of Things (IoT) network is projected to increase dramatically from 8 billion in 2017 to 70 billion in 2025. However, mobile devices and IoT devices lack deep neural network computing capabilities and rely on cloud or data server computing. In a hyper-connected information and communication society, there is a need to significantly reduce the power consumption required for data processing and communication. Therefore, in the era of the Fourth Industrial Revolution, represented by hyper-connectivity based on IoT and big data technologies, a new concept computing technology that minimizes power consumption and innovatively differentiates itself from existing methods is needed. Brain-like neural network simulation computing, as a next-generation computing solution required for artificial intelligence, big data, sensor networks, pattern / object recognition, etc., achieves high energy efficiency similar to the human brain by receiving large amounts of unstructured data.

[0005] To date, research on brain neural network simulation computing devices has primarily focused on utilizing variable resistive memory, phase-change memory, and ferroelectric memory to ensure the symmetry of multiple conductance levels and the linear increase and decrease characteristics of conductance. However, due to the non-ideal characteristics of experimental memory devices, hardware-implemented neural networks may significantly lag behind software-based deep neural networks in terms of recognition and classification accuracy. Although hardware implementations using analog memory offer the advantage of high energy efficiency, only training accuracy at the software level can maximize the advantages of neural network computational efficiency.

[0006] In previous studies, non-volatile storage devices were only suitable for weighted update training of synaptic devices and for inference to recognize and classify images, objects, sounds, etc. This is because the number of conductance levels required for effective training needs to reach 2. 10 There are more than 1,000 synapses, and the increase or decrease of synaptic weights needs to be symmetrical and linear. Therefore, existing storage devices have physical and technical limitations.

[0007] To improve this limitation, existing research has used software to perform training by moving synaptic weights to an analog memory array so that the hardware performs only inference functions. Summary of the Invention Technical issues

[0008] The technical objective of this invention is to provide a charge storage type synaptic device for training deep neural networks, which provides sufficient retention time and parallel on-chip training operations, in addition to linear and symmetric weighted value updates.

[0009] Furthermore, another object of the present invention is to provide a charge storage type synaptic device for training deep neural networks, which provides device-algorithm co-optimization by using an efficient and realistic training algorithm to compensate for residual device non-idealities such as drifting reference and long-term retention loss.

[0010] Furthermore, another object of the present invention is to provide a charge storage type synaptic device for training deep neural networks that achieves software-level on-chip learning capability and software-level accuracy by realizing symmetrical linear training characteristics.

[0011] The objectives of this invention are not limited to those mentioned above. Those skilled in the art to which this invention pertains can clearly understand other objectives not mentioned through the following description. Technical solution

[0012] According to an embodiment of the present invention, a charge storage type synaptic device for training a deep neural network includes: a weighted capacitor having a first terminal and a second terminal for storing a voltage corresponding to a weighting value; four control transistors for changing the voltage or weighting value of the capacitor; a first output transistor including a first gate terminal coupled to the first terminal of the capacitor, for outputting a first drain current according to a voltage applied to the first gate terminal; and a second output transistor including a second gate terminal coupled to the second terminal of the capacitor, for outputting a second drain current according to a voltage applied to the second gate terminal, wherein the weighting value can be read as the difference between the first drain current and the second drain current. Of the four control transistors, the first and third control transistors each have a first source terminal, including a pass transistor for transmitting a first voltage connected to the first source terminal to the weighted capacitor. Of the four control transistors, the second and fourth control transistors each have a second source terminal, including a transistor that serves as a current source based on the ground terminal connected to the second source terminal. The first and fourth control transistors each have a first drain terminal, which are connected to each other and connected to the first terminal of the weighted capacitor. The second and third control transistors each have a second drain terminal, which are connected to each other and can be connected to the second terminal of the weighted capacitor.

[0013] The first control transistor is connected between the first voltage and the first terminal of the weighted capacitor, and connects the first voltage to the first terminal of the weighted capacitor in response to a first control signal. The second control transistor is connected between the ground and the second terminal of the weighted capacitor, and connects the ground to the second terminal in response to a second control signal. The third control transistor is connected between the first voltage and the second terminal of the weighted capacitor, and connects the first voltage to the second terminal in response to a third control signal. The fourth control transistor is connected between the ground and the first terminal of the weighted capacitor, and connects the ground to the first terminal in response to a fourth control signal. The first output transistor has a third drain terminal and a third source terminal. The third drain terminal is connected to the first input line, and the third source terminal is connected to the first output line. The second output transistor has a fourth drain terminal and a fourth source terminal. The fourth drain terminal is connected to the second input line, and the fourth source terminal is connected to the second output line. The first drain current of the first output transistor is supplied by the first output line and depends on the voltage of the first terminal of the weighted capacitor, the voltage of the first input line, and the voltage of the first output line. The second drain current of the second output transistor can be supplied by the second output line and depends on the voltage of the second terminal of the weighted capacitor, the voltage of the second input line, and the voltage of the second output line. The second control transistor and the fourth control transistor can be subjected to an overdrive voltage that is relatively low compared to the first voltage.

[0014] In one embodiment, the weighting value is positively increased by enabling a potential update performed by the first and second control transistors, and negatively increased by enabling a depression update performed by the third and fourth control transistors. The weighting value may depend on the discharge current of the second or fourth control transistor, the pulse width applied to the second or fourth control transistor, and the capacitance of the weighting capacitor. The weighting value can be determined by reading the first drain current of the first output transistor by enabling the third control transistor and reading the second drain current of the second output transistor by enabling the first control transistor. The third drain current of the first output transistor is read using a reference read operation with the first control transistor turned on, and the fourth drain current of the second output transistor is read using a reference read operation with the third control transistor turned on. The difference between the third drain current and the fourth drain current is determined as the reference conductance. When the weighted capacitor has the reference conductance, the voltage V of the weighted capacitor is... cap It can be 0. At least one of the aforementioned potentiation update, depression update, read operation, and reference read operation can be reversed. A reset operation can be performed by turning on the second and fourth control transistors to adjust the voltage V of the weighted capacitor. cap The value is reset to 0. This reset can be performed before the inversion operation. The four control transistors, the first output transistor, and the second output transistor can be amorphous indium gallium zinc oxide (InGaZnO) field-effect transistors (FETs), polycrystalline InGaZnO FETs, monocrystalline InGaZnO FETs, or C-axis aligned InGaZnO FETs. The nonlinearity of the synaptic device can be adjusted according to the pulse conditions applied to the four control transistors.

[0015] According to another embodiment of the present invention, the driving method of the synaptic device is used in the synaptic device according to claim 1 to perform a reference read operation in the case of linear learning, and to perform the above-mentioned reference read operation, reset operation and invert operation in the case of nonlinear learning.

[0016] According to another embodiment of the present invention, a neural network learning method comprises a core device array and an auxiliary device array. The core device array includes M×N first synaptic devices, and the auxiliary device array includes M×N second synaptic devices as described in claim 1. The neural network learning method may include: a first step of generating output values ​​by applying forward propagation and back propagation to the core device array; a second step of applying pulses corresponding to the output values ​​from the core device array to the auxiliary device array to perform a first update; a third step of selecting a specific column of the auxiliary device array and generating output currents from the specific column after performing the first update; a fourth step of converting each output current into an input value of the core device array by performing read and reference read operations on each synaptic device of the specific column as described in claim 1; and a fifth step of performing a second update on the specific column of the core device array using the input values. The neural network learning method may further include the following steps: using each synaptic device of a specific column of the aforementioned auxiliary device array according to claim 1 to perform a reset or inversion operation according to a probability variable. In the case of linear learning, the aforementioned reset or inversion operation is not performed; in the case of nonlinear learning, the aforementioned reset or inversion operation may be performed. Alternatively, during the initial learning period, the aforementioned reset or inversion operation is not performed; after the initial learning period, the aforementioned reset or inversion operation may be performed. After the aforementioned fifth step, the first to fifth steps may be repeatedly performed on the remaining columns of the aforementioned core device array and the aforementioned auxiliary device array. The effects of the invention

[0017] According to an embodiment of the present invention, a charge storage synaptic device for deep neural network training has a 6T1C structure, comprising: a weighted capacitor; four control transistors for changing the voltage or weighting value of the capacitor; a first output transistor including a first gate terminal connected to a first terminal of the capacitor, outputting a first drain current according to the voltage applied to the first gate terminal; and a second output transistor including a second gate terminal connected to a second terminal of the capacitor, outputting a second drain current according to the voltage applied to the second gate terminal. Therefore, in addition to linear and symmetrical weighting updates, sufficient retention time and parallel on-chip training operations can be provided.

[0018] Furthermore, efficient and realistic training algorithms can be used to provide device-algorithm co-optimization in order to compensate for residual device non-idealities such as drifting references and long-term retention loss.

[0019] Furthermore, without utilizing existing analog memory devices, software-level on-chip learning capabilities and software-level accuracy can be improved by implementing symmetric linear training characteristics.

[0020] Furthermore, when applied to linear and nonlinear learning algorithms, the synaptic device of this invention can efficiently transfer the weighted values ​​accumulated by capacitor-based devices with leakage to non-volatile memory. Leveraging the advantages of the 6T1C device, the leakage converging conductance can be read even without the reference device array required for an auxiliary device array, thus improving integration density. Moreover, the reference reading of the leakage converging conductance exhibits robust characteristics in terms of retention time, thereby mitigating accuracy degradation caused by leakage.

[0021] Furthermore, in the case of linear learning, there is almost no accuracy degradation caused by asymmetry.

[0022] Furthermore, in the case of nonlinear learning, inversion can be performed randomly to improve accuracy degradation caused by asymmetry. In addition, the asymmetry of the transistors in the synaptic device 100 with a 6T1C structure can be compensated. Moreover, the weight regularization of the nonlinear device itself can be utilized.

[0023] However, the effects of the present invention are not limited to the above-described effects, and various extensions can be made without departing from the technical concept of the present invention. Attached Figure Description

[0024] Figure 1a This is a conceptual diagram of the brain neural simulation computing system according to an embodiment of the present invention.

[0025] Figure 1b for Figure 1a The circuit diagram of the synaptic device 100 shown is shown.

[0026] Figure 2a This diagram illustrates the structure and fabrication method of an indium gallium zinc oxide (IGZO) thin-film transistor (TFT) according to an embodiment of the present invention.

[0027] Figure 2b The figure illustrates the structure and fabrication method of the capacitor device in the embodiments of the present invention.

[0028] Figure 3a This is a schematic diagram illustrating the operation of the synaptic device 100 of the present invention performing a potentiation update to increase the weighting value.

[0029] Figure 3b This is a schematic diagram illustrating the operation of the synaptic device 100 of the present invention performing a potentialization update to reduce the weighting value.

[0030] Figure 3c and Figure 3d This is a schematic diagram illustrating the reading operation of the synaptic device 100 of the present invention.

[0031] Figure 3e and Figure 3f This is a schematic diagram illustrating the reference read operation of the synaptic device 100 of the present invention.

[0032] Figure 3g This is a schematic diagram illustrating the reset method of the synaptic device 100 of the present invention.

[0033] Figures 4a to 4e This diagram illustrates the learning method of the core device of the linear synaptic device (6T1C) of the present invention.

[0034] Figures 5a to 5f This diagram illustrates the learning method of the core device of the synaptic device (6T1C) with nonlinear characteristics utilizing the present invention.

[0035] Figure 6 An image of a printed circuit board (PCB) used for measuring the synaptic device in an embodiment of the present invention.

[0036] Figure 7a This is a graph showing the weighted value update result of a single synaptic device with a 6T1C structure according to an embodiment of the present invention.

[0037] Figure 7b This is a graph illustrating the weighted value update curve of an embodiment of the present invention.

[0038] Figure 7c A graph illustrating the retention characteristics of a single synaptic device with a 6T1C structure according to an embodiment of the present invention.

[0039] Figure 7d A graph showing the measurement results during the initial cycle for determining the cyclic durability of a single synaptic device with a 6T1C structure according to an embodiment of the present invention.

[0040] Figure 7e To apply 10 to the single synaptic device with a 6T1C structure according to an embodiment of the present invention 9 The measurement results curve obtained from each update pulse.

[0041] Figure 8a This is a flowchart for linear regression training according to an embodiment of the present invention. Figure 8b This is a graph showing the overall training loss and error evaluation results of an embodiment of the present invention.

[0042] Figure 9a This is a graph showing the results of conductivity-conductivity change patterns obtained under various measurement conditions according to an embodiment of the present invention.

[0043] Figure 9b The graph illustrates the accuracy of the synaptic device with a 6T1C structure according to an embodiment of the present invention, reflecting multiple values ​​within the NL range and representing the device's accuracy according to the retention characteristics of the existing Tiki-taka algorithm.

[0044] Figure 9cThe graph illustrates the accuracy of the device according to the retention characteristics when the present invention is applied at NL=0.2 and NL=2.0 according to the embodiments of the present invention.

[0045] Figure 10 This is a diagram illustrating the reference conductance setting method of an embodiment of the present invention.

[0046] Figure 11a and Figure 11b The graph shows the results of comparing the present invention with existing linear learning results in the LENET5 and MLP models.

[0047] Figure 12a and Figure 12b The graphs show the results of comparing nonlinear learning outcomes with and without performing inversion and reset operations on the LENET5 model. Detailed Implementation

[0048] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0049] In the following description, the embodiments of the present invention are intended only to enable those skilled in the art to further understand the present invention. The scope of the present invention is not limited to the following embodiments, and the following embodiments can be modified into various different implementation methods.

[0050] In this specification, the terminology used is for illustrative purposes only and is not intended to limit the invention. Unless otherwise expressly indicated in the context, the singular form may include the plural form in the terminology used herein. Furthermore, the terms "comprise" and / or "comprising" as used herein are used to specify the presence of mentioned shapes, steps, numbers, operations, components, elements, and / or combinations thereof, and do not exclude the presence or addition of more than one other shape, step, number, operation, component, element, and / or combination thereof. Moreover, the term "connection" as used herein not only means a direct connection between components but also includes indirect connections between components involving other components.

[0051] The terms "first" or "second" can be used to describe various structural elements; however, the aforementioned structural elements are not limited to these terms. These terms are used only to distinguish one structural element from others. For example, without departing from the scope of the invention based on the concept of this invention, a first structural element may be named a second structural element, and similarly, a second structural element may be named a first structural element.

[0052] Furthermore, in the specification of this application, when it is stated that a component is "on" another component, this not only indicates that the component is in contact with the other component, but also includes the situation where other components exist between the two components. In this specification, the term "and / or" includes one or more of the corresponding listed items in all combinations. Also, in the specification of this application, terms indicating degree such as "about," "actual," etc., represent inherent permissible errors in preparation and materials, and are used as a range or approximate meaning of their numerical values ​​or degrees, solely to prevent infringers from improperly using the disclosure of accurate or absolute numerical values ​​provided to aid in understanding this application.

[0053] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings. To ensure clarity and ease of explanation, the dimensions or thicknesses of the areas or portions shown in the drawings may be enlarged. Throughout the specification, the same reference numerals denote the same structural elements.

[0054] The present invention will now be described in detail with reference to the accompanying drawings, which will be based on preferred embodiments of the invention.

[0055] Figure 1a This is a conceptual diagram of the brain neural simulation computing system according to an embodiment of the present invention. As a structural diagram of the neurons and synapses required for brain neural simulation computing, the presynaptic neuron sends input data (voltage) to a crisscrossing array of synaptic units and reads the current value (I = GV, where G stores the conductance value of each synapse according to the array configuration) from the postsynaptic neuron. The update method for the conductance value of each synapse can be determined by forward / backward propagation according to the neural network computing method, or, locally using spike-timing dependent plasticity learning rules, etc.

[0056] Reference Figure 1a The brain neural simulation computing system 10 includes presynaptic neurons (N... pre1 To N prem Postsynaptic neurons (N) post1 To N postn ) and multiple synaptic devices 100.

[0057] exist Figure 1a In the text, for ease of explanation, although the connection to the presynaptic neuron N... pre1 To the presynaptic neuron N prem The line is represented as input line I. L1 To input line I Lm This will connect to the postsynaptic neuron N post1 To the postsynaptic neuron Npostn The line is represented as output line O. L1 To output line O Ln However, this is only used to distinguish the connections between presynaptic neurons N pre1 To the presynaptic neuron N prem The lines and connections in the postsynaptic neuron N post1 To the postsynaptic neuron N postn The line.

[0058] For example, when the input value is transmitted from the presynaptic neuron N via the synaptic device 100... pre1 To the presynaptic neuron N prem Transmission to postsynaptic neuron N post1 To the postsynaptic neuron N postn During the forward propagation operation, input line I... L1 To input line I Lm Used as input line, output line O L1 To output line O Ln It can be used as an output line.

[0059] Conversely, the input value is transmitted from the postsynaptic neuron N via the synaptic device 100. post1 To the postsynaptic neuron N postn Transmission to presynaptic neuron N pre1 To the presynaptic neuron N prem During the backward propagation process, input line I... L1 To input line I Lm Used as an output line, output line O L1 To output line O Ln It can be used as an input line.

[0060] Unless otherwise stated, the above forward propagation process is assumed to illustrate the concept of the present invention; however, the concept of the present invention is not limited thereto.

[0061] Synaptic device 100 is located in presynaptic neuron N pre1 To the presynaptic neuron N prem One of them is related to the postsynaptic neuron N post1 To the postsynaptic neuron N postn Between one of them.

[0062] Although not in Figure 1a As shown, however, the synaptic device 100 receives control signals from an external circuit (not shown).

[0063] During training, an external circuit (not shown) updates the weighting value of the synaptic device 100 by repeatedly outputting control signals to it. In other words, the external circuit (not shown) can strengthen or weaken the synaptic device 100 by outputting control signals with a specified waveform to it.

[0064] When training the brain neural simulation computing system 10, the external circuit (not shown) connects the capacitors included in the synaptic device 100 described below. Figure 1b The voltage V across C1) cap If the target voltage is set, the strengthening or weakening operation can be repeated multiple times according to the number of times corresponding to the difference between the charging voltage and the target voltage.

[0065] Figure 1b It shows Figure 1a The circuit diagram of the synaptic device 100 is shown. Non-limitingly, the synaptic device 100 is connected between one of the presynaptic neurons and one of the postsynaptic neurons constituting the brain neural simulation system 10, and can store / update / read synaptic weighted values.

[0066] Reference Figure 1b The single-synaptic device 100 may consist of six transistors (N1 to N6) and one capacitor (hereinafter referred to as "6T1C"). The weighted capacitor C1 serves as a memory within the cell, storing the weighted value as a charge. Two of the six transistors (N1 to N6) are output transistors (N5 and N6) used as read FETs to perform read operating and reference read operating on the weighted value stored in capacitor C1. The remaining four control transistors (N1 to N4) perform potentiation update and depression update to change the capacitor voltage V. cap The work involves changing the voltage V across the weighted capacitor C1 (T1, T2). cap During the process, the first control transistor N1 and the third control transistor N3 are used as pass-gate field-effect transistors (FETs) to transmit the first voltage V. dd / 2 The first terminal T1 and the second terminal T2 of the weighted capacitor C1 are transferred from the drain terminal D. The second control transistor N2 and the fourth control transistor N4 can be used as current source field-effect transistors to discharge constant current.

[0067] Specifically, the weighted capacitor C1 includes a first terminal T1 and a second terminal T2, and can store a voltage corresponding to the weighted value. The weighted value can be equivalent to the voltage difference between the first terminal T1 and the second terminal T2. This voltage difference refers to the voltage V applied to the first terminal T1. CP With the voltage V applied to the second terminal T2 CN difference.

[0068] Four control transistors (N1 to N4) change the voltage V of the weighted capacitor C1. cap Alternatively, with control transistors N1, N2, and N4 off and only control transistor N3 on, the first output transistor N5 outputs a first read current corresponding to the weighted value of the weighting capacitor. With only control transistor N1 on and control transistors (N2 to N4) off, the second output transistor N6 can also output a second read current corresponding to the weighted value of the weighting capacitor. Furthermore, the first output transistor N1 includes a first gate terminal G1 connected to the first terminal T1 of capacitor C1, and the second output transistor N2 includes a second gate terminal G2 connected to the second terminal T2 of capacitor C1. The four control transistors (N1 to N4) can respectively receive control signals S1, S2, S3, and S4 through their gate terminals.

[0069] The first control transistor N1 and the third control transistor N3 have a first source terminal S1, including a first voltage V connected to the source terminal S1 for transmitting to the capacitor C1. dd The pass transistors N2 and N4 have a second source terminal S2 and may include a transistor that serves as a current source based on the ground terminal GND connected to the second source terminal S2. The first control transistor N1 and the fourth control transistor N4 include a first drain terminal D1 connected to the first terminal T1 of the capacitor C1. The second control transistor N2 and the third control transistor N3 include a second drain terminal D2, which may be connected to the second terminal T2 of the capacitor C1.

[0070] Furthermore, the first control transistor N1 is connected to the first voltage V. dd / 2 is connected between the capacitor C1 and the first terminal T1, and the first voltage can be connected to the first terminal T1 of the capacitor in response to the first control signal S1. The second control transistor N2 is connected between the ground GND and the second terminal T2 of the capacitor C1, and the ground can be connected to the second terminal T2 in response to the second control signal S2. The third control transistor is connected to the first voltage V ddBetween / 2 and the second terminal T2 of capacitor C1, the first voltage V can be maintained in response to the third control signal S3. dd / 2 is connected to the second terminal T2 of capacitor C1. The fourth control transistor N4 is connected between the ground GND and the first terminal T1 of capacitor C1, and can connect the ground GND to the first terminal T1 in response to the fourth control signal S4.

[0071] The first output transistor N5 has a third drain terminal D3 and a third source terminal S3. The third drain terminal D3 is connected to a first input line WLU connected to a presynaptic neuron, and the third source terminal S3 is connected to a first output line BLU connected to a postsynaptic neuron. The second output transistor N6 has a fourth drain terminal D4 and a fourth source terminal S4. The fourth drain terminal D4 is connected to a second input line WLD connected to a presynaptic neuron, and the fourth source terminal S4 is connected to a second output line BLD connected to a postsynaptic neuron.

[0072] The first read current of the first output transistor N5 can be supplied by the first output line BLU, depending on the voltage V at the first terminal T1 of capacitor C1. CP The voltage of the first input line WLU and the voltage of the first output line BLU. The second read current of the second output transistor N6 can be supplied by the second output line BLD, depending on the voltage V at the second terminal T2 of the capacitor. CN The voltage of the second input line WLD and the voltage of the second output line BLD.

[0073] To realize a charge storage device with reasonable device size without sacrificing learning accuracy and meeting retention requirements, the capacitor area needs to be reduced based on sufficiently small transistor leakage current. For this purpose, the present invention uses an indium gallium zinc oxide thin-film transistor (IGZO TFT) with sufficient mobility and extremely low leakage current characteristics. IGZO TFTs have a larger bandgap than silicon, operate in accumulation mode, and are suitable for use as intrinsic N-channel transistors (NMOS) due to almost no hole tunneling gate leakage current and a large effective hole mass. Non-limitingly, IGZO TFTs can also be used as P-channel transistors (PMOS) by changing the dopant. Furthermore, the weighted capacitor C1 includes a metal-insulator-metal (MIM) capacitor, which can be fabricated by depositing a high-k dielectric insulator using an atomic layer deposition (ALD) process. The amount of charge that the capacitor can store and the leakage current depend on the material properties of the metal material acting as the electrodes and the high-k dielectric material acting as the insulator, as well as the structure of the fabricated capacitor and the voltage conditions applied across the capacitor. In this case, to improve the retention characteristics of the capacitor in effectively storing charge, a high-gap material that can increase the dielectric constant of the insulator while controlling various leakage current mechanisms can be used.

[0074] Furthermore, after the training of the synaptic device 100 is completed, only the weighted values ​​set in the synaptic device 100 can be retained for inference based on the learning results. These weighted values ​​are stored as the voltage across capacitor C1 (V). cap =V CP -V CNTherefore, the turn-off current of the first control transistor N1 to the fourth control transistor N4 is relatively low, that is, the lower the leakage current in the turn-off state, the better. Preferably, the first control transistor N1 to the fourth control transistor N4 and the first output transistor N5 to the second output transistor N6 are amorphous indium gallium zinc oxide field-effect transistors (InGaZnO FETs), polycrystalline indium gallium zinc oxide field-effect transistors (InGaZnO FETs), or monocrystalline indium gallium zinc oxide field-effect transistors (InGaZnO FETs), or they can be metal oxide transistors containing at least one element selected from In, Ga, Zn, Sn, Al, Hf, Zr, Si, and O. In particular, the off-current of the C-axis grown indium gallium zinc oxide field-effect transistor (InGaZnO FET) is about 10-24 [A / μm], because the leakage current component caused by the multi-carrier accumulation mode operation of the metal oxide transistor, the high band gap, the sub-gap state near the valence band, and the high hole effective mass is blocked at the source.

[0075] The following is for reference Figures 3a to 3g This section details the update, read, reference read, invert, and reset operations of the synaptic device 100. A positive update refers to a positive update of the capacitor voltage, storing positive charges in the synaptic device according to the direction of strengthening synaptic connection strength based on the synaptic weighting values ​​of the artificial neural network. A negative update refers to a negative update of the capacitor voltage, storing negative charges in the synaptic device according to the direction of weakening synaptic connection strength based on the synaptic weighting values ​​of the artificial neural network.

[0076] Figure 2a This diagram illustrates the structure and fabrication method of an indium gallium zinc oxide (IGZO) thin-film transistor (TFT) according to an embodiment of the present invention.

[0077] Reference Figure 2aCharge storage synaptic devices that perform weighted value updates can be fabricated using indium gallium zinc oxide thin-film transistors (N1 to N6) with excellent low leakage current characteristics. Non-limitingly, the indium gallium zinc oxide thin-film transistors have a top-gate staggered structure. Furthermore, to deposit amorphous indium gallium zinc oxide (IGZO), an assembled sputtering apparatus is used in an atmosphere of 1 Pa Ar 100 sccm at a speed of 2.44 W / cm². 2 RFBias sputters In:Ga:Zn = 1:1:1 target material.

[0078] Specifically, the fabrication method of indium gallium zinc oxide thin-film transistor devices may include a silicon substrate oxidation process using wet oxidation (approximately...). Thick oxide layer), metal evaporation (approximately) The process includes: a tungsten (W) metal layer of approximately 10 nm thickness; source and drain patterning and dry etching; channel evaporation using sputtering (e.g., amorphous indium gallium zinc oxide approximately 10 nm thick); gate insulating layer evaporation using atomic layer deposition (ALD) (e.g., hafnium oxide approximately 10 nm thick); and gate terminal forming (e.g., approximately...). (Thickness of tungsten (W) metal layer).

[0079] In this context, to effectively control the hydrogen concentration in indium gallium zinc oxide (IGZO), IGZO thin-film transistors can be fabricated after the capacitor devices are prepared. This is to prevent the hydrogen generated during the trimethylaluminum (TMA)-based atomic layer deposition (ALD) process from affecting the characteristics of the IGZO channels and thus degrading the performance of the IGZO thin-film transistors. Excessive hydrogen injection into the IGZO channels will increase conductivity with the increase in electron carriers; therefore, ensuring effective control of the process conditions is crucial.

[0080] Figure 2b The figure illustrates the structure and fabrication method of the capacitor device in the embodiments of the present invention.

[0081] Reference Figure 2b The weighted values ​​of the charge storage synaptic device can be stored in capacitor C1 via an indium gallium zinc oxide (IGNI) thin-film transistor. In this study, a high dielectric was used to ensure no problematic high capacitance levels during the verification of the new synaptic structure using IGNI. Metal-Insulator-Metal (MIM) capacitors. High dielectric strength. The application of a trimethylaluminum-based source and an O3 reactant in approximately Evaporation in the middle.

[0082] Specifically, the method for fabricating capacitor devices may include a silicon substrate oxidation process using wet oxidation (approximately...). Thick oxide layer), lower electrode layer vapor deposition (approximately) The process includes: a thick tungsten (W) metal layer, lower electrode patterning and dry etching, gate insulating layer deposition using atomic layer deposition (e.g., hafnium oxide approximately 10 nm thick), and upper electrode layer deposition (approximately...). The process involves a tungsten (W) metal layer of appropriate thickness, patterning of the upper electrode, and dry etching. In this case, a high-permeability oxide, used as the capacitor insulator, is deposited to the desired thickness via atomic layer deposition (ALD). The capacitor, using a suitable high-permeability material, can be fabricated considering the capacitance and leakage current requirements of the synaptic capacitor.

[0084] Figure 3a This is a schematic diagram illustrating the operation of the synaptic device 100 of the present invention performing a potentiation update to increase the weighting value. Figure 3b This is a schematic diagram illustrating the operation of the synaptic device 100 of the present invention performing a potentialization update to reduce the weighting value.

[0085] Reference Figure 3a During the potentiation update, a pulse is applied to the gate terminal G of the first control transistor N1 to apply voltage V to the first terminal T1 of the weighted capacitor C1. CP (upper terminal voltage) becomes V dd After / 2, a pulse can be applied to the gate terminal G of the second control transistor N2 to positively increase the potential difference V across the weighting capacitor C1. cap (V CP -V CN ).

[0086] The 6T1C structure lacks a PMOS transistor, requiring only NMOS transistors to form the synaptic device structure. To ensure linear and asymptotic update characteristics, the source of the NMOS transistor needs to be at a fixed voltage. In the 6T1C structure, transistor N1 operates to cause the lower node voltage V of the capacitor to... CNThe effect of the voltage being higher than or equal to the ground terminal helps the first transistor N2 to perform weighted value updates according to a constant gate pulse voltage. The second control transistor N2, connected between the lower node T2 of capacitor C1 and the ground node GND, performs updates via pulsed current. Due to the enhanced potency enable of the first control transistor N1, the voltage V at the upper node of the capacitor is increased. CP Boost up to V dd / 2, therefore, the capacitor voltage change can be enhanced to +V. dd / 2.

[0087] Reference Figure 3b During the depression update, a pulse is applied to the gate terminal G of the third control transistor N3 to apply voltage V to the second terminal T2 of the weighted capacitor C1. CN (lower terminal voltage) becomes V dd After / 2, a pulse can be applied to the fourth control transistor N4 to negatively reduce the potential difference V across the weighting capacitor C1. cap (V CP -V CN ).

[0088] In other words, by turning on the third control transistor N3, the voltage V at the lower node of capacitor C1 is... CN Boost up to V dd / 2 to prevent the voltage V at the upper node of capacitor C1 CP Below ground (Depression Enable). The fourth control transistor N4, connected between the upper node T1 of capacitor C1 and the ground node GND, performs an update via a pulsed current. Due to the depression enable of the third control transistor N3, the voltage V at the lower node of the capacitor is reduced. CN Boost up to V dd / 2, therefore, the capacitor voltage change can be reduced to -V dd / 2.

[0089] During the potentiation and depression updates, if probability pulses of control transistors N1 (N3) and N2 (N4) are generated simultaneously, a weighted update can be performed and the voltage change for each update can be calculated according to the following [Mathematical Formula 1].

[0090] [Mathematical Expression 1]

[0091]

[0092] Among them, i N2，N4 i N2，N4 The discharge currents t and t are the control transistors N2 and N4, respectively. pw t pw The pulse width applied to the control transistor N2 (N4) is C, and C is the capacitance of capacitor C1.

[0093] Figure 3c and Figure 3d This is a schematic diagram illustrating the read operation of the synaptic device 100 of the present invention. The read operation can be divided into a process of reading the current flowing through the first output transistor N5 and the second output transistor N6.

[0094] Reference Figure 3c In order for the first output transistor N5 to read out, a pulse is applied to the third control transistor N3 to change the voltage at the upper node T1 and the lower node T2 of capacitor C1 to V respectively. dd / 2+V cap and V dd / 2. When V is applied to the gate terminal G of the first output transistor N5 dd / 2+V cap Under voltage conditions, a small bias voltage can be applied between the source (S) and drain (D) of the first output transistor N5 to determine the first weighted current I. N5 That is, the upper node T1 of capacitor C1 is connected to the gate terminal G of the first output transistor N5, and a voltage of less than 0.1V can be applied to the drain terminal D of the first output transistor N5 to generate a drain current of the first output transistor N5 that varies with the potential difference across the capacitor. In this case, as a pulse voltage is applied to the gate terminal G of the third control transistor N3 and a voltage of V is applied to the lower node T2 of capacitor C1... dd A voltage of / 2 is used to make the first output transistor N5 operate in the triode region, which allows the first current I to... N5 It can operate linearly according to the gate voltage.

[0095] Reference Figure 3d When reading the first weighted current I mentioned above N5_ref Then, the reading operation of the second output transistor N6 can be performed. To enable the reading operation of the second output transistor N6, a pulse is applied to the first control transistor N1 to change the voltage at the upper node T1 and the lower node T2 of capacitor C1 to V respectively. dd / 2 and V dd / 2-V capWhen V is applied to the gate terminal G of the second output transistor N6 dd / 2-V cap Under voltage conditions, a small bias voltage can be applied between the source (S) and drain (D) of the second output transistor N6 to measure the second current I. N6 That is, the lower node T2 of capacitor C1 is connected to the gate terminal G of the second output transistor N6, and a voltage less than 0.1V can be applied to the drain terminal D of the second output transistor N6 to generate a drain current of the second output transistor N6 that varies with the potential difference across the capacitor. In this case, as a pulse voltage is applied to the gate terminal G of the first control transistor N1 and a voltage of V is applied to the upper node T1 of capacitor C1... dd A voltage of / 2 is used to make the second output transistor N6 operate in the triode region, which allows the second weighted current I to... N6 It can operate linearly according to the gate voltage.

[0096] In this case, in order to represent both positive and negative weighted values, the following mathematical formula 2 can be used to calculate the first current I. N5 Subtract the second current I N6 To define the weighted value W ij .

[0097] [Mathematical Expression 2]

[0098] E ij =I ijN5 -I ijN6 (2)

[0099] Where i and j represent the rows and columns of the array, I ijN5 Represents the first weighted current I in the corresponding array. N5_ref I ijN6 Represents the second weighted current I in the corresponding array N6_ref .

[0100] Figure 3e and Figure 3f This is a schematic diagram illustrating the reference read operation of the synaptic device 100 of the present invention. (V) cap_ij When V = 0, the matched voltage is called a reference. The above reference reading operation refers to... cap_ij The operation involves reading the matching voltage when the voltage is 0.

[0101] Figure 3e and Figure 3f This is a schematic diagram illustrating the reference reading operation of the synaptic device 100 of the present invention.

[0102] Reference Figure 3e In order for the reference read operation of the first output transistor N5, a pulse is applied to the first control transistor N1 to change the voltage at the upper node T1 of capacitor C1 to V. dd / 2. When V is applied to the gate terminal G of the first output transistor N5 dd Under a voltage of / 2, a small bias voltage can be applied between the source S and drain D of the first output transistor N5 to determine the first reference current I. N5_ref That is, the upper node T1 of capacitor C1 is connected to the gate terminal G of the first output transistor N5. When a voltage less than 0.1V is applied to the drain terminal D of the first output transistor N5, the voltage V applied to the gate terminal G of the first output transistor N5 can be released. dd The voltage is 2 / 2 to generate the drain current flowing through the first output transistor N5.

[0103] Reference Figure 3f When reading the first reference current I mentioned above N5_ref Then, the reference read operation of the second output transistor N6 can be performed. To enable the reference read operation of the second output transistor N6, a pulse is applied to the third control transistor N3 to change the voltage at the lower node T2 of capacitor C1 to V. dd / 2. Applying V to the gate terminal G of the second output transistor N6 dd Under a voltage of / 2, a small bias voltage can be applied between the source S and drain D of the second output transistor N6 to measure the second reference current I. N6_ref That is, the lower node T2 of capacitor C1 is connected to the gate terminal G of the second output transistor N6. When a voltage less than 0.1V is applied to the drain terminal D of the second output transistor N6, the voltage V applied to the gate terminal G of the second output transistor N6 can be increased. dd The voltage is 2 / 2 to generate the drain current flowing through the second output transistor N6.

[0104] Among them, with the calculation of the first reference current I N5_ref With the second reference current I N6_ref The difference can be read when the capacitor has no accumulated charge, that is, at V. capThe conductance in the state of =0 (hereinafter referred to as "reference conductance" or "leakage converging conductance") can be read even without an additional reference array. The present invention can stably read the "reference conductance" using leakage converging conductance in a 6T1C structure device.

[0105] Furthermore, the 6T1C structure device 100 of the present invention can perform inverting operation. Specifically, Figure 3a The enhancement update work can be performed by turning on the first transistor N1 and the second transistor N2. Figure 3b The depression update operation can be performed by turning on the third control transistor N3 and the fourth control transistor N4. The potency update operation is performed by turning on the third control transistor N3 and the fourth control transistor N4 in reverse order. Figure 3b The depression update operation can be performed by turning on the first transistor N1 and the second transistor N2.

[0106] Similarly, the first weighted current I is read by turning on the third control transistor. N5 back, Figure 3c and Figure 3d The read operation can be performed by turning on the first transistor to read the second weighted current I. N6 To execute this, the second weighted current I is read by turning on the first transistor through inversion. N6 Subsequently, the read operation can be performed by turning on the third control transistor to read the first weighted current I. N5 To execute.

[0107] Similarly, the first reference current I is read by turning on the first transistor. N5_ref back, Figure 3e and Figure 3f The reference read operation can be performed by turning on the third control transistor to read the second reference current I. N6_ref To execute this, the second reference current I is read by turning on the third control transistor through inversion.N6_ref Subsequently, the reference read operation can be performed by turning on the first transistor to read the first reference current I. N5_ref The control transistors (N1 to N4) and output transistors N5 and N6 are used to perform the above-mentioned update operation, read operation, reference read operation, and invert operation. The on / off operation is shown in Table 1 below.

[0108] [Table 1]

[0110] By performing the invert operation, the values ​​of symmetry conductance and leakage converging conductance are different, which improves the accuracy degradation that may occur due to asymmetry when performing the reference read operation. Furthermore, it can compensate for transistor variations within the device. Moreover, it increases integration density without requiring an additional reference array.

[0111] Figure 3g This is a schematic diagram illustrating the reset method of the synaptic device 100 of the present invention.

[0112] Reference Figure 3g If only the second control transistor N2 and the fourth control transistor N4 are turned on, the capacitor can be reset to V as the charge accumulated in the weighted capacitor C1 disappears. cap =0V. Preferably, the reset operation is performed before the inversion operation. This is to prevent the weighted value sign corresponding to the previously accumulated charge from being inverted and read when the reset operation is performed after the inversion operation.

[0113] Figures 4a to 4eThis diagram illustrates the learning method of the core device of the linear synaptic device (6T1C) of the present invention. Linear and nonlinear learning can be performed by a core device array (or inference cell array) and an auxiliary device array, each consisting of multiple synaptic devices arranged in a column (N) × row (M) array. Here, M and N are natural numbers. Furthermore, the synaptic devices in the core device array and the auxiliary device array can be the same or different. Preferably, existing synaptic devices are used as the synaptic devices in the core device array, and the 6T1C device described above can be used as the synaptic devices in the auxiliary device array. Alternatively, the 6T1C device described above can be used for both the core device array and the auxiliary device array.

[0114] Reference Figure 4a First, the core device array can obtain output values ​​using forward propagation and back propagation. Specifically, the core device array outputs a forward output value fo by inputting a first input value (input(x)) and outputs a backward output value bo by inputting a second input value (Delta(d)). The aforementioned backward output value bo can be the error of the back propagation. The algorithm for determining the update amount using forward propagation and back propagation can refer to existing known techniques.

[0115] Reference Figure 4b ,exist Figure 4aSubsequently, as the core device array generates pulses based on the input values ​​(x, d) obtained through forward and backward propagation, the auxiliary device array (6T1C array) can perform updates. That is, with the aforementioned pulses proportional to the x, d values ​​input to the auxiliary device array, a fully-parallel update can be performed via pulse overlap. Typically, resistive processing units (RPUs) update techniques can be employed.

[0116] Reference Figure 4c ,exist Figure 4b After the update, the output current can be obtained from the individual devices in a specific column of the auxiliary device array by selecting that column via input. For example, in Figure 4c In this process, a predetermined pulse voltage V is supplied to the first column, and a 0V pulse voltage is supplied to the remaining columns. This can be achieved from the device G configured in the first column. 11 G 21 、◎、G M1 Obtain the output currents I1, I2, ◎, I M Wherein, p = Ouput(I1, I2...I...) is defined. M ) × transfer_learning_rate. transfer_learning_rate is the transfer learning rate. The above output currents I1, I2...I M It is possible Figure 4d Public read operations and reference read operations are converted to p.

[0117] Reference Figure 4d 1-(a) and 2-(a) are the above Figure 3c and Figure 3d The reading operation, 2-(a) and 2-(b) are as described above. Figure 3e and Figure 3f The reference reading operation described above. The detailed explanation of the reference reading operation described above can be applied to... Figures 3c to 3f The detailed work. The post-processing operation used for the above p conversion can be (Output) 1-(a) - Output 2-(a) )-(Output 1-(b) - Output 2-(b) (Hereinafter referred to as the first operation) or (Output)1-(a) +Output 1-(b) )-(Output 2-(a) +Output 2-(b) (Hereinafter referred to as the second operation).

[0118] Among them, Output 1-(a) The output current I from the circuit 1-(a) is... N5 Output 1-(b) The output current I from the circuit 1-(b) is... N6_ref Output 2-(a) The output current I from the circuit in 2-(a) is... N6 Output 2-(b) The output current I from the circuit in 2-(b) is... N5_ref Preferably, the result of the first operation and the result of the second operation can be the same. In the second operation, (Output) 1-(a) +Output 1-(b) The term refers to the simultaneous execution of circuit operation 1-(a) and circuit operation 1-(b). (Output) 2-(a) +Output 2-(b) The term refers to the simultaneous execution of circuit operations 2-(a) and 2-(b). In the second operation described above, since operations are performed simultaneously whenever a read occurs, the time consumed by the read operation can be reduced. However, there are also cases where reading a reference is unnecessary during each read operation. Considering circuit operation issues, simultaneous reads need to be limited. Therefore, in the first operation described above, operations can be performed according to (Output)... 1-(a) - Output 2-(a) ) items and (Output) 1-(b) - Output 2-(b) Each item performs a read operation. For example, after circuit 1-(a) operates, circuit 2-(a) can be operated, or after circuit 1-(b) operates, circuit 2-(b) can be operated.

[0119] Reference Figure 4e The column in the core cell array at the same position as the selected column in the auxiliary device array can be updated proportionally to p. If p > 0, it is potentiation; if p < 0, it is depression. For example, in Figure 4dIn the example, the device G in the first column of the core unit array can be proportional to p. 11 G 21 ...G M1 The weighted value is updated. The above p can be obtained through... Figure 4d The values ​​obtained from the publicly disclosed circuit operation. If the core device array and auxiliary device array have completed updating the first column, then the above process can be repeated for the second to Nth columns. Figures 4a to 4e .

[0120] Figures 5a to 5f This diagram illustrates the learning method of the core device of the synaptic device (6T1C) with nonlinear characteristics utilizing the present invention. Because... Figures 5a to 5c and Figures 4a to 4c They are the same, therefore, unless they contradict each other, they can be referred to. Figures 4a to 4c Explanation.

[0121] In the aforementioned read scenario, during the reading of leakage converging conductance, if the device is nonlinear, an unexpected force may arise during the update process, changing the conductance to symmetry conductance. Due to this unexpected force within the device, the device cannot be configured according to the desired conductance, thus leading to accuracy degradation. Therefore, the accuracy degradation caused by the difference between the leakage converging conductance and the symmetry conductance is not due to the convergence of the leakage converging conductance and the symmetry conductance to zero. This can be compensated for by randomly inverting the directionality of the conductance to become symmetry conductance.

[0122] Specifically, when the device itself has a symmetrical conductance (weight > 0) > leakage convergence conductance (representing weight = 0), the weight may have an unexpected tendency to increase positively as updates are performed. However, through the inverting process of the present invention, the aforementioned symmetrical conductance can be expressed as a weight < 0, thus periodically offsetting the unexpected directional change in weight.

[0123] In one embodiment, a reset or reversal operation can be performed by generating random numbers and using those random numbers to calculate probabilities. Figure 5d It can be executed or not executed selectively based on probability.

[0124] Figure 5d The reset work is the same as the above. Figure 3g The reset process is the same, therefore, unless they contradict each other, refer to [reference needed]. Figure 3g The reset instructions are as follows. Furthermore, Figure 5d The reversal process is the same as the reversal process in Table 1 above. Therefore, unless there are contradictions, please refer to the reset process instructions in Table 1 above.

[0125] then, Figure 5e The output current is converted to p by reading the work and referencing the read work. Figure 4d They are the same, therefore, unless they contradict each other, they can be referred to. Figure 4d Reset instructions.

[0126] Subsequently, Figure 5f The output current is converted to p by reading the work and referencing the read work. Figure 4e They are the same, therefore, unless they contradict each other, they can be referred to. Figure 4e Update notes for the core device array.

[0127] In yet another embodiment, Figure 5d The reset or reverse job can be done Figure 5f Execution later or during core device array updates ( Figure 5f )implement.

[0128] In existing methods, a neural network consists of a core device array and an auxiliary device array, both having the same dimension. The conductance of the reference device needs to be initialized using the linear conductance of the auxiliary devices, and the auxiliary devices themselves also need to be initialized with symmetrical conductance. Therefore, an additional reference device array is essential. Furthermore, in existing methods, since pulses increasing and decreasing conductance need to be alternately applied to all auxiliary devices, there is an inconvenience in initializing symmetrical conductance.

[0129] However, the device with a 6T1C structure disclosed in this invention can utilize a driving algorithm including the aforementioned device's weighted value update operation (potentiation, depression), read operation, reference read operation, invert operation, and reset operation to obtain the features described below, thereby solving the existing problems.

[0130] First, if the synaptic device 100 of the present invention is applied to linear learning algorithms and nonlinear learning algorithms, the weight accumulated by the capacitor-based device with leakage can be effectively transferred to non-volatile memory. Taking advantage of the 6T1C device, the leakage converging conductance can be read even without the reference device array required by the auxiliary device array, thus improving the integration density.

[0131] Furthermore, the higher the nonlinearity of the device, the more it is subjected to the force of symmetry conductance with repeated updates. In existing methods, the corresponding force is made into a weighted value = 0 (weighted value = conductance - reference conductance (symmetry conductance)) by changing the reference conductance to symmetry conductance. However, apart from symmetry issues, the 6T1C device of the present invention may have factors that prevent the conductance from changing due to retention issues. If the linearity of the 6T1C device is very high, the force of symmetry conductance weakens due to asymmetry. Therefore, by changing the conductance change caused by retention to a weighted value = 0, the leakage converging conductance can be read by reference. Moreover, the leakage converging conductance, that is, when V capWhen Vcap = 0, under ideal conditions (ideal conditions: when transistors N1 and N3 have the same characteristics, and transistors N2 and N4 have the same characteristics), the change in Vcap due to potentiation is less than the change in Vcap due to depression. cap Since the change in magnitude is the same, the leakage converging conductance can be converted into a symmetry conductance. To some extent, because the expected value is the same, by setting the reference conductance in the manner disclosed in this invention, if the asymmetry of the device is relatively large, an inverting process can be performed to compensate for erroneous learning in the core device caused by the difference between the symmetry conductance and the leakage converging conductance. This results in robust characteristics in terms of retention time, thus improving accuracy degradation caused by leakage.

[0132] Furthermore, in the case of linear learning, there is almost no accuracy degradation caused by asymmetry.

[0133] Furthermore, in the case of nonlinear learning, random inversion can be performed to improve accuracy degradation caused by asymmetry. Additionally, it can compensate for the asymmetry of the transistors within the synaptic device 100 with a 6T1C structure. Moreover, it can prevent the weights represented by the corresponding devices from becoming too large or too small as the nonlinearity of the device increases; the higher the nonlinearity, the more susceptible it is to the influence of symmetry conductance with repeated updates.

[0135] Experimental measurement setup and various properties of single-synaptic devices

[0136] Figure 6 An image of a printed circuit board (PCB) used for measuring the synaptic device in an embodiment of the present invention. Figure 7a This is a graph showing the weighted value update result of a single synaptic device with a 6T1C structure according to an embodiment of the present invention. Figure 7b This is a graph illustrating the weighted value update curve of an embodiment of the present invention. Figure 7c A graph illustrating the retention characteristics of a single synaptic device with a 6T1C structure according to an embodiment of the present invention. Figure 7dA graph showing the measurement results during the initial cycle for determining the cyclic durability of a single synaptic device with a 6T1C structure according to an embodiment of the present invention. Figure 7e To apply 10 to the single synaptic device with a 6T1C structure according to an embodiment of the present invention 9 The measurement results curve obtained from each update pulse.

[0137] Reference Figure 6 To measure various characteristics of a single synaptic device, a printed circuit board (PCB) can be used, consisting of a microcontroller unit (MCU) and individual integrated circuit components (e.g., shifters, integrators, noise filters, input / output pins, power modules) that interact with the synaptic cell array. The shifters, integrators, and noise filters can be constructed from existing publicly available IC chips or components; detailed descriptions of the aforementioned PCB are omitted. The synaptic cell current can be measured by a current integrator and the microcontroller unit (ADC) on the PCB.

[0138] Reference Figure 7a The first voltage received by the single synaptic device (=V) dd / 2) is 2.0V, and the overdrive voltage (= is defined as V) is 2.0V. gs -V th V ov The result is obtained by applying 1000 up / down pulses of 0.25V each with a pulse width of 300ns to the second control transistor N2 and the fourth control transistor N4. (Refer to...) Figure 7b First voltage (=V) dd / 2) is supplied at 1.5, overdrive voltage (V) ov =V gs -V th The result is obtained by applying a 1.4V 1000 up / down pulse to the second control transistor N2 and the fourth control transistor N4.

[0139] Figure 7a and Figure 7b Demonstrates the use of Figure 6 The weighted update characteristics of a single synaptic device with a 6T1C structure were measured on the printed circuit board shown. Figure 7aThe diagram shows the ADC variation of a single cell measured over four cycles with 1000 positive updates and 1000 negative updates. To preserve the improved linearity and symmetry of the synaptic device, the second control transistor N2 and the fourth control transistor N4 need to reach the saturation region. For this purpose, a voltage lower than the first voltage (= V) can be applied to the second control transistor N2 and the fourth control transistor N4. dd / 2) overdrive voltage (V ov =V gs -V th ) and to the first voltage (=V dd / 2) Apply high voltage. (Refer to...) Figure 7b The conductivity modulation of voltage pulses at 100ns, 200ns, and 400ns is shown respectively. (Refer to...) Figure 7a and Figure 7b The synaptic device with a 6T1C structure exhibits highly linear and symmetrical weighted value update characteristics under 1000 conductance states, indicating that the conductance modulation of the device can be precisely controlled by changing the measurement conditions of the same device.

[0140] Reference Figure 7c Retention characteristics were measured by applying a -2V off-voltage to each control transistor (N1-N4). First, to evaluate the device's exposure characteristics, enhancement pulses were repeatedly applied to the synaptic unit to intentionally fill capacitor C1. Then, an off-voltage was applied to all control transistors (N1-N4), and readouts were performed at specified time intervals (60 minutes). The measured ADC values ​​were converted to capacitor voltages, and a time constant of approximately 775 minutes was obtained through exponential fitting. These results demonstrate that the 6T1C synaptic device exhibits superior retention characteristics compared to existing silicon- and capacitor-based synaptic devices.

[0141] Reference Figure 7d and Figure 7e It shows the application of 10 9 Measurement results after one update pulse (upper pulse height 0.5V / -2V, length 1μs). The results were obtained by repeatedly applying 1000 up / 1000 down pulses 500,000 times. 9 An update pulse is applied to the synaptic mechanism. It can be confirmed that, when compared separately... Figure 7d , Figure 7e The output ADC of the initial and final loops shown is then applied at 10... 9Even after one pulse, the device continues to operate, and the ADC output range remains almost unchanged. This confirms that the 6T1C synaptic device not only has a long service life but also exhibits stable analog characteristics over multiple cycles.

[0143] Experimental results of linear regression based on random update method on 5X16T1C array

[0144] Figure 8a This is a flowchart for linear regression training according to an embodiment of the present invention. Figure 8b This is a graph showing the overall training loss and error evaluation results of an embodiment of the present invention.

[0145] Reference Figure 8a Training consists of two steps: feedforward and weighted value update (potentiation, depression). The loss is defined using the mean square error (MSE) function.

[0146] Reference Figure 8b As training progresses, both the loss and error converge to zero. The training is performed on 25 input datasets per epoch. The total number of epochs is 20. In the demonstration, the bit length is set to 10, and the learning rate is 0.05. Figure 8b The error is defined as

[0148] Achieving linear regression using a cross array

[0149] Linear regression was performed using a 6T1C5X1 cross-array experimental setup to evaluate the on-chip training performance of the synaptic device. The training process was as follows: Figure 8a The flowchart illustrates that during the feedforward process, random update pulses for the input data and weighted value update process are generated in real time by a microcontroller unit located on a printed circuit board. First, an input dataset for the feedforward process is generated and applied in pulse-width modulo operations to the word lines (WL) of five synaptic devices. The input data rows and columns can be composed of four randomly generated data points and a sequence of x... i The y-intercept is a fixed value in the form of [x1, x2, x3, x4, a]. If a feedforward process is executed, the following y-values ​​are generated [Mathematical Formula 3].

[0150] [Mathematical Expression 3]

[0151] y = x i [w1, w2, w3, w4, w5]T

[0152] Where, x i The input data rows and columns are represented by [w1, w2, w3, w4, w5], which represent the weighted value rows and columns. Next, Y can be compared with the object value t of [Mathematical Formula 4a] to generate the error vector δ of [Mathematical Formula 4b]. i δ i .

[0153] [Mathematical expression 4a]

[0154] t = x i [t1, t2, t3, t4, t5] T

[0155] [Mathematical Expression 4b]

[0156] δ i =x i [w1, w2, w3, w4, w5] T -t

[0157] Where [t1, t2, t3, t4, t5] represent the target weighting matrix. The process of converting the output ADC value into a weighted total and the loss calculation process can be executed by a microcontroller unit located on the printed circuit board. Then, the weighting value is updated using a random update technique. The weighting value update amount for each synaptic unit follows the following [Mathematical Formula 5a] and [Mathematical Formula 5b].

[0158] [Mathematical expression 5a]

[0159] Δw n =-ηx n δ i (n=1~4) (5a)

[0160] [Mathematical expression 5b]

[0161] Δw n =-ηaδ i (5b)

[0162] Where, x n δ and 'a' represent the input data used by each synaptic unit. i Let x represent the error extracted through feedforward, and η represent the learning rate. During the weighted update process, x... n And a is converted into the pulse occurrence probability of the first control transistor N1 or the third control transistor N3, δ i The probability of pulse occurrence is converted into that of the second control transistor N2 or the fourth control transistor N4. For example... Figure 8aAs shown, the sign of (y-t) is used to determine whether to generate the necessary pulse for strengthening or weakening. Repeating this process trains the 6T1C 5X1 cross-array and solves linear regression problems. Figure 8b The results show that the loss and error converge to zero as training progresses. This linear regression result demonstrates the automatic parallel on-chip training capability of the 6T1C array.

[0164] Pattern recognition simulation using the 6T1C device

[0165] Figure 9a This is a graph showing the results of conductivity-conductivity change patterns obtained under various measurement conditions according to an embodiment of the present invention. Figure 9b The graph illustrates the accuracy of the synaptic device with a 6T1C structure according to an embodiment of the present invention, reflecting multiple values ​​within the NL range and representing the device's accuracy in accordance with the retention characteristics of the existing Tiki-taka algorithm. Figure 7c This is a graph illustrating the accuracy of the device according to its retention characteristics when applied to NL=0.2 and NL=2.0 according to embodiments of the present invention. In the following description, "NL" represents the parameter indicating linearity and nonlinearity. p "The square added to the conductivity, i.e., to enhance linearity and nonlinearity in the operation," NL d "Reducing the square of conductance means weakening the linearity and nonlinearity in the operation. Specifically, the closer the 'NL' value is to 0, the more linear it is; the closer the 'NL' value is to 2, the more nonlinear it is. LENET5 refers to the convolutional neural network structure described in Yann LeCun's 1998 paper 'Gradient-Based Learning Applied to Document Recognition.' A multilayer perceptron (MLP) is a multilayer neural network structure model composed of multiple perceptron neurons stacked in multiple layers."

[0166] Reference Figure 9a The curves for NL=0.2 and NL=2.0 represent the conversion... Figure 7a and 7b The results were obtained using the red and green lines. With NL=2.0, linear regression analysis was used only for the portion of the region used for learning.

[0167] Reference Figure 9bWith the existing Tiki-taka algorithm, accuracy decreases as the retention time (t / RC) of the applied retention feature decreases. This is because devices based on existing capacitors experience leakage due to leakage converging conductance.

[0168] Furthermore, under current conditions, as the neural network required for learning increases in size, a reference array is needed to assist in learning. As the area occupied by this reference array increases, it leads to a decrease in integration density. Moreover, as learning progresses, changes in device characteristics can cause alterations in symmetry conductance. This symmetry conductance, as the conductance of each pulse applied to each device, has a conductance value with the same rate of increase and decrease.

[0169] Reference Figure 9c The synaptic device of the present invention with a 6T1C structure is different from... Figure 7b Given the current situation, in a linear environment (NL=0.2), setting the leakage converging conductance as a reference confirms that the neural network training results, i.e., the learning accuracy, can reach over 97% even with a relatively short retention time (t / RC). That is, in the case of the LENET5 model, if in 5e... -2 and the 5e of the MLP model -3 Using the optimal learning rate (linear learning), approximately 97% accuracy is achieved. However, in cases of greater asymmetry, the forces toward symmetric conductance are relatively strong, meaning that setting the reference solely based on leakage converging conductance will not yield optimal accuracy.

[0170] Figure 10 This diagram illustrates the reference conductance setting method according to an embodiment of the present invention. The reference conductance refers to the V... cap Conductance when = 0.

[0171] Reference Figure 10 The aforementioned conductance is read as the current I of the first output transistor N5 when the pulse is applied (①) to the first control transistor N1. N5 (②) and the current I of the second output transistor N6 applied by the pulse to the third control transistor N3 (③)N6 (④) is the difference (⑤). Specifically, in pulse V DD After / 2 is applied to the first control transistor N1 (①), the current I flowing through the first output transistor N5 is measured. N5 (②). Next, after the pulse is applied to the third control transistor N3 (③), the current I flowing through the second output transistor N6 is measured. N6 (④). Then, calculate the current I. N5 With current I N6 The difference (⑤).

[0173] Figure 11a and Figure 11b The graph shows the results of comparing the present invention with existing linear learning methods in LENET5 and MLP models. The linear learning method of the present invention (referred to as Published Invention 1 (Modified TTv1)) refers to learning performed through the aforementioned reference read operation, while existing methods refer to learning performed through the TTv1 algorithm in linear or nonlinear learning.

[0174] Reference Figure 11a In the case of the LENET5 model, if in 5e -4 The following applications of the disclosed invention (red) have a lower error rate than those using the existing Tiki-taka algorithm (black). However, if in 5e -5 The above-mentioned application of the publicly disclosed invention (red) results in a higher error rate than the application of the existing attack-defense algorithm (Tiki-taka algorithm).

[0175] Reference Figure 11b ,and Figure 9a Similarly, in the case of the MLP model, if in 5e -5 The following applications of the disclosed invention (red) have a lower error rate than those using the existing Tiki-taka algorithm (black). However, if in 5e -6 The above-mentioned application of the publicly disclosed invention (red) results in a higher error rate than the application of the existing attack-defense algorithm (Tiki-taka algorithm).

[0176] As described above, in the case of linear learning, the algorithm of disclosed invention 1 (Modified TTv1) is executed based on a specific critical value. After the aforementioned specific critical value, the TTv1 algorithm in the conventional manner can be executed to improve the error rate.

[0177] In another embodiment, for linear or nonlinear learning, an algorithm (e.g., referred to as Published Invention 2) for performing the above-described reference read, reset, and invert operations can be used to achieve an improvement in the error rate across the entire interval.

[0178] Figure 12a and Figure 12b The graphs show the results of comparing nonlinear learning outcomes with and without performing inversion and reset operations on the LENET5 model. Figure 12a To set the retention value to 5e 8 The experimental results Figure 12b The results show the experimental outcome of setting the retention value to infinite. The X-axis (epoch) represents the number of learning iterations. The red line represents the application of the algorithm of disclosed method 2 with the above-described invert and reset operations, while the black line represents the application of the algorithm of disclosed invention 1 without the above-described invert and reset operations.

[0179] Reference Figure 12a and Figure 12b In the case of disclosed invention 1 (black), the error rate increases due to the degradation of the learning degree as nonlinear learning is repeatedly performed. However, in the case of disclosed invention 2 (red), the error rate can be reduced as the degradation of the learning degree is improved through repeated nonlinear learning. As described above, when the device itself has symmetrical conductance (weight > 0) > leakage convergence conductance (indicating conductance where weight = 0), an unexpected tendency for the weight to increase positively occurs during updates, which leads to accuracy degradation. However, the inverting process of the present invention can make the aforementioned symmetrical conductance represent weight < 0, thereby improving the degradation by periodically offsetting the unexpected directionality of weight changes.

[0180] In another embodiment, in the early stages of nonlinear learning (approximately in the range of 0 < epoch < 18), the error rate of disclosed invention 1 (black) is relatively lower than that of disclosed invention 2 (red). Learning is performed using disclosed invention 1 in the early stages of learning. After the critical value is reached, if learning is performed using disclosed invention 2, the error rate can be lower than that of nonlinear learning performed solely using disclosed invention 2.

[0182] Optimal Algorithm for Synaptic Devices with 6T1C Structure

[0183] Performance improvements in the AiMC system require consideration of both algorithm-level and hardware-level access methods. This invention aims for optimal optimization through a hardware-algorithm co-design. Simulations were performed using existing SGD and TTv1 (Tiki-Taka) algorithms applied to the device of this invention. Simulation results demonstrate that this invention is applicable not only to the SGD algorithm but also to TTv1. Additionally, this invention discloses a driving algorithm for a 6T1C structure synaptic device that surpasses TTv1 performance. The powerful driving algorithm of this invention 1) does not reduce learning accuracy even with increased retention levels required for learning, and 2) allows for easy setting of reference conductance within the device itself without the need for an additional reference cell array.

[0184] First, this invention uses the SGD algorithm based on the weighted value update characteristics and retention time. Figure 7b , Figure 7c The measurement results shown simulate neural network training.

[0185] Furthermore, the device variations of the 6T1C structure, as a parameter representing the device asymmetry, are applied at 15% to NL and 15% to G. max and G min Applying 7%, to Δw min Apply 6% to retention time, 15% to G leak Application 15%. G max and G min G represents the maximum electrodynamic force and minimum electrical conductance of the device, respectively. leak This represents the conductance at which the volatile device converges after a complete retention failure. Under cyclic standard deviation, a 5% standard deviation is applied to write noise, a 6% standard deviation to the current sum, and a Δw... min Applying 30%. The following variations are applied to all simulations except the SGD algorithm. Assuming a training cycle length of 200 ns per layer (Forward + Backward + Update), approximately 98.5% accuracy is achieved. This result stems from the symmetrical action and excellent preservation properties of the 6T1C synaptic apparatus.

[0186] Second, this invention uses the TTv1 training algorithm, designed for existing asymmetric synaptic devices, to perform neural network training. Existing TTv1 operates entirely in parallel, training the core device with update information executed by an auxiliary device. In this case, the 6T1C structure synaptic device, with its excellent update characteristics but leakage, is used as an auxiliary device. The core device can periodically transfer the weighted values ​​of 6T1C to non-volatile memory (NVM) to read ordinary non-volatile memory (NVM) during inference without weight loss. To utilize TTv1 for training, the 6T1C weighted update measurement results are converted into… Figure 7a The conductivity-conductance variation pattern. Subsequently, linear regression was used to analyze... Figure 7a Modeling is performed to extract simulation parameters from the following [Mathematical Formula 6a] and [Mathematical Formula 6b].

[0187] [Mathematical expression 6a]

[0188]

[0189] [Mathematical expression 6b]

[0190]

[0191] Wherein, ΔG p ΔG d These represent the conductance changes of a strengthening and weakening pulse, respectively. G sym This indicates that ΔG is satisfied. p =ΔG d Symmetrical conductance. For example... Figure 7a As shown, in the same apparatus, both linear update results (NL≈0.2) and intentional asymmetric update results (NL≈2.0) can be extracted by changing the measurement conditions. In existing methods, the NL combination of the core and auxiliary devices is particularly important for achieving optimal learning accuracy using TTv1. That is, obtaining the target NL value is crucial for finding the optimal combination. However, in ordinary resistive switching devices, the target NL value cannot be obtained because the conductance modulation mechanism depends on random processes at the atomic level. Conversely, as... Figure 7a As shown, the device with the 6T1C structure of the present invention can obtain a wide range of NL between 0.2 and 2 by changing the measurement conditions in the same device, and the target NL value can be easily obtained based on explicit conductance modulation. Figure 7bThe results of applying TTv1 with a 6T1C structure device, reflecting multiple values ​​within the NL range, are shown under the same core device conditions. Similar to prior art results, the learning accuracy varies depending on the NL of the 6T1C structure device. However, the device of the present invention allows for easy acquisition of the target NL value by changing the measurement conditions; therefore, optimal learning accuracy can be achieved with TTv1 regardless of the type of core device.

[0192] Furthermore, weight transfer can also be performed using TTv1 with a 6T1C device. Even with excellent retention characteristics, devices with a 6T1C architecture require a weight transfer process to transfer stored weights to non-volatile memory (NVM) due to long-term retention loss. However, weight transfer techniques require sequential or row-by-row access to cross-point elements. Since simple weight transfer involves time-consuming sequential work and repeated programming and weight verification, it can incur significant overhead in large-scale networks. Conversely, with TTv1, learning and weight transfer can be performed simultaneously and in complete parallel.

[0193] Although devices with a 6T1C structure have been proven suitable for existing TTv1, however, as Figure 7b As shown, learning accuracy can decrease as the learning time increases. Therefore, in cases where longer retention is required, the driving algorithm of this invention is used to restore learning accuracy. First, the phenomenon that the accuracy of existing TTv1 decreases with the retention level is analyzed.

[0194] Using volatile devices as auxiliary devices and non-volatile devices as core devices, when executing TTv1, the weighting updates of the auxiliary devices and core devices follow [Mathematical Formula 7a] and [Mathematical Formula 7b], respectively.

[0195] [Mathematical expression 7a]

[0197] [Mathematical Expression 7b]

[0198]

[0199] Among them, t update Let η represent the training epoch length of each layer of the auxiliary array, and ε(t) represent the probabilistic effect that occurs during the update process. A and η C The learning speeds of Pepsi's auxiliary and core devices, respectively. E represents the cost function.

[0200] However, the weighted values ​​of the auxiliary device and the core device need to satisfy [Mathematical Formula 8a] and [Mathematical Formula 8b] respectively to achieve normal operation. In TTv1 using non-volatile memory (NVM), A ref Set as A sym After thorough learning, because it can satisfy |A-A sym =0|condition, therefore, the global minimum can be reached. However, when a volatile device is used as an auxiliary device, the global minimum cannot be reached because the right side of [Mathematical Equation 8a] cannot converge to 0. The result is as follows: Figure 7b As shown, learning accuracy decreases as the retention time required for training increases.

[0201] [Mathematical expression 8a]

[0203] [Mathematical expression 8b]

[0204]

[0205] However, the reduction in accuracy caused by retention can be mitigated by adjusting A... ref Let A be the answer. leak The driving algorithm of the device of the present invention (modified TTv1) is used to solve this problem. When V cap When = 0, the device with the 6T1C structure makes A sym and A leak The expected value is the same, such as Figure 7a As shown, the device with the 6T1C structure can perform highly linear weighted value updates. Therefore, the effects of terms that are asymmetrically related to the first term on the right side of [Mathematical Expression 8a] can be ignored if A ref Set as A leak If so, it can be predicted that the global minimum will be reached. If the global minimum is reached, then with the [Mathematical Equation 8a]... The smaller size further reduces the asymmetric effect. Figure 7c The training results of applying the modified TTv1 to neural networks with NL = 0.2 and 2.0 are shown. In the highly linear example with NL = 0.2, approximately 97.5% accuracy is achieved even with an increase in the required retention time. Furthermore, as analyzed above [Mathematical Formula 7a], it can be confirmed that the accuracy decreases with increasing device asymmetry.

[0206] The improved TTv1 of this invention has the advantage of being able to quickly and easily set the reference conductance in a 6T1C structure device even without an additional reference cell array. In existing TTv1 devices, it is known that accurately setting a stable reference conductance through symmetrical conductance is particularly important; however, existing symmetrical conductance setting methods are not only relatively complex but also require an additional array. However, the device with a 6T1C structure of this invention can quickly and accurately obtain the reference conductance (see reference) by performing a read operation again. Figure 7d Furthermore, during training, changes in device characteristics can lead to decreased accuracy due to variations in the device's own symmetrical conductance or the conductance of the reference device. However, with the improved TTv1 of this invention, the reference conductance can be stably read even if device characteristics change during training.

[0207] Refer again Figure 9a and Figure 9b The diagram illustrates the learning results of applying existing and improved TTv1 at various retention levels. It can be confirmed in [Mathematical Formula 8a] that the retention characteristics and asymmetry of the device have a combined effect on learning accuracy, and the algorithm required for optimal learning varies with the retention level. However, if a device with a 6T1C structure is used, an appropriate algorithm can be selected according to the retention level. If the retention characteristics required for learning increase due to complex datasets or neural networks, optimal accuracy can be obtained by applying TTv1 modified with highly linear update conditions. If the retention characteristics of the device are sufficient for learning, optimal accuracy can be obtained by applying TTv1 with update conditions suitable for the asymmetry of the core device.

[0208] Furthermore, the drawbacks of capacitor-based synapses, namely scalability, can be mitigated by devices with a 6T1C structure and optimal algorithms. The smaller the capacitor, the more difficult it is to ensure sufficient retention time for learning, thus limiting the scalability of capacitor-based synaptic devices. For example, in the case of convolutional neural networks (CNNs), a large capacitor of 100 fF per cell is known to be required. The scalability of the device can be improved by reducing its size. For example, by using indium gallium zinc oxide thin-film transistors (IGZO TFTs) with the lowest current rating currently available and the capacitor, high learning accuracy can be achieved by training large amounts of input data with synapses of 10 fF per cell. Therefore, devices with a 6T1C structure can be used as versatile and practical synaptic devices capable of handling large volumes of input data and complex neural networks.

[0209] As described above, to address the retention problem of capacitor-based charge storage synapses, this invention discloses a synaptic device consisting of a low-leakage-current indium gallium zinc oxide thin-film transistor (IGZO TFT), a capacitor, and six transistors. With the fabrication of a single synaptic device and a 5×5 cross array, it has been demonstrated that the device of this invention can provide sufficient retention time and parallel on-chip training operations, except for linear and symmetric weighted updates. Furthermore, an efficient and realistic training algorithm is developed to compensate for residual device non-ideals such as drifting references and long-term retention loss, thereby demonstrating the importance of device-algorithm co-optimization.

[0210] Furthermore, the algorithm of this invention does not require an additional reference cell array and achieves a high learning accuracy of approximately 97% even with increased retention time required for training. Therefore, a smaller synaptic array size can be achieved with smaller capacitors. It is anticipated that existing ultra-low-leakage and nanoscale indium gallium zinc oxide thin-film transistors (IGZO TFTs) and capacitors can further reduce the size of the 6T1C device. The device footprint can be further improved through vertical channel thin-film transistors (VTFTs) based on three-dimensional monolithic 3D integration and indium gallium zinc oxide atomic layer deposition (atomic layer evaporation). Therefore, the 6T1C device of this invention can be viewed as a synaptic device for neuromorphic computing.

[0211] This specification discloses preferred embodiments of the present invention. Although specific terminology is used, it is not intended to limit the scope of the invention, but rather to provide a general meaning for easy explanation of the technical content and to aid in understanding the invention. It is evident that, in addition to the embodiments disclosed herein, those skilled in the art can implement other modifications based on the technical concept of the present invention. It should be understood that those skilled in the art can refer to... Figures 1a to 12b The illustrated embodiments involve various substitutions, modifications, and variations of the charge storage synaptic device and its driving method for deep neural network training without departing from the inventive concept. Therefore, the scope of this invention should be defined based on the inventive concept described in the claims, and not on the illustrated embodiments. Industrial availability

[0212] This invention relates to a charge storage synaptic device for training deep neural networks and its driving method, which has industrial applicability.

Claims

1. A synaptic device, characterized in that, include: A weighted capacitor has a first terminal and a second terminal for storing a voltage corresponding to a weighted value; Four control transistors are used to change the voltage or weighting value of the above capacitors; A first output transistor includes a first gate terminal coupled to a first terminal of the aforementioned capacitor, and outputs a first drain current according to a voltage applied to the first gate terminal; and The second output transistor includes a second gate terminal connected to the second terminal of the aforementioned capacitor, and outputs a second drain current according to the voltage applied to the second gate terminal. The weighted value is read as the difference between the first drain current and the second drain current.

2. The synaptic device according to claim 1, characterized in that, Of the four control transistors mentioned above, the first control transistor and the third control transistor each have a first source terminal, including a transmission transistor for transmitting a first voltage connected to the first source terminal to the weighted capacitor. Of the four control transistors mentioned above, the second and fourth control transistors each have a second source terminal, including a transistor that serves as a current source based on the ground terminal connected to the second source terminal. The first control transistor and the fourth control transistor each include a first drain terminal, the first drain terminals are connected to each other, and are connected to the first terminal of the weighted capacitor. The second control transistor and the third control transistor each include a second drain terminal, the second drain terminals are connected to each other and connected to the second terminal of the weighted capacitor.

3. The synaptic device according to claim 2, characterized in that, The first control transistor is connected between the first voltage and the first terminal of the weighted capacitor, and connects the first voltage to the first terminal of the weighted capacitor in response to a first control signal. The second control transistor is connected between the ground electrode and the second terminal of the weighted capacitor, and connects the ground electrode and the second terminal in response to a second control signal. The third control transistor is connected between the first voltage and the second terminal of the weighting capacitor, and connects the first voltage to the second terminal of the weighting capacitor in response to a third control signal. The aforementioned fourth control transistor is connected between the aforementioned ground electrode and the aforementioned first terminal of the aforementioned weighted capacitor, and connects the aforementioned ground electrode and the aforementioned first terminal in response to the fourth control signal. The first output transistor described above has a third drain terminal and a third source terminal. The third drain terminal is connected to the first input line, and the third source terminal is connected to the first output line. The second output transistor described above has a fourth drain terminal and a fourth source terminal. The fourth drain terminal is connected to the second input line, and the fourth source terminal is connected to the second output line. The first drain current of the first output transistor is supplied by the first output line and depends on the voltage at the first terminal of the weighted capacitor, the voltage of the first input line, and the voltage of the first output line. The second drain current of the second output transistor is supplied by the second output line and depends on the voltage of the second terminal of the weighted capacitor, the voltage of the second input line, and the voltage of the second output line.

4. The synaptic device according to claim 2, characterized in that, The second control transistor and the fourth control transistor are subjected to an overdrive voltage that is relatively lower than the first voltage.

5. The synaptic device according to claim 2, characterized in that, The weighted value is increased positively by performing enhanced updates by activating the first and second control transistors. The weighted value is negatively increased by performing a weakening update by activating the third and fourth control transistors.

6. The synaptic device according to claim 5, characterized in that, The aforementioned weighting value depends on the discharge current of the second control transistor or the fourth control transistor, the pulse width applied to the second control transistor or the fourth control transistor, and the capacitance of the weighting capacitor.

7. The synaptic device according to claim 2, characterized in that, The first drain current of the first output transistor is read by activating the third control transistor. The second drain current of the second output transistor is read by means of the read operation where the first control transistor is turned on. The difference between the first drain current and the second drain current is determined as the weighted value.

8. The synaptic device according to claim 2, characterized in that, The third drain current of the first output transistor is read by means of the reference read operation when the first control transistor is turned on. The fourth drain current of the second output transistor is read by means of the reference read operation when the third control transistor is enabled. The difference between the third drain current and the fourth drain current is defined as the reference conductance. When the aforementioned weighted capacitor has the aforementioned reference conductance, the voltage (V) of the aforementioned weighted capacitor... cap The value is 0.

9. The synaptic device according to claim 5, 7 or 8, characterized in that, Reverse at least one of the above-mentioned strengthening update and weakening update, the above-mentioned read operation and the above-mentioned reference read operation.

10. The synaptic device according to claim 2, characterized in that, To perform a reset, the voltage (V) of the weighted capacitor is adjusted by turning on the second and fourth control transistors. cap Reset to 0.

11. The synaptic device according to claim 10, characterized in that, The reset operation described above is performed before the reversal operation.

12. The synaptic device according to claim 1, characterized in that, The four control transistors, the first output transistor, and the second output transistor are amorphous indium gallium zinc oxide field-effect transistors, polycrystalline indium gallium zinc oxide field-effect transistors, monocrystalline indium gallium zinc oxide field-effect transistors, or C-axis grown crystalline indium gallium zinc oxide field-effect transistors.

13. The synaptic device according to claim 1, characterized in that, The nonlinearity of the synaptic device is adjusted according to the pulse conditions applied to the four control transistors.

14. A method for driving a synaptic device, used in the synaptic device according to claim 1, characterized in that, In the case of linear learning, reference reading is performed. In the case of non-linear learning, the above-mentioned reference reading, reset, and inversion operations are performed.

15. A neural network learning method, comprising a core device array and an auxiliary device array, wherein the core device array includes M×N first synaptic devices, and the auxiliary device array includes M×N second synaptic devices according to claim 1, characterized in that... include: The first step is to use forward propagation and backward propagation methods to generate output values ​​in the aforementioned core device array. The second step is to apply a pulse corresponding to the output value from the core device array to the auxiliary device array to perform the first update on the auxiliary device array. The third step is to select a specific column of the auxiliary device array and generate an output current from the specific column after performing the first update. The fourth step involves converting each output current into an input value for the core device array by performing read and reference read operations through the synaptic devices of the aforementioned specific column according to claim 1; and The fifth step involves performing a second update on a specific column of the core device array using the input values ​​described above.

16. The neural network learning method according to claim 15, characterized in that, It also includes the following steps: using each of the synaptic devices in a specific column of the above-described auxiliary device array according to claim 1 to perform a reset or inversion operation according to a probability variable.

17. The neural network learning method according to claim 16, characterized in that, In the case of linear learning, the above reset or reversal work is not performed. In the case of nonlinear learning, perform the above reset operation or the above inversion operation.

18. The neural network learning method according to claim 16, characterized in that, During the initial learning phase, the aforementioned reset or reversal steps are not performed. After the initial learning period described above, perform the reset or reversal process described above.

19. The neural network learning method according to claim 16, characterized in that, After the fifth step described above, the first to fifth steps are repeatedly performed on the remaining columns of the core device array and the auxiliary device array described above.

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