Method for manufacturing semiconductor device and bonded wafer

Abstract

The purpose of the present disclosure is to improve productivity and suppress wafer breakage in the manufacture of a semiconductor device in which a wafer is reused. This method for manufacturing a semiconductor device is provided with: (a) a step for obtaining at least one divided wafer (20, 23), which does not include a device structure (12, 16), from each SiC wafer (13, 17) by dividing each of a plurality of SiC wafers (13, 17) in the thickness direction; (b) a step for obtaining a bonded wafer (24) by bonding a plurality of divided wafers (20, 23) obtained from different SiC wafers (13, 17); and (c) a step for forming a device structure (26) on the surface of the bonding wafer (24).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a manufacturing method of a semiconductor device and a bonded wafer. BACKGROUND

[0002] In the past, a technique for efficiently utilizing a high-cost single-crystal wafer in order to reduce the cost of a semiconductor device has been proposed. For example, in Patent Literature 1, a method of slicing a wafer at the time of a thinning process of a device process and reusing a divided wafer on which a device is not formed is proposed.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: Japanese Patent Application Publication No. 2019-50362 SUMMARY

[0006] In the method disclosed in Patent Literature 1, in order to reduce the breakage of the reused divided wafer, it is necessary to form an epitaxial film that becomes a buffer layer irrelevant to the operation of a device to be thicker on the divided wafer, and to make the divided wafer have the same thickness as the wafer from which the divided wafer is divided. From the viewpoint of productivity, it is disadvantageous to form a thick epitaxial film. On the other hand, when the epitaxial film is formed to be thinner, there is a problem that the risk of breakage when the divided wafer is reused becomes higher.

[0007] The present disclosure was completed in order to solve the above problems, and aims to improve productivity and suppress wafer breakage in the manufacturing of a semiconductor device in which a wafer is reused.

[0008] The manufacturing method of a semiconductor device of the present disclosure includes: (a) a step of obtaining at least one first divided wafer that does not include a device structure, from each of a plurality of first wafers, by dividing each of the first wafers in the thickness direction; (b) a step of bonding a plurality of first divided wafers obtained from different first wafers to obtain a first bonded wafer as a bonded wafer; and (c) a step of forming a device structure on a surface of the first bonded wafer.

[0009] According to the manufacturing method of a semiconductor device of the present disclosure, a device structure is formed in a bonded wafer in which divided wafers are bonded to each other. Therefore, a bonded wafer of a sufficient thickness in consideration of breakage is formed at a lower cost than when an epitaxial film is formed on a divided wafer, and the wafer can be reused. The object, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a view showing a basic process of the manufacturing method of a semiconductor device according to Embodiment 1.

[0011] Figure 2 This is a flowchart illustrating a method for manufacturing a semiconductor device according to Embodiment 1.

[0012] Figure 3 This is a diagram illustrating a method for manufacturing a semiconductor device according to Embodiment 1, where the thickness of the bonded wafer is 500 μm.

[0013] Figure 4 This is a diagram illustrating a method for manufacturing a semiconductor device according to Embodiment 1, where the thickness of the bonded wafer is 500 μm.

[0014] Figure 5 This is a diagram illustrating a method for manufacturing a semiconductor device according to Embodiment 1, where the thickness of the bonded wafer is 350 μm.

[0015] Figure 6 This is a diagram illustrating a method for manufacturing a semiconductor device according to Embodiment 1, where the thickness of the bonded wafer is 350 μm.

[0016] Figure 7 This is a diagram showing the depth of the bonding surface in a bonding wafer composed of two split wafers.

[0017] Figure 8 This is a diagram showing the depth of the bonding surface in a bonding wafer composed of three split wafers.

[0018] Figure 9 This is a diagram illustrating the pattern of wafer dicing timing in the semiconductor device manufacturing method according to Embodiment 1.

[0019] Figure 10 This is a diagram illustrating the basic process of dividing a SiC wafer before forming an epitaxial film in the semiconductor device manufacturing method according to Embodiment 1.

[0020] Figure 11 This is a diagram illustrating the basic process of the semiconductor device manufacturing method according to Embodiment 2.

[0021] Figure 12 This is a diagram illustrating the basic process of a semiconductor device manufacturing method according to a variation of Embodiment 2.

[0022] Figure 13 This is a diagram illustrating the basic process of the semiconductor device manufacturing method according to Embodiment 3.

[0023] Figure 14 This is a diagram illustrating the basic process of a semiconductor device manufacturing method according to a variation of Embodiment 3. Detailed Implementation

[0024] <A. Embodiment 1>

[0025] <A-1. Basic Process>

[0026] Figure 1 It is a schematic diagram showing the outline of the basic process of the manufacturing method of the semiconductor device in this embodiment. Figure 2 It is a flowchart of the manufacturing method of the semiconductor device in this embodiment. Hereinafter, referring to Figure 1 and Figure 2 the manufacturing method of the semiconductor device in this embodiment will be described.

[0027] First, in step S101, an epitaxial film 11 is formed on a single-crystal SiC wafer 10, and a surface structure (hereinafter referred to as a device structure) 12 of the device is formed on the epitaxial film 11. In the formation of the device structure 12, ion implantation and the formation of a surface electrode are included. The device structure 12 is, for example, a SiC power device structure. In the case of using a GaN wafer or a gallium oxide wafer instead of the SiC wafer, the device structure 12 is, for example, a GaN high-frequency device structure, a GaN power device structure, or a gallium oxide power device structure. A GaN high-frequency device structure, a GaN power device structure, or a gallium oxide power device structure may also be formed on the SiC wafer. The SiC wafer 10 on which the epitaxial film 11 and the device structure 12 are formed is referred to as the SiC wafer 13.

[0028] In step S101, a SiC wafer 17 identical to the SiC wafer 13 is also formed. That is, an epitaxial film 15 is formed on a single-crystal SiC wafer 14, and a device structure 16 is formed on the epitaxial film 15. The SiC wafer 14 on which the epitaxial film 15 and the device structure 16 are formed is referred to as the SiC wafer 17. The SiC wafers 13 and 17 are also referred to as the first wafers. Here, the SiC wafers 10 and 14 may be bonded wafers formed by bonding multiple SiC wafers. The SiC wafers 10 and 14 have an N-type or P-type conductivity type, or semi-insulating properties.

[0029] Next, in step S102, the SiC wafer 13 is divided into a device wafer 19 including the device structure 12 and a divided wafer 2​​In step S102, SiC wafer 17 is also diced in the same way as SiC wafer 13. That is, SiC wafer 17 is diced into a device-ribbed wafer 22 containing device structures 16 and a diced wafer 23 not containing device structures 16. The device-ribbed wafer 22 has a SiC wafer 21 diced from SiC wafer 14, an epitaxial film 15 on the SiC wafer 21, and device structures 16 on the epitaxial film 15. Device-ribbed wafers 19 and 22 are also referred to as first device-ribbed wafers, and diced wafers 20 and 23 are also referred to as first diced wafers. Furthermore, laser slicing technology or the like is used in the dicing of SiC wafers 13 and 17 in this step.

[0031] Next, in step S103, the back side of the device wafers 19 and 22, which is the side opposite to the device structures 12 and 16, is processed. First, the damaged layer on the back side of the device wafers 19 and 22, which was damaged due to laser slicing, is removed by grinding or polishing, and the device wafers 19 and 22 are adjusted to the desired thickness. Then, conventional back-side processes, such as forming a back electrode (not shown), are performed on the back side of the device wafers 19 and 22.

[0032] Next, in step S104, surface processing of the segmented wafers 20 and 23 is performed. The segmented wafers 20 and 23 also include damage layers resulting from laser slicing; these damage layers are removed by grinding or polishing, thereby adjusting the segmented wafers 20 and 23 to the desired thickness. Considering the depth of the bonding surface in the bonded wafer described later, the thickness of the segmented wafers 20 and 23 is preferably 50 μm or more, more preferably 80 μm or more, and most preferably 100 μm or more. When adjusting the thickness of the segmented wafers 20 and 23, processing of the back side of the segmented wafers 20 and 23 can also be performed as needed, such as grinding or polishing. By performing back side processing, in addition to adjusting the thickness, damage occurring during the device manufacturing process can be removed. As a result, a high-quality bonded wafer can be obtained in the subsequent step S105. Here, a high-quality bonded wafer refers to a wafer that has undergone damage suppression, warpage suppression, or flatness improvement, etc. The processing of the back side of the split wafers 20 and 23 can also be described as a process that has a certain effect when making device wafers by splitting and bonding.

[0033] Next, in step S105, the segmented wafers 20 and 23 are bonded. The wafer formed by bonding the segmented wafers 20 and 23 is called the bonded wafer 24. The bonded wafer 24 is also called the first bonded wafer. At this time, surface processing such as grinding, lapping, or CMP can be performed on the bonding surfaces of the segmented wafers 20 and 23. In order to reduce the warpage of the bonded wafer 24, the warpage or surface condition of the segmented wafers 20 and 23 can be checked, and the combination of the segmented wafers 20 and 23 to be bonded can be determined according to the results. Thus, a high-quality bonded wafer is obtained. Here, the two segmented wafers 20 and 23 can be manufactured simultaneously or separately. That is, the two segmented wafers 20 and 23 can be manufactured simultaneously or sequentially using different processing equipment, or sequentially using the same processing equipment. Thus, flexible production is possible, and the productivity of segmented wafers can be improved. Furthermore, although the bonding of two segmented wafers 20 and 23 has been described here, any number of segmented wafers, more than three, can also be bonded to form the bonded wafer 24.

[0034] The segmented wafers 20 and 23 are joined, for example, by room temperature bonding. Room temperature bonding results in a clean interface without a metal layer. Furthermore, room temperature bonding creates an amorphous layer at the bonding interface. After joining the segmented wafers 20 and 23, the joined wafer 24 can be processed to the desired thickness by grinding, lapping, or CMP. In this process, the joined wafer 24 becomes the same thickness as a conventionally used SiC wafer, thus allowing for the reuse of the segmented wafers 20 and 23 at a lower cost and without the risk of breakage compared to forming a thick epitaxial film on a thin SiC wafer to maintain overall strength.

[0035] The segmented wafers 20 and 23 can also undergo beveling before joining to remove the pointed portions at the intersection of their outer peripheral surfaces and the cutting surfaces; in other words, beveling the corner portions of the segmented wafers 20 and 23. In this case, the shape of the end of the joined wafer 24 in the cross-sectional view is a shape like "3," or a polygonal shape with 5 to 7 inflection points. When the end shapes of the segmented wafers 20 and 23 are curved, the end shape of the joined wafer 24 is joined to a shape like "3." When the end shapes of the segmented wafers 20 and 23 are triangular, joining repeats one inflection point, resulting in a polygonal shape with 5 inflection points at the end of the joined wafer 24. When the end shapes of the segmented wafers 20 and 23 are trapezoidal, joining repeats one inflection point, resulting in a polygonal shape with 7 inflection points at the end of the joined wafer 24. In this case, beveling after joining is unnecessary, and the amount of cutting is small enough, thus increasing the area of ​​the joined wafer 24.

[0036] Alternatively, the pre-joining wafers 20 and 23 can be beveled instead of the joining wafer 24. In this case, the bevel shape of the joining wafer is the same as that of a normal wafer that is not joined, appearing as a curved shape or trapezoidal shape in cross-sectional view, such as “)”. In this case, the chip prevention effect of the joining wafer 24 is improved compared to a shape such as “3”. Furthermore, beveling can be performed on both the pre-joining wafers 20 and 23 and the joining wafer 24 after joining. In this case, both chip prevention during processing and chip prevention effects on the joining wafer 24 can be achieved.

[0037] Next, in step S106, an epitaxial film 25 is formed on the bonding wafer 24, and a device structure 26 is formed on the epitaxial film 25. The wafer thus formed is referred to as the bonding wafer 27.

[0038] Next, in step S107, the bonding wafer 27 is divided in the thickness direction to obtain a device-bearing wafer 29 containing the device structure 26 and a divided wafer 30 not containing the device structure 26. The device-bearing wafer 29 is also referred to as the second device-bearing wafer, and the divided wafer 30 is also referred to as the second divided wafer. The device-bearing wafer 29 has an epitaxial film 25 formed on the SiC wafer 10, and the device structure 26 is formed on the epitaxial film 25. This process is the same as step S102.

[0039] Furthermore, the bonding wafer 27 includes bonding surfaces of the two segment wafers 20 and 23, which preferably are not included in the device wafer 29. This avoids variations in device characteristics caused by the bonding surfaces in the device wafer 29. Here, in the case where the bonding wafer 27 is formed by room temperature bonding, an amorphous layer is generated at its bonding interface, so it is also preferable that the SiC wafer 28 containing the device wafer 29 does not contain an amorphous layer. However, even if the device wafer 29 includes bonding surfaces of the two segment wafers 20 and 23, this is not always a problem when considering the type of device structure or the required characteristics of the device. In this case, it is not necessary to eliminate the bonding surfaces when obtaining the device wafer 29, which increases the freedom of process adjustment or thickness adjustment in the wafer dicing process.

[0040] The device wafer 29 obtained in step S107 is subjected to the back-side processing (not shown) of step S103 again. Alternatively, the diced wafer 30 obtained in step S107 may be subjected to the processing after step S104 again. Afterwards, the diced wafer 30 can be further utilized in the fabrication of device wafers by bonding it with other diced wafers. That is, the diced wafer 30, which is the second diced wafer, is used as a new first diced wafer, and the processing of steps S105 to S107 is repeated at least once.

[0041] Thus, three device wafers 19, 22, and 29 are obtained from two SiC wafers 13 and 17. By repeatedly performing the above process, a larger number of device wafers than the original SiC wafers can be obtained. In addition, based on SiC wafers with a small amount of various defects, so-called high-quality wafers, multiple device wafers can be fabricated, and a large number of high-quality devices can be efficiently produced.

[0042] Regarding a bonded wafer formed by bonding multiple divided wafers, depending on the state of each divided wafer, the amount of various defects such as crystal defects, for example, threading dislocations, may differ across the bonding surface. In this case, the density of crystal defects present on the surface layer is different between the device structure formation surface side and the opposite side of the bonded wafer, or the density of crystal defects present near the bonding interface is different. Furthermore, threading dislocations that are continuous from the surface to the back surface in a normal wafer become discontinuous at the bonding interface in the bonded wafer. However, even when the amount of various defects differs between multiple divided wafers, the influence on the device process or device characteristics is negligible. Here, by appropriately selecting the device structure or divided wafers, the influence of the above-mentioned defect discontinuity, etc. on the device process or device characteristics can be further suppressed. Furthermore, when the bonding surface is not included in the device wafer, the influence of the above-mentioned defect discontinuity, etc. on the device characteristics can be eliminated.

[0043] <A-2. Practical Application>

[0044] Figures 3 to 6 is a diagram showing the Figure 1 flow of the situation where the basic process shown is put into actual use. Figure 3 and Figure 4 shows an example of the process in a 500-μm-thick SiC wafer, Figure 5 and Figure 6 shows an example of the process in a 350-μm-thick SiC wafer.

[0045] Figure 3 and Figure 5 show the process from SiC wafers A3 and B3 to the formation of the bonded wafer E1. Figure 4 and Figure 6 show the process from the bonded wafer E1 and SiC wafer F3 to the formation of the bonded wafer G1. In Figures 3 to 6 , the numbers shown in the wafers represent the thickness (μm) of the wafers. In addition, the numbers enclosed in parentheses above or below the wafers represent the thickness (μm) of the removed wafers. In addition, the dashed lines within the wafers represent the bonding surfaces, and the numbers enclosed in large parentheses next to the bonding surfaces represent the depth (μm) of the bonding surfaces, that is, the depth (μm) from the surface of the bonded wafer to the bonding surface. However, the thicknesses and depths of the respective layers shown in these figures are examples and can be appropriately changed.

[0046] like Figure 3 As shown, SiC wafers A3 and B3 are prepared. The thickness of SiC wafers A3 and B3, including the epitaxial film, is 510 μm. SiC wafer A3 is a wafer on which device structure A2 is formed on the surface of SiC wafer A1. Similarly, SiC wafer B3 is a wafer on which device structure B2 is formed on the surface of SiC wafer B1. Furthermore, in... Figures 3 to 6 In the description, the device structure is assumed to include an epitaxial film. More specifically, device structure A2 includes an epitaxial film formed on a SiC wafer A1 and a device structure formed on that epitaxial film. This is in... Figures 3 to 6 The same applies to the construction of other devices mentioned in the description.

[0047] The SiC wafer A3 is diced into a device-embedded wafer A4 with device structure A2 and a diced wafer A12 without device structure A2. Device-embedded wafer A4 consists of a SiC wafer A11 and the device structure A2 thereon. 50 μm of the back side of the SiC wafer A11 is removed, resulting in a thickness of 100 μm. Divided wafer A12 has 50 μm of surface material and 10 μm of back side material removed, resulting in a thickness of 300 μm.

[0048] The wafer A12 is then split, and 25 μm is removed from the back side, resulting in a thickness of 275 μm.

[0049] The SiC wafer B3 is diced into a device-bearing wafer B4 with device structure B2 and a diced wafer B12 without device structure B2. Device-bearing wafer B4 consists of a SiC wafer B11 and the device structure B2 thereon. 50 μm of the back side of the SiC wafer B11 is removed, resulting in a thickness of 100 μm. Divided wafer B12 has 50 μm of surface material and 10 μm of back side material removed, resulting in a thickness of 300 μm.

[0050] The surface of wafer B12 is then removed by 25 μm, resulting in a thickness of 275 μm.

[0051] Next, the split wafers A12 and B12 are joined together to obtain a joined wafer C1 with a thickness of 550 μm. Here, the depth of the joining surface of the joined wafer C1 is 275 μm.

[0052] Subsequently, 50 μm of the surface thickness of the bonding wafer C1 was removed, resulting in a thickness of 500 μm for the bonding wafer C1. Here, the depth of the bonding surface of the bonding wafer C1 is 225 μm.

[0053] Next, a device structure C2 is formed on the bonding wafer C1. The wafer consisting of the bonding wafer C1 and the device structure C2 is called the bonding wafer C3. The thickness of the bonding wafer C3 is 510 μm, and the depth of the bonding surface in the bonding wafer C3 is 235 μm.

[0054] Subsequently, the bonding wafer C3 is divided into a device-bearing wafer C4 with device structure C2 and a segmented wafer C5 without device structure C2. The device-bearing wafer C4 is composed of a SiC wafer A121, which is part of the segmented wafer A12, and the device structure C2 on the SiC wafer A121. The bonding surface in the bonding wafer C3 is not included in the device-bearing wafer C4. By removing 50 μm from the back side of the SiC wafer A121, the thickness of the device-bearing wafer C4 becomes 100 μm. The segmented wafer C5 is composed of a SiC wafer A122, which is part of the segmented wafer A12, and a segmented wafer B12. The segmented wafer C5 has 50 μm of surface and 10 μm of back side removed, resulting in a thickness of 300 μm. Here, the depth of the bonding surface in the segmented wafer C5 is 35 μm.

[0055] The back side of the segmented wafer C5 is then removed by 25μm, resulting in a thickness of 275μm.

[0056] Prepare SiC wafer D3. Device structure D2 is formed on the surface of SiC wafer D1 in SiC wafer D3.

[0057] The SiC wafer D3 is diced into a device-bearing wafer D4 with device structure D2 and a diced wafer D12 without device structure D2. Device-bearing wafer D4 consists of SiC wafer D11 and the device structure D2 thereon. By removing 50 μm from the back side of SiC wafer D11, the thickness of SiC wafer D11 becomes 100 μm. The surface of diced wafer D12 is removed by 50 μm, and the back side is removed by 10 μm, resulting in a thickness of 300 μm.

[0058] The wafer D12 is then divided, and 25 μm of the surface is removed, resulting in a thickness of 275 μm.

[0059] Next, the segmented wafers C5 and D12 are bonded to obtain a bonded wafer E1 with a thickness of 550 μm. At this point, the bonded wafer E1 includes a first bonding surface that serves as the bonding surface between the SiC wafer A122 and the segmented wafer B12, and a second bonding surface that serves as the bonding surface between the segmented wafer B12 and the segmented wafer D12. The depth of the first bonding surface is 35 μm, and the depth of the second bonding surface is 275 μm.

[0060] After that, as Figure 4 As shown, 50 μm of the surface of the bonding wafer E1 is removed. Thus, the SiC wafer A122 is removed from the bonding wafer E1, resulting in a thickness of 500 μm for the bonding wafer E1. Here, the depth of the bonding surface in the bonding wafer E1 is 225 μm.

[0061] Next, a device structure E2 is formed on the surface of the bonding wafer E1. The SiC wafer consisting of the bonding wafer E1 and the device structure E2 thereon is called the bonding wafer E3. The thickness of the bonding wafer E3 is 510 μm, and the depth of the bonding surface in the bonding wafer E3 is 235 μm.

[0062] Subsequently, the bonding wafer E3 is diced into a device-bearing wafer E4 with device structure E2 and a diced wafer E5 without device structure E2. Device-bearing wafer E4 consists of a SiC wafer B121, which is part of diced wafer B12, and the device structure E2 thereon. Divided wafer E5 consists of diced wafer D12 and a SiC wafer B122, which is part of diced wafer B12. 50 μm of the surface layer and 10 μm of the back layer of diced wafer E5 are removed, resulting in a thickness of 300 μm.

[0063] The wafer D12 is then split, and 25μm is removed from the back side, resulting in a thickness of 275μm.

[0064] Prepare SiC wafer F3. Device structure F2 is formed on the surface of SiC wafer F1 on SiC wafer F3.

[0065] The SiC wafer F3 is diced into a device-embedded wafer F4 with device structure F2 and a diced wafer F12 without device structure F2. Device-embedded wafer F4 consists of a SiC wafer F11 and the device structure F2 thereon. By removing 50 μm from the back side of SiC wafer F11, the thickness of SiC wafer F11 becomes 100 μm. Divided wafer F12 has 50 μm removed from its surface and 10 μm removed from its back side, resulting in a thickness of 300 μm.

[0066] The wafer F12 is then divided, and 25 μm of the surface is removed, resulting in a thickness of 275 μm.

[0067] Next, the segmented wafers E5 and F12 are bonded together to obtain a bonded wafer G1 with a thickness of 550 μm. At this point, the bonded wafer G1 includes a first bonding surface that serves as the bonding surface between the SiC wafer B122 and the segmented wafer D12, and a second bonding surface that serves as the bonding surface between the segmented wafers D12 and F12. The depth of the first bonding surface is 35 μm, and the depth of the second bonding surface is 275 μm.

[0068] Subsequently, 50 μm of the surface of the bonding wafer G1 was removed. This resulted in the removal of the SiC wafer B122 from the bonding wafer G1, leaving a thickness of 500 μm for G1. The depth of the bonding surface within the bonding wafer G1 was 225 μm.

[0069] exist Figure 3 as well as Figure 4The text describes how, even after the formation of the bonding wafer G1, a device structure can still be formed on the bonding wafer G1, and then a dicing wafer can be further removed from the bonding wafer G1. In this way, by repeatedly performing the bonding wafer obtained by bonding the dicing wafers to each other, the formation of the device structure on the bonding wafer, and the dicing of the bonding wafer, it is possible to repeatedly fabricate a device wafer using the dicing wafers.

[0070] Three tape-device wafers, A4, B4, and C4, are obtained from two SiC wafers A3 and B3. Additionally, five tape-device wafers, A4, B4, C4, D4, and E4, are obtained from three SiC wafers A3, B3, and D3. In other words, (2n-1) tape-device wafers are obtained from n SiC wafers (10). This allows for the production of tape-device wafers with a reduced number of SiC wafers, resulting in cost reduction.

[0071] exist Figure 3 as well as Figure 4 In the example, SiC wafers A3, B3, D3, and F3 are described as wafers with 10 μm epitaxial films formed on a 500 μm thick SiC wafer. However, the thickness of each layer constituting SiC wafers A3, B3, D3, and F3 is not limited to this and can be appropriately varied according to the desired device characteristics or wafer thickness. For example, Figure 5 as well as Figure 6 This illustrates a case where the wafer thickness is 350 μm and the epitaxial film thickness is 10 μm.

[0072] exist Figure 3 as well as Figure 4 In the example, the thickness of the device wafers A4, C4, and E4 is 100 μm, but it is not limited to this and can be appropriately selected according to the device characteristics. Additionally, 50 μm of the back side of the SiC wafers A11, A121, and B121 is removed, but it is not limited to this. To remove the damage layer from the dicing process and achieve the desired thickness for the device wafers A4, C4, and E4, the amount of back side removal for the SiC wafers A11, A121, and B121 can be appropriately selected between 10 μm and 100 μm.

[0073] exist Figure 3 as well as Figure 4 In the example, the thickness of the segmented wafers A12, C5, and E5 is 275 μm, but it is not limited to this. The thickness of the segmented wafers A12, C5, and E5 can be 50 μm or more, preferably 80 μm or more, and most preferably 100 μm or more. This prevents the segmented wafers from breaking, and allows for the use of wafers C4 and E4 without bonding surfaces. Since the wafers do not contain bonding surfaces, the influence of bonding surfaces on device characteristics can be eliminated, and characteristics equivalent to those of devices using conventional wafers without bonding methods can be obtained.

[0074] The surfaces of the diced wafers A12, C5, and E5 are removed by 50 μm, but not limited to this. In order to remove the damaged layer during dicing or to make the diced wafers A12, C5, and E5 reach the desired thickness, for example, the amount of surface removal of the diced wafers A12, C5, and E5 can be appropriately selected between 10 μm and 100 μm.

[0075] exist Figure 3 as well as Figure 4 In the example, the processing of the back side of the segmented wafers A12, C5, and E5 is performed in two steps, but it is not limited to this; it can also be performed simultaneously, or it can be performed in multiple steps. When performed simultaneously, the number of steps is reduced. When performed in multiple steps, an improvement in the quality after removal can be expected.

[0076] exist Figure 3 as well as Figure 4 In the example, the back surfaces of each of the segmented wafers A12, C5, and E5 are removed by a total of 35 μm in two processing steps. However, the amount of back surface removal for segmented wafers A12, C5, and E5 is not limited to this; any method that allows segmented wafers A12, C5, and E5 to achieve the desired thickness can be selected. Furthermore, if the desired thickness of segmented wafers A12, C5, and E5 can be achieved through surface processing, back surface processing may not be necessary. By removing the back surfaces of segmented wafers A12, C5, and E5, laser-printed text applied to ordinary wafers can be removed, thus eliminating the influence of laser-printed text during bonding, i.e., damage or unevenness on the bonding surface, and improving the quality of the bonded wafers. This effect is evident when the total back surface removal amount of the segmented wafers is 1 μm or more, and becomes particularly significant when it is 30 μm or more.

[0077] exist Figure 3 as well as Figure 4 In the examples, the total amount of material removed from the surfaces of segmented wafers A12, C5, and E5, as well as segmented wafers B12, D12, and F12, differs, but can also be the same. Under the same conditions, the processing technology for these segmented wafers can be standardized, thus offering an advantage from a productivity perspective. Furthermore, in Figure 3 as well as Figure 4 In the example, the total amount of material removed from the back side of the segmented wafers A12, C5, E5 and B12, D12, F12 may differ, but they can also be the same. Under the same conditions, the processing technology of these segmented wafers can be standardized, which is advantageous from a productivity point of view.

[0078] exist Figure 3 as well as Figure 4In the example, two 275μm thick segment wafers are bonded together to create bonded wafers C1, E1, and G1 with a thickness of 550μm. However, the thickness of the segment wafers is not limited to this and can be appropriately varied. Alternatively, segment wafers of different thicknesses can be bonded together; for example, segment wafers A12 and B12 can have different thicknesses.

[0079] exist Figure 3 as well as Figure 4 In the example, 50 μm of the surface layer of the bonding wafers C1, E1, and G1 is removed. However, the amount of surface layer removal for the bonding wafers C1, E1, and G1 is not limited to this, and the method for achieving the desired thickness of the bonding wafers C1, E1, and G1 can be adapted accordingly. Furthermore, if the desired thickness is achieved at the time of bonding, this removal is unnecessary. Moreover, the film thickness of the bonding wafer does not need to be the same as the film thickness of the original wafer, and can be different. When the bonded wafer is thicker, cracking and warping can be further reduced during device manufacturing. Under the same conditions, the same process as for conventional wafers can be used. Even in the case of thin wafers, if the thickness of the bonding wafer is 100 μm or more, more preferably 250 μm, and most preferably 300 μm or more, the device manufacturing process becomes easier.

[0080] In addition, finishing processes such as grinding, lapping, or CMP can be performed after each film thickness removal step. Especially for the finishing of the bonding surfaces of split wafers, precision machining is sometimes required to reduce surface roughness, and mirror finishing using lapping or CMP is preferable. This results in high-quality bonded wafers.

[0081] In addition, Figure 3 as well as Figure 4 The device structures A2, B2, C2, D2, E2, and F2 illustrated herein can be the same or different. That is, the device structures on a typical wafer and the device structures on a bonded wafer can be different. For example, device structure A2 and device structure C2 can also be different. When the bonded wafer is thin and therefore more sensitive to warpage or breakage than a typical wafer, manufacturing devices on this bonded wafer with low process load can avoid warpage or breakage. Alternatively, by manufacturing devices that require thick epitaxial films, the effects of warpage or breakage on the bonded wafer can also be reduced. The device structures referred to herein can also be structures that form semiconductor elements such as diodes, transistors, and thyristors, or combinations thereof.

[0082] In addition, the device structure on the bonded wafer can be determined based on the manufacturing yield of devices fabricated using normal wafers. That is, when the quality of the normal wafer is low and the manufacturing yield of devices fabricated using it is low, a device structure insensitive to the quality of the wafer can be formed on the bonded wafer obtained by dividing and bonding the wafer. In addition, when the quality of the normal wafer is high and the manufacturing yield of devices fabricated using it is high, a device structure sensitive to the quality of the wafer can be formed on the bonded wafer obtained by dividing and bonding the wafer. Here, the quality of the wafer is sometimes determined by the amount or type of defects that affect device characteristics. Therefore, not only based on the manufacturing yield of the device, but also at least one of the amount and type of the defects can be measured in advance before fabricating the device structure, and after obtaining information for judging the desired characteristics, the device structure on the bonded wafer can be determined. Thus, by changing the formed device structure between wafers with high yield and high quality and wafers with low yield and low quality, the overall manufacturing yield of the factory can be improved.

[0083] In addition, even when the processes exemplified in Figure 5 and Figure 6 are appropriately changed, (2n - 1) device wafers can be obtained from n SiC wafers 10. Thus, the usage amount of SiC wafers is reduced, and a cost reduction effect can be obtained. That is, the effects of the technology of the present disclosure can be sufficiently obtained.

[0084] In Figure 3 and Figure 4 only the thickness of the wafer is different from Figure 3 and Figure 4 , so the description of these figures is omitted. Similar to Figure 5 and Figure 6 , Figure 1 and Figure 3 The exemplified numerical values can also be appropriately changed.

[0085] <A-3. Thickness of Wafer and Depth of Bonding Surface>

[0086] When using Figure 4When explaining with an example, when the bonding surface is included in the device wafer 29, the bonding surface sometimes affects the characteristics of the device. Especially in the case where poor bonding occurs at the bonding surface, it will have an adverse effect on the characteristics of the device. To avoid such risks, it is best to form the device wafer 29 avoiding the bonding surface of the bonding wafer. Therefore, the depth of the bonding surface in the bonding wafer 24 is preferably greater than the thickness of the device wafer 29. Considering this, the depth of the bonding surface in the bonding wafer 24 is preferably 50 μm or more, more preferably 80 μm or more, and most preferably 100 μm or more. Thus, even when using a bonding wafer to form a device structure, the bonding surface will not affect the device characteristics, and characteristics equivalent to those obtained when using a normal wafer without bonding can be obtained.

[0087] In addition, in Figure 5 and Figure 6 In the bonding wafers C1, E1, and G1 before forming the device structure shown, the depth of the bonding surface is 225 μm in each case. Additionally, in Figure 7 and Figure 8 In the bonding wafers C1, E1, and G1 before forming the device structure shown, the depth of the bonding surface is 160 μm in each case.

[0088] As Figure 3 shown, when the bonding wafer is formed by bonding two divided wafers, the depth of its bonding surface is preferably 50 μm or more from the surface of the bonding wafer. Additionally, as Figure 4 shown, when the bonding wafer is formed by bonding three divided wafers, the depth of the shallowest bonding surface is preferably 50 μm or more from the surface of the bonding wafer.

[0089] In Figure 5 and Figure 6 the thickness of the bonding wafers C1, E1, and G1 is 500 μm, and in Figures 1 to 6 and Figure 9 the thickness of the bonding wafers C1, E1, and G1 is 350 μm. The thickness of these bonding wafers is determined considering that no warping occurs when forming a device structure on the bonding wafer. That is, the thickness of the bonding wafer is preferably 100 μm or more, more preferably 250 μm, and most preferably 300 μm or more.

[0090] <A-4. Timing of wafer division>

[0091] In Figure 10 the divided wafers were divided from the SiC wafer with a device structure. That is, the division was performed after forming the device structure on the SiC wafer. However, the timing of dividing the divided wafers that constitute the bonding wafer from the original SiC wafer is not limited to after forming the device structure on the original SiC wafer. In Figure 10In this diagram, a "+" sign indicates the timing of dicing for various wafer types. Divided wafers that become the surface side of the bonded wafer after subsequent bonding, and divided wafers that become the back side, can both be diced before epitaxial film formation on the original SiC wafer (pre-epitaxy), after epitaxial film formation on the original SiC wafer but before device fabrication (post-epitaxy), or after device fabrication on the original SiC wafer. Furthermore, the timing of dicing from the original SiC wafer can differ between divided wafers that become the surface side of the bonded wafer after subsequent bonding and divided wafers that become the back side. In other words, the dicing process can be performed before epitaxial film formation, before device fabrication, or after device fabrication.

[0092] Figures 1 to 6 This illustrates the basic process of dicing SiC wafers before forming the epitaxial film. The following is a description of the process. Figures 3 to 6 Explain the basic process.

[0093] First, prepare a high-quality SiC wafer 40 and a low-quality SiC wafer 43. The quality difference between the two SiC wafers 40 and 43 is manifested in, for example, the number of defects or flatness. Compared with the low-quality SiC wafer 43, the high-quality SiC wafer 40 has fewer surface defects or dislocation density in the crystal. The quality of the SiC wafers is evaluated using methods such as optical microscopy, photoluminescence imaging, or X-ray diffraction analysis.

[0094] The SiC wafer 40 is divided into two high-quality wafers 41 and 42. Similarly, the SiC wafer 43 is divided into two low-quality wafers 44 and 45. Then, the damaged layer formed in the cut surfaces of the wafers 41, 42, 44, and 45 is removed by grinding or polishing.

[0095] Next, the high-quality segmentation wafer 41 and the low-quality segmentation wafer 44 are bonded together to form a bonded wafer 46. Additionally, the high-quality segmentation wafer 42 and the low-quality segmentation wafer 45 are bonded together to form a bonded wafer 47.

[0096] Next, an epitaxial film 48 and a device structure 49 are formed on the bonding wafer 46. The wafer composed of the bonding wafer 46, the epitaxial film 48, and the device structure 49 is called the bonding wafer 50. Similarly, an epitaxial film 51 and a device structure 52 are formed on the bonding wafer 47. The wafer composed of the bonding wafer 47, the epitaxial film 51, and the device structure 52 is called the bonding wafer 53.

[0097] Next, the bonding wafer 50 is divided into a device wafer 54 having a device structure 49 and a divided wafer 44. The device wafer 54 is configured to include a high-quality divided wafer 41, an epitaxial film 48, and a device structure 49. Similarly, the bonding wafer 53 is divided into a device wafer 55 having a device structure 52 and a divided wafer 45. The device wafer 55 is configured to include a high-quality divided wafer 42, an epitaxial film 51, and a device structure 52.

[0098] According to this method, by using a low-quality SiC wafer as the wafer on the back side, i.e., the support substrate, in the bonding wafer, multiple device wafers are fabricated from high-quality SiC wafers. In addition, by dividing multiple wafers from the initial SiC wafer before forming the epitaxial film, all the divided wafers can be reused. Furthermore, regarding the point of making the high-quality divided wafer the surface side of the bonding wafer and the low-quality wafer the back side of the bonding wafer, it can also be applied in the case of dividing the wafer after forming the device as described in Figure 3 . By evaluating the quality of the wafers as in this method and effectively using the high-quality divided wafers as the surface of the bonding wafer, high-quality wafers can be utilized more efficiently, the overall device yield as a manufacturing factory can be improved, and the productivity can be further enhanced.

[0099] <A-5. Variation Example>

[0100] In the above description, the wafer as the division source is a single-crystalline SiC wafer. In this case, since SiC is easy to process, it has the advantage of being easy to bond the divided wafers to each other. However, the wafer as the division source (e.g., the first wafer, the first divided wafer, or the first bonding wafer, etc.) is not limited to SiC and can also be composed of other single-crystalline materials such as diamond, gallium nitride (GaN), gallium oxide (Ga2O3), aluminum nitride (AlN), etc. Even in such a case, since there is no difference in the coefficient of thermal expansion between the divided wafers, bonding can be performed stably.

[0101] In Figure 5 's example, the thicknesses of the divided wafers constituting the bonding wafer are the same. For example, in Figures 3 to 6 , the thicknesses of the divided wafers A12 and B12 constituting the bonding wafer C1 are both 275 μm. Additionally, in Figure 10 , the thicknesses of the divided wafers A12 and B12 constituting the bonding wafer C1 are both 190 μm. However, the thicknesses of the divided wafers constituting the bonding wafer can also be different.

[0102] In Figure 10In the example, one bonded wafer is divided into one device-bearing wafer and one divided wafer without a device structure. However, one bonded wafer can also be divided into one device-bearing wafer and multiple divided wafers without a device structure.

[0103] In addition, in Figure 1 the example, one SiC wafer 40 is divided into two divided wafers 41 and 42. However, one SiC wafer 40 can also be divided into multiple divided wafers. This is the same for the SiC wafer 43 in Figure 1 the example.

[0104] <A-6. Effects>

[0105] Illustrated with Figure 11 the example, the method for manufacturing a semiconductor device according to Embodiment 1 includes: (a) a step of obtaining at least one divided wafer 20, 23 without a device structure from SiC wafers 13, 17 by dividing each of the multiple SiC wafers 13, 17 in the thickness direction; (b) a step of bonding the multiple divided wafers 20, 23 obtained from different SiC wafers 13, 17 to obtain a bonded wafer 24; and (c) a step of forming a device structure 26 on the surface of the bonded wafer 24. Thus, by reusing the remaining divided wafer 20 after obtaining the device-bearing wafer 19 from the SiC wafer 13 together with other divided wafers 23, a device-bearing wafer 29 can be further obtained.

[0106] Regarding the method of forming a thick epitaxial layer on a divided wafer as a method of reusing wafers described in Patent Document 1, there are problems such as poor economy, and the wafers are prone to warping and cracking. In contrast, in the method of this embodiment, the divided wafers are bonded to each other, so the wafers can be reused at low cost while suppressing warping.

[0107] In addition, for Figure 11 the example, the bonded wafer 24 is a bonded wafer formed by bonding multiple divided wafers 20, 23 without a device structure divided from different SiC wafers 13, 17. And, at a position 50 μm or more deep from the surface of the bonded wafer 24, there are bonding surfaces of the multiple divided wafers 20, 23. Thus, a device-bearing wafer 29 without a bonding surface can be manufactured using the bonded wafer 24. Therefore, the influence of the bonding surface on the device characteristics can be avoided.

[0108] <B. Embodiment 2>

[0109] In Embodiment 1, multiple divided wafers are bonded to form a bonded wafer. In contrast, in Embodiment 2, a bonded wafer is formed by bonding one divided wafer and a single-crystal wafer that is not a divided wafer.

[0110] <B-1. Basic Process>

[0111] Figure 11 It is a schematic diagram showing the outline of the basic process in the manufacturing method of the semiconductor device in Embodiment 2. Hereinafter, referring to Figure 12 , the manufacturing method of the semiconductor device in Embodiment 2 will be described.

[0112] First, prepare a SiC wafer 63 and a single crystal SiC wafer 67. An epitaxial film 61 is formed on the SiC wafer 60 of the SiC wafer 63, and a device structure 62 is further formed on the epitaxial film 61.

[0113] Next, the SiC wafer 63 is divided into a device wafer 65 having the device structure 62 and a divided wafer 66 not having the device structure 62. The device wafer 65 is configured to include a SiC wafer 64 divided from the SiC wafer 60, the epitaxial film 61 on the SiC wafer 64, and the device structure 62 on the epitaxial film 61.

[0114] Damage layers are generated on the back surface of the device wafer 65 and the front surface of the divided wafer 66 due to the division. These damage layers are removed by grinding or polishing, etc.

[0115] Next, the divided wafer 66 is bonded to the single crystal SiC wafer 67 to form a bonded wafer 68 in this way. The divided wafer 66 is on the front surface side of the bonded wafer 68, and the single crystal SiC wafer 67 is on the back surface side of the bonded wafer 68. In this way, the single crystal SiC wafer 67 is used as a support substrate for the divided wafer 66.

[0116] After that, an epitaxial film 69 is formed on the bonded wafer 68, and a device structure 70 is further formed on the epitaxial film 69. The wafer composed of the bonded wafer 68, the epitaxial film 69, and the device structure 70 is called a bonded wafer 71.

[0117] Next, the bonded wafer 71 is divided into a device wafer 72 having the device structure 70 and the single crystal SiC wafer 67. Here, it is preferable that the device wafer 72 does not include the bonding surface of the divided wafer 66 and the single crystal SiC wafer 67. Therefore, considering the thickness of the device structure 70, the bonding surface of the divided wafer 66 and the single crystal SiC wafer 67 in the bonded wafer 68 is preferably at a position deeper than 50 μm from the surface of the bonded wafer 68, more preferably at a depth of 80 μm, and most preferably at a position deeper than 100 μm. In other words, the thickness of the divided wafer 66 is preferably 50 μm or more, more preferably 80 μm or more, and most preferably 100 μm or more. Thereby, the bonding surface is not included in the device wafer 72, and the influence on the device caused by the bonding surface can be removed.

[0118] Thus, the single-crystal SiC wafer 67 is used as a support substrate when forming the device structure 70 on the diced wafer 66. After being diced from the bonding wafer 71, the single-crystal SiC wafer 67 can be used again as a support substrate for other diced wafers. Here, the support substrate sometimes does not have a warp, surface roughness, or surface unevenness suitable for bonding with the SiC wafer. Therefore, before bonding the SiC wafer and the support substrate, the surface of the SiC wafer that is to be bonded to the support substrate can be treated by grinding, polishing, or CMP, or the SiC wafer can be treated by applying pressure or heat, thereby forming a warp, surface roughness, or surface unevenness suitable for bonding with the support substrate in the SiC wafer or the support substrate, or both. This allows for better bonding between the SiC wafer and the support substrate.

[0119] Furthermore, the thickness of the single-crystal SiC wafer 67 diced from the bonding wafer 71 can also vary compared to the original thickness of the single-crystal SiC wafer 67. That is, when dicing the single-crystal SiC wafer 67 from the bonding wafer 71, it is not necessary to dice at the bonding surface between the dicing wafer 66 and the single-crystal SiC wafer 67. Alternatively, the bonding surface can be removed by removing the damaged layer of the diced single-crystal SiC wafer 67. Alternatively, the bonding surface can be left in the diced single-crystal SiC wafer 67.

[0120] exist Figure 12 In the example, one SiC wafer 63 is divided into one wafer 65 with a device and one partitioned wafer 66 without a device structure. However, one SiC wafer 63 can also be divided into one wafer 65 with a device and multiple partitioned wafers without a device structure.

[0121] Alternatively, a single-crystal GaN wafer or a single-crystal gallium oxide wafer can be used instead of a single-crystal SiC wafer 67. From the perspective of thermal management in device manufacturing processes, such as heat dissipation or heat storage of the wafer, such alternative wafers can also be used.

[0122] Alternatively, wafers made of other materials mentioned in Embodiment 1 can be used instead of SiC wafer 63. In this case, when the wafer used as the support substrate and the dicing wafer are made of the same material, it is easy to ensure bonding strength.

[0123] Regarding a bonded wafer formed by bonding a divided wafer and a support substrate, depending on the state of each wafer, the amount of various defects such as crystal defects, for example, threading dislocations, may differ across the bonding surface. In such a case, the density of crystal defects present on the surface layer is different between the device structure formation surface side and the opposite side of the bonded wafer, or the density of crystal defects present near the bonding interface is different. Furthermore, threading dislocations that are continuous from the surface to the back surface in a normal wafer become discontinuous at the bonding interface in the bonded wafer. However, even when the amount of various defects differs between multiple wafers, the impact on the device process or device characteristics is negligible. Here, by appropriately selecting the device structure, divided wafer, or support substrate, the impact of discontinuities and the like of the above-mentioned defects on the device process or device characteristics can be further suppressed. Furthermore, when the bonding surface is not included in the wafer with devices, the impact of discontinuities and the like of the above-mentioned defects on the device characteristics can be eliminated.

[0124] <B-2. Modified Example>

[0125] Figure 12 is a schematic diagram showing the outline of the basic process in the manufacturing method of a semiconductor device in the modified example of Embodiment 2. In this modified example, the SiC wafer is divided before forming the epitaxial film. Hereinafter, referring to Figure 10 , the manufacturing method of the semiconductor device in the modified example of Embodiment 2 will be described.

[0126] First, prepare a SiC wafer 80 and two single-crystal SiC wafers 83, 84.

[0127] Next, the SiC wafer 80 is divided into two divided wafers 81, 82.

[0128] Damage layers are generated on the back surface of the divided wafer 81 and the surface of the divided wafer 82 due to the division. These damage layers are removed by grinding or polishing, etc.

[0129] After that, the divided wafer 81 and the single-crystal SiC wafer 83 are bonded to form a bonded wafer 85, and the divided wafer 82 and the single-crystal SiC wafer 84 are bonded to form a bonded wafer 86. In this way, the single-crystal SiC wafers 83, 84 are used as the support substrates for the divided wafers 81, 82.

[0130] Next, an epitaxial film 87 is formed on the bonded wafer 85, and a device structure 88 is formed on the epitaxial film 87. The wafer composed of the bonded wafer 85, the epitaxial film 87, and the device structure 88 is called a bonded wafer 89. Similarly, an epitaxial film 90 is formed on the bonded wafer 86, and a device structure 91 is formed on the epitaxial film 90. The wafer composed of the bonded wafer 86, the epitaxial film 90, and the device structure 91 is called a bonded wafer 92.

[0131] Subsequently, the bonding wafer 89 is divided into a device wafer 93 with device structure 88 and a single-crystal SiC wafer 83. The device wafer 93 includes a segmentation wafer 81, an epitaxial film 87, and the device structure 88. Similarly, the bonding wafer 92 is divided into a device wafer 94 with device structure 91 and a single-crystal SiC wafer 84. The device wafer 94 includes a segmentation wafer 82, an epitaxial film 90, and the device structure 91.

[0132] Here, the device wafers 93 and 94 preferably do not include the bonding surfaces of the segmented wafers 81 and 82 and the single-crystal SiC wafers 83 and 84. Therefore, considering the thickness of the device structures 88 and 91, the bonding surfaces of the segmented wafers 81 and 82 and the single-crystal SiC wafers 83 and 84 in the bonding wafers 85 and 86 are preferably located at a depth of 50 μm or more from the surface of the bonding wafers 85 and 86, more preferably at a depth of 80 μm, and most preferably at a depth of 100 μm or more. In other words, the thickness of the segmented wafers 81 and 82 is preferably 50 μm or more, more preferably 80 μm or more, and most preferably 100 μm or more. Thus, by not including bonding surfaces in the device wafers 93 and 94, the influence on the device caused by bonding surfaces can be eliminated.

[0133] According to the above method, by using single-crystal SiC wafers 83 and 84 as support substrates, device structures 88 and 91 can be formed on multiple segmented wafers 81 and 82 divided from the SiC wafer. In addition, single-crystal SiC wafers 83 and 84 divided from bonding wafers 89 and 92 can be used again as support substrates for other segmented wafers.

[0134] Furthermore, the thickness of the single-crystal SiC wafers 83 and 84 slicing from the bonding wafers 89 and 92 can also vary compared to the original thickness of the single-crystal SiC wafers 83 and 84. That is, when slicing the single-crystal SiC wafers 83 and 84 from the bonding wafers 89 and 92, it is not necessary to slicing at the bonding surface between the slicing wafers 81 and 82 and the single-crystal SiC wafers 83 and 84. Alternatively, the bonding surface can be removed by removing the damaged layer from the slicing single-crystal SiC wafers 83 and 84. Alternatively, the bonding surface can be left in the slicing single-crystal SiC wafers 83 and 84.

[0135] exist Figure 13 In the example, one SiC wafer 80 is divided into two wafers 81 and 82. However, one SiC wafer 80 can also be divided into three or more wafers.

[0136] Alternatively, wafers made of other materials mentioned in Embodiment 1 can be used instead of SiC wafer 80. In this case, to ensure bonding strength, the wafer used as the support substrate and the dicing wafer are preferably made of the same material.

[0137] <B-3. Effect>

[0138] The manufacturing method of the semiconductor device according to Embodiment 2 includes: (a) a process of obtaining divided wafers by dividing a wafer in the thickness direction; (b) a process of bonding the divided wafers to a single crystal support substrate to obtain bonded wafers; and (c) a process of forming a device structure on the bonded wafers. Thus, it is possible to reuse the wafer to manufacture a semiconductor device with high productivity while suppressing wafer breakage.

[0139] In addition, the bonded wafer according to Embodiment 2 is preferably a bonded wafer formed by bonding a divided wafer that does not include a device structure divided from the wafer to the support substrate, and a bonding surface of the divided wafer and the support substrate exists at a position 50 μm or more deep from the surface. In this case, when a device structure is formed on the bonded wafer and then the wafer with the device structure including the device structure is divided from the bonded wafer, the bonding surface is not included in the wafer with the device structure, so the influence on the device caused by the bonding surface can be removed.

[0140] In the case of using the divided wafer as the support substrate shown in Embodiment 1 (for example Figure 13 the process shown), the wafer that becomes the support substrate is manufactured by dividing a normal wafer, so sometimes there are limitations in the thickness of the support substrate, or waste occurs when removing the support substrate or the divided wafer to obtain a bonded wafer with a desired film thickness. In the present embodiment, the support substrate is directly manufactured by dividing from an ingot. Therefore, there is no limitation on the plate thickness, and a single crystal wafer with the necessary plate thickness can be directly manufactured as the support substrate, so waste can be reduced. Thus, a high cost reduction effect can be obtained. In addition, by using a low-quality crystal with many crystal defects that is not suitable for device manufacturing as the support substrate, the material loss in the overall manufacturing process can be reduced.

[0141] <C. Embodiment 3>

[0142] In Embodiment 2, a bonded wafer is formed by bonding one divided wafer to a single crystal wafer that is not a divided wafer. In contrast, in Embodiment 3, a bonded wafer is formed by bonding one divided wafer to a polycrystalline wafer that is not a divided wafer.

[0143] <C-1. Basic process>

[0144] Figure 13 It is a schematic diagram showing the outline of the basic process in the manufacturing method of the semiconductor device in Embodiment 3. Hereinafter, refer to Figure 14 to describe the manufacturing method of the semiconductor device in Embodiment 3.

[0145] First, a SiC wafer 103 and a polycrystalline SiC wafer 107 are prepared. An epitaxial film 101 is formed on the SiC wafer 100 in the SiC wafer 103, and a device structure 102 is formed on the epitaxial film 101.

[0146] Next, the SiC wafer 103 is divided into a device-bearing wafer 105 having device structure 102 and a divided wafer 106 without device structure 102. The device-bearing wafer 105 is configured to have a SiC wafer 104 divided from the SiC wafer 100, an epitaxial film 101 on the SiC wafer 104, and a device structure 102 on the epitaxial film 101.

[0147] Damage layers are generated on the back side of the device wafer 105 and on the surface of the diced wafer 106 due to dicing. These damage layers are removed by grinding or polishing.

[0148] Next, the segmented wafer 106 is bonded to the polycrystalline SiC wafer 107 to form a bonded wafer 108. The segmented wafer 106 is on the surface side of the bonded wafer 108, and the polycrystalline SiC wafer 107 is on the back side of the bonded wafer 108. In this way, the polycrystalline SiC wafer 107 serves as a support substrate for the segmented wafer 106.

[0149] Subsequently, an epitaxial film 109 is formed on the bonding wafer 108, and then a device structure 110 is formed on the epitaxial film 109. The wafer composed of the bonding wafer 108, the epitaxial film 109, and the device structure 110 is called the bonding wafer 111.

[0150] Next, the bonding wafer 111 is divided into a device wafer 112 with device structure 110 and a polycrystalline SiC wafer 107. The polycrystalline SiC wafer 107 is then used as a support substrate when forming the device structure 110 on the diced wafer 106. After being diced from the bonding wafer 111, the polycrystalline SiC wafer 107 can be used again as a support substrate for other diced wafers. Here, the support substrate sometimes lacks structures such as warpage, surface roughness, or surface unevenness suitable for bonding with the SiC wafer. Therefore, before bonding the SiC wafer and the support substrate, the bonding surface of the SiC wafer to the support substrate can be treated by grinding, polishing, or CMP, or the SiC wafer can be treated by applying pressure or heating, thereby forming structures such as warpage, surface roughness, or surface unevenness suitable for bonding with the support substrate on the SiC wafer or the support substrate, or both. This allows for better bonding between the SiC wafer and the support substrate.

[0151] Furthermore, the thickness of the polycrystalline SiC wafer 107 slit from the bonding wafer 111 can vary compared to the original thickness of the polycrystalline SiC wafer 107. That is, when slitting the polycrystalline SiC wafer 107 from the bonding wafer 111, slitting can be performed at the bonding surface between the slitting wafer 106 and the polycrystalline SiC wafer 107, but this is not necessary. Alternatively, the bonding surface can be removed by removing the damaged layer from the slit polycrystalline SiC wafer 107. Alternatively, the bonding surface can be left in the slit polycrystalline SiC wafer 107.

[0152] The bonding wafer 108 includes a bonding surface between the segmented wafer 106 and the polycrystalline SiC wafer 107. The device wafer 112 preferably does not include this bonding surface. Therefore, the depth of the bonding surface between the segmented wafer 106 and the polycrystalline SiC wafer 107 in the bonding wafer 108 is preferably 50 μm or more, more preferably 80 μm or more, and most preferably 100 μm or more. In other words, the thickness of the segmented wafer 106, which is segmented from the SiC wafer 103, is preferably 50 μm or more, more preferably 80 μm or more, and most preferably 100 μm or more. Thus, by not including a bonding surface in the device wafer 112, the influence on the device caused by the bonding surface can be eliminated.

[0153] exist Figure 14 In the example, one SiC wafer 103 is divided into one wafer with device 105 and one diced wafer without device construction. However, one SiC wafer 103 can also be divided into one wafer with device 105 and multiple diced wafers without device construction.

[0154] Alternatively, wafers made of other materials also mentioned in Embodiment 1 can be used instead of SiC wafer 63. In this case, to ensure bonding strength, the wafer used as the support substrate and the dicing wafer are preferably made of the same material.

[0155] Regarding bonded wafers formed by joining split wafers and support substrates, depending on the state of each wafer, the amount of various defects, such as crystal defects and through dislocations, may differ at the bonding interface. In this case, the density of crystal defects present on the surface layer differs between the device fabrication side and the opposite side of the bonded wafer, or the density of crystal defects present near the bonding interface may differ. Furthermore, through dislocations that are continuous from the surface to the back side in a typical wafer become discontinuous at the bonding interface in a bonded wafer. However, even when the amount of various defects differs among multiple wafers, their impact on device fabrication or device characteristics is negligible. Here, by appropriately selecting the device fabrication, split wafers, or support substrate, the impact of the aforementioned defect discontinuities on device fabrication or device characteristics can be further suppressed. Furthermore, when the device wafer does not contain a bonding interface, the impact of the aforementioned defect discontinuities on device characteristics can be eliminated.

[0156] <C-2. Modified Example>

[0157] Figure 14 This is a schematic diagram showing the basic process in the manufacturing method of a semiconductor device in the modified example of Embodiment 3. In this modified example, the SiC wafer is divided before forming the epitaxial film. Additionally, the SiC wafer may also be divided after forming the epitaxial film and before forming the device structure. Hereinafter, referring to Figure 14 , the manufacturing method of the semiconductor device in the modified example of Embodiment 3 will be described.

[0158] First, prepare a SiC wafer 120 and two polycrystalline SiC wafers 123 and 124.

[0159] Next, the SiC wafer 120 is divided into two divided wafers 121 and 122.

[0160] On the back surface of the divided wafer 121 and the front surface of the divided wafer 122, damage layers are generated due to the division. These damage layers are removed by grinding or polishing, etc.

[0161] After that, the divided wafer 121 and the polycrystalline SiC wafer 123 are bonded to form a bonded wafer 125, and the divided wafer 122 and the polycrystalline SiC wafer 124 are bonded to form a bonded wafer 126. In this way, the polycrystalline SiC wafer 123 is used as the support substrate for the divided wafer 121, and the polycrystalline SiC wafer 124 is used as the support substrate for the divided wafer 122.

[0162] Next, an epitaxial film 127 is formed on the bonded wafer 125, and a device structure 128 is formed on the epitaxial film 127. The wafer composed of the bonded wafer 125, the epitaxial film 127, and the device structure 128 is called the bonded wafer 129. Similarly, an epitaxial film 130 is formed on the bonded wafer 126, and a device structure 131 is formed on the epitaxial film 130. The wafer composed of the bonded wafer 126, the epitaxial film 130, and the device structure 131 is called the bonded wafer 132.

[0163] The bonding wafers 125 and 126 include the bonding surfaces of the divided wafers 121 and 122 and the polycrystalline SiC wafers 123 and 124. The device-bearing wafers 133 and 134 preferably do not include such bonding surfaces. Therefore, the depth of the bonding surfaces of the divided wafers 121 and 122 and the polycrystalline SiC wafers 123 and 124 in the bonding wafers 125 and 126 is preferably 50 μm or more, more preferably 80 μm or more, and most preferably 100 μm or more. In other words, the thicknesses of the divided wafers 121 and 122 divided from the SiC wafer 120 are preferably 50 μm or more, more preferably 80 μm or more, and most preferably 100 μm or more. Thereby, the bonding surfaces are not included in the device-bearing wafers 133 and 134, and the influence on the devices caused by the bonding surfaces can be removed.

[0164] After that, the bonding wafer 129 is divided into the device-bearing wafer 133 having the device structure 128 and the polycrystalline SiC wafer 123. The device-bearing wafer 133 includes the divided wafers 121, the epitaxial film 127, and the device structure 128. Similarly, the bonding wafer 132 is divided into the device-bearing wafer 134 having the device structure 131 and the polycrystalline SiC wafer 124. The device-bearing wafer 134 includes the divided wafers 122, the epitaxial film 130, and the device structure 131.

[0165] According to the above method, by using the polycrystalline SiC wafers 123 and 124 as support substrates, the device structures 128 and 131 can be formed on the plurality of divided wafers 121 and 122 divided from the SiC wafer. In addition, the polycrystalline SiC wafers​​​​​​​​​​​​​​​For example, the semiconductor device manufacturing method according to Embodiment 3 includes: (a) a step of dividing a SiC wafer 120 in the thickness direction to obtain divided wafers 121 and 122 with a thickness of 50 μm or more; (b) a step of bonding the divided wafers 121 and 122 to polycrystalline SiC wafers 123 and 124, which serve as support substrates, to obtain bonded wafers 125 and 126; and (c) a step of forming device structures 128 and 131 on the bonded wafers 125 and 126. Thus, while suppressing wafer breakage, it is possible to reuse the wafer to manufacture semiconductor devices with high productivity.

[0170] In addition, for ​ For example, in Embodiment 3, the bonded wafer is a bonded wafer formed by bonding segmented wafers 121 and 122 (which do not contain device structures) from a SiC wafer 120 to polycrystalline SiC wafers 123 and 124, which serve as a support substrate. The bonding surfaces of the segmented wafers 121 and 122 and the polycrystalline SiC wafers 123 and 124 are located at a depth of 50 μm or more from the surface. Therefore, it is possible to reuse the wafer to manufacture semiconductor devices with high productivity while suppressing wafer breakage.

[0171] In the case where the diced wafer is used as a support substrate as shown in Embodiment 1 (e.g.) ​ The process illustrated involves manufacturing a wafer that serves as a support substrate from a conventional wafer dicing process. This can sometimes limit the thickness of the support substrate, or lead to waste when removing the support substrate or dicing the wafer to obtain a bonding wafer with the desired film thickness. In this embodiment, the support substrate is manufactured directly from the die. Therefore, there is no limitation on the substrate thickness, and a single-crystal wafer of the necessary thickness can be directly manufactured as the support substrate, thus reducing waste. This results in significant cost reduction. Furthermore, by using a low-quality crystal with numerous defects that is unsuitable for device manufacturing as the support substrate, overall material loss in the manufacturing process can be reduced.

[0172] Furthermore, compared to the case where a single-crystal wafer is used as a support substrate as shown in Embodiment 2, a polycrystalline substrate can be manufactured at a low cost, thus achieving a cost reduction effect.

[0173] Furthermore, the various embodiments can be freely combined or appropriately modified or omitted. The above description is merely illustrative in all embodiments. It should be understood that numerous modifications not illustrated are conceivable. For example, the processes of dividing, joining, and processing the wafer surface and back side associated with them shown in Embodiment 1, or the features of dividing wafers, joining wafers, and wafers with devices, can be combined or appropriately modified or omitted in the manner of using a support substrate shown in Embodiments 2 and 3.

[0174] (Explanation of reference numerals in the attached diagram)

[0175] 10, 13: SiC wafers; 11, 15, 25: Epitaxial films; 12, 16, 26: Device structures; 19, 22, 29: Wafers with devices; 20, 23, 30, 66, 106: Divided wafers; 67: Single-crystal SiC substrate; 107: Polycrystalline SiC substrate.

Claims

1. A method for manufacturing a semiconductor device, comprising: (a) A process of obtaining at least one first segmented wafer without device construction from each of the plurality of first wafers by dividing each of the plurality of first wafers in the thickness direction; (b) A process of joining multiple first segments obtained from different first wafers to obtain a first joined wafer as a joined wafer; and (c) The process of forming a device structure on the surface of the first bonded wafer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein, The process (a) is the following process: dividing each of the first wafers on which a device structure is formed on the surface into a first device wafer containing a device structure and at least one of the first divided wafers.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, further comprising: (d) The process of dividing the first bonding wafer with a device structure into a second device wafer with a device structure and at least one second split wafer without a device structure.

4. The method for manufacturing a semiconductor device according to claim 3 further comprises: (e) After the process (d), the second segmented wafer is used as the new first segmented wafer, and the process (b) to the process (d) is repeated at least once.

5. A method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein, At least one of the first wafers is a bonded wafer formed by bonding multiple wafers.

6. The method for manufacturing a semiconductor device according to claim 3, wherein, In the case where the wafer of the segmentation source of the device wafer is a bonded wafer formed by bonding multiple wafers, the device wafer does not include the bonding surface contained in the bonded wafer of the segmentation source.

7. A method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein, The material of the first wafer is SiC.

8. The method for manufacturing a semiconductor device according to claim 7, wherein, The material of the first wafer is single-crystal SiC.

9. A method for manufacturing a semiconductor device according to any one of claims 1 to 8, wherein, The thickness of the first segmented wafer is 50 μm or more.

10. A method for manufacturing a semiconductor device according to any one of claims 1 to 9, wherein, The device is constructed using a SiC power device architecture.

11. A method for bonding wafers, comprising bonding a plurality of segments of wafers not containing device structures, segments of different wafers, wherein, At a depth of more than 50 μm from the surface, there are multiple bonding surfaces of the segmented wafers.

12. The bonding wafer according to claim 11, wherein, The material of the wafer is SiC.

13. The bonding wafer according to claim 12, wherein, The material of the wafer is single-crystal SiC.

14. The bonded wafer according to any one of claims 11 to 13, wherein, The wafer has an N-type or P-type conductivity type or is semi-insulating.

15. The bonded wafer according to any one of claims 11 to 14, wherein, An amorphous layer exists at the bonding surface of the plurality of said segmented wafers.

16. A method for manufacturing a semiconductor device, comprising: (a) A process of obtaining a divided wafer by dividing the wafer in the thickness direction; (b) The process of bonding the diced wafer to a support substrate to obtain a bonded wafer; and (c) The process of forming a device structure on the bonded wafer.

17. The method for manufacturing a semiconductor device according to claim 16, wherein, The bonding surface between the segmented wafer and the supporting substrate in the bonding wafer is located at a depth of more than 50 μm from the surface of the bonding wafer.

18. The method for manufacturing a semiconductor device according to claim 16 or 17, wherein, The supporting substrate is a single-crystal SiC or a single-crystal GaN.

19. The method for manufacturing a semiconductor device according to claim 16 or 17, wherein, The supporting substrate is a polycrystalline substrate.

20. A method for bonding a wafer, wherein a slit wafer not containing the device structure, cleaved from a wafer, is bonded to a support substrate, wherein, At a depth of 50 μm or more from the surface, there is a bonding surface between the segmented wafer and the supporting substrate.

21. The bonding wafer according to claim 20, wherein, The wafer and the supporting substrate are made of single-crystal SiC or single-crystal GaN.

22. The bonding wafer according to claim 20, wherein, The material of the wafer is polycrystalline SiC.

23. The bonded wafer according to any one of claims 20 to 22, wherein, The wafer has an N-type or P-type conductivity type or is semi-insulating.

24. The bonded wafer according to any one of claims 20 to 23, wherein, An amorphous layer exists at the bonding surface between the segmented wafer and the supporting substrate.

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