Gate drive circuit

Abstract

In a gate drive circuit (101), a first switch (121) turns a driven element (1) into an ON state when a gate drive signal (GDS) is a first logic value. The second switch (122) turns the driven element (1) off when the gate drive signal (GDS) is a second logic value. The diode (108) is connected between the second switch (122) and the reference node (103). A first electrode of the capacitor (109) is connected to a connection node between the second switch (122) and the diode (108). A reference potential (VSS) is supplied to the second electrode of the capacitor (109) after the gate drive signal (GDS) is switched from the first logic value to the second logic value and after the charge of the gate terminal (4) of the driven element (1) is discharged, and a positive potential (VCC) is supplied to the second electrode of the capacitor (109) before the gate drive signal is switched from the second logic value to the first logic value.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a gate drive circuit, for example, for driving a power semiconductor device. BACKGROUND

[0002] Among power semiconductor devices, there are MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors), and the like. These power semiconductor devices are applied to semiconductor apparatuses such as inverters. In an inverter, a plurality of power semiconductor devices are connected in series and used. Most simply, by connecting two power semiconductor devices in series and making them turn on / off alternately, the potential at the connection point of these devices is moved up and down.

[0003] In order to turn on a power semiconductor device, a positive voltage is applied to the gate terminal of the power semiconductor device. In order to turn off a power semiconductor device, a zero voltage or a negative voltage is applied to the gate terminal of the power semiconductor device. A gate drive circuit is a device for applying these voltages to a power semiconductor device, that is, a driven element.

[0004] Each of the power semiconductor devices connected in series is called an arm. With respect to arms connected above and below, control is performed in such a manner that they become on states alternately, that is, in such a manner that they do not become on states at the same time, in such a manner that one becomes off when the other is on. When looking at an arbitrary arm, the other arm (hereinafter referred to as a counter arm) becomes on only when the arm (hereinafter referred to as a self arm) is off. The instant when a power semiconductor device is turned on is called turn-on, and the instant when a power semiconductor device is turned off is called turn-off.

[0005] If the arms above and below are turned on at the same time, the power supply voltage is short-circuited via both arms. In this case, a large current flows to both arms, and sometimes the power semiconductor devices are destroyed due to heat generation.

[0006] When the self arm is off and the counter arm is on, the voltage at the connection point of the arms above and below rapidly changes, and thus a voltage is rapidly applied to the power semiconductor device of the self arm. For example, if it is a MOSFET, a voltage is rapidly applied between the drain terminal and the source terminal. This is due to the operation of the counter arm, and in the self arm, it is also necessary to maintain off at this instant.

[0007] Generally, in a case where a voltage is rapidly applied to a power semiconductor device, a phenomenon of voltage rise of a gate terminal occurs. For example, in a case of a MOSFET, a current that charges a parasitic capacitor between a drain terminal and a gate terminal flows from the drain terminal to the gate terminal, and the current flows through a resistor (gate resistor) connected to the gate terminal. As a result, a potential difference occurs across the gate resistor, and the potential of the gate terminal rises.

[0008] If the ability of the gate drive device to maintain the potential of the gate terminal at a low voltage is low, the gate voltage excessively rises at this time to exceed a gate voltage (gate threshold voltage) required for turning on the power semiconductor device. As a result, both the power semiconductor devices of the main branch and the opposite branch are turned on, and sometimes, a power supply short circuit or even a power semiconductor device breakdown occurs.

[0009] The phenomenon of erroneously turning on the main branch at the time of turning on the opposite branch is called a false turn-on phenomenon. In order to prevent the false turn-on, a method of reducing the resistance value of the gate resistor, a method of increasing an apparent gate capacitance by providing an additional capacitor between the gate terminal and the source terminal, or a method of applying a negative voltage to the gate terminal can be used. However, in the case of reducing the resistance value of the gate resistor, the switching speed becomes fast, and there is a possibility that electromagnetic noise increases. In the case of increasing the gate capacitance, the burden on the gate drive circuit and heat generation become large.

[0010] Therefore, generally, a method of making the gate voltage at the time of turning off negative, that is, applying a negative bias is used. In order to apply the negative bias, generally, a negative power supply is required. However, another power supply needs to be provided independently of a positive power supply for turning on the gate, so the method of using the negative power supply becomes a cause of an increase in circuit size and an increase in cost. In order to avoid these problems, a method of generating a negative bias using only a positive power supply is known.

[0011] For example, in Japanese Patent Application Publication No. 2004-159424 (Patent Literature 1) of Japanese Patent Application No. 2003-359593, Figure 2 The disclosed drive circuit includes a capacitor for generating a negative bias. The capacitor is pre-charged when a MOSFET as a driven element is turned on, and is connected in reverse polarity between the gate terminal and the source terminal of the driven element when the driven element is turned off.

[0012] In Japanese Patent Application Publication No. 2013-201883 (Patent Literature 2) of Japanese Patent Application No. 2012-257593, a negative bias generation circuit similar to the above-described Patent Literature 1 is also shown. In particular, in the drive circuit of FIG. 20 of the document, the above-described capacitor for generating a negative bias is connected only for a certain period between the gate terminal and the source terminal of the MOSFET from the time of turning off the MOSFET.

[0013] Prior Art Documents

[0014] Patent Documents

[0015] Patent Document 1: Japanese Patent Application Publication No. 2004-159424

[0016] Patent Document 2: Japanese Patent Application Publication No. 2013-201883 SUMMARY

[0017] In the above-described conventional technology, the connection of the capacitor is switched at the time of turning off, so the negative electric charge accumulated in one of the electrodes of the capacitor and the positive electric charge accumulated in the gate terminal of the driven element cancel each other out. Therefore, there is a problem that a negative bias cannot be sufficiently applied to the gate terminal of the driven element. This problem becomes particularly significant in the case where the gate capacitance of the driven element is large. If the capacitance of the capacitor used for the generation of the negative bias is further increased, although the influence due to the cancellation of the electric charges can be suppressed, the circuit size is increased and the cost is increased.

[0018] The present disclosure was completed in order to solve the above-described problem, and has an object to provide a gate drive circuit capable of applying a necessary negative bias to a gate with a minimum capacitance of a capacitor.

[0019] In one embodiment, a gate drive circuit that drives a gate of a driven element in accordance with a gate drive signal is provided. The gate drive circuit includes a first switch, a second switch, a diode, a capacitor, a potential switching circuit, and a signal generation circuit. The first switch is connected between a power supply node to which a positive potential is supplied and the gate terminal of the driven element, and is turned on when the gate drive signal is a first logic value, thereby causing the driven element to become in an on state. The second switch is connected between a reference node to which a reference potential is supplied and the gate terminal of the driven element, and is turned on when the gate drive signal is a second logic value, thereby causing the driven element to become in an off state. The diode is connected between the second switch and the reference node in such a manner that the reference node becomes a cathode side. A first electrode of the capacitor is connected to a connection node of the second switch and the diode. The potential switching circuit supplies the reference potential to a second electrode of the capacitor when a control signal is active, and supplies the positive potential to the second electrode of the capacitor when the control signal is inactive. The signal generation circuit generates the above-described control signal in accordance with the gate drive signal. The signal generation circuit makes the control signal active after the charge of the gate terminal of the driven element is discharged after the gate drive signal is switched from the first logic value to the second logic value, and makes the control signal inactive before the gate drive signal is switched from the second logic value to the first logic value.

[0020] The gate drive circuit according to the above-described embodiment, after the charge of the gate terminal of the driven element is discharged after the gate drive signal is switched from the first logic value to the second logic value, the control signal for making the negative bias effective is made effective, and the control signal is made ineffective before the gate drive signal is switched from the second logic value to the first logic value. Thus, it is possible to provide a gate drive circuit capable of applying a necessary negative bias to a gate with a capacitor of a minimum capacity. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a circuit diagram showing a structure example of the gate drive circuit according to Embodiment 1.

[0022] Figure 2 is a timing chart showing an operation of the gate drive circuit according to Figure 1

[0023] Figure 3 is a circuit diagram conceptually showing a charging state of a capacitor and a charging state of a gate capacitor after the second electrode of the capacitor is just connected to a reference potential.

[0024] Figure 4 is a graph showing a temporal change of an actual gate voltage after the off of the driven element.

[0025] Figure 5 is a timing chart showing an operation of the gate drive circuit according to Figure 1

[0026] Figure 6 is a timing chart showing an operation of a modification example of the gate drive circuit according to Figure 1

[0027] Figure 7 is a circuit diagram showing a structure example of the gate drive circuit according to Embodiment 2.

[0028] Figure 8 is a timing chart showing an operation of the gate drive circuit according to Figure 7

[0029] Figure 9 is a circuit diagram showing a structure example of the gate drive circuit according to Embodiment 3.

[0030] Figure 10 is a circuit diagram showing a structure example of the gate drive circuit according to Embodiment 4. DETAILED DESCRIPTION

[0031] Hereinafter, each embodiment will be described in detail with reference to the drawings. Furthermore, the same reference numerals are added to the same or equivalent portions, and repeated description thereof will not be made. ​​​​

[0032] Embodiment 1

[0033] [Structure of Gate Drive Circuit]

[0034] Figure 1 is a circuit diagram showing a structure example of the gate drive circuit according to Embodiment 1. In Figure 1 , the driven element 1 is a MOSFET.

[0035] The driven element 1 has a drain terminal 2 as a first main terminal, a source terminal 3 as a second main terminal, and a gate terminal 4 as a control terminal. The on and off of the main current flowing between the first and second main terminals is controlled by a gate voltage applied to the gate terminal 4. In Figure 1 , the driven element 1 has a source reference terminal 5 between the source electrode and the source terminal 3 in order to obtain a source potential.

[0036] Between the gate and the source of the driven element 1, there is a parasitic gate capacitance 6. The gate capacitance does not exist as a part, but is virtually shown by a broken line as if connecting the part in Figure 1

[0037] The gate drive circuit 101 is connected to the gate terminal 4 and the source terminal 3 of the driven element 1. In Figure 1 , instead of the source terminal 3, the source reference terminal 5 provided between the source electrode and the source terminal 3 of the driven element 1 is connected. The gate drive circuit 101 has, inside, a power source node 102 to which a positive potential V CC is supplied by a positive power source and a reference node 103 to which a reference potential V SS is supplied. The reference potential V SS is equal to the potential of the source reference terminal 5.

[0038] The gate drive circuit 101 is driven by a gate drive signal GDS input to a signal input terminal 104. The gate drive circuit 101 has a mechanism that switches whether the gate terminal 4 of the driven element 1 is connected to the positive potential side or the reference potential side in accordance with the input gate drive signal GDS.

[0039] Specifically, in Figure 1 , in order to switch the gate terminal 4 to the positive potential side, the gate drive circuit 101 has a gate resistor 106 for turning on and a switch 121 (first switch) connected in series between the gate terminal 4 and the power source node 102. In addition, in order to connect the gate terminal 4 to the reference potential side, the gate drive circuit 101 has a gate resistor 107 for turning off and a switch 122 (second switch) connected in series between the gate terminal 4 and the reference node 103. In Figure 1 ​In this example, switch 121 is a P-channel MOSFET, and switch 122 is an N-channel MOSFET. Gate resistor 106 is connected to the gate terminal 4 side compared to switch 121, and gate resistor 107 is connected to the gate terminal 4 side compared to switch 122.

[0040] Furthermore, the gate drive circuit 101 includes a non-inverting buffer 105 for driving the gate terminals of switch 121 and switch 122 according to the gate drive signal GDS. The gate drive signal GDS input to the signal input terminal 104 is input to the non-inverting buffer 105.

[0041] Furthermore, the gate drive circuit 101 includes a diode 108, a capacitor 109, a potential switching circuit 201, a non-inverting buffer 110, and a signal generation circuit 301 as a mechanism for inputting a negative potential to the gate terminal 4 of the driven element 1.

[0042] Diode 108 is connected between switch 122 and reference node 103 such that the anode of diode 108 is on the switch 122 side and the cathode of diode 108 is on the reference node 103 side.

[0043] The first electrode 109A of capacitor 109 is connected to the junction of switch 122 and diode 108. The second electrode 109B of capacitor 109 is connected to potential switching circuit 201.

[0044] The potential switching circuit 201 includes a pull-up resistor 202 and a switch 203 (the third switch). In this example, switch 203 is an N-channel MOSFET. The first terminal of pull-up resistor 202 is connected to power node 102, and the second terminal of pull-up resistor 202 is connected to both the second electrode 109B of capacitor 109 and the drain terminal of switch 203. The source terminal of switch 203 is connected to reference node 103. The gate terminal of switch 203 is driven by a non-inverting buffer 110.

[0045] The signal generation circuit 301 accepts the gate drive signal input to the signal input terminal 104 as input and outputs a control signal to drive the non-inverting buffer 110. By outputting a high-level control signal from the signal generation circuit 301 to the non-inverting buffer 110, the switch 203 is turned on, thereby activating the negative bias of the gate terminal 4 of the driven element 1. By outputting a low-level control signal from the signal generation circuit 301 to the non-inverting buffer 110, the switch 203 is turned off, thereby deactivating the negative bias of the gate terminal 4 of the driven element 1. In the above cases, the high-level control signal is referred to as the active control signal, and the low-level control signal is referred to as the inactive control signal.

[0046] The signal generation circuit 301 includes a first delay circuit 320, a logic operation circuit 306, and a second delay circuit 321.

[0047] A negative logic gate drive signal GDS is input to the first delay circuit 320. The first delay circuit 320 generates a first delay signal by delaying the turn-on edge (i.e., the falling edge) and delaying the turn-off edge (i.e., the rising edge) of the input negative logic gate drive signal GDS. Furthermore, the first delay circuit 320 outputs a signal that inverts the logic value of the first delay signal.

[0048] More specifically, such as Figure 1 As shown, the first delay circuit 320 includes a low-pass filter (also called an RC filter) consisting of a resistor 303 and a capacitor 304, a diode 302, and a Schmitt trigger inverter 305. The resistor 303 and capacitor 304 are connected in series between the signal input terminal 104 and the reference node 103 in this order. The diode 302 is connected in parallel with the resistor 303. The anode terminal of the diode 302 is connected to the connection node B of the resistor 303 and capacitor 304. Thus, the RC filter functions as a unidirectional RC filter that only delays the rising side of the gate drive signal GDS. The signal after passing through the RC filter is input to the Schmitt trigger inverter 305. The Schmitt trigger inverter 305 shapes the input signal and inverts its logic value.

[0049] The logic operation circuit 306 performs a logical AND operation on the inverted signal of the first delayed signal output from the first delay circuit 320 and the gate drive signal GDS. Figure 1 In the example, a NAND (Not AND) circuit is used as the logic operation circuit 306, so the logic operation circuit 306 inverts the result of the logical AND operation and outputs it. Furthermore, the logic operation circuit 306 can also calculate the logical OR of the first delayed signal and the inverted signal of the gate drive signal GDS, with the same logical operation result.

[0050] The output signal of the logic operation circuit 306 is input to the second delay circuit 321. The second delay circuit 321 delays the output signal of the logic operation circuit 306 (both the rising and falling sides). The delayed signal output from the second delay circuit 321 is input to the non-inverting buffer 110. This generates a control signal for controlling the potential switching circuit 201.

[0051] More specifically, such as Figure 1As shown, the second delay circuit 321 includes a low-pass filter (also called an RC filter) composed of a resistor 307 and a capacitor 308, and a Schmitt trigger inverter 309. The resistor 307 and capacitor 308 are connected in series between the output node D of the logic operation circuit 306 and the reference node 103. The signal after passing through the RC filter is input to the Schmitt trigger inverter 309. The Schmitt trigger inverter 309 shapes the input signal and inverts its logic value.

[0052] [Operation of the gate drive circuit]

[0053] Next, an explanation Figure 1 The operation of the gate drive circuit 101, and especially the operation of the signal generation circuit 301.

[0054] Figure 2 It is shown Figure 1 The timing diagram shows the operation of the gate drive circuit 101. Figure 2 In, it is shown Figure 1 The signal waveforms of nodes A~F and the gate voltage V of driven element 1 G The waveform. The following sections will explain each waveform in turn.

[0055] The signal at node A is the gate drive signal GDS, which is input to the gate terminal of switch 121 (P-channel MOSFET) and the gate terminal of switch 122 (N-channel MOSFET) via non-inverting buffer 105. Switches 121 and 122 constitute a complementary MOS (CMOS: Complementary Metal-Oxide-Semiconductor).

[0056] When the gate drive signal GDS is high, switch 122 is turned on, connecting the gate terminal 4 of the driven element 1 to the reference node 103. Thus, the driven element 1 is in the off state. Conversely, when the gate drive signal GDS is low, switch 121 is turned on, connecting the gate terminal 4 of the driven element 1 to the power supply node 102. Thus, the driven element 1 is in the on state. Therefore, the gate drive signal GDS is negative logic.

[0057] The moment t1 when the gate drive signal GDS switches from high to low (i.e., the falling edge of the gate drive signal GDS) corresponds to the turn-on edge. The moment t3 when the gate drive signal GDS switches from low to high (i.e., the rising edge of the gate drive signal GDS) corresponds to the turn-off edge.

[0058] The signal at node B represents the signal output from the unidirectional RC filter by inputting the signal at node A (i.e., the gate drive signal GDS) into the unidirectional RC filter of the first delay circuit 320.

[0059] A low-pass filter, typically composed of resistors and capacitors, cuts off the high-frequency components of the input signal while allowing the low-frequency components to pass. As a result, the signal passing through the low-pass filter exhibits a blunted edge shape compared to the input signal. However, in... Figure 1 In the low-pass filter of the first delay circuit 320, diode 302 and resistor 303 are connected in parallel. The cathode of diode 302 is connected to the input side of the low-pass filter, and the anode of diode 302 is connected to the output side of the low-pass filter. Therefore, when the input signal rises, the diode is cut off and the low-pass filter becomes active. Conversely, when the input signal falls, the diode becomes on and the voltage of capacitor 304 drops rapidly. Thus, the RC filter of the first delay circuit 320 functions as a unidirectional filter that is active only on the rising edge of the input signal.

[0060] Specifically, at time t1, which is the falling edge (i.e., the turn-on edge) of the gate drive signal GDS, the output signal of the unidirectional RC filter (i.e., the signal at node B) drops rapidly. On the other hand, at time t3, which is the rising edge (i.e., the turn-off edge) of the gate drive signal GDS, the output signal of the unidirectional RC filter (i.e., the signal at node B) rises slowly.

[0061] The signal at node C represents the signal output from the Schmitt trigger inverter 305 by inputting the signal at node B (i.e., the output signal of the unidirectional RC filter) into the Schmitt trigger inverter 305.

[0062] Generally, a Schmitt trigger element is a component that adds hysteresis to the input threshold voltage. However, in the first delay circuit 320, a Schmitt trigger inverter 305 is used, so the output is a signal that inverts the logic value of the input signal.

[0063] Specifically, in Figure 2 When the input signal (i.e., the signal at node B) of the Schmitt-triggered inverter 305 decreases at time t1, the Schmitt-triggered inverter 305 outputs a signal that inverts the input signal after the input signal is quite below the intermediate potential. At time t1, the signal at node B decreases rapidly, so the output signal of the Schmitt-triggered inverter 305 rises from time t1 almost without delay at time t2.

[0064] On the other hand, when the input signal (i.e., the signal at node B) of the Schmitt trigger inverter 305 rises at time t3, the Schmitt trigger inverter 305 outputs a signal that inverts the input signal after the input signal is significantly higher than the intermediate potential. At time t3, the signal at node B rises slowly, so the output signal of the Schmitt trigger inverter 305 drops at time t5, which is significantly delayed from time t3.

[0065] When a waveform with only the rising edge of the signal blunted is input to the Schmitt trigger inverter 305 as described above, the Schmitt trigger inverter 305 outputs an inverted signal that significantly delays only the rising edge of the input signal.

[0066] The signal at node D represents the output signal of the NAND circuit in the logic operation circuit 306. For example... Figure 1 As shown, the NAND circuit 306 outputs a signal that performs a logical AND inversion between the signal at node A (i.e., the gate drive signal GDS) and the signal at node C (i.e., the output signal of the Schmitt trigger inverter 305).

[0067] exist Figure 2 In this case, the logical AND of the signals of node A and node C only occurs for a certain period T from the turn-off edge (e.g., ...). Figure 2 The signal at node D (i.e., the output signal of NAND circuit 306) becomes true only during a certain period T from the turn-off edge, and false during other periods.

[0068] The signal at node E represents the signal output from an RC filter formed by inputting the signal at node D into the RC filter consisting of resistor 307 and capacitor 308. Since no diode is connected to resistor 307 of this RC filter, the signal waveform at node D becomes a waveform with both the rising and falling sides blunted.

[0069] The signal at node F represents the signal output from the Schmitt trigger inverter 309 by inputting the signal at node E (i.e., the output signal of the RC filter) into the Schmitt trigger inverter 309. For example... Figure 2 As shown, the signal of node F becomes a signal whose logic value is inverted after delaying both the rising and falling edges of the signal of node D. Specifically, the signal of node F changes from low to high at time t4 after a certain time elapsed from the turn-off edge at time t3, and then returns from high to low at time t6.

[0070] The signal generation circuit 301 uses the signal from node F as a control signal to enable the negative bias, and inputs it to the gate terminal of switch 203 in the potential switching circuit 201 via the non-inverting buffer 110. Therefore, during the period when the gate drive signal GDS is high (time t3 to time t7) and the period when the signal from node F is high (time t4 to t6), switch 203 is turned on. During other periods, switch 203 is turned off.

[0071] As described above, the first electrode 109A of capacitor 109 is connected to the junction of switch 122 for cutoff drive and diode 108. The second electrode 109B of capacitor 109 is connected to power node 102 via pull-up resistor 202 and to reference node 103 via switch 203.

[0072] Therefore, during the period when switch 203 is not conducting, current flows in the order of power node 102, pull-up resistor 202, capacitor 109, diode 108, and reference node 103, thereby charging capacitor 109 such that its second electrode 109B is positive and its first electrode 109A is negative. On the other hand, during the period when switch 203 is conducting, the second electrode 109B of capacitor 109 is connected to reference node 103 via switch 203, so the source terminal of switch 122 connected to the first electrode 109A of capacitor 109 is at a relative potential V to the reference node. SS It is biased to a negative potential.

[0073] Through the operation of the aforementioned signal generation circuit 301 and potential switching circuit 201, etc., the following is obtained: Figure 2 The bottom part shows the gate voltage waveform.

[0074] Specifically, in Figure 2 During the period from the turn-on edge of time t1 to the turn-off edge of time t3, the switch 121 of the gate drive circuit 101 is turned on, thereby providing a positive potential to the gate terminal 4 of the driven element 1.

[0075] During the period from the turn-off edge at time t3 to time t4, switch 121 of the gate drive circuit 101 is de-conducted, and switch 122 is turned on, thereby discharging the charge accumulated at the gate terminal 4 of the driven element 1 through the gate resistor, switch 122, and forward-biased diode 108. As a result, the gate terminal 4 of the driven element 1 changes from a positive potential to a reference potential. During this period, the signal at node F is low, so switch 203 of the potential switching circuit 201 is de-conducted. Therefore, the first electrode 109A of capacitor 109 is maintained at the reference potential V via diode 108. SS Same potential.

[0076] During the subsequent period from time t4 to time t6, the signal at node F becomes high, and switch 203 of the potential switching circuit 201 becomes active. Consequently, the second electrode 109B of capacitor 109 is connected to the reference node 103 via switch 203. As a result, the first electrode 109A of capacitor 109 becomes negatively biased, and the gate terminal 4 of the driven element 1, connected to the first electrode 109A of capacitor 109 via the active switch 122 and the gate resistor, also becomes negatively biased. That is, the potential of gate terminal 4 changes from the reference potential to a negative potential. Furthermore, diode 108 is non-conductive due to the reverse application of voltage. During the period of negative bias application from time t4 to time t6, the driving element of the opposing branch is turned on, thereby preventing false arcing in this branch.

[0077] During the turn-on edge from time t6 to time t7, the signal at node F becomes low, and switch 203 of the potential switching circuit 201 becomes non-conducting. Consequently, the second electrode 109B of capacitor 109 is disconnected from reference node 103 and reconnected to power node 102. Thus, the first electrode 109A of capacitor 109 is connected to reference node 103 via forward diode 108. The gate terminal 4 of the driven element 1, connected to the first electrode 109A of capacitor 109 via the on-state switch 122 and the gate resistor, also becomes the reference potential. Thereafter, the aforementioned voltage changes are repeated.

[0078] [Effects of Implementation Method 1]

[0079] Based on the structure and operation of the gate drive circuit 101 described above, even using a capacitor 109 with minimal capacitance, accidental arcing of the driven element 1 can be prevented. The reasons for this will be explained in detail below.

[0080] Figure 3 This is a conceptual circuit diagram showing the charging state of capacitor 109 and gate capacitor 6 immediately after the second electrode 109B of capacitor 109 is connected to the reference potential.

[0081] Figure 3 (A) Shows the charging states of capacitor 109 and gate capacitor 6 in the comparative example. In the comparative example, capacitor 109 for generating negative bias is connected to gate capacitor 6 of driven element 1 immediately after driven element 1 is turned off. That is, when positive charge is accumulated on gate terminal 4 from driven element 1 being turned on, capacitor 109 for generating negative bias is connected to gate capacitor 6 at the same time gate terminal 4 is disconnected from power node 102.

[0082] In this case, the negative charge accumulated at the first electrode 109A of the capacitor 109 used for negative bias generation and the positive charge accumulated at the gate terminal 4 cancel each other out. As a result, the potential at the gate terminal 4 does not decrease sufficiently. That is, the effect of negative bias is reduced.

[0083] For example, let's say the gate capacitance C. GS The capacitance C1 of capacitor 109 is equal to that of gate capacitor 6. Assume that before connecting gate capacitor 6 and capacitor 109, both gate capacitor 6 and capacitor 109 are at a positive potential V. CC Charging. In this case, since the gate capacitor 6 and the capacitor 109 are connected, the charges completely cancel each other out. As a result, the gate potential after connecting the negative bias generation capacitor 109 becomes zero, that is, it is equal to the reference potential V. SS The capacitance should be the same, not negative. In order to apply a sufficient negative bias to the gate terminal 4, the electrostatic capacitance C1 of the capacitor 109 needs to be increased significantly, which leads to problems such as increased circuit size and increased cost.

[0084] Figure 3 (B) Shows the charging status of capacitor 109 and gate capacitor 6 in this embodiment. In this embodiment, the disadvantages of the comparative example described above can be overcome.

[0085] Specifically, as explained previously, when the driven element 1 is turned off, the gate terminal 4 is temporarily connected to the reference node 103. As a result, the charge stored in the gate capacitor 6 is discharged, so the voltage at the gate terminal 4 temporarily becomes zero. Afterwards, the capacitor 109 for generating the negative bias is connected between the gate terminal 4 and the reference node 103 with the opposite polarity. Figure 3 (B) illustrates this situation.

[0086] like Figure 3 As shown in (B), when the charge connected to the gate capacitor 6 is zero, the negative bias generation capacitor 109 is connected between the gate terminal 4 and the reference node 103. Therefore, a portion of the negative charge accumulated at the first electrode 109A of the capacitor 109 is transferred to the gate terminal 4, and the remaining negative charge remains at the first electrode 109A of the capacitor 109. Thus, with... Figure 3 Unlike the comparative example in (A), the negative charge on the first electrode 109A of capacitor 109 does not cancel out the positive charge on the gate terminal 4. As a result, there is no need to increase the electrostatic capacitance C1 of capacitor 109 used for generating negative bias.

[0087] Thus, in the gate drive circuit 101 of this embodiment, the electrostatic capacitance of the capacitor 109 used for generating the negative bias can be reduced compared to the conventional method. Next, the extent to which the electrostatic capacitance C1 of the capacitor 109 can be reduced will be explained.

[0088] In the following description, the gate capacitance of the driven element 1 is set to C. GS Set the electrostatic capacitance of the capacitor used for generating the negative bias to C1, and set the gate power supply voltage to V. CC The turn-on threshold of the driven element 1 is set to V. TH Without the capacitor 109 for generating negative bias, i.e., without applying negative bias to the gate terminal 4, the peak value of the surge voltage generated at the gate terminal of this branch when the opposing branch is turned on is set to V. SURGE .

[0089] The peak value V of the surge voltage generated at the gate terminal of this branch when the opposing branch is turned on. SURGE The turn-on threshold V of the driven element 1 in this branch exceeds TH At this time, a false arc may occur in this branch. As a result, there is a possibility that the driven components in this branch may be damaged. Therefore, in order to reduce the peak value of the surge voltage V... SURGE Become the activation threshold V TH The following method can be used to apply a negative bias to gate terminal 4.

[0090] In this embodiment, the gate capacitance C GS The capacitor 109 used for generating negative bias after temporary discharge and the gate capacitor C GS Connection. As a result, in capacitor 109 and gate capacitor C... GS In this process, the charge Q1 accumulated in the capacitor 109 used for negative bias generation is distributed proportionally.

[0091] First, when the electrostatic capacitance of capacitor 109 is set as C1, the charge Q1 mentioned above is expressed by the following formula.

[0092]

[0093] Connect capacitor 109 to gate capacitor C GS The charges then proportionally distributed between the two become capacitor C1 and capacitor C. GS The capacitance ratio. Therefore, the residual charge Q1 in capacitor 109 with electrostatic capacitance C1. R Expressed as follows.

[0094]

[0095]

[0096] Similarly, the transfer from capacitor 109 to gate capacitor C GS The charge Q G R Expressed as follows.

[0097]

[0098] Therefore, when capacitor 109 is connected to gate capacitor C GS Then, the absolute value of the potential difference across capacitor 109, |V C1 R | Expressed as follows.

[0099]

[0100] Similarly, when capacitor 109 is connected to gate capacitor C GS After that, the gate capacitance C GS The absolute value of the potential difference between the two ends |V GS R | Expressed as follows.

[0101]

[0102] Of course, the absolute value of the voltage across capacitor 109 is |V C1 R |and gate capacitance C GS The absolute value of the voltage |V GS R They are equal. This voltage acts as a negative bias.

[0103] To prevent accidental arcing of the driven element 1, a negative bias is used to reduce the peak value of the surge voltage to become the gate threshold voltage V. TH The following is sufficient. That is, the absolute value of the voltage required as the minimum necessary for negative bias is equal to the surge peak V of the gate voltage of this branch when the opposing branches are turned on without applying negative bias. SURGE With the gate threshold voltage V of the driven element TH The difference. That is, the absolute value of the potential difference across capacitor 109, |V. C1 R The difference must be greater than or equal to the given value, therefore the following formula is true.

[0104]

[0105] When transforming the above equation (6), the following equation is finally obtained.

[0106]

[0107] Therefore, the right side of equation (7) above is the lower limit of the capacitance C1 of capacitor 109. The capacitance C1 should not be lower than this lower limit.

[0108] The lower limit value of this capacitor C1 is unattainable in conventional technology. As described in this embodiment, the gate capacitor C is only reduced after the driven element 1 is turned off. GSAfter a temporary discharge, the capacitor 109 used for generating the negative bias is connected to the gate capacitor C. GS Only then can it be achieved.

[0109] Figure 4 This is a graph showing the actual time-varying gate voltage after the driven element is turned off. Figure 4 The thin solid line represents the time variation of the gate voltage when no negative bias is used, that is, when there is no capacitor 109 for generating negative bias.

[0110] Specifically, after this branch is turned off at time t10, the opposing branch is turned on at time t12 after a dead time. When this opposing branch is turned on, a boost occurs in the gate voltage of this branch, and the voltage rises to the surge peak V. SURGE .exist Figure 4 In the case of a waveform with a thin solid line, the surge peak V SURGE Exceeding the gate threshold voltage V TH Therefore, there is a possibility that the component may be damaged due to mis-pointing of the arc.

[0111] Therefore, during the period from time t11 to time t13, including the time t12 when the opposite branch is turned on, the capacitor 109 for generating the negative bias and the gate capacitor C GS The connection is made so that a negative bias is applied to the gate terminal 4. In this case, it is important not to unnecessarily increase the capacitance C1 of capacitor 109.

[0112] For example, if the capacitance C1 of capacitor 109 is increased to an extreme degree, then as Figure 4 The thick solid line waveform can represent the gate voltage V. G The power supply voltage V is reduced to the gate drive circuit 101. CC Reverse voltage -V CC The area near the gate threshold voltage. However, such a large negative bias is unnecessary. The reason is that even if the peak surge voltage is significantly lower than the gate threshold voltage V, TH The effect of preventing accidental arcing will not change. Furthermore, unnecessarily increasing the capacitance C1 of capacitor 109 leads to problems such as increased circuit size and cost. Moreover, it is known that when the driven element is a SiC-MOSFET (silicon carbide MOSFET), excessively increasing the negative bias voltage causes unnecessary stress on the gate oxide film of the driven element, resulting in a decrease in the gate threshold voltage. Therefore, the magnitude of the negative bias should be a necessary minimum. In this embodiment, the minimum value of the negative bias voltage has been defined as described above, and the circuit structure required to achieve it has been defined.

[0113] Furthermore, there is no operational limit to the upper limit of capacitor C1, but unnecessarily increasing it as mentioned above leads to increased circuit size and cost, and also has a detrimental effect on the gate oxide film. As a possibility that capacitor C1 must be increased to some extent, consider the gate threshold voltage V. TH The decrease in gate threshold voltage V. TH There is a possibility that the value may decrease from its initial value due to various factors, in which case the capacitor C1 needs to be increased accordingly. However, even considering the worst-case scenario, the gate threshold voltage V... TH It is also a positive value, greater than 0V.

[0114] Let V be the value in equation (6). TH When =0, we get the following formula.

[0115]

[0116] When the equation (8) is transformed, the following equation is obtained.

[0117]

[0118] The right side of equation (9) is in the worst case (i.e., V). TH In the case where C1 = 0, the capacitance C1 of the necessary capacitor 109 does not need to be increased further. Therefore, the right side of equation (9) is the upper limit of capacitance C1. That is, the equation that specifies the upper limit of capacitance C1 is the following equation.

[0119]

[0120] When combining equation (10) and equation (7), we get the following equation.

[0121]

[0122] Equation (11) specifies the upper and lower limits of the capacitance C1 of capacitor 109.

[0123] Figure 4 The dashed waveform represents the gate voltage V when the capacitance of capacitor 109 used for negative bias generation is optimized. G Changes over time.

[0124] Negative bias is suppressed to a minimum, and the surge peak of the gate voltage of this branch when the opposing branch is turned on does not exceed V. TH .

[0125] Furthermore, in this embodiment, a negative bias is applied after the gate voltage is temporarily reduced to 0 when the branch is turned off, so the duration of the negative bias application is also minimized. As described above, when a negative bias is applied to the gate in a SiC-MOSFET, pressure is applied to the gate oxide film, so not only the magnitude of the negative bias but also the duration of the negative bias application is preferably as short as possible. According to this embodiment, the duration of the negative bias application to the gate can be limited to a short period including the instant of the opposite branch being turned on.

[0126] The time width for applying the negative bias can be adjusted by the time used to generate Figure 1 The time constant of the low-pass filter for the first signal, i.e., the values ​​of resistor 303 and / or capacitor 304, is controlled. Furthermore, the timing of the instant the negative bias begins to be applied can be controlled by adjusting the time constant of the low-pass filter that delays the first signal, i.e., the values ​​of resistor 307 and / or capacitor 308. By controlling these, the application time of the negative bias can be suppressed to the necessary minimum. This is an effect not achieved in conventional techniques.

[0127] [Reasons for needing a unidirectional RC filter]

[0128] The following explains the reason for using a unidirectional RC filter in the first delay circuit 320 of the signal generation circuit 301.

[0129] In this embodiment, the first delay circuit 320 is configured as a unidirectional RC filter that delays only the turn-off edge of the gate drive signal GDS without delaying the turn-on edge. Therefore, even when the turn-on pulse width of the gate drive signal GDS is very short, a negative bias can be reliably applied to the gate terminal 4 of the driven element 1. Specific examples will be described below.

[0130] Figure 5 This illustrates the case where the turn-on pulse width of the gate drive signal GDS is very short. Figure 1 Timing diagram of the operation of the gate drive circuit 101. Figure 5 The timing diagram and Figure 2 The corresponding timing diagram shows Figure 1 The signal waveforms of nodes A~F and the gate voltage V of driven element 1 G The waveform. Figure 5 Time t1 to t7 and Figure 2 The times t1 to t7 correspond to respectively.

[0131] like Figure 5As shown, the turn-on pulse width of the gate drive signal GDS (i.e., the signal at node A) (i.e., from time t1 to time t3) is very short. Even under such circumstances, it is possible to apply a negative bias to the gate terminal 4 during the period from time t4 to time t6 after the turn-off edge at time t3.

[0132] Figure 6 It is shown Figure 1 A timing diagram showing the operation of a modified example of the gate drive circuit 101. In the modified example of the gate drive circuit, it is configured as follows: Figure 1 The first delay circuit 320 of the signal generation circuit 301 does not include diode 302. Therefore, the modified first delay circuit is a bidirectional delay circuit that delays both the turn-on edge and the turn-off edge.

[0133] Figure 6 The timing diagram illustrates the situation described above under the change conditions. Figure 1 The signal waveforms of nodes A~F and the gate voltage V of driven element 1 G The waveform. In Figure 6 In the diagram, the waveform of the gate drive signal GDS (the signal at node A) is similar to... Figure 5 The situation is the same.

[0134] The waveform of the signal at node B (i.e., the output signal of the modified first delay circuit) begins to decrease slowly at the turn-on edge of the gate drive signal GDS at time t1. However, the turn-on pulse width of the gate drive signal GDS is very short, so the signal at node B immediately and slowly recovers towards its original high level at the turn-off edge at time t3.

[0135] As a result, the signal at node B does not exceed the operating threshold of the Schmitt trigger inverter 305 in the first delay circuit 320, so the Schmitt trigger inverter 305 does not operate. Consequently, the deformed signal generation circuit cannot detect the turn-off edge of the gate drive signal GDS. Therefore, the signal at node C remains unchanged at a low (L) level, and correspondingly, the signals at nodes D and E remain unchanged at a high (H) level. As a result, the signal at node F remains unchanged at a low (L) level. Ultimately, no negative bias is applied to gate terminal 4. This is the cause of the false trigger arc.

[0136] To avoid such undesirable phenomena, a unidirectional filter is needed in the first delay circuit 320 of the signal generation circuit 301 to delay only the turn-off edge of the gate drive signal GDS, without delaying the turn-on edge.

[0137] Implementation method 2.

[0138] [Structure of the gate drive circuit]

[0139] Figure 7This is a circuit diagram showing a structural example of the gate drive circuit 101A according to Embodiment 2. Figure 7 The gate drive circuit 101A is Figure 1 A modified example of the gate drive circuit 101.

[0140] Specifically, Figure 7 The gate drive circuit 101A replaces the switch 121, which is composed of a P-channel MOSFET, with an NPN transistor 131 (the first switch), and replaces the switch 122, which is composed of an N-channel MOSFET, with a PNP transistor 132 (the second switch). In this respect, it is similar to... Figure 1 The gate drive circuit 101 is different.

[0141] The base terminals of NPN transistor 131 and PNP transistor 132 are connected to signal input terminal 104. The connection point 133 between NPN transistor 131 and PNP transistor 132 is connected to the gate terminal 4 of driven element 1 via a gate resistor 106 for on-state and a forward diode, and is also connected to the gate terminal 4 of driven element 1 via a gate resistor 107 for off-state and a reverse diode.

[0142] The aforementioned NPN transistor 131 and PNP transistor 132 constitute an emitter follower circuit, where the logic value of the input signal is the same as the logic value of the output signal. On the other hand, in the case of… Figure 1 In the CMOS circuit composed of switches 121 and 122, the logic values ​​of the input signal and the output signal are inverted. Therefore, the input signal... Figure 1 The gate drive circuit 101 inputs the gate drive signal GDS with negative logic, and in contrast, to... Figure 7 The gate drive circuit 101 receives the gate drive signal GDS with positive logic input.

[0143] By making the gate drive signal GDS a positive logic value, even if the circuit that generates the gate drive signal GDS fails for some reason, the input signal of the gate drive circuit 101 will remain at the reference potential for a long time, and the driven element 1 will not be turned on for an extended period. Therefore, it has advantages such as being less prone to short-circuit accidents.

[0144] By making the gate drive signal GDS a positive logic signal. Figure 1 The signal generation circuit 301 was changed to Figure 7 The signal generation circuit 301A. Specifically, Figure 7The signal generation circuit 301A includes a first delay circuit 320A, a NOT circuit 311, a logic operation circuit 306, a second delay circuit 321, a diode 108, a capacitor 109, and a non-inverting buffer 110. The structure and connections of the second delay circuit 321, diode 108, capacitor 109, and non-inverting buffer 110 are detailed below. Figure 1 The signal generation circuit 301 is the same, so the same reference symbol is added to the same or equivalent parts without repeated explanation.

[0145] A positive logic gate drive signal GDS is input to the first delay circuit 320A. The first delay circuit 320A generates a first delayed signal by delaying the turn-on edge (rising edge) and delaying the turn-off edge (falling edge) of the input positive logic gate drive signal GDS. The first delay circuit 320A outputs the generated first delayed signal.

[0146] More specifically, such as Figure 7 As shown, the first delay circuit 320A includes a low-pass filter (also referred to as an RC filter) consisting of a resistor 303 and a capacitor 304, a diode 302, and a Schmitt trigger buffer 305A. The resistor 303 and capacitor 304 are connected in series between the signal input terminal 104 and the reference node 103 in this order. The diode 302 is connected in parallel with the resistor 303 and in accordance with... Figure 1 The connections are in the opposite direction. That is, the cathode terminal of diode 302 is connected to node B of resistor 303 and capacitor 304. Thus, the RC filter functions as a unidirectional RC filter that only delays the falling side of the gate drive signal GDS. The signal after passing through the RC filter is input to Schmitt trigger buffer 305A. Schmitt trigger buffer 305A shapes the input signal but does not invert its logic value.

[0147] The logic operation circuit 306 performs a logical AND operation on the first delayed signal output from the first delay circuit 320 and the signal obtained by inverting the gate drive signal GDS using the NOT circuit 311. Figure 1 In the example, NAND circuitry is used as the logic operation circuit 306, so the logic operation circuit 306 inverts the result of the logical AND operation and outputs it. Furthermore, the logic operation circuit 306 can also calculate the logical OR of the inverted signal of the first delayed signal and the gate drive signal GDS, with the same logical operation result.

[0148] Figure 7 Other structures and Figure 1 The situations are the same, so the same reference symbol is added to the same or equivalent parts without repeated explanation.

[0149] [Operation of the gate drive circuit]

[0150] Next, an explanation Figure 7 The operation of the gate drive circuit 101A, and especially the operation of the signal generation circuit 301A.

[0151] Figure 8 It is shown Figure 7 Timing diagram of the operation of gate drive circuit 101A. Figure 8 The timing diagram and Figure 2 The corresponding timing diagram shows Figure 8 The signal waveforms of nodes A~F and the gate voltage V of driven element 1 G The waveform. The following is an explanation of... Figure 2 The differences.

[0152] The signal at node A is the gate drive signal GDS, which is input to the base terminal of NPN transistor 131 and the base terminal of PNP transistor 132.

[0153] When the gate drive signal GDS is low, the PNP transistor 132 is turned on, thereby connecting the gate terminal 4 of the driven element 1 to the reference node 103. Thus, the driven element 1 is in the off state. Conversely, when the gate drive signal GDS is high, the NPN transistor 131 is turned on, thereby connecting the gate terminal 4 of the driven element 1 to the power supply node 102. Thus, the driven element 1 is in the on state.

[0154] Therefore, the gate drive signal GDS is positive logic. The moment t1 when the gate drive signal GDS switches from low to high (i.e., the rising edge of the gate drive signal GDS) corresponds to the turn-on edge. The moment t3 when the gate drive signal GDS switches from high to low (i.e., the falling edge of the gate drive signal GDS) corresponds to the turn-off edge.

[0155] The signal at node B represents the signal output from the unidirectional RC filter of the first delay circuit 320A, obtained by inputting the signal at node A (i.e., the gate drive signal GDS). In the unidirectional RC filter of the first delay circuit 320A, the diode is in the on state when the input signal rises, so the low-pass filter becomes inactive. Conversely, the diode is in the off state when the input signal falls, so the low-pass filter becomes active.

[0156] Specifically, at time t1, which is the rising edge (i.e., the turn-on edge) of the gate drive signal GDS, the output signal of the unidirectional RC filter (i.e., the signal at node B) rises rapidly. On the other hand, at time t3, which is the falling edge (i.e., the turn-off edge) of the gate drive signal GDS, the output signal of the unidirectional RC filter (i.e., the signal at node B) falls slowly.

[0157] The signal at node C represents the signal output from the Schmitt trigger buffer 305A by inputting the signal at node B (i.e., the output signal of the unidirectional RC filter) into the Schmitt trigger buffer 305A. In the case of... Figure 8 When a signal with only a blunted falling edge, like the signal from node B, is input to the Schmitt trigger buffer 305A, the output of the Schmitt trigger buffer 305A is a signal that only significantly delays the falling edge of the input signal.

[0158] The signal at node D represents the output signal of the NAND circuit in the logic operation circuit 306. For example... Figure 8 As shown, the output of NAND circuit 306 is a signal obtained by the logical AND inversion of the signal obtained by the NOT circuit 311 inverting the signal of node A (i.e., the gate drive signal GDS) and the signal of node C (i.e., the output signal of Schmitt trigger buffer 305A).

[0159] exist Figure 8 In this case, the logical AND of the inverted signal of node A and the signal of node C only occurs for a certain period T from the turn-off edge (e.g., ...). Figure 2 The signal at node D (from time t3 to time t5) becomes true, and false during other periods. Therefore, the signal at node D (i.e., the output signal of NAND circuit 306) becomes a reference potential only for a certain period T from the turn-off edge, and a positive potential during other periods. This signal at node D is similar to that in Implementation 1. Figure 2 The signals are the same.

[0160] The signals and gate voltage waveforms V of nodes E and F G and Figure 2 The situation is the same, so I won't repeat it again.

[0161] [Effects of Implementation Method 2]

[0162] As described above, when the gate drive signal GDS is positive logic, a logical AND operation is performed on the first delayed signal (which delays only the turn-off edge of the gate drive signal GDS without delaying the turn-on edge) and the inverted signal of the original gate drive signal GDS. Furthermore, by delaying both the rising and falling edges of the result of this logical AND operation, a control signal for enabling the negative bias is generated and output to the potential switching circuit 201. With this structure in Embodiment 2, similar to Embodiment 1, a minimum necessary negative bias is applied to the gate terminal 4 of the driven element 1, thereby preventing accidental arcing.

[0163] Implementation method 3.

[0164] Figure 9 This is a circuit diagram showing a structural example of the gate drive circuit 101B in Embodiment 3. Figure 7 In the gate drive circuit 101B, the structure of the potential switching circuit 201B is similar to... Figure 1 The structure of the potential switching circuit 201 is different.

[0165] Specifically, Figure 1 The potential switching circuit 201 utilizes a pull-up resistor 202 and an open-drain switch 203 composed of an N-channel MOSFET. In contrast, Figure 9 The potential switching circuit 201B is constructed using an emitter follower circuit employing an NPN transistor 204 (the third switch) and a PNP transistor 205 (the fourth switch). Furthermore, the aforementioned emitter follower circuit is similar to... Figure 1 Unlike open-drain circuits, it operates with positive logic, therefore it replaces... Figure 1 Instead of the non-inverting buffer 110, an inverting buffer 111 is set.

[0166] More specifically, NPN transistor 204 and PNP transistor 205 are connected in series between power node 102 and reference node 103 in this order. The base terminals of NPN transistor 204 and PNP transistor 205 are output to the output terminal of inverting buffer 111. The connection point of NPN transistor 204 and PNP transistor 205 is connected to the second electrode 109B of capacitor 109.

[0167] When the control signal output from the inverting buffer 111 is low (active), the PNP transistor 205 is turned on and the NPN transistor 204 is turned off, so the negative bias is active. When the control signal output from the inverting buffer 111 is high (inactive), the PNP transistor 205 is turned off and the NPN transistor 204 is turned on, so the negative bias is inactive and the capacitor 109 is charged.

[0168] Figure 9 Other structures and Figure 1 The situations are the same, so the same reference symbol is added to the same or equivalent parts without repeated explanation.

[0169] exist Figure 1 In the case of the potential switching circuit 201 shown, when the switch 203 is turned on in order to apply a negative bias to the gate terminal 4, the power supply node 102 is connected to the reference node 103 via the pull-up resistor 202. Therefore, there is a problem of increased power consumption.

[0170] In contrast, Figure 9 In the case of the potential switching circuit 201B shown, when the PNP transistor 205 is turned on in order to apply a negative bias to the gate terminal 4, the NPN transistor 204 in the off state is used to disconnect the power supply node 102 from other circuits. Therefore, the gate drive circuit 101B of Embodiment 3 has the advantage of reducing power consumption compared to the gate drive circuit 101 of Embodiment 1.

[0171] Implementation method 4.

[0172] Figure 10 This is a circuit diagram showing a structural example of the gate drive circuit 101C in Embodiment 4. Figure 10 In the gate drive circuit 101C, the structure of the potential switching circuit 201C is similar to... Figure 1 The structure of the potential switching circuit 201 and Figure 9 The structure of any one of the potential switching circuits 201B is different.

[0173] Specifically, Figure 1 The potential switching circuit 201 utilizes a pull-up resistor 202 and a switch 203 composed of an N-channel MOSFET in an open-drain configuration. Figure 9 The potential switching circuit 201B is constructed using an emitter follower circuit utilizing an NPN transistor 204 and a PNP transistor 205. On the other hand, Figure 10 The potential switching circuit 201C is constructed from a CMOS push-pull circuit using a P-channel MOSFET 206 (the third switch) and an N-channel MOSFET 207 (the fourth switch). The CMOS push-pull circuit operates with negative logic, just like the open-drain circuit.

[0174] More specifically, the P-channel MOSFET 206 and the N-channel MOSFET 207 are connected in series between the power supply node 102 and the reference node 103 in this order. The connection point of the P-channel MOSFET 206 and the N-channel MOSFET 207 is connected to the second electrode 109B of the capacitor 109. A resistor 208 and a diode 210 are connected in parallel between the gate terminal of the P-channel MOSFET 206 and the output terminal of the non-inverting buffer 110. The cathode of the diode 210 is connected to the gate terminal of the P-channel MOSFET 206, and the anode of the diode 210 is connected to the output terminal of the non-inverting buffer 110. Similarly, a resistor 209 and a diode 211 are connected in parallel between the gate terminal of the N-channel MOSFET 207 and the output terminal of the non-inverting buffer 110. The cathode of the diode 211 is connected to the output terminal of the non-inverting buffer 110, and the anode of the diode 211 is connected to the gate terminal of the N-channel MOSFET 207.

[0175] When the control signal output from the non-inverting buffer 110 is high (active), the N-channel MOSFET 207 is turned on and the P-channel MOSFET 206 is turned off, so the negative bias is active. When the control signal output from the non-inverting buffer 110 is low (inactive), the N-channel MOSFET 207 is turned off and the P-channel MOSFET 206 is turned on, so the negative bias is inactive and the capacitor 109 is charged.

[0176] Figure 10 Other structures and Figure 1 The situations are the same, so the same reference symbol is added to the same or equivalent parts without repeated explanation.

[0177] exist Figure 1 In the case of the potential switching circuit 201 shown, when the switch 203 is turned on to apply a negative bias to the gate terminal 4, the power supply node 102 is connected to the reference node 103 via the pull-up resistor 202. Therefore, there is a problem of increased power consumption. Furthermore, in Figure 9 In the case of the emitter follower circuit used in the potential switching circuit 201B, there is a problem of power consumption due to the base current during switching. In contrast, in Figure 10 In the case of the push-pull circuit used in the potential switching circuit 201C, these problems can be avoided, and it has the advantage of reducing power consumption compared to the cases of embodiments 1 to 3.

[0178] [Summary of each implementation method]

[0179] In summary, according to the gate drive circuits 101, 101A, 101B, and 101C of Embodiments 1-4, a capacitor with a minimum necessary capacitance can be used to apply a sufficient negative bias to the gate of the driven element 1 to prevent accidental arcing. Furthermore, the gate drive circuits 101, 101A, 101B, and 101C of Embodiments 1-4 do not require a negative power supply, do not require special processing of the gate drive signal, and do not require other signals to make the negative bias effective. That is, the gate drive circuits of Embodiments 1-4 can be used to replace conventional simplified gate drive circuits without negative bias. This means they can be easily installed in operating devices, thereby easily adding an accidental arcing prevention function. Therefore, the gate drive circuits of Embodiments 1-4 have the significant advantage of having a wide range of applications.

[0180] [Variations on various implementation methods]

[0181] The types of semiconductor elements used in the above embodiments are not limited to these and can be replaced with other types. For example, the driven element 1 is not limited to MOSFET but can also be IGBT. In the case of IGBT, the drain terminal of MOSFET is rewritten as the collector terminal, and the source terminal of MOSFET is rewritten as the emitter terminal. The potential switching circuit 201 of Embodiments 1 and 2 is not only an open-drain circuit but can also be an open-collector circuit. The potential switching circuit 201B described in Embodiment 3 and the potential switching circuit 201C described in Embodiment 4 can also be combined with the emitter follower circuit composed of NPN transistor 131 and PNP transistor 132 described in Embodiment 2.

[0182] The embodiments disclosed herein should be considered illustrative rather than limiting in all respects. The scope of this application is not defined by the foregoing description but by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0183] (Explanation of reference numerals in the attached image)

[0184] 1: Driven element; 2: Drain terminal; 3: Source terminal; 4: Gate terminal; 5: Source reference terminal; 6: Gate capacitor; 101, 101A, 101B, 101C: Gate drive circuit; 102: Power node; 103: Reference node; 104: Signal input terminal; 105, 110: Non-inverting buffer; 106, 107: Gate resistor; 108, 210, 211, 302: Diode; 109, 304, 308: Capacitor; 109A: First electrode; 109B: Second electrode; 111: Inverting buffer; 121, 122, 20 3: Switch; 131, 132, 204, 205: Bipolar Transistors; 133: Connection Point; 201, 201B, 201C: Potential Switching Circuit; 202: Pull-up Resistor; 206, 207: MOSFET; 208, 209, 303, 307: Resistors; 301, 301A: Signal Generation Circuit; 305, 309: Schmitt Triggered Inverter; 305A: Schmitt Triggered Buffer; 306: Logic Operation Circuit (NAND Circuit); 311: NOT Circuit; 320, 320A: First Delay Circuit; 321: Second Delay Circuit.

Claims

1. A gate driving circuit for driving a driven element according to a gate driving signal, comprising: The first switch is connected between the power supply node that is provided with a positive potential and the gate terminal of the driven element. It turns on when the gate drive signal is the first logic value, so that the driven element is in the ON state. The second switch is connected between the reference node to which the reference potential is provided and the gate terminal of the driven element. It turns on when the gate drive signal is the second logic value, thereby turning off the driven element. A diode is connected between the second switch and the reference node in such a manner that the reference node becomes the cathode side; The capacitor, with its first electrode connected to the connection node of the second switch and the diode; A potential switching circuit provides the reference potential to the second electrode of the capacitor when the control signal is valid, and provides the positive potential to the second electrode of the capacitor when the control signal is invalid; as well as The signal generation circuit generates the control signal based on the gate drive signal. The signal generation circuit enables the control signal after the charge at the gate terminal of the driven element is discharged after the gate drive signal switches from the first logic value to the second logic value, and deactivates the control signal before the gate drive signal switches from the second logic value to the first logic value.

2. The gate driving circuit according to claim 1, wherein, The signal generation circuit includes: The first delay circuit generates a first delay signal by delaying the turn-off edge of the gate drive signal from the first logic value to the second logic value and delaying the turn-on edge of the gate drive signal from the second logic value to the first logic value. A logic operation circuit that performs logic operations using the first delayed signal and the gate drive signal; and The second delay circuit generates the control signal or its inverted signal by delaying the operation result of the logic operation circuit.

3. The gate driving circuit according to claim 2, wherein, The first logic value is low, and the second logic value is high. The logic operation of the logic operation circuit includes a logical AND of the inverted signal of the first delayed signal and the gate drive signal, or a logical OR of the inverted signal of the first delayed signal and the gate drive signal.

4. The gate driving circuit according to claim 2, wherein, The first logic value is a high level, and the second logic value is a low level. The logic operation of the logic operation circuit includes a logical AND of the first delayed signal and the inverted signal of the gate drive signal, or a logical OR of the inverted signal of the first delayed signal and the gate drive signal.

5. The gate drive circuit according to any one of claims 1 to 4, wherein, The potential switching circuit includes: A resistor is connected between the power supply node and the second electrode of the capacitor; and A third switch is connected between the second electrode of the capacitor and the reference node. The third switch is in the ON state when the control signal is set to OFF, and in the OFF state when the control signal is set to OFF.

6. The gate driving circuit according to any one of claims 1 to 4, wherein, The potential switching circuit includes: A third switch is connected between the power supply node and the second electrode of the capacitor; and A fourth switch is connected between the second electrode of the capacitor and the reference node. The third switch is in the off state when the control signal is set to valid, and in the on state when the control signal is set to invalid. The fourth switch is in the ON state when the control signal is set to OFF, and in the OFF state when the control signal is set to OFF.

7. The gate drive circuit according to any one of claims 1 to 6, wherein, The branch consisting of the driven element is connected in series with the opposing branch consisting of other driving elements. The period during which the control signal is set to be valid includes the timing during which the drive element of the opposing branch is turned on.

8. The gate driving circuit according to claim 7, wherein, The potential difference between the positive potential and the reference potential is set as V. CC The gate capacitance of the driven element is set to C. GS The turn-on threshold of the driven element is set to V. TH The peak value of the surge voltage when the driving element of the opposing branch is turned on without the capacitor is set to V. SURGE hour, The lower limit of the capacitance of the capacitor is ， The upper limit of the capacitance of the capacitor is 。

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