Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention provides a semiconductor device including a transistor having a large on-state current. The semiconductor device includes a transistor and a first insulating layer. The transistor includes a semiconductor layer, a first conductive layer, and a second conductive layer. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer. The first insulating layer includes a first opening to the first conductive layer. The second conductive layer includes a second opening in a region overlapping the first opening. The semiconductor layer has, in the first opening and the second opening, a region in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a side surface of the second conductive layer. The first insulating layer comprises a second insulating layer and a third insulating layer on the second insulating layer. The second insulating layer contains silicon and oxygen. The third insulating layer contains oxygen and one or both of aluminum and hafnium.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and a method for manufacturing the same. Another aspect of the present invention relates to a transistor and a method for manufacturing the same. A third aspect of the present invention relates to a display device including a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the technical fields described above. Examples of technical fields encompassing one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), and driving or manufacturing methods for the aforementioned devices.

[0003] Note that in this specification, etc., a semiconductor device refers to a device that utilizes the properties of semiconductors, and includes circuits that include semiconductor elements (transistors, diodes, photodiodes, etc.) and devices that include such circuits. Furthermore, a semiconductor device refers to all devices capable of functioning by utilizing the properties of semiconductors. Examples of semiconductor devices include integrated circuits, chips incorporating integrated circuits, and electronic components that house chips in packages. In addition, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and sometimes all include semiconductor devices. Background Technology

[0004] Semiconductor devices, including transistors, are widely used in electronic devices. For example, in display devices, by reducing the area occupied by transistors, pixel size can be reduced, thereby improving resolution. Therefore, miniature transistors are needed.

[0005] The development of devices that require high-definition display devices, such as those for Virtual Reality (VR), Augmented Reality (AR), Substitutional Reality (SR), and Mixed Reality (MR), is very active.

[0006] As a display device, for example, a light-emitting device incorporating organic EL (Electro Luminescence) elements or light-emitting diodes (LEDs) is being developed.

[0007] Patent document 1 discloses a high-definition display device using organic EL elements. [Preliminary Technology Documents] [Patent Literature]

[0008] [Patent Document 1] International Patent Application Publication No. 2016 / 038508 Summary of the Invention The technical problem that the invention aims to solve

[0009] One objective of this invention is to provide a semiconductor device comprising micro-sized transistors. Another objective of this invention is to provide a semiconductor device comprising transistors with short channel lengths. Another objective of this invention is to provide a semiconductor device comprising transistors with large on-state currents. Another objective of this invention is to provide a semiconductor device comprising transistors with high field-effect mobility. Another objective of this invention is to provide a semiconductor device comprising transistors with good electrical characteristics. Another objective of this invention is to provide a semiconductor device that operates at high speeds. Another objective of this invention is to provide a semiconductor device with a small footprint. Another objective of this invention is to provide a semiconductor device with low wiring resistance. Another objective of this invention is to provide a semiconductor device or display device with low power consumption. Another objective of this invention is to provide a transistor, semiconductor device, or display device with high reliability. Another objective of this invention is to provide a high-definition display device. Another objective of this invention is to provide a method for manufacturing a semiconductor device or display device with high productivity. Another objective of this invention is to provide a novel transistor, semiconductor device, display device, or method for manufacturing the same.

[0010] Note that the description of these objectives does not preclude the existence of other objectives. One aspect of the invention does not require achieving all of the above objectives. Objectives other than those described above can be extracted from the specification, drawings, and claims. means of solving technical problems

[0011] One aspect of the present invention is a semiconductor device including a transistor and a first insulating layer. The transistor includes a semiconductor layer, a first conductive layer, and a second conductive layer. A first insulating layer is located on the first conductive layer. A second conductive layer is located on the first insulating layer. The first insulating layer includes a first opening extending into the first conductive layer. The second conductive layer includes a second opening in a region overlapping with the first opening. The semiconductor layer has regions in the first and second openings that contact the top surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer. The first insulating layer includes a second insulating layer and a third insulating layer on the second insulating layer. The second insulating layer comprises silicon and oxygen. The third insulating layer comprises one or both of aluminum and hafnium, and oxygen.

[0012] In the above-described semiconductor device, the semiconductor layer preferably comprises a metal oxide.

[0013] In the aforementioned semiconductor device, the first insulating layer preferably includes a fourth insulating layer. The fourth insulating layer is preferably located between the first conductive layer and the second insulating layer. The fourth insulating layer preferably comprises silicon and nitrogen.

[0014] In the aforementioned semiconductor device, the first insulating layer preferably includes a fifth insulating layer and a sixth insulating layer. The fifth insulating layer is preferably located between the first conductive layer and the fourth insulating layer. The sixth insulating layer is preferably located between the second conductive layer and the third insulating layer. The fifth insulating layer preferably comprises silicon and nitrogen. The sixth insulating layer preferably comprises silicon and nitrogen. The fifth insulating layer preferably has a region with a higher hydrogen content than the fourth insulating layer.

[0015] In the aforementioned semiconductor device, a fifth insulating layer is preferably included. The first insulating layer preferably includes a sixth insulating layer. The top surface of the fifth insulating layer preferably has a region that contacts the bottom surface of the first conductive layer. The sixth insulating layer is preferably located between the second conductive layer and the third insulating layer. The fifth insulating layer preferably comprises silicon and nitrogen. The sixth insulating layer preferably comprises silicon and nitrogen. The fifth insulating layer preferably has a region where its hydrogen content is higher than that of the fourth insulating layer.

[0016] In the aforementioned semiconductor device, the semiconductor layer preferably has a first region in contact with the top surface of the first conductive layer and a second region in contact with the top surface of the second conductive layer. Both the first and second regions preferably contain a first element. The first element is preferably boron or phosphorus.

[0017] In the aforementioned semiconductor device, the semiconductor layer preferably includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The second semiconductor layer is preferably located on the first semiconductor layer. The third semiconductor layer is preferably located on the second semiconductor layer. The first semiconductor layer preferably comprises a first metal oxide. The second semiconductor layer preferably comprises a second metal oxide. The third semiconductor layer preferably comprises a third metal oxide. The band gap of the first metal oxide is preferably larger than the band gap of the second metal oxide. The band gap of the third metal oxide is preferably larger than the band gap of the second metal oxide.

[0018] In the aforementioned semiconductor device, the band gap of the third metal oxide is preferably larger than that of the first metal oxide. The thickness of the third semiconductor layer is preferably larger than that of the first semiconductor layer. The thickness of the second semiconductor layer is preferably larger than that of the third semiconductor layer.

[0019] In the aforementioned semiconductor device, the semiconductor layer preferably includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The second semiconductor layer is preferably located on the first semiconductor layer. The third semiconductor layer is preferably located on the second semiconductor layer. The first semiconductor layer preferably comprises a first metal oxide. The second semiconductor layer preferably comprises a second metal oxide. The third semiconductor layer preferably comprises a third metal oxide. The first metal oxide preferably comprises indium, a second element, and zinc. The second metal oxide preferably comprises indium. The third metal oxide preferably comprises indium, a third element, and zinc. The second element is preferably one or more of gallium, aluminum, and tin. The third element is preferably one or more of gallium, aluminum, and tin. The content of the second element in the first metal oxide is preferably higher than the sum of the contents of gallium, aluminum, and tin in the second metal oxide. The content of the third element in the third metal oxide is preferably higher than the sum of the contents of gallium, aluminum, and tin in the second metal oxide.

[0020] In the aforementioned semiconductor device, the content of the third element in the third metal oxide is preferably higher than the content of the second element in the first metal oxide. The thickness of the third semiconductor layer is preferably greater than the thickness of the first semiconductor layer. The thickness of the second semiconductor layer is preferably greater than the thickness of the third semiconductor layer.

[0021] One aspect of the present invention is a method for manufacturing a semiconductor device, comprising the steps of: forming a first conductive layer; forming a first insulating film on the first conductive layer; forming a second insulating film on the first insulating film; forming a first conductive film on the second insulating film; processing the first conductive film to form a second conductive layer including a first opening in a region overlapping with the first conductive layer; processing the first and second insulating films to form a first insulating layer and a second insulating layer including a second opening in a region overlapping with the first opening; and forming a semiconductor layer on the first conductive layer, the second conductive layer, the first insulating layer, and the second insulating layer. The first insulating layer comprises silicon and oxygen. The second insulating layer comprises one or both of aluminum and hafnium, and oxygen.

[0022] In the above-described semiconductor device manufacturing method, the second insulating film is preferably formed by sputtering in an oxygen-containing atmosphere. Invention Effects

[0023] According to one aspect of the present invention, a semiconductor device comprising micro-sized transistors can be provided. Additionally, a semiconductor device comprising transistors with short channel lengths can be provided. Additionally, a semiconductor device comprising transistors with large on-state currents can be provided. Additionally, a semiconductor device comprising transistors with high field-effect mobility can be provided. Additionally, a semiconductor device comprising transistors with good electrical characteristics can be provided. Additionally, a semiconductor device operating at high speeds can be provided. Additionally, a semiconductor device with a small footprint can be provided. Additionally, a semiconductor device with low wiring resistance can be provided. Additionally, a semiconductor device or display device with low power consumption can be provided. Additionally, a transistor, semiconductor device, or display device with high reliability can be provided. Additionally, a high-definition display device can be provided. Additionally, a method for manufacturing a semiconductor device or display device with high productivity can be provided. Additionally, a novel transistor, semiconductor device, display device, or method for manufacturing the same can be provided.

[0024] Note that the description of these effects does not preclude the existence of other effects. One aspect of the invention does not necessarily require all of the aforementioned effects. Effects other than those described above can be extracted from the specification, drawings, and claims. Brief description of the attached figures

[0025] FIG. 1A This is a top view showing an example of a semiconductor device. FIG. 1B and FIG. 1C This is a cross-sectional view showing an example of a semiconductor device. FIG. 2A to FIG. 2D This is a perspective view showing an example of a semiconductor device. FIG. 3A This is a top view showing an example of a semiconductor device. FIG. 3B This is a cross-sectional view showing an example of a semiconductor device. FIG. 4 This is a cross-sectional view showing an example of a semiconductor device. FIG. 5A to FIG. 5D This is a cross-sectional view showing an example of a semiconductor device. FIG. 6 This is a cross-sectional view showing an example of a semiconductor device. FIG. 7A to FIG. 7C This is a cross-sectional view showing an example of a semiconductor device. FIG. 8A to FIG. 8C This is a cross-sectional view showing an example of a semiconductor device. FIG. 9A to FIG. 9C This is a cross-sectional view showing an example of a semiconductor device. FIG. 10A and FIG. 10BThis is a cross-sectional view showing an example of a semiconductor device. FIG. 11A and FIG. 11B This is a cross-sectional view showing an example of a semiconductor device. FIG. 12A and FIG. 12B This is a cross-sectional view showing an example of a semiconductor device. FIG. 13A and FIG. 13B This is a cross-sectional view showing an example of a semiconductor device. FIG. 14A and FIG. 14B This is a cross-sectional view showing an example of a semiconductor device. FIG. 15 This is a cross-sectional view showing an example of a semiconductor device. FIG. 16A and FIG. 16B This is a cross-sectional view showing an example of a semiconductor device. FIG. 17A to FIG. 17C This is a cross-sectional view showing an example of a semiconductor device. FIG. 18A This is a top view showing an example of a semiconductor device. FIG. 18B and FIG. 18C This is a cross-sectional view showing an example of a semiconductor device. FIG. 19A This is a top view showing an example of a semiconductor device. FIG. 19B and FIG. 19C This is a cross-sectional view showing an example of a semiconductor device. FIG. 20A to FIG. 20I This is a circuit diagram illustrating an example of a semiconductor device. FIG. 21A This is a top view showing an example of a semiconductor device. FIG. 21B and FIG. 21C This is a cross-sectional view showing an example of a semiconductor device. FIG. 22A and FIG. 22B This is a cross-sectional view showing an example of a semiconductor device. FIG. 23A This is a top view showing an example of a semiconductor device. FIG. 23B and FIG. 23C This is a cross-sectional view showing an example of a semiconductor device. FIG. 24A This is a top view showing an example of a semiconductor device. FIG. 24B and FIG. 24C This is a cross-sectional view showing an example of a semiconductor device. FIG. 25A This is a top view showing an example of a semiconductor device. FIG. 25BThis is a cross-sectional view showing an example of a semiconductor device. FIG. 26A This is a top view showing an example of a semiconductor device. FIG. 26B This is a cross-sectional view showing an example of a semiconductor device. FIG. 27A and FIG. 27B It is the equivalent circuit diagram of a semiconductor device. FIG. 27C This is a top view showing an example of a semiconductor device. FIG. 28 This is a cross-sectional view showing an example of a semiconductor device. FIG. 29 This is a perspective view showing an example of a semiconductor device. FIG. 30A to FIG. 30D This is a perspective view showing an example of a semiconductor device. FIG. 31A and FIG. 31B It is the equivalent circuit diagram of a semiconductor device. FIG. 31C This is a top view showing an example of a semiconductor device. FIG. 32 This is a cross-sectional view showing an example of a semiconductor device. FIG. 33 This is a perspective view showing an example of a semiconductor device. FIG. 34A to FIG. 34D This is a perspective view showing an example of a semiconductor device. FIG. 35A to FIG. 35E This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. FIG. 36A to FIG. 36D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. FIG. 37A to FIG. 37D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. FIG. 38 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. FIG. 39 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. FIG. 40 This is a perspective view showing an example of a display device. FIG. 41A and FIG. 41B This is a cross-sectional view showing an example of a display device. FIG. 42 This is a cross-sectional view showing an example of a display device. FIG. 43A to FIG. 43C This is a cross-sectional view showing an example of a display device. FIG. 44A and FIG. 44BThis is a cross-sectional view showing an example of a display device. FIG. 45 This is a cross-sectional view showing an example of a display device. FIG. 46 This is a cross-sectional view showing an example of a display device. FIG. 47 This is a cross-sectional view showing an example of a display device. FIG. 48A and FIG. 48B This is a cross-sectional view showing an example of a display device. FIG. 49A to FIG. 49D This is a diagram illustrating an example of an electronic device. FIG. 50A to FIG. 50F This is a diagram illustrating an example of an electronic device. FIG. 51A to FIG. 51G This is a diagram illustrating an example of an electronic device. FIG. 52A to FIG. 52C This is a cross-sectional view showing the structure of a sample and its manufacturing method according to an embodiment. FIG. 53 This is a graph showing the TDS analysis results according to an embodiment. FIG. 54 This is a graph showing the TDS analysis results according to an embodiment. FIG. 55 This is a diagram illustrating the Id-Vg characteristics of a transistor according to an embodiment. FIG. 56A to FIG. 56C This is an example of the structure of pixels according to an embodiment. Methods of implementing the invention

[0026] The embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited only to the contents described in the embodiments shown below.

[0027] Note that in the invention structure described below, the same symbols are used in different figures to show the same parts or parts with the same function, and repeated descriptions are omitted. Furthermore, when parts with the same function are indicated, the same shading lines are sometimes used without additional symbols.

[0028] For ease of understanding, the positions, sizes, and extents of the components shown in the accompanying drawings may not represent their actual positions, sizes, and extents. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and extents disclosed in the accompanying drawings.

[0029] Note that, for convenience, ordinal numbers such as "first" and "second" are used in this specification, etc., but these do not limit the number of constituent elements or the order of the constituent elements (e.g., process sequence or stacking sequence). Furthermore, the ordinal numbers used for constituent elements in one part of this specification may sometimes differ from those used for the same constituent element in other parts of this specification or in the claims.

[0030] Furthermore, depending on the situation or state, the "film" and "layer" can be interchanged. For example, a "conductive layer" can be changed into a "conductive film." In addition, an "insulating film" can be changed into an "insulating layer."

[0031] A transistor is a type of semiconductor device that can amplify current or voltage and control switching operations, such as turning on or off. The transistors discussed in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0032] In situations where transistors with different polarities are used or the direction of current in the circuit changes, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be used interchangeably. Note that, depending on the situation, the source and drain of the transistor can be appropriately referred to as source terminal and drain terminal, or source electrode and drain electrode, etc.

[0033] In this specification, "electrical connection" includes connections made via "elements that have a certain electrical function." Here, "elements that have a certain electrical function" are not particularly limited as long as they can transmit and receive electrical signals between the connected objects. For example, "elements that have a certain electrical function" include, in addition to electrodes or wiring, switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0034] In this specification, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in the off state (also known as the non-conducting state or the blocked state). Unless otherwise specified, in an n-channel transistor, the off state refers to the state where the voltage Vgs between the gate and source is lower than the threshold voltage Vth (in a p-channel transistor, Vgs is higher than Vth).

[0035] In this specification, "generally consistent top surface shapes" means that at least a portion of the outline of each layer in a stack overlaps. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion thereof. However, there are actually cases where the outlines do not overlap; sometimes the upper layer is inside or outside the lower layer. In such cases, it can also be said that the "top surface shapes are generally consistent." When the top surface shapes are consistent or generally consistent, it can also be said that the ends are aligned or substantially aligned.

[0036] Note that, in this specification, a conical shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region where the angle (also referred to as the cone angle) formed by the inclined side surface and the substrate surface or the surface to be formed is less than 90 degrees. Here, the side surface of the constituent element, the substrate surface, and the surface to be formed do not necessarily have to be completely flat; they may also be approximately planar with slight curvature or approximately planar with slight irregularities.

[0037] In this specification, devices manufactured using metal masks or FMM (Fine Metal Mask) are sometimes referred to as devices with an MM (Metal Mask) structure. Furthermore, devices manufactured without metal masks or FMM are sometimes referred to as devices with an MML (Metal Mask Less) structure. Note that because MML structure devices can be manufactured without metal masks, the resolution can exceed the upper limit of the alignment accuracy required by metal masks. Furthermore, MML structure devices do not require the equipment needed for metal mask manufacturing or the metal mask washing process. In addition, MML structure devices can reduce manufacturing costs, making them suitable for mass production.

[0038] In this specification and other materials, the structure in which light-emitting elements (also called light-emitting devices) with different emission wavelengths are separately fabricated is sometimes referred to as an SBS (Side By Side) structure. Because the SBS structure allows for optimization of materials and structure for each light-emitting element, the freedom of material and structure selection is increased, making it easier to achieve improvements in brightness and reliability.

[0039] In this specification and other materials, holes or electrons are sometimes referred to as "carriers." Specifically, the hole injection layer or electron injection layer of a light-emitting element is sometimes called a "carrier injection layer," the hole transport layer or electron transport layer is called a "carrier transport layer," and the hole blocking layer or electron blocking layer is called a "carrier blocking layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier blocking layer may not be clearly distinguished. In addition, sometimes a single layer functions as two or three of the carrier injection layer, carrier transport layer, and carrier blocking layer.

[0040] In this specification, the light-emitting element includes an EL layer between a pair of electrodes. The EL layer includes at least a light-emitting layer. Examples of layers included in the EL layer (also referred to as functional layers) include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier blocking layer (hole blocking layer and electron blocking layer). In this specification, the light-receiving element (also referred to as a light-receiving device) includes at least an active layer serving as a photoelectric conversion layer between a pair of electrodes. In this specification, sometimes one of the pairs of electrodes is referred to as a pixel electrode and the other as a common electrode.

[0041] In this specification, the sacrificial layer (also known as a mask layer) is located at least above the light-emitting layer (more specifically, the layer that is processed into an island shape in the layers constituting the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.

[0042] In this specification and the like, "disconnection" refers to the phenomenon where a layer, film, or electrode is disconnected due to the shape of the surface to which it is formed (e.g., a step).

[0043] (Implementation Method 1) In this embodiment, refer to FIG. 1A to FIG. 34D A semiconductor device according to one aspect of the present invention is described.

[0044] One aspect of the present invention is a semiconductor device including a transistor and a first insulating layer.

[0045] A transistor includes a semiconductor layer, a first conductive layer, a second conductive layer, a gate insulating layer, and a gate electrode. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer. The first insulating layer includes a first opening (also called an opening portion) reaching the first conductive layer. The second conductive layer includes a second opening in a region overlapping with the first opening. The semiconductor layer has regions in the first and second openings that contact the top surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer. A gate insulating layer is disposed on the semiconductor layer. A gate electrode is disposed on the gate insulating layer. The first conductive layer is used as one of the source and drain electrodes of the transistor, and the second conductive layer is used as the other of the source and drain electrodes. The region of the semiconductor layer that contacts the first insulating layer is used as a channel forming region. Therefore, the channel length of the transistor can be made smaller than the minimum size that the exposure apparatus can expose (hereinafter also referred to as the minimum size), and a transistor with a large on-state current can be realized.

[0046] The first insulating layer includes a second insulating layer and a third insulating layer on top of the second insulating layer. The second insulating layer comprises silicon and oxygen. The third insulating layer comprises one or both of aluminum and hafnium, as well as oxygen.

[0047] The semiconductor layer preferably comprises a metal oxide. Furthermore, the second insulating layer is preferably made of an oxygen-releasing material. This allows oxygen to be supplied from the second insulating layer to the semiconductor layer (especially the channel formation region), thus reducing the oxygen vacancies (V) in the semiconductor layer. O Oxygen Vacancy).

[0048] In transistors with short channel lengths, the more oxygen supplied from the second insulating layer to the semiconductor layer, the better. The third insulating layer disposed on the second insulating layer is preferably formed in an oxygen-containing atmosphere. This allows oxygen to be supplied to the second insulating layer. Furthermore, the third insulating layer is preferably made of a material that is not easily permeable to other materials. Specifically, the third insulating layer is preferably made of a material that is not easily permeable to oxygen. This suppresses the diffusion of oxygen from the second insulating layer through the third insulating layer to the second conductive layer side. Therefore, increasing the amount of oxygen supplied from the second insulating layer to the channel formation region of the semiconductor layer reduces the oxygen vacancies (V0) in the channel formation region. O Therefore, even transistors with short channel lengths can simultaneously possess good electrical characteristics and high reliability.

[0049] <Structure Example 1> [Structure Example 1-1] A semiconductor device according to one aspect of the present invention will be described. FIG. 1A A top view (also known as a plan view) of the semiconductor device 10 is shown. FIG. 1B Show along FIG. 1A A cross-sectional view of the section between the dotted line A1 and A2 in the diagram. FIG. 1C This shows a cross-sectional view along the dashed line B1-B2. Note that... FIG. 1A In the diagram, some components of the semiconductor device 10 (such as the gate insulating layer) are omitted. Regarding the top view of the semiconductor device, [the diagram is incomplete]. FIG. 1A Similarly, some of the constituent elements are omitted in the following figures. FIG. 2A to FIG. 2D A perspective view of the semiconductor device 10 is shown. Note that... FIG. 2B Show along FIG. 2A The cross-section of the dashed line C1-C2 in the diagram. FIG. 2C Shown in perspective FIG. 2A The insulating layer shown is outlined with dashed lines. Similarly, in FIG. 2D Shown in perspective FIG. 2B The insulating layer shown is outlined with dashed lines. FIG. 3A and FIG. 3B Show FIG. 1A and FIG. 1B Enlarged image.

[0050] The semiconductor device 10 includes a transistor 100 and an insulating layer 110. The semiconductor device 10 is disposed on a substrate 102.

[0051] Transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. Conductive layer 104 serves as the gate electrode. A portion of the insulating layer 106 serves as the gate insulating layer. Conductive layer 112a serves as one of the source and drain electrodes, and conductive layer 112b serves as the other of the source and drain electrodes. In semiconductor layer 108, the region between the source and drain electrodes, separated by the gate insulating layer and overlapping with the gate electrode, serves as a channel forming region. Furthermore, in semiconductor layer 108, the region in contact with the source electrode serves as the source region, and the region in contact with the drain electrode serves as the drain region.

[0052] A conductive layer 112a is disposed on a substrate 102, an insulating layer 110 is disposed on the conductive layer 112a, and a conductive layer 112b is disposed on the insulating layer 110. The insulating layer 110 is in contact with the conductive layers 112a and 112b and has a region that is held between them. The conductive layer 112a includes a region that overlaps with the conductive layer 112b through the insulating layer 110. The insulating layer 110 includes an opening 141 that extends to the conductive layer 112a. Alternatively, the conductive layer 112a may be exposed in the opening 141. The conductive layer 112b includes an opening 143 in the region that overlaps with the conductive layer 112a. The opening 143 is disposed in the region that overlaps with the opening 141.

[0053] Semiconductor layer 108 is disposed such that it covers openings 141 and 143. Semiconductor layer 108 includes regions that contact the top and side surfaces of conductive layer 112b, the side surface of insulating layer 110, and the top surface of conductive layer 112a. Semiconductor layer 108 is electrically connected to conductive layer 112a through openings 141 and 143. Semiconductor layer 108 has a shape that extends along the top and side surfaces of conductive layer 112b, the side surface of insulating layer 110, and the top surface of conductive layer 112a.

[0054] There are no particular limitations on the semiconductor material used for semiconductor layer 108. For example, a semiconductor or compound semiconductor composed of a single element can be used. Examples of semiconductors composed of a single element include silicon or germanium. Examples of compound semiconductors include gallium arsenide and silicon-germanium. In addition, examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS). Note that these semiconductor materials may also contain impurities as dopants.

[0055] There are no particular restrictions on the crystallinity of the semiconductor material used for semiconductor layer 108; amorphous semiconductors, single-crystal semiconductors, or semiconductors with crystallinity other than single crystal (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors with a portion of crystalline regions) can be used. When using single-crystal semiconductors or semiconductors with crystallinity, the degradation of transistor characteristics can be suppressed, so they are preferred.

[0056] For example, silicon can be used as the semiconductor layer 108. Examples of silicon include monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. For example, low-temperature polycrystalline silicon (LTPS) can be used as the polycrystalline silicon. Transistors using amorphous silicon as the channel formation region can be formed on large glass substrates and can be manufactured at low cost. Transistors using polycrystalline silicon as the channel formation region have high field-effect mobility and can operate at high speeds. Furthermore, transistors using microcrystalline silicon as the channel formation region have higher field-effect mobility than transistors using amorphous silicon and can operate at high speeds.

[0057] Semiconductor layer 108 preferably comprises a metal oxide (also known as an oxide semiconductor) exhibiting semiconductor properties. Compared to transistors using amorphous silicon, transistors using oxide semiconductors (hereinafter referred to as OS transistors) have very high field-effect mobility. Furthermore, OS transistors have extremely low off-state currents, allowing them to retain the charge stored in the capacitor connected in series with the transistor for extended periods. Additionally, the power consumption of semiconductor devices can be reduced by using OS transistors.

[0058] As the insulating layer 110, one or both of inorganic and organic insulating layers can be used. Examples of materials suitable for organic insulating layers include acrylic resin and polyimide resin. The insulating layer 110 preferably comprises one or more inorganic insulating layers. Examples of materials suitable for inorganic insulating layers include oxides, nitrides, oxynitrides, and oxynitrides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride. Examples of oxynitrides include silicon oxynitride and aluminum oxynitride.

[0059] Note that in this specification, oxynitrides refer to materials in which the oxygen content is greater than the nitrogen content. Nitrogen oxides refer to materials in which the nitrogen content is greater than the oxygen content.

[0060] The insulating layer 110 has a region that contacts the semiconductor layer 108. When a metal oxide is used as the semiconductor layer 108, at least a portion of the region of the insulating layer 110 that contacts the semiconductor layer 108 preferably contains oxygen in order to improve the interface characteristics between the semiconductor layer 108 and the insulating layer 110. Specifically, the portion of the insulating layer 110 that contacts the channel forming region of the semiconductor layer 108 preferably contains oxygen. The portion of the insulating layer 110 that contacts the channel forming region of the semiconductor layer 108 can suitably use one or more of oxides and oxynitrides.

[0061] When a metal oxide is used as the semiconductor layer 108, it is preferable that at least a portion of the region of the insulating layer 110 in contact with the semiconductor layer 108 releases oxygen by heating. This allows oxygen to be supplied from the insulating layer 110 to the semiconductor layer 108, reducing oxygen vacancies (V) in the semiconductor layer 108. O ) and defects in oxygen vacancies where hydrogen enters (hereinafter referred to as V) O H).

[0062] An insulating layer 106, serving as the gate insulating layer of transistor 100, is disposed such that it covers openings 141 and 143. The insulating layer 106 is disposed on semiconductor layer 108, conductive layer 112b, and insulating layer 110. The insulating layer 106 includes regions that contact the top and side surfaces of semiconductor layer 108, conductive layer 112b, and insulating layer 110. The insulating layer 106 has a shape that extends along the top and side surfaces of insulating layer 110, conductive layer 112b, and semiconductor layer 108.

[0063] A conductive layer 104, serving as the gate electrode of the transistor 100, is disposed on the insulating layer 106 and includes a region that contacts the top surface of the insulating layer 106. The conductive layer 104 includes a region that overlaps with the semiconductor layer 108 across the insulating layer 106. The conductive layer 104 has a shape that extends along the top and side surfaces of the insulating layer 106.

[0064] Transistor 100 is a so-called top-gate transistor having a gate electrode above semiconductor layer 108. Furthermore, since the bottom surface of semiconductor layer 108 is in contact with both the source and drain electrodes, it can be considered a TGBC (Top Gate Bottom Contact) type transistor. Additionally, in transistor 100, the heights of the source and drain electrodes relative to the surface of the substrate 102 on which they are formed are different, and drain current flows in a direction perpendicular to or substantially perpendicular to the surface of substrate 102. Alternatively, in transistor 100, drain current flows in the longitudinal direction or substantially the longitudinal direction. Therefore, a transistor according to one aspect of the present invention can be considered a longitudinal channel transistor, a longitudinal transistor, or a VFET (Vertical Field Effect Transistor).

[0065] The channel length of transistor 100 can be controlled by the thickness of the insulating layer 110 disposed between conductive layers 112a and 112b. Therefore, transistors with channel lengths smaller than the minimum exposure dimensions of the exposure apparatus used for transistor manufacturing can be manufactured with high precision. Furthermore, characteristic inhomogeneities among multiple transistors 100 can be reduced. Consequently, the semiconductor device 10 operates stably, improving reliability. Moreover, reduced characteristic inhomogeneities in transistors increase circuit design freedom and allow for a reduction in the operating voltage of the semiconductor device. This, in turn, reduces the power consumption of the semiconductor device.

[0066] Because the source electrode, semiconductor layer, and drain electrode can be stacked, the area occupied by a transistor of one aspect of the present invention can be much smaller than that of a so-called planar transistor in which the semiconductor layer is configured as a planar shape.

[0067] Conductive layers 112a, 112b, and 104 can all be used as wiring, and transistor 100 can be disposed in the area where these wirings overlap. That is, in a circuit including transistor 100 and wiring, the area occupied by transistor 100 and wiring can be reduced. Therefore, a smaller semiconductor device can be realized by reducing the area occupied by the circuit.

[0068] For example, when the semiconductor device of one aspect of the present invention is used in the pixel circuit of a display device, the occupied area of ​​the pixel circuit can be reduced, and a high-definition display device can be realized. Furthermore, for example, when the semiconductor device of one aspect of the present invention is used in the driving circuit of a display device (e.g., one or both of a gate line driving circuit and a source line driving circuit), the occupied area of ​​the driving circuit can be reduced, thus enabling a display device with a narrow bezel.

[0069] The insulating layer 110 preferably has a laminated structure. FIG. 1BExamples of insulating layer 110 include insulating layer 110a, insulating layer 110b on insulating layer 110a, and insulating layer 110c on insulating layer 110b. Insulating layer 110a, insulating layer 110b, and insulating layer 110c can all be made of materials exemplified as insulating layer 110.

[0070] The region in semiconductor layer 108 that contacts insulating layer 110b is used as a channel formation region. Insulating layer 110b preferably contains oxygen, and preferably uses one or more of the oxides and oxynitrides described above. Specifically, insulating layer 110b may suitably use one or both of silicon oxide and silicon oxynitride.

[0071] More preferably, the insulating layer 110b uses a material that releases oxygen upon heating. Oxygen is released from the insulating layer 110b by heat applied during the manufacturing process of the semiconductor device 10, thereby supplying oxygen to the semiconductor layer 108. By supplying oxygen from the insulating layer 110b to the semiconductor layer 108, particularly to the channel formation region of the semiconductor layer 108b, oxygen vacancies (V) are filled. O This can reduce oxygen vacancies (V). O Additionally, it can reduce V. O H. Therefore, transistors exhibiting good electrical characteristics and high reliability can be realized.

[0072] For example, oxygen can be supplied to the insulating layer 110b by heating or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied by forming a film on the top surface of the insulating layer 110b using a sputtering method in an oxygen-containing atmosphere. This film can then be removed. Furthermore, the method for supplying oxygen to the insulating layer 110b will be specifically described in Embodiment 2.

[0073] The insulating layer 110b is preferably formed using a deposition method such as sputtering or plasma-enhanced chemical vapor deposition (PECVD). In particular, by using a sputtering method and not using hydrogen-containing gases (such as hydrogen and ammonia) as the deposition gas, a film with extremely low hydrogen content can be achieved. Therefore, the supply of hydrogen to the channel formation region can be suppressed, thereby stabilizing the electrical characteristics of the transistor 100.

[0074] An insulating layer 110a is disposed between an insulating layer 110b and a conductive layer 112a. An insulating layer 110c is disposed between an insulating layer 110b and a conductive layer 112b. The amount of impurities (e.g., hydrogen and water) released from each of the insulating layers 110a and 110c is preferably minimal. Furthermore, both the insulating layers 110a and 110c are preferably impermeable to substances. In other words, the insulating layers 110a and 110c function as barrier films. Specifically, both the insulating layers 110a and 110c are preferably impermeable to impurities. This suppresses the diffusion of impurities from the insulating layers 110a and 110c into the channel formation region. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be realized.

[0075] Both insulating layers 110a and 110c are preferably made of materials that are not easily permeable to oxygen. This prevents oxygen in insulating layer 110b from diffusing through insulating layer 110a to the conductive layer 112a side. Similarly, it prevents oxygen in insulating layer 110b from diffusing through insulating layer 110c to the conductive layer 112b side. This increases the amount of oxygen supplied from insulating layer 110b to the channel formation region of semiconductor layer 108, thereby reducing oxygen vacancies (V) in the channel formation region. O ) and V O H. Therefore, transistors exhibiting good electrical characteristics and high reliability can be realized. Furthermore, the increase in resistance of conductive layer 112a due to oxidation of conductive layer 112a caused by oxygen in insulating layer 110b can be suppressed. Similarly, the increase in resistance of conductive layer 112b due to oxidation of conductive layer 112b caused by oxygen in insulating layer 110b can be suppressed. Therefore, transistors with large on-state current can be realized.

[0076] Furthermore, in this specification and the like, a barrier film refers to a film that has barrier properties. Barrier properties refer to one or both of the functions of inhibiting the permeation of a substance through the membrane due to its poor diffusion (also known as low permeability) and trapping or fixing the substance (also known as gettering). For example, an insulating layer with barrier properties can be referred to as a barrier insulating layer.

[0077] The insulating layers 110a and 110c used as the barrier film can, for example, be one or more of oxides containing one or both of aluminum and hafnium, oxides containing magnesium, oxides containing gallium, nitrides containing silicon, and oxide oxynitrides containing silicon. Specifically, the insulating layers 110a and 110c can suitably be one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, silicon nitride, and silicon oxynitride. Furthermore, the insulating layers 110a and 110c can be made of the same material. Alternatively, the insulating layers 110a and 110c can be made of different materials.

[0078] In this specification, different materials refer to materials whose constituent elements are partially or wholly different, or materials whose constituent elements are the same but whose composition is different.

[0079] The formation of insulating layer 110 is described below. Insulating layer 110 can be formed by forming an insulating film that becomes insulating layer 110 and forming an opening 141 in the insulating film. Specifically, the opening 141 is formed after forming a first insulating film that becomes insulating layer 110a, a second insulating film that becomes insulating layer 110b, and an insulating film that becomes insulating layer 110c, thereby forming insulating layer 110 including insulating layer 110a, insulating layer 110b, and insulating layer 110c.

[0080] Oxygen is preferably supplied to the second insulating film after it has been formed as insulating layer 110b. For example, a third insulating film, forming insulating layer 110c, is formed on the second insulating film in an oxygen-containing atmosphere, thereby supplying oxygen to the second insulating film. An oxygen-containing material can be suitably used as the third insulating film. Furthermore, by using a material that is not easily permeable to oxygen as the third insulating film, the diffusion of oxygen supplied to the second insulating film through the third insulating film can be suppressed. One or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, and zinc gallium oxide can be suitably used as the third insulating film (the subsequent insulating layer 110c).

[0081] The higher the proportion of oxygen in the overall deposition gas used to form the third insulating membrane (hereinafter also referred to as the oxygen flow ratio) or the higher the oxygen partial pressure in the processing chamber of the deposition apparatus, the more efficiently oxygen can be supplied to the second insulating membrane.

[0082] Here, when the substrate temperature is high during the formation of the third insulating film, oxygen in the second insulating film may diffuse outwards, resulting in a decrease in the oxygen content in the second insulating film. Consequently, the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 may decrease. Therefore, the substrate temperature during the formation of the third insulating film is preferably low. The substrate temperature during formation can be adjusted, for example, according to the temperature of the stage on which the substrate is placed during formation. The substrate temperature during the formation of the third insulating film is preferably lower than the substrate temperature during the formation of the second insulating film. This increases the amount of oxygen supplied to the channel formation region, thereby reducing the oxygen vacancies (V) in the channel formation region. O ) and V O H. The third insulating film can be formed appropriately using sputtering or atomic layer deposition (ALD). By using these methods, a dense film can be formed even at a relatively low substrate temperature. Therefore, a third insulating film that is not easily permeable to oxygen can be achieved.

[0083] Since the first insulating film is formed before the second insulating film, there is no need to worry about oxygen escaping from the second insulating film due to heating during the formation of the first insulating film. Therefore, the substrate temperature during the formation of the first insulating film can be higher than the substrate temperature during the formation of the third insulating film. By increasing the substrate temperature during formation, a dense film can be formed, thereby achieving a first insulating film that is not easily permeable by oxygen.

[0084] Preferably, the second insulating film is formed continuously using the same apparatus after the first insulating film is formed. This helps to suppress the adhesion of atmospheric impurities to the surface of the first insulating film. Examples of such impurities include water and organic matter. Furthermore, using the same processing chamber of the apparatus allows for the formation of both the first and second insulating films at a high productivity. When using the same processing chamber, it is preferable to set the substrate temperature during the formation of the first insulating film to the same temperature as the substrate temperature during the formation of the second insulating film. For example, the first and second insulating films can be formed using the same processing chamber of a PECVD apparatus. Specifically, using the same processing chamber of a PECVD apparatus, a silicon nitride film can be formed as the first insulating film and a silicon oxynitride film can be formed as the second insulating film.

[0085] The thickness T110a of the insulating layer 110a is preferably 3 nm or more and 500 nm or less, more preferably 5 nm or more and 400 nm or less, more preferably 10 nm or more and 300 nm or less, more preferably 20 nm or more and 300 nm or less, more preferably 50 nm or more and 300 nm or less, more preferably 100 nm or more and 300 nm or less, more preferably 100 nm or more and 250 nm or less, and more preferably 150 nm or more and 250 nm or less. For example... FIG. 3B As shown, the thickness T110a can be the shortest distance between the surface of the insulating layer 110a that is formed (here, the top surface of the conductive layer 112a) and the top surface of the insulating layer 110a when viewed from the cross section.

[0086] When the thickness T110a of the insulating layer 110a is small, oxygen in the insulating layer 110b may diffuse through the insulating layer 110a to the conductive layer 112a side, reducing the amount of oxygen supplied to the channel formation region. On the other hand, when the thickness T110a is thick, the amount of impurities released from the insulating layer 110a may increase, resulting in more impurities diffusing into the channel formation region. By setting the thickness T110a within the above range, the amount of oxygen supplied to the channel formation region can be increased, thereby reducing the oxygen vacancies (V) in the channel formation region. O ) and V O H. Furthermore, it can suppress the increase in resistance of conductive layer 112a due to oxidation of conductive layer 112a caused by oxygen in insulating layer 110b. Note that the thickness T110a is not limited to the above range.

[0087] The thickness T110a of the insulating layer 110a can be greater than the thickness T110c of the insulating layer 110c. When the region of the semiconductor layer 108 in contact with the insulating layer 110a is used as a source region or a drain region, increasing the thickness T110a can make the distance from the source region or drain region to the gate electrode more uniform. This further makes the electric field applied to the gate electrode in the channel formation region more uniform. FIG. 3B As shown, the thickness T110c can be the shortest distance between the surface of the insulating layer 110c that is formed (here, the top surface of the insulating layer 110b) and the top surface of the insulating layer 110c when viewed from the cross section.

[0088] The thickness T110c of the insulating layer 110c is preferably 3nm or more and 100nm or less, more preferably 3nm or more and 50nm or less, more preferably 3nm or more and 30nm or less, more preferably 3nm or more and 20nm or less, more preferably 3nm or more and 10nm or less, and more preferably 5nm or more and 10nm or less.

[0089] The thickness T110c is preferably a value that at least acts as a barrier film against oxygen. The thickness T110c can be smaller than the thickness T110a. When the thickness T110c of the insulating layer 110c is thick, sometimes more impurities are released from the insulating layer 110c, and more impurities diffuse into the channel formation region. On the other hand, when the thickness T110c is small, sometimes oxygen in the insulating layer 110b diffuses through the insulating layer 110c to the conductive layer 112b side, reducing the amount of oxygen supplied to the channel formation region. By setting the thickness T110c within the above range, the amount of oxygen supplied to the channel formation region can be increased, thereby reducing the oxygen vacancies (V) in the channel formation region. O ) and V O H. Furthermore, it can suppress the increase in resistance of the conductive layer 112b due to oxidation of the conductive layer 112b caused by oxygen in the insulating layer 110b. Note that the thickness T110c is not limited to the above range.

[0090] At least one of the regions of semiconductor layer 108 that contact the insulating layer 110a and the region that contact the insulating layer 110c can also be a region with low resistance compared to the channel formation region (hereinafter also referred to as a low-resistance region). This region can also be described as a region with high carrier concentration and high oxygen vacancy density compared to the channel formation region. By using a material that releases impurities (e.g., water and hydrogen) in the insulating layer 110a, the region of semiconductor layer 108 that contacts the insulating layer 110a can be used as a low-resistance region. Semiconductor layer 108 can have a structure that includes a low-resistance region between the region that contacts the conductive layer 112a (one of the source region and drain region) and the channel formation region. Similarly, by using an impurity-releasing material as the insulating layer 110c, the region of semiconductor layer 108 that contacts the insulating layer 110c can be used as a low-resistance region. Semiconductor layer 108 can have a structure that includes a low-resistance region between the region that contacts the conductive layer 112b (the other of the source region and drain region) and the channel formation region. Low-resistance regions can be used as buffer regions to mitigate the drain electric field. These low-resistance regions can also be used as source or drain regions.

[0091] Additionally, impurities released from insulating layer 110a sometimes diffuse to the channel formation region via insulating layer 110b or one of the source and drain regions of semiconductor layer 108. Similarly, impurities released from insulating layer 110c sometimes diffuse to the channel formation region via insulating layer 110b or the other of the source and drain regions of semiconductor layer 108. However, at least the region of semiconductor layer 108 in contact with insulating layer 110b is supplied with oxygen from insulating layer 110b, thus reducing the oxygen vacancies (V) in the channel formation region. O ) and V O H. Therefore, threshold voltage drift can be suppressed, thereby enabling transistors with low cutoff current and high on-state current. This allows for the creation of semiconductor devices that simultaneously achieve low power consumption and high performance.

[0092] However, when too much impurity is released from insulating layers 110a and 110c, oxygen vacancies (V) generated by these impurities... O ) and V O The amount of H may be greater than the oxygen vacancies repaired by the oxygen supplied from the insulation layer 110b (V O ) and V O The amount of H. Even if materials that release impurities are used as insulating layers 110a and 110c, the amount of released impurities is preferably small.

[0093] The insulating layer 110 preferably includes at least insulating layers 110b and 110c. For example, a structure excluding insulating layer 110a may also be used. In addition, the insulating layer 110 may also have a stacked structure of four or more layers.

[0094] Notice, FIG. 1B Examples are shown where the semiconductor layer 108, insulating layer 106, and conductive layer 104 cover openings 141 and 143, but one aspect of the invention is not limited thereto. Alternatively, the structure may have a step formed by the insulating layer 110, conductive layer 112b, and conductive layer 112a, along which the semiconductor layer 108, insulating layer 106, and conductive layer 104 are disposed.

[0095] [Semiconductor layer 108] Specifically, the metal oxide that can be used in semiconductor layer 108 will be described. Examples of metal oxides include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium or zinc. Furthermore, the metal oxide preferably contains one or more elements selected from indium, element M, and zinc. Note that element M is a metallic or half-metallic element with a high bond energy with oxygen, for example, a metallic or half-metallic element with a higher bond energy with oxygen than indium. Specifically, elements M can be aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. Element M in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more selected from gallium, aluminum, and tin. These elements have high bond energies with oxygen, and their ionic radii are approximately the same as those of indium or zinc, so they are more preferred. Furthermore, since tin is tetravalent, it can improve carrier mobility, making it a preferred choice. Note that in this specification, etc., metallic elements and half-metallic elements are sometimes collectively referred to as "metallic elements," and the term "metallic element" as used in this specification, etc., sometimes includes half-metallic elements.

[0096] Semiconductor layer 108 may be made of, for example, indium zinc oxide (In-Zn oxide, also known as IZO (registered trademark)), indium tin oxide (In-Sn oxide, also known as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also known as IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also known as IGTO), gallium zinc oxide (Ga-Zn oxide, also known as GZO), or aluminum zinc oxide (Al-Zn oxide). Oxides, also abbreviated as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also abbreviated as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also abbreviated as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also abbreviated as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also abbreviated as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also abbreviated as IGAZO, IGZAO, or IAGZO), etc. Alternatively, silicon-containing oxides such as indium tin oxide (also abbreviated as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide) can be used.

[0097] Note that metal oxides can adopt structures that replace indium or include one or more metals with high period numbers in the periodic table, in addition to indium. There is a tendency that the greater the orbital overlap of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including metals with high period numbers, the field-effect mobility of transistors can sometimes be improved. Examples of metals with high period numbers include those belonging to the 5th and 6th periods. Specifically, examples of such metals include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0098] Metal oxides can also contain one or more non-metallic elements. When metal oxides contain non-metallic elements, the field-effect mobility of transistors can sometimes be improved due to increased carrier concentration or narrower band gap. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0099] Increasing the proportion of indium atoms in a metal oxide relative to the sum of the atomic numbers of all metal elements can improve the field-effect mobility of a transistor. Furthermore, it allows for the realization of transistors with high on-state currents.

[0100] In this specification, the proportion of the number of indium atoms relative to the sum of the number of atoms of all the contained metallic elements is sometimes described as the indium content. The same applies to other metallic elements. When multiple elements are contained as element M, the sum of the ratios of the number of atoms of element M relative to the sum of the number of atoms of all the contained metallic elements can be described as the content of element M.

[0101] When the zinc content in a metal oxide is increased, the metal oxide becomes highly crystallinity, which suppresses the diffusion of impurities within the metal oxide. Therefore, variations in the electrical characteristics of the transistor are suppressed, thereby improving reliability.

[0102] Increasing the content of element M in metal oxides can result in metal oxides with large band gaps. Furthermore, suppressing the formation of oxygen vacancies (V) in metal oxides can also achieve this. O ), caused by oxygen vacancies (V O Carrier generation is suppressed, thereby suppressing threshold voltage drift in the transistor. This reduces the cutoff current, enabling normally-off transistors. Furthermore, transistors with low off-state current can be achieved. Additionally, variations in the transistor's electrical characteristics are suppressed, thus improving reliability.

[0103] The electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the semiconductor layer 108. Therefore, by changing the composition of the metal oxide according to the required electrical characteristics and reliability of the transistor, a semiconductor device with both excellent electrical characteristics and high reliability can be realized.

[0104] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably greater than or equal to the atomic ratio of element M. Examples of such atomic ratios for the metal elements in this In-M-Zn oxide include: In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, and In:M:Zn = 5:1:8. The following compositions are considered: In:M:Zn = 5:1:9, In:M:Zn = 6:1:6, In:M:Zn = 10:1:1, In:M:Zn = 10:1:3, In:M:Zn = 10:1:4, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10, and their vicinity. Furthermore, vicinity compositions include a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in metal oxides, gold can improve the on-state current or field-effect mobility of transistors.

[0105] In In-M-Zn oxides, the atomic ratio of In can also be less than the atomic ratio of element M. Examples of such atomic ratios of the metal element in In-M-Zn oxides include In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6, and compositions close to these. By increasing the proportion of M atoms in the metal oxide, oxygen vacancies (V) can be suppressed. O The generation of ).

[0106] Note that when element M contains multiple elements, the sum of the atomic ratios of these elements can be set as the atomic ratio of element M.

[0107] By using materials with a high indium content in semiconductor layer 108, the on-state current or field-effect mobility of the transistor can be improved. Furthermore, by including element M, oxygen vacancies (V0) can be suppressed. OThe content of element M (the ratio of the number of atoms of element M relative to the sum of the number of atoms of all contained metallic elements) is preferably 0.1% or more and 25% or less, more preferably 0.1% or more and 20% or less, more preferably 0.1% or more and 10% or less, more preferably 0.1% or more and 8% or less, more preferably 0.1% or more and 6% or less, and more preferably 0.1% or more and 4% or less. This allows for the realization of transistors with excellent electrical characteristics. For example, metal oxides with In:M:Zn = 40:1:10 and its vicinity are preferably used. Element M is preferably any one or more of the above-mentioned elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, metal oxides with In:Sn:Zn = 40:1:10 and its vicinity can be used appropriately. Alternatively, metal oxides with In:Al:Zn = 40:1:10 and its vicinity can be used appropriately.

[0108] Here, by using a metal oxide with a polycrystalline structure as the semiconductor layer 108, grain boundaries become recombination centers, trapping charge carriers, thus sometimes reducing the on-state current of the transistor. Furthermore, when a metal oxide with a polycrystalline structure is used as the semiconductor layer 108, the surface roughness of the semiconductor layer 108 sometimes increases. Consequently, the steps on the formed surfaces of layers (e.g., insulating layer 106) on the semiconductor layer 108 sometimes become larger, leading to problems such as breaks or voids in the layer. When using a metal oxide with a composition that easily becomes polycrystalline in the semiconductor layer 108, it is preferable to include elements that inhibit crystallization. This can suppress the semiconductor layer 108 from becoming polycrystalline, thereby enabling the realization of transistors with high on-state currents. Furthermore, the coverage of the layers (e.g., insulating layer 106) formed on the semiconductor layer 108 can be improved, thereby suppressing problems such as breaks or voids in the layer.

[0109] For example, compared to indium tin oxide (ITO), silicon-containing indium tin oxide (ITSO) is less likely to form a polycrystalline structure, so it can be appropriately used for semiconductor layer 108. When using ITSO, the silicon content (the ratio of silicon atoms to the sum of the atomic numbers of all contained metal elements) is preferably 1% or more and 20% or less, more preferably 3% or more and 20% or less, more preferably 3% or more and 15% or less, and even more preferably 5% or more and 15% or less. Specifically, In:Sn:Si = 45:5:4, In:Sn:Si = 95:5:8, and metal oxides near them can be appropriately used. When silicon-containing indium tin oxide (ITSO) is used as semiconductor layer 108, it is preferable to have crystallinity. Furthermore, semiconductor layer 108 may include amorphous regions or be amorphous.

[0110] Metal oxides that do not contain element M can be used for semiconductor layer 108. When the metal oxide is an In-Zn oxide, examples of the atomic ratios of the metal elements include In:Zn = 1:1, In:Zn = 2:1, In:Zn = 1:2, In:Zn = 3:1, In:Zn = 3:2, In:Zn = 2:3, In:Zn = 4:1, In:Zn = 4:3, In:Zn = 5:1, In:Zn = 5:2, In:Zn = 5:3, In:Zn = 5:4, In:Zn = 5:6, In:Zn = 5:7, In:Zn = 5:8, In:Zn = 5:9, In:Zn = 7:1, In:Zn = 10:1, In:Zn = 10:3, In:Zn = 10:7, and compositions near these ratios. Furthermore, the atomic ratio of In is more preferably greater than that of Zn. By increasing the atomic ratio of In in the metal oxide, the on-state current or field-effect mobility of the transistor can be improved.

[0111] In the analysis of the composition of semiconductor layer 108, methods such as energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS or ESCA), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES) can be used. Alternatively, multiple methods can be combined. Peak separation of the obtained spectra is preferred to identify and quantify elements. Note that due to the influence of analytical precision, the actual content of elements with low content may differ from the content obtained from the analysis. For example, when the content of element M is low, the content of element M obtained from the analysis may sometimes be lower than the actual content, difficult to quantify, or below the detection limit.

[0112] Metal oxides can be formed appropriately using sputtering or atomic layer deposition (ALD). Note that when metal oxides are formed using sputtering, the composition of the resulting metal oxide sometimes differs from that of the sputtering target. In particular, the zinc content in the resulting metal oxide can sometimes be reduced to about 50% of that in the sputtering target.

[0113] Semiconductor layer 108 is preferably made of a crystalline metal oxide. Examples of crystalline metal oxide structures include CAAC (c-axis aligned crystal) structures, polycrystalline structures, and nano-crystal (nc) structures. By using a crystalline metal oxide, the defect state density in semiconductor layer 108 can be reduced, thereby enabling a highly reliable semiconductor device.

[0114] Semiconductor layer 108 preferably uses CAAC-OS or nc-OS.

[0115] The CAAC-OS has multiple layered crystals. The c-axis of these crystals is oriented in the normal direction of the formed surface. The semiconductor layer 108 preferably has layered crystals parallel to or substantially parallel to the formed surface. For example, the semiconductor layer 108 preferably has layered crystals parallel to or substantially parallel to the top surface of the conductive layer 112b in the region contacting the top surface of the conductive layer 112b, and layered crystals parallel to or substantially parallel to the side surface in the region contacting the side surface of the conductive layer 112b. In particular, the semiconductor layer 108 preferably has layered crystals in the opening 141 parallel to or substantially parallel to the side surface of the insulating layer 110, which is the formed surface. By employing this structure, the layered crystals of the semiconductor layer 108 are parallel to or substantially parallel to the channel length direction of the transistor 100, thus enabling the realization of a transistor with a large on-state current.

[0116] By using highly crystalline metal oxides in the channel formation region, the defect state density in the channel formation region can be reduced. On the other hand, by using low-crystallinity metal oxides, transistors capable of carrying large currents can be realized.

[0117] The higher the substrate temperature during metal oxide formation, the more crystalline the metal oxide can be formed. The substrate temperature during formation can be adjusted, for example, according to the temperature of the stage on which the substrate is placed. Furthermore, the higher the oxygen flow rate ratio of the deposition gas used for formation or the higher the oxygen partial pressure in the processing chamber, the more crystalline the metal oxide can be formed.

[0118] The crystallinity of the semiconductor layer 108 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, multiple of the above methods can be combined for analysis.

[0119] When a metal oxide is used as the semiconductor layer 108, it is preferable to minimize the Vc in the channel formation region. OH is made to be a high-purity intrinsic or substantially high-purity intrinsic. Thus, in order to obtain V... O For metal oxides with sufficiently reduced H, it is important to: remove impurities such as water and hydrogen from the metal oxide (sometimes described as dehydration or dehydrogenation); and supply oxygen to the metal oxide to repair oxygen vacancies (V). O ). By V O Metal oxides with sufficiently low levels of impurities such as hydrogen (H) used in the channel formation region of transistors can impart stable electrical characteristics. Note that sometimes oxygen is supplied to the metal oxide to repair oxygen vacancies (V0). O The treatment of ) is called oxidation treatment.

[0120] When a metal oxide is used as the semiconductor layer 108, the carrier concentration in the channel formation region is preferably 1 × 10⁻⁶. 18 cm -3 Below, less than 1×10 is preferred. 17 cm -3 Further optimization of less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 Further preferred is less than 1×10 12 cm -3 There is no lower limit to the carrier concentration in the channel formation region; for example, it can be set to 1 × 10⁻⁶. -9 cm -3 .

[0121] OS transistors exhibit minimal changes in electrical characteristics due to radiation exposure, meaning they possess high radiation tolerance and can therefore be appropriately used in environments where radiation is likely to occur. OS transistors can also be described as having high reliability against radiation. For example, OS transistors can be appropriately used in the pixel circuitry of X-ray flat panel detectors. Furthermore, OS transistors can be appropriately used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton radiation, and neutron radiation).

[0122] Semiconductor layer 108 may also contain layered materials used as semiconductors. Layered materials are a general term for materials with layered crystal structures. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked through bonds weaker than covalent and ionic bonds, such as van der Waals bonds. Layered materials have high conductivity per unit layer, that is, high two-dimensional conductivity. By using a material that serves as a semiconductor and has high two-dimensional conductivity in the channel formation region, transistors with large on-state currents can be provided.

[0123] Examples of the aforementioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen elements (belonging to Group 16 elements). Furthermore, examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as channel forming regions in transistors include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0124] Semiconductor layer 108 may employ a stacked structure comprising two or more metal oxide layers. The compositions of the two or more metal oxide layers comprising semiconductor layer 108 may be identical or substantially identical. By employing a stacked structure of metal oxide layers with identical compositions, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. When the compositions of the two or more metal oxide layers comprising semiconductor layer 108 are identical or substantially identical, it is sometimes impossible to clearly identify the boundaries (interfaces) of these metal oxide layers.

[0125] [Insulation layer 110] As described above, the insulating layer 110 preferably has a stacked structure. It is preferable that the material readily diffuses within the insulating layer 110b. In other words, the diffusion coefficient of the material in the insulating layer 110b is preferably large. Particularly preferred is that oxygen readily diffuses within the insulating layer 110b. That is, the oxygen diffusion coefficient in the insulating layer 110b is preferably large. Oxygen diffuses within the insulating layer 110b and is supplied to the semiconductor layer 108 via the interface between the insulating layer 110b and the semiconductor layer 108. By using the oxygen-diffusive insulating layer 110b, oxygen in the insulating layer 110b can be efficiently supplied to the semiconductor layer 108 (especially the channel formation region).

[0126] The oxygen diffusion coefficient of insulating layer 110b at 350°C is preferably 5 × 10⁻⁶. -12 cm 2 / sec or higher, more preferably 1×10 -11 cm 2 / sec or higher, further preferably 5×10 -11 cm 2 / sec or higher, and further preferred to be 1×10 -10 cm 2 / sec or higher. This allows for efficient supply of oxygen from the insulating layer 110b to the semiconductor layer 108. A higher diffusion coefficient is better, therefore no specific upper limit is set. Note that the diffusion coefficient of oxygen in the insulating layer 110b is not limited to the range described above.

[0127] In the calculation of diffusion coefficients, thermal desorption mass spectrometry (TDS) can be used, for example. Alternatively, secondary ion mass spectrometry (SIMS) can also be used.

[0128] The formation of insulating layer 110b will be explained in detail. Here, an example of forming silicon oxynitride using the PECVD method will be explained.

[0129] As the source gas for the insulating layer 110b, a gas containing a silicon-containing deposition gas and an oxidizing gas can be used. For example, one or more of the following can be used as the silicon-containing deposition gas: silane (SiH4), disilane (Si2H6), propane (Si3H8), fluorinated silane (SiF4), and TEOS (Tetraethoxysilane, Si(OC2H5)4). As the oxidizing gas, an oxygen-containing gas can be suitably used. For example, one or more of the following can be used as the oxidizing gas: oxygen (O2), ozone (O3), nitrous oxide (N2O), nitric oxide (NO), and nitrogen dioxide (NO2). When silane (SiH4) is used as the silicon-containing deposition gas and nitrous oxide (N2O) is used as the oxidizing gas, it is preferable to use oxygen (O2) as it reduces particulate matter. Alternatively, when silicon oxide is formed in the insulating layer 110b and TEOS is used as the silicon-containing deposition gas, oxygen (O2) can be suitably used as the oxidizing gas.

[0130] In the formation of the insulating layer 110b using the PECVD method, an insulating layer with a large diffusion coefficient can be formed by reducing the plasma density relative to the flow rate of the depositing gas, i.e., reducing the ratio of plasma density to flow rate of the depositing gas. Here, when plasmaification of the source gas is performed using an RF power supply, the plasma density can be reduced by decreasing the power of the RF power supply (hereinafter also referred to as RF power). By reducing the RF power relative to the flow rate of the depositing gas (reducing the ratio of RF power to flow rate of the depositing gas), an insulating layer with a large diffusion coefficient can be formed. By reducing the ratio of RF power relative to the flow rate of the depositing gas (hereinafter also referred to as the F ratio), the oxygen diffusion coefficient in the insulating layer 110b increases, allowing for efficient supply of oxygen from the insulating layer 110b to the semiconductor layer 108 (especially the channel formation region). However, when a hydrogen-containing gas (e.g., SiH4) is used as the source gas, sometimes the hydrogen content in the insulating layer 110b increases when the F ratio is too low. When there is a lot of hydrogen in the insulating layer 110b, the amount of impurities including hydrogen (e.g., water, hydrogen and ammonia) released from the insulating layer 110b may increase.

[0131] When the gas flow rate is expressed in sccm (Standard Cubic Centimeters Per Minute) and the RF power is expressed in W (Watt), the F ratio is preferably 12 or less, 10 or less, 9 or less, 8 or less, 7 or less, 6 or less, or 5 or less, and is 2 or more or more. For example, when the flow rate of silane (SiH4) is 290 sccm and the RF power is 1160 W, the F ratio is 4. By setting the F ratio within the above range, oxygen in the insulating layer 110b can be efficiently supplied to the semiconductor layer 108 (especially the channel formation region), and the amount of impurities released from the insulating layer 110b can be reduced. Note that the F ratio when forming the insulating layer 110b is not limited to the above range.

[0132] In this specification, sccm represents the flow rate at 1 atmosphere and 0°C (273.15 K). Although the F-ratio is shown with gas flow rate in sccm and RF power in W, it can be converted to other units to calculate the F-ratio when using different units. For example, at a flow rate of 0.3 SLM (Standard Liter Per Minute), the flow rate can be converted to 300 sccm to calculate the F-ratio.

[0133] Compared to transistors with long channel lengths, in transistor 100 with short channel lengths, there are more oxygen vacancies (V0) in the channel formation region. O ) and V OHydrogen (H) has a significant impact on electrical characteristics. Therefore, it is crucial to reduce impurities released from the insulating layer 110b while efficiently supplying oxygen from the insulating layer 110b to the semiconductor layer 108 (especially the channel formation region of the semiconductor layer 108b). By setting the F-ratio during the formation of the insulating layer 110b within the aforementioned range, transistors exhibiting good electrical characteristics and high reliability can be achieved.

[0134] When gas is released from the membrane due to heating, the rate-limiting processes for gas release can be categorized as diffusion rate limiting within the membrane and reaction rate limiting at the membrane surface. Membranes where substances diffuse easily are less likely to become diffusion rate limiting agents, and therefore the temperature at which gas release begins upon heating (hereinafter also referred to as the release temperature) is lower. On the other hand, membranes where substances do not diffuse easily become diffusion rate limiting agents, and therefore the gas release temperature is higher. As described above, the insulating layer 110b preferably uses a membrane where substances diffuse easily. Therefore, the gas release temperature when the insulating layer 110b is heated is preferably low. For example, the gas release temperature is preferably low in the TDS of the insulating layer 110b. In particular, in the TDS of the insulating layer 110b, oxygen ( 16 The release temperature of O2 (m / z = 32) is preferably low.

[0135] Furthermore, during the manufacturing process of the semiconductor device 10, oxygen is sometimes supplied from the insulating layer 110b to the semiconductor layer 108. After the manufacturing process, the amount of oxygen released from the insulating layer 110b in the semiconductor device 10 may decrease. Therefore, during the TDS (Total Dissipation System) of the semiconductor device 10, sometimes less oxygen is released. However, because substances other than oxygen can also diffuse easily in a film where oxygen diffuses easily, the film can be considered an oxygen-diffuse film if the release temperature for gases other than oxygen is low. For example, in the TDS of the semiconductor device 10, in the presence of nitrogen (… 14 When the release temperature of N2 (m / z = 28) is low, it can be assumed that the release temperature of oxygen is also low, thus suggesting that the film is one where oxygen readily diffuses. In the TDS of semiconductor device 10, nitrogen ( 14 The release temperature of N2 (m / z = 28) is preferably below 250°C, below 200°C, below 180°C, below 170°C, or below 160°C but above 140°C. This allows for efficient supply of oxygen from the insulating layer 110b to the semiconductor layer 108 (especially the channel formation region) and reduces the amount of impurities released from the insulating layer 110b. Furthermore, during TDS of the semiconductor device 10, it is preferable to remove the upper layer of the insulating layer 110b to expose it. In this embodiment, the heating rate of the sample surface temperature during TDS is approximately 14°C / min. Additionally, the heating rate of the sample stage can be, for example, around 32°C / min. Note that the nitrogen release temperature of the insulating layer 110b is not limited to the above ranges.

[0136] An example of how to calculate the release temperature in TDS is explained. In a graph where the X-axis represents the sample surface temperature and the Y-axis represents the mass spectrometer's detection intensity (e.g., current value), a tangent line can be drawn at the point of maximum slope on the low-temperature side of the peak, and the intersection of this tangent line with the X-axis (Y=0) can be set as the release temperature. It is preferable to perform background processing on the mass spectrometer's detection intensity. As a background processing method, for example, one approach is to subtract the minimum detection intensity across the entire measured temperature range from the measured value as a background value.

[0137] Note that a high F-ratio during film formation results in a slower etching rate relative to the etchant, while a low F-ratio during film formation results in a faster etching rate relative to the etchant. Therefore, the etching rate can be used as an indicator of diffusion ease. For example, an etchant containing hydrofluoric acid can be used. Specifically, hydrofluoric acid and BHF (Buffered Hydrofluoric Acid) are examples. BHF is an etchant containing hydrofluoric acid and a buffer (e.g., ammonium fluoride (NH4F)). Alternatively, etchants with added surfactants can also be used. For example, when silicon oxide or silicon oxynitride is used for the insulating layer 110b, the etching rate of the insulating layer 110b relative to 0.5 wt% hydrofluoric acid at 25°C is preferably 8 nm / min or more, 9 nm / min or more, 10 nm / min or more, 11 nm / min or more, or 12 nm / min or more and 15 nm / min or less. Note that the etching rate of the insulating layer 110b is not limited to the above ranges.

[0138] Here, by using a material with high conductivity in semiconductor layer 108, a transistor with a large on-state current can be realized. However, oxygen vacancies (V0) are easily formed when using a material with high conductivity. O ), oxygen vacancies (V) in the channel formation region O When the number of oxygen vacancies increases, the threshold voltage of the transistor sometimes drifts, and the drain current (hereinafter also referred to as the cutoff current) flowing through it when the gate voltage is 0V increases. For example, in an n-channel transistor, the cutoff current sometimes increases when the threshold voltage drifts negatively. By providing an insulating layer 110b, oxygen is supplied at least to the region of the semiconductor layer 108 that is in contact with the insulating layer 110b, i.e., to the channel formation region, thus reducing the number of oxygen vacancies (V) in the channel formation region. O ) and V O H. Therefore, threshold voltage drift can be suppressed, thereby enabling transistors with low cutoff current and high on-state current. This allows for the creation of semiconductor devices that simultaneously achieve low power consumption and high performance.

[0139] In semiconductor layer 108, the region in contact with conductive layer 112a is used as one of the source and drain regions of transistor 100, and the region in contact with conductive layer 112b is used as the other. The source and drain regions are regions with lower resistance compared to the channel formation region. The source and drain regions can also be described as regions with higher carrier concentration and higher oxygen vacancy density compared to the channel formation region.

[0140] [Opening 141, Opening 143] There are no restrictions on the shape of the top surfaces of openings 141 and 143. For example, they can both be circles, ellipses, triangles, quadrilaterals (including rectangles, rhombuses, and squares), pentagons, or other polygons with rounded corners. Note that the polygons can also be concave polygons (polygons with at least one interior angle exceeding 180 degrees) or convex polygons (polygons with all interior angles less than 180 degrees). FIG. 1A As shown, the top surface shapes of openings 141 and 143 are preferably circular. Having a circular top surface shape improves the machining accuracy during opening formation and allows for the creation of fine openings. Note that in this specification, the circular shape is not limited to a perfect circle.

[0141] In this specification, the top surface shape of opening 141 refers to the shape of the top surface end of the insulating layer 110 on the side of opening 141. Furthermore, the top surface shape of opening 143 refers to the shape of the bottom surface end of the conductive layer 112b on the side of opening 143.

[0142] like FIG. 1A As shown, the top surface shape of opening 141 can be made to be the same as or approximately the same as the top surface shape of opening 143. In this case, as... FIG. 1B and FIG. 1C As shown, the bottom end of the conductive layer 112b on the side of the opening 143 preferably coincides with or substantially coincides with the top end of the insulating layer 110 on the side of the opening 141. The bottom surface of the conductive layer 112b refers to the surface on the side of the insulating layer 110. The top surface of the insulating layer 110 refers to the surface on the side of the conductive layer 112b.

[0143] Furthermore, the top surface shape of opening 141 may not be the same as that of opening 143. In addition, when the top surface shapes of opening 141 and opening 143 are circular, opening 141 and opening 143 may or may not be concentric circles.

[0144] Reference FIG. 3A and FIG. 3B Explain the channel length and channel width of transistor 100.

[0145] exist FIG. 3BThe dashed double arrows in the diagram represent the channel length L100 of transistor 100. The channel length L100 of transistor 100 is equivalent to the length of the side surface of the insulating layer 110b on the side of the opening 141, as viewed in cross-section. In other words, the channel length L100 is determined by the thickness T110b of the insulating layer 110b and the angle θ110b between the side surface of the insulating layer 110b on the side of the opening 141 and the surface of the insulating layer 110b to which it is formed (here, the top surface of the insulating layer 110a). Therefore, the channel length L100 can be made smaller than the minimum exposure size of the exposure apparatus, enabling the realization of micro-transistors. Specifically, transistors with extremely short channel lengths that cannot be achieved by the exposure apparatuses used in the mass production of existing flat panel displays (e.g., with a minimum linewidth of approximately 2 μm or 1.5 μm) can be realized. Furthermore, transistors with channel lengths less than 10 nm can be realized without using the very expensive exposure apparatuses used in the most advanced LSI technology.

[0146] The channel length L100 can be, for example, 5nm or more, 7nm or more, or 10nm or more and less than 3μm, less than 2.5μm, less than 2μm, less than 1.5μm, less than 1.2μm, less than 1μm, less than 500nm, less than 300nm, less than 200nm, less than 100nm, less than 50nm, less than 30nm, or less than 20nm. For example, the channel length L100 can be set to 100nm or more and less than 1μm.

[0147] By shortening the channel length L100, the on-state current of the transistor 100 can be increased. Using the transistor 100, circuits capable of high-speed operation can be manufactured. Furthermore, the circuit's footprint can be reduced. Therefore, a miniaturized semiconductor device can be realized. For example, in the case of a semiconductor device according to one aspect of the present invention used in a large display device or a high-definition display device, the signal delay of each wiring can be reduced even when the number of wirings increases, thereby suppressing display unevenness. In addition, since the circuit's footprint can be reduced, the bezel of the display device can be reduced.

[0148] The channel length L100 can be controlled by adjusting the thickness T110b and angle θ110b of the insulating layer 110b.

[0149] The thickness T110b of the insulating layer 110b can be, for example, 5nm or more, 7nm or more, or 10nm or more and less than 3μm, less than 2.5μm, less than 2μm, less than 1.5μm, less than 1.2μm, less than 1μm, less than 500nm, less than 300nm, less than 200nm, less than 100nm, less than 50nm, less than 30nm, or less than 20nm.

[0150] The side of the insulating layer 110 with opening 141 preferably has a tapered shape. The angle θ110b is preferably less than 90 degrees. By reducing the angle θ110b, the coverage of the layer (e.g., semiconductor layer 108) formed on the insulating layer 110 can be improved. In addition, the smaller the angle θ110b, the longer the channel length L100 can be, and the larger the angle θ110b, the shorter the channel length L100 can be.

[0151] Angle θ110b can be, for example, greater than 30 degrees, greater than 35 degrees, greater than 40 degrees, greater than 45 degrees, greater than 50 degrees, greater than 55 degrees, greater than 60 degrees, greater than 65 degrees, or greater than 70 degrees but less than 90 degrees, less than 85 degrees, or less than 80 degrees. Angle θ110b can also be less than 75 degrees, less than 70 degrees, less than 65 degrees, or less than 60 degrees.

[0152] Note that, although in FIG. 1B The isoelectric angle θ110b is less than 90 degrees, but one aspect of the invention is not limited to this. For example... FIG. 4 As shown, the angle θ110b can be 90 degrees or approximately 90 degrees. This can shorten the channel length L100 of the transistor 100.

[0153] exist FIG. 1B In the examples shown, the side of the insulating layer 110 with the opening 141 is depicted as having a straight shape when viewed in cross-section; however, one aspect of the invention is not limited to this. When viewed in cross-section, the side of the insulating layer 110 with the opening 141 may also be curved, and may have both a region with a straight side shape and a region with a curved side shape.

[0154] Here, the conductive layer 112b is preferably not disposed inside the opening 141. Specifically, the conductive layer 112b preferably does not have a region that contacts the side of the insulating layer 110 on the side of the opening 141. When the conductive layer 112b is also disposed inside the opening 141, the channel length L100 of the transistor 100 is shorter than the length of the side of the insulating layer 110b, so sometimes controlling the channel length L100 becomes difficult. Therefore, it is preferable that the top surface shape of the opening 143 is consistent with the top surface shape of the opening 141, or that the opening 143 includes the opening 141 when viewed from above (also known as planar view).

[0155] exist FIG. 3A and FIG. 3B The width D141 of the opening 141 is indicated by a double-headed arrow with double dots. FIG. 3AAn example is shown where the top surface of opening 141 is circular. In this case, the width D141 is equivalent to the diameter of the circle, and the channel width W100 of transistor 100 is equivalent to the circumference of the circle. That is, the channel width W100 is π × D141. Thus, when the top surface of opening 141 is circular, a transistor with a smaller channel width W100 can be realized compared to other shapes.

[0156] The width D141 of the opening 141 sometimes varies in the depth direction. For example, the width D141 of the opening 141 can be the average of the diameters of the highest, lowest, and midpoints of the insulating layer 110b (or insulating layer 110) as viewed from the cross-section. Alternatively, any diameter among the diameters of the highest, lowest, and midpoints of the insulating layer 110b (or insulating layer 110) as viewed from the cross-section can be used as the diameter of the opening 141.

[0157] When forming the opening 141 using photolithography, the width D141 of the opening 141 is greater than or equal to the minimum exposure size of the exposure apparatus. For example, the width D141 can be 200 nm or more, 300 nm or more, 400 nm or more, or 500 nm or more and less than 5 μm, 4.5 μm or less, 4 μm or less, 3.5 μm or less, 3 μm or less, 2.5 μm or less, 2 μm or less, 1.5 μm or less, or 1 μm or less.

[0158] Note that this description uses the region of semiconductor layer 108 in contact with insulating layer 110b as an example to illustrate a channel formation region; however, the invention is not limited to this. The region of semiconductor layer 108 in contact with insulating layer 110a can also be used as a channel formation region. Similarly, the region in contact with insulating layer 110c can also be used as a channel formation region.

[0159] [Conductive layer 112a, conductive layer 112b, conductive layer 104] Conductive layers 112a, 112b, and 104 can have a single-layer structure or a stacked structure of two or more layers. Examples of materials that can be used for conductive layers 112a, 112b, and 104 include one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys composed of one or more of the aforementioned metals. Conductive materials with low resistance containing one or more of copper, silver, gold, and aluminum can be suitably used for conductive layers 112a, 112b, and 104. Copper or aluminum are particularly advantageous in terms of mass production and are therefore preferred.

[0160] Conductive layers 112a, 112b, and 104 can be made of conductive metal oxides (also known as oxide conductors). Examples of oxide conductors (OC) include indium oxide, zinc oxide, In-Sn oxide (ITO), In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (ITO containing silicon, also known as ITSO), zinc oxide with gallium addition, and In-Ga-Zn oxide. In particular, indium-containing oxide conductors are preferred because of their high conductivity.

[0161] Oxygen vacancies are formed in metal oxides with semiconductor properties. Adding hydrogen to these vacancies creates donor levels near the conduction band. As a result, the conductivity of the metal oxide increases, making it a conductor. Metal oxides that can become conductors are called oxide conductors.

[0162] As conductive layers 112a, 112b, and 104, a stacked structure of conductive films containing the aforementioned oxide conductor (metal oxide) and conductive films containing metals or alloys can also be used. By using conductive films containing metals or alloys, wiring resistance can be reduced.

[0163] Cu-X alloy films (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can also be used as conductive layers 112a, 112b, and 104. By using Cu-X alloy films, processing can be performed using wet etching, thereby reducing manufacturing costs.

[0164] Note that the materials used for conductive layers 112a, 112b and 104 may all be the same or at least some of them may be different.

[0165] Conductive layers 112a and 112b have regions that contact the semiconductor layer 108. When an oxide semiconductor is used as the semiconductor layer 108, there is a concern that if an easily oxidizable metal (e.g., aluminum) is used as the conductive layer 112a or 112b, an insulating oxide (e.g., aluminum oxide) forms between the conductive layer 112a or 112b and the semiconductor layer 108, hindering their conduction. Therefore, conductive layers 112a and 112b are preferably made of conductive materials that are not easily oxidized, conductive materials that maintain low resistance even when oxidized, or oxide conductors.

[0166] As conductive layers 112a and 112b, materials such as titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferably used. These materials are preferred because they are conductive materials that are not easily oxidized or maintain low resistance even when oxidized. Note that when conductive layers 112a or 112b have a stacked structure, the layer at least in contact with the semiconductor layer 108 is preferably made of a conductive material that is not easily oxidized.

[0167] The conductive layers 112a and 112b can use the aforementioned oxide conductors. Specifically, oxide conductors such as indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn oxide containing silicon, and zinc oxide with gallium added can be used.

[0168] The conductive layers 112a and 112b may also be made of nitride conductors. Examples of nitride conductors include tantalum nitride and titanium nitride.

[0169] The conductive layer 112a, conductive layer 112b and conductive layer 104 may each have a single-layer structure or a stacked structure of two or more layers.

[0170] exist FIG. 5A and FIG. 5B The diagram shows a two-layer structure of conductive layer 112a having conductive layer 112a_1 and conductive layer 112a_2 on conductive layer 112a_1.

[0171] The conductive layer 112a_2, including the region in contact with the semiconductor layer 108, is preferably made of a conductive material that is not easily oxidized, a conductive material that maintains low resistance even if oxidized, or an oxide conductor. Materials that can be used for the conductive layer 112a_2 can be found in the description of the conductive layer 112a.

[0172] The conductive layer 112a_1 does not include the region in contact with the semiconductor layer 108, therefore there are no particular limitations on the materials used. For example, the conductive layer 112a_1 is preferably made of a material with a lower resistivity than the conductive layer 112a_2. This reduces the resistance of the conductive layer 112a. For example, the conductive layer 112a_2 can be made of In-Sn-Si oxide (ITSO), and the conductive layer 112a_1 can be made of copper or tungsten.

[0173] like FIG. 5AAs shown, the end of conductive layer 112a_2 can also be aligned or substantially aligned with the end of conductive layer 112a_1. For example, conductive layer 112a can be formed by forming a first film as conductive layer 112a_1 and a second film as conductive layer 112a_2 and processing the first film and the second film. By processing the first film and the second film in the same way, manufacturing costs can be reduced.

[0174] The end of conductive layer 112a_2 may not be aligned with the end of conductive layer 112a_1. For example... FIG. 5B As shown, conductive layer 112a_2 can be provided to cover conductive layer 112a_1. Conductive layer 112a_2 has regions that contact the top and side surfaces of conductive layer 112a_1. Conductive layer 112a_2 can also be described as having a portion that protrudes beyond the end of conductive layer 112a_1. For example, conductive layer 112a_2 can be formed by forming conductive layer 112a_1 and a film on conductive layer 112a_1 that becomes conductive layer 112a_2, and then processing the film. By making conductive layer 112a_2 protrude beyond the end of conductive layer 112a_1, the step of the formed surface of the layer (e.g., insulating layer 110) on conductive layer 112a is reduced, thereby improving the coverage of the layer. This can suppress problems such as breaks or voids in the layer.

[0175] Note that in FIG. 5A and FIG. 5B The layers constituting conductive layer 112a are shown with the same or approximately the same thickness, but the invention is not limited to this. The thicknesses of the layers constituting conductive layer 112a may be different, and some layers may also have different thicknesses. For example, by making the thickness of the layer using a low-resistance material larger than that of the other layers, the resistance of conductive layer 112a can be reduced, which is therefore more preferable. Specifically, a material with lower resistance than conductive layer 112a_2 can be used as conductive layer 112a_1, and the thickness of conductive layer 112a_1 can be greater than that of conductive layer 112a_2. This reduces the resistance of conductive layer 112a.

[0176] FIG. 5C and FIG. 5D The conductive layer 112a is shown to have a three-layer structure, including a conductive layer 112a_3, a conductive layer 112a_1 on the conductive layer 112a_3, and a conductive layer 112a_2 on the conductive layer 112a_1.

[0177] like FIG. 5CAs shown, the end of conductive layer 112a_1 can contact the top surface of conductive layer 112a_3. Conductive layer 112a_2 has areas that contact the top and side surfaces of conductive layer 112a_1 and the top surface of conductive layer 112a_3. That is, it can also be said that conductive layers 112a_2 and 112a_3 have portions that protrude beyond the end of conductive layer 112a_1. Furthermore, it can also be said that the top, side, and bottom surfaces of conductive layer 112a_1 are surrounded by conductive layers 112a_2 and 112a_3. Conductive layer 112a_3 is preferably made of a material with high adhesion to the surface on which it is formed (here, the surface of substrate 102).

[0178] As described above, conductive layer 112a_1 is preferably made of a material with low resistivity. However, depending on the material, the adhesion between conductive layer 112a_1 and the surface to which it is formed (e.g., the surface of substrate 102) is low, which may lead to a decrease in the manufacturing yield of the semiconductor device. By using a material with higher adhesion to the surface to which it is formed as conductive layer 112a_3, the manufacturing yield of the semiconductor device can be improved. Note that the thickness of conductive layer 112a_3 is preferably sufficient to improve the adhesion to the surface to which it is formed, and may also be smaller than the thickness of conductive layers 112a_1 and 112a_2. By reducing the thickness of conductive layer 112a_3, manufacturing costs can be reduced.

[0179] like FIG. 5C As shown, the end of conductive layer 112a_2 can also be aligned or substantially aligned with the end of conductive layer 112a_3. For example, a first film is formed as conductive layer 112a_3, a conductive layer 112a_1 is formed on the first film, and a second film as conductive layer 112a_2 is formed on the first film and conductive layer 112a_1. Furthermore, a conductive layer 112a including conductive layer 112a_3, conductive layer 112a_1, and conductive layer 112a_2 can be formed by processing the first film and the second film. By processing the first film and the second film in the same way, manufacturing costs can be reduced.

[0180] For example, In-Sn-Si oxide (ITSO) can be appropriately used as conductive layer 112a_3, copper can be appropriately used as conductive layer 112a_1, and In-Sn-Si oxide (ITSO) can be appropriately used as conductive layer 112a_2. When a glass substrate is used as substrate 102, the adhesion between the glass substrate and the ITSO film is higher than that between the glass substrate and the copper film. In addition, by using the same material for conductive layers 112a_2 and 112a_3, the processing of conductive layers 112a_2 and 112a_3 through the same process becomes easier, thereby improving the manufacturing yield of semiconductor devices.

[0181] like FIG. 5D As shown, the end of conductive layer 112a_1 can be aligned or substantially aligned with the end of conductive layer 112a_3. For example, a first film is formed to become conductive layer 112a_3, a second film to become conductive layer 112a_1 is formed on the first film, and the first film and the second film are processed, thereby forming conductive layer 112a_3 and conductive layer 112a_1. Conductive layer 112a_2 is formed on conductive layer 112a_3 and conductive layer 112a_1, thereby forming conductive layer 112a. By processing the first film and the second film in the same process, manufacturing costs can be reduced.

[0182] Examples of conductive layer 112a having a two- or three-layer stacked structure are shown herein, but the invention is not limited to this. Conductive layer 112a may also have a four- or more-layered stacked structure.

[0183] Note that you can FIG. 5A to FIG. 5D The structure of the conductive layer 112a shown is used for other structural examples.

[0184] [Insulation layer 106] The insulating layer 106 preferably comprises one or more inorganic insulating layers. The insulating layer 106 may be made of a material that can be used for the insulating layer 110.

[0185] The insulating layer 106 has a region that contacts the semiconductor layer 108, the conductive layer 112b, the conductive layer 104, and the insulating layer 110. When a metal oxide is used for the semiconductor layer 108, the film constituting the insulating layer 106 that is at least in contact with the semiconductor layer 108 preferably uses the aforementioned oxide or oxynitride. When the insulating layer 106 has a single-layer structure, silicon oxide, silicon oxynitride, or aluminum oxide can be suitably used for the insulating layer 106.

[0186] Note that in microtransistors, leakage current sometimes increases when the gate insulating layer is thin. By using a material with a relatively high permittivity (also known as a high-k material) in the gate insulating layer, it is possible to achieve low voltage operation of the transistor while maintaining the physical thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0187] FIG. 1B The diagram shows that the insulating layer 106 is a single-layer structure, but this is not the only aspect of the invention. The insulating layer 106 may be a multilayer structure with two or more layers. FIG. 6The structure shown is a two-layer structure of insulating layer 106 having insulating layer 106a and insulating layer 106b on insulating layer 106a.

[0188] When the insulating layer 106 has a stacked structure, the insulating layer on the semiconductor layer 108 side (here, insulating layer 106a) preferably comprises an oxide or an oxynitride. Insulating layer 106a may, for example, suitably use one or more of silicon oxide, silicon oxynitride, and aluminum oxide.

[0189] Preferably, a material that is not easily permeable to other substances is used in one or more of the layers constituting the insulating layer 106. This layer can also be described as acting as a barrier film. By providing a layer that acts as a barrier film, the diffusion of metallic components in the conductive layer 104 and impurities (e.g., water and hydrogen) in the layers formed on the transistor 100 through the insulating layer 106 to the semiconductor layer 108 can be suppressed. Furthermore, the diffusion of oxygen in the semiconductor layer 108 through the insulating layer 106 to the conductive layer 104 side can be suppressed. Thus, the formation of oxygen vacancies (V0) in the semiconductor layer 108 can be suppressed. O Furthermore, the high resistance of the conductive layer 104 caused by oxidation of the conductive layer 104 due to oxygen in the semiconductor layer 108 can be suppressed. As a result, a transistor exhibiting good electrical characteristics and high reliability can be realized. Preferably, one or more of the above-mentioned nitrides and oxynitrides are used for this layer as a barrier film. Alternatively, one or more of oxides and oxynitrides can also be used as this layer, for example, aluminum oxide can be suitably used.

[0190] When the insulating layer 106 has a stacked structure, for example, silicon oxynitride can be used for insulating layer 106a and silicon nitride can be used for insulating layer 106b. Alternatively, silicon oxynitride can be used for insulating layer 106a and aluminum oxide can be used for insulating layer 106b. Alternatively, aluminum oxide can be used for insulating layer 106a and silicon oxynitride can be used for insulating layer 106b. Alternatively, aluminum oxide can be used for insulating layer 106a and silicon nitride can be used for insulating layer 106b.

[0191] An example of a two-layer stacked structure for insulating layer 106 is shown here, but the invention is not limited to this. Alternatively, insulating layer 106 may also have a stacked structure of three or more layers.

[0192] Notice, FIG. 6 The structure of the insulating layer 106 shown can also be used for other structural examples.

[0193] [Substrate 102] While there are no particular restrictions on the material of substrate 102, it must at least possess heat resistance capable of withstanding subsequent heat treatments. For example, single-crystal or polycrystalline semiconductor substrates made of silicon or silicon carbide, compound semiconductor substrates such as silicon-germanium, SOI substrates, glass substrates, quartz substrates, sapphire substrates, ceramic substrates, or organic resin substrates can be used as substrate 102. Furthermore, semiconductor elements can also be disposed on substrate 102. Note that the shapes of the semiconductor substrate and the insulating substrate can be circular or angular.

[0194] A flexible substrate can also be used as substrate 102, and transistors such as 100 can be formed directly on the flexible substrate. Alternatively, a release layer can be provided between substrate 102 and transistors such as 100. By providing a release layer, a portion or all of a semiconductor device can be fabricated on the release layer and then separated from substrate 102 and transferred to another substrate. In this case, transistors such as 100 can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0195] The following describes a semiconductor device whose structure differs from the examples described above. Note that descriptions of parts that overlap with the examples described above are sometimes omitted. Furthermore, in the accompanying drawings, parts that have the same function as those in the examples described above are depicted using the same shading lines, and sometimes no symbols are added.

[0196] [Structure Examples 1-2] FIG. 7A and FIG. 7B A cross-sectional view of a semiconductor device 10A according to one embodiment of the present invention is shown. A top view of the semiconductor device 10A can be seen in [reference needed]. FIG. 1A . FIG. 7A It is along FIG. 1A A cross-sectional view of the section between the dotted line A1 and A2 in the diagram. FIG. 7B It is along FIG. 1A The cross-sectional view of the section between the dotted and dashed lines B1-B2 in the figure.

[0197] Semiconductor device 10A includes transistor 100A and insulating layer 110. Transistor 100A is mainly distinguished from transistor 100A by having region 108D in semiconductor layer 108. FIG. 1B The transistor 100 shown is different.

[0198] FIG. 7C Show FIG. 7A An enlarged view. Semiconductor layer 108 has region 108D in a portion thereof. Region 108D contains impurity elements. Region 108D is a region with a higher concentration of impurity elements and lower resistance (low resistance region) compared to other regions of semiconductor layer 108 (e.g., channel formation regions).

[0199] existFIG. 7A to FIG. 7C The diagram shows an example where region 108D is formed in the region of semiconductor layer 108 that contacts the top surface of conductive layer 112a, located between the top surface of conductive layer 112a and the bottom surface of conductive layer 104. The region where region 108D is formed is not limited to this; for example, the entire region in contact with the top surface of conductive layer 112a may be formed with region 108D. For example, impurity elements sometimes diffuse during the supply of impurity elements to semiconductor layer 108, or due to heat applied in a process following the supply of impurity elements.

[0200] exist FIG. 7A to FIG. 7C The example shown illustrates a region 108D formed in the area of ​​the semiconductor layer 108 that contacts the top surface of the conductive layer 112b. Note that region 108D may also be provided in the area of ​​the semiconductor layer 108 that contacts the side surface of the conductive layer 112b. Furthermore, region 108D may also be provided in a portion of the area of ​​the semiconductor layer 108 that contacts the side surface of the insulating layer 110.

[0201] The first element is preferably used as an impurity element. Alternatively, hydrogen is preferably used as an impurity element in addition to the first element.

[0202] As the primary element, one or more of the following are preferred: boron, aluminum, indium, carbon, silicon, germanium, tin, phosphorus, arsenic, antimony, magnesium, calcium, titanium, copper, zinc, tungsten, molybdenum, tantalum, hafnium, cerium, and noble gases (helium, neon, argon, krypton, xenon, etc.).

[0203] The first element is not limited to the elements mentioned above, and may be one or more elements included in the first transition elements (3d transition elements, 3d transition metals), the second transition elements (4d transition elements, 4d transition metals), the third transition elements (5d transition elements, 5d transition metals), alkaline earth metals and rare earth elements.

[0204] When the first element is supplied (or added or injected) to the source and drain regions, oxygen vacancies (Vo) are generated in the source and drain regions. O Then, hydrogen enters the oxygen vacancy (V). O Defects (V) O H) generates charge carriers. This reduces the resistance of the source and drain regions. Furthermore, it reduces the resistance of semiconductor layer 108, the contact resistance between semiconductor layer 108 and conductive layer 112a, and the contact resistance between semiconductor layer 108 and conductive layer 112b. Therefore, the on-state current of transistor 100A can be increased. By increasing the on-state current, the operating voltage of transistor 100A can be reduced. This, in turn, reduces the power consumption of the semiconductor device.

[0205] When an element that readily bonds with oxygen is used as the first element, the first element abstracts oxygen from the semiconductor layer 108 and exists in an oxygen-bonded state. Additionally, oxygen vacancies (V0) are generated in the semiconductor layer 108. O When an element that becomes stable through bonding with oxygen is used as the first element, since the first element in the semiconductor layer 108 exists stably in an oxidized state, it is not easily detached by heat or other factors applied during the manufacturing process of the transistor 100A, thus maintaining a low resistance. Therefore, it is preferable to use an element whose oxide can exist in a solid state at least within the temperature range of the manufacturing process. Specifically, typical non-metallic elements other than hydrogen, typical metallic elements, and transition elements (transition metals) can be cited as preferred first elements, and boron, phosphorus, magnesium, aluminum, and silicon can be cited as particularly preferred first elements.

[0206] Therefore, it is preferable to use boron, phosphorus, magnesium, aluminum, or silicon as one of the first elements. In addition, it is particularly preferable to use boron or phosphorus as one of the first elements.

[0207] In addition to generating oxygen vacancies, hydrogen also has the ability to bond with oxygen vacancies, making it suitable as an impurity element.

[0208] In addition to the first element, hydrogen is used as an impurity element, which easily reduces the resistance of region 108D and can maintain a low resistance state.

[0209] When both the first element and hydrogen are supplied, they can be added without mass separation, thus improving productivity, which is preferred. For example, boron and hydrogen can be supplied as impurity elements by using B₂H₆ gas. Furthermore, phosphorus and hydrogen can be supplied as impurity elements, for example, by using PH₃ gas. However, the method of supplying impurity elements is not limited to these. For example, specific elements can also be added by mass separation. For example, boron can be added to region 108D using B₂H₆ gas after mass separation.

[0210] Region 108D preferably has an impurity element concentration of 1×10⁸. 19 atoms / cm 3 Above and 1×10 23 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 Above and 5×10 22 atoms / cm 3 Hereinafter, 1×10 is more preferred. 20 atoms / cm 3 Above and 1×10 22 atoms / cm 3The following regions. Furthermore, in cases where two or more impurity elements are present, at least one impurity element is preferably within the aforementioned range. Moreover, the concentration of each impurity element is more preferably within the aforementioned range.

[0211] Furthermore, impurity elements are sometimes supplied to the channel formation region in semiconductor layer 108. Alternatively, due to the effects of heat applied during the manufacturing process, a portion of the impurity elements in region 108D may diffuse into the channel formation region. The concentration of impurity elements in the channel formation region is preferably less than one-tenth of the concentration of impurity elements in region 108D, more preferably less than one-hundredth.

[0212] For example, the concentration of impurity elements in the semiconductor layer 108 (including region 108D) and the insulating layer 106 can be analyzed using analytical methods such as secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). In the case of XPS analysis, by combining XPS analysis with ion sputtering from one side of the surface or the back side, the concentration distribution in the depth direction can be determined.

[0213] When manufacturing a semiconductor device according to one aspect of the present invention, the source and drain regions of the semiconductor layer 108 are preferably more readily incorporating impurity elements compared to the channel formation region. Therefore, it is preferable to add impurity elements along a direction perpendicular to or substantially perpendicular to the top surface of the substrate 102. In this case, the amount of impurity elements added in the region of the semiconductor layer 108 inclined to the top surface of the substrate 102 is less than that in the region parallel to or substantially parallel to the top surface of the substrate 102. In other words, the amount of impurity elements added in the source and drain regions of the semiconductor layer 108 is greater than that in the channel formation region. Therefore, the resistance of the source and drain regions can be preferentially reduced.

[0214] Furthermore, when manufacturing a semiconductor device according to one aspect of the present invention, it is preferable to add impurity elements to the semiconductor layer 108 via the insulating layer 106. In this case, the thickness of the insulating layer 106 in the direction of impurity element addition is greater in the region along the side of the insulating layer 110 than in the region disposed along the top surface of the conductive layer 112a or the top surface of the conductive layer 112b. As an example, in... FIG. 7C The thickness T2 is greater than the thickness T1. Thickness T2 is greater than thickness T3. Therefore, the amount of impurity elements added to the region along the top surface of the conductive layer 112a or the top surface of the conductive layer 112b in the semiconductor layer 108 is greater than that in the region along the side surface of the insulating layer 110. This suppresses the addition of impurity elements to the channel formation region of the semiconductor layer 108, and preferentially reduces the resistance of the source and drain regions.

[0215] Here, the thickness of the insulating layer 106 (the thickness in the direction perpendicular or substantially perpendicular to the surface to which it is formed, for example, thickness T1) is preferably 1 nm or more and 200 nm or less, more preferably 1 nm or more and 150 nm or less, and even more preferably 1 nm or more and 100 nm or less. For example, when the channel length is 100 nm or more and 500 nm or less, the thickness of the insulating layer 106 is preferably 30 nm or more and 100 nm or less. For example, when the channel length is 10 nm or more and 100 nm or less, the thickness of the insulating layer 106 is preferably 1 nm or more and 50 nm or less. For example, when the channel length is 1 nm or more and 10 nm or less, the thickness of the insulating layer 106 is preferably 1 nm or more and 10 nm or less.

[0216] The greater the thickness of the insulating layer 106, the greater the difference between thickness T1 and thickness T2 can be. Therefore, the addition of impurity elements to the channel formation region of the semiconductor layer 108 can be suppressed, and the resistance of the source and drain regions can be preferentially reduced. On the other hand, in order to miniaturize transistors or manufacture transistors with extremely short channel lengths, from the viewpoint of increasing on-state current and suppressing short-channel effects, the thickness T1 is preferably small.

[0217] When impurity elements are supplied to the semiconductor layer 108 through the insulating layer 106, the insulating layer 106 may also contain impurity elements. Region 108D preferably has a higher concentration of impurity elements than the insulating layer 106, thereby further reducing the resistance of region 108D.

[0218] The insulating layer 106 preferably comprises an oxygen-containing insulating layer. When an element that readily bonds with oxygen is used as the impurity element, similar to the semiconductor layer 108, the impurity element also exists in the insulating layer 106 in a state of oxygen bonding. Because oxygen is stabilized by bonding with the impurity element, the region containing the impurity element remains in a state where oxygen is not easily detached even when heated, i.e., oxygen does not easily diffuse to other layers. Therefore, oxygen can be supplied to the channel formation region while suppressing the supply of oxygen from the insulating layer 106 to region 108D. Thus, oxygen vacancies in the channel formation region can be reduced while preventing an increase in the resistance of region 108D. As a result, a transistor with good electrical characteristics and high reliability can be realized.

[0219] For example, when boron is used as an impurity element, boron in region 108D and insulating layer 106 can exist in a state bonded to oxygen. This is confirmed by observing spectral peaks caused by B2O3 bonding in XPS analysis. Furthermore, no spectral peaks caused by boron existing alone are observed in XPS analysis, or their peak intensities are so small as to be barely visible in the background.

[0220] Note that the structure of semiconductor layer 108 shown in structural examples 1-2 can also be applied to other structural examples.

[0221] [Structure Examples 1-3] FIG. 8A and FIG. 8B A cross-sectional view of a semiconductor device 10B according to one embodiment of the present invention is shown. A top view of the semiconductor device 10B can be seen from [reference needed]. FIG. 1A . FIG. 8A It is along FIG. 1A A cross-sectional view of the section between the dotted line A1 and A2 in the diagram. FIG. 8B It is along FIG. 1A The cross-sectional view of the section between the dotted and dashed lines B1-B2 in the figure.

[0222] Semiconductor device 10B includes transistor 100 and insulating layer 110. Semiconductor device 10B differs from others in that the insulating layer 110 includes insulating layer 110d and insulating layer 110e. FIG. 1B The semiconductor device 10 shown is different.

[0223] FIG. 8C Show FIG. 8A An enlarged view is shown. The insulating layer 110 includes insulating layer 110d, insulating layer 110a on insulating layer 110d, insulating layer 110b on insulating layer 110a, insulating layer 110c on insulating layer 110b, and insulating layer 110e on insulating layer 110c. Insulating layers 110d and 110e can both use materials suitable for insulating layer 110a. Insulating layers 110d and 110e can both suitably use, for example, a silicon nitride film or a silicon oxynitride film. Note that insulating layers 110d and 110e can use the same material or different materials.

[0224] An insulating layer 110d is disposed between the substrate 102 and the conductive layer 112a. The insulating layer 110d is disposed such that it covers the conductive layer 112a. The insulating layer 110d has regions that contact the top and side surfaces of the conductive layer 112a, the top surface of the substrate 102, and the side surfaces of the semiconductor layer 108.

[0225] An insulating layer 110e is disposed between the conductive layer 112b and the insulating layer 110c. The insulating layer 110e has a region that contacts the top surface of the insulating layer 110c, the bottom surface of the conductive layer 112b, the bottom surface of the insulating layer 106, and the side surface of the semiconductor layer 108.

[0226] More preferably, insulating layers 110d and 110e use materials that release impurities (e.g., water and hydrogen) that reduce the resistance of semiconductor layer 108. Thus, the region of semiconductor layer 108 in contact with insulating layer 110d can be used as a low-resistance region. Semiconductor layer 108 may have a structure including a low-resistance region between the region in contact with conductive layer 112a (one of the source and drain regions) and the channel formation region. Similarly, when the impurity-releasing material is used for insulating layer 110e, the region of semiconductor layer 108 in contact with insulating layer 110e can be a low-resistance region. Semiconductor layer 108 may have a structure including a low-resistance region between the region in contact with conductive layer 112b (the other of the source and drain regions) and the channel formation region. The low-resistance region can be used as a buffer region to mitigate the drain electric field. These low-resistance regions can also be used as source or drain regions.

[0227] By providing a low-resistance region between the drain region and the channel formation region, a high electric field is less likely to be generated near the drain region, thus suppressing the generation of hot carriers and inhibiting transistor degradation. For example, when conductive layer 112a is used as the drain electrode and conductive layer 112b is used as the source electrode, by using the region of semiconductor layer 108 in contact with insulating layer 110d as a low-resistance region, a high electric field is less likely to be generated near the drain region, suppressing the generation of hot carriers and thus inhibiting transistor degradation. When conductive layer 112a is used as the source electrode and conductive layer 112b is used as the drain electrode, by using the region of semiconductor layer 108 in contact with insulating layer 110e as a low-resistance region, a high electric field is less likely to be generated near the drain region, suppressing the generation of hot carriers and thus inhibiting transistor degradation.

[0228] When the region of the semiconductor layer 108 that contacts the insulating layer 110d is used as a source region or a drain region, the distance from the source region to the gate electrode and the distance from the drain region to the gate electrode of the semiconductor layer 108 can be further made uniform. As a result, the electric field applied to the gate electrode in the channel formation region can be further made uniform.

[0229] The insulating layer 110a preferably releases minimal impurities and is not easily permeable by impurities. This suppresses the diffusion of impurities through the insulating layers 110a and 110b into the channel formation region of the semiconductor layer 108. Similarly, the insulating layer 110c preferably releases minimal impurities and is not easily permeable by impurities. This suppresses the diffusion of impurities through the insulating layers 110c and 110b into the channel formation region of the semiconductor layer 108. This results in a transistor exhibiting excellent electrical characteristics and high reliability.

[0230] When a metal oxide is used as the semiconductor layer 108, the impurities released from the insulating layers 110d and 110e more preferably include hydrogen. Hydrogen reacts with the oxygen atom bonded to the metal oxide to form water, thereby creating oxygen vacancies (V0). O Furthermore, hydrogen enters oxygen vacancies (V... O ) defects (V) O H) is used as a donor to generate electrons as charge carriers. As a result, the charge carrier concentration in the regions of semiconductor layer 108 that are in contact with insulating layer 110d and insulating layer 110e is increased, which can reduce resistance.

[0231] The insulating layer 110d preferably has a region with a higher hydrogen content than the insulating layer 110a. The hydrogen content of the insulating layer 110 can be analyzed, for example, using secondary ion mass spectrometry (SIMS).

[0232] The amount of hydrogen released can be adjusted by differentiating the deposition conditions of insulating layer 110d from those of insulating layer 110a. Specifically, this can be achieved by differentiating one or more of the following factors between insulating layer 110d and insulating layer 110a: deposition power (deposition power density), deposition pressure, type of deposition gas, deposition gas flow rate ratio, deposition temperature, and distance between the substrate and the electrode. For example, by making the deposition power density of insulating layer 110d lower than that of insulating layer 110a, the hydrogen content in insulating layer 110d can be higher than that in insulating layer 110a. Therefore, the amount of hydrogen released from insulating layer 110d itself can be increased by increasing the heat applied to insulating layer 110d.

[0233] The hydrogen content in the deposition gas used to form the insulating layer 110d is preferably higher than that in the deposition gas used to form the insulating layer 110a. Specifically, when forming silicon nitride or silicon oxynitride films in both insulating layers 110d and 110a using PECVD, the ratio of the overall ammonia flow rate (hereinafter also referred to as the ammonia flow rate ratio) of the deposition gas used to form the insulating layer 110d is higher than that of the deposition gas used to form the insulating layer 110a. By forming the insulating layer 110d under conditions of a high ammonia flow rate ratio, the hydrogen content in the insulating layer 110d can be increased. Furthermore, the amount of hydrogen released from the insulating layer 110d itself can be increased by applying heat to the insulating layer 110d.

[0234] The film density of insulating layer 110a is preferably higher than that of insulating layer 110d. This suppresses the diffusion of hydrogen from insulating layer 110d through insulating layers 110a and 110b into the channel formation region of semiconductor layer 108. The film density can be evaluated, for example, using Rutherford backscattering (RBS) or X-ray reflectance measurement (XRR). Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscopy (TEM) images. In TEM observation, a higher film density results in a darker (deeper) transmission electron (TE) image, while a lower film density results in a lighter (brighter) TE image. Therefore, in TE images, insulating layer 110a sometimes appears darker (darker) than insulating layer 110d. Note that even if insulating layers 110d and 110a use the same material, their film densities differ, and these boundaries can sometimes be observed in cross-sectional TEM images due to differences in contrast.

[0235] The insulating layer 110e preferably has a region with a higher hydrogen content than the insulating layer 110c. The film density of the insulating layer 110c is more preferably higher than that of the insulating layer 110e. For information on the insulating layers 110c and 110e, please refer to the description of the insulating layers 110a and 110d.

[0236] Note that an example of a five-layer stacked structure of insulating layer 110 is shown here, but the invention is not limited to this. Insulating layer 110 may have a two-, three-, four-, or six-layer stacked structure. Furthermore, insulating layer 110 may have a single-layer structure.

[0237] like FIG. 9A and FIG. 9B As shown, an insulating layer 110f may be included between insulating layer 110c and insulating layer 110e.

[0238] FIG. 9C Show FIG. 9A An enlarged view is shown. The insulating layer 110 includes an insulating layer 110d, an insulating layer 110a on the insulating layer 110d, an insulating layer 110b on the insulating layer 110a, an insulating layer 110c on the insulating layer 110b, an insulating layer 110f on the insulating layer 110c, and an insulating layer 110e on the insulating layer 110f. The insulating layer 110f can use a material suitable for the insulating layer 110a. For example, the insulating layer 110f can suitably use a silicon nitride film or a silicon oxynitride film.

[0239] The insulating layer 110f has a region that contacts the side of the semiconductor layer 108.

[0240] The insulating layer 110f is more preferably made of a material that releases impurities (e.g., water and hydrogen) that reduce the resistance of the semiconductor layer 108. Furthermore, the amount of impurities released from the insulating layer 110f is preferably less than the amount released from the insulating layer 110e. Thus, a structure can be achieved where the resistance of the region of the semiconductor layer 108 in contact with the insulating layer 110f is lower than that of the channel formation region and higher than that of the region of the semiconductor layer 108 in contact with the insulating layer 110e. Therefore, a transistor with a high drain breakdown voltage can be realized.

[0241] The insulating layer 110e preferably has a region with a higher hydrogen content than the insulating layer 110f. The amount of hydrogen released can be adjusted by making the deposition conditions of the insulating layer 110e different from those of the insulating layer 110f. For information on the insulating layers 110e and 110f, please refer to the description of the insulating layers 110d and 110a.

[0242] Note that the structure of insulating layer 110 shown in structural examples 1-3 can also be used in other structural examples.

[0243] [Structure Examples 1-4] FIG. 10A and FIG. 10B This is a cross-sectional view of a semiconductor device 10C according to one embodiment of the present invention. A top view of the semiconductor device 10C can be seen in [reference needed]. FIG. 1A . FIG. 10A It is along FIG. 1A A cross-sectional view of the section between the dotted line A1 and A2 in the diagram. FIG. 10B It is along FIG. 1A The cross-sectional view of the section between the dotted and dashed lines B1-B2 in the figure.

[0244] Semiconductor device 10C includes transistor 100, insulating layer 110, and insulating layer 109. Semiconductor device 10C differs from others primarily in that it includes insulating layer 109 between substrate 102 and conductive layer 112a. FIG. 1B The semiconductor device 10 shown is different.

[0245] An insulating layer 109 is disposed on a substrate 102, a conductive layer 112a is disposed on the insulating layer 109, and an insulating layer 110 is disposed on the conductive layer 112a. The insulating layer 109 has a region that contacts the bottom surface of the conductive layer 112a and the bottom surface of the insulating layer 110. The conductive layer 112a contacts the insulating layers 109 and 110 and has a region that is held between them. The insulating layer 110 has a region that contacts the top and side surfaces of the conductive layer 112a, the top surface of the insulating layer 109, the side surface of the semiconductor layer 108, the bottom surface of the conductive layer 112b, and the bottom surface of the insulating layer 106.

[0246] The insulating layer 109 is preferably made of a material that releases impurities (e.g., water and hydrogen) that reduce the resistance of the semiconductor layer 108. The insulating layer 109 can be made of a material that can be used for insulating layers 110d and 110e. For example, silicon nitride or silicon oxynitride can be suitably used for the insulating layer 109.

[0247] Impurities released from the insulating layer 109 diffuse into the region of the conductive layer 112a that contacts the insulating layer 109. Additionally, impurities diffused into the conductive layer 112a diffuse into the region of the semiconductor layer 108 that contacts the conductive layer 112a. This reduces the resistance of one of the source or drain regions in the region of the semiconductor layer 108 that contacts the conductive layer 112a. Therefore, transistors with high on-state current can be realized, enabling high-speed semiconductor devices.

[0248] When a metal oxide is used in the semiconductor layer 108, the impurities released from the insulating layer 109 more preferably contain hydrogen. As the hydrogen diffuses from the insulating layer 109 through the conductive layer 112a to the semiconductor layer 108, the carrier concentration in the region of the semiconductor layer 108 in contact with the conductive layer 112a increases, which can reduce the resistance of one of the source and drain regions.

[0249] The insulating layer 109 is more preferably made of a material that releases impurities that reduce the resistance of the conductive layer 112a. This reduces the resistance of the conductive layer 112a. For example, when a metal oxide is used as the conductive layer 112a, the impurity more preferably contains hydrogen. This increases the carrier concentration in the conductive layer 112a, thereby reducing resistance. Furthermore, the conductive layer 112a can be used for wiring, enabling a semiconductor device with low wiring resistance. Note that the impurity reducing the resistance of the conductive layer 112a can be the same as or different from the impurity reducing the resistance of the semiconductor layer 108.

[0250] The material that can be used for the conductive layer 112a is the material described above. Furthermore, the conductive layer 112a is more preferably designed to allow impurities to pass through easily. The conductive layer 112a is also more preferably designed to resist the adsorption of impurities.

[0251] The insulating layer 110a has a region that contacts the top surface of the insulating layer 109 and the top and side surfaces of the conductive layer 112a. This can suppress the diffusion of impurities in the insulating layer 109 and the conductive layer 112a through the insulating layer 110b into the channel formation region of the semiconductor layer 108.

[0252] The insulating layer 109 preferably has a region with a higher hydrogen content than the insulating layer 110a. The film density of the insulating layer 110a is preferably higher than that of the insulating layer 109. Regarding the insulating layer 109, refer to the descriptions of the insulating layers 110d and 110e.

[0253] Note that sometimes impurities released from insulating layer 109 diffuse into the channel formation region via one of the source and drain regions of conductive layer 112a and semiconductor layer 108. However, at least the region of semiconductor layer 108 in contact with insulating layer 110b is supplied with oxygen from insulating layer 110b, thus reducing oxygen vacancies (V) in the channel formation region. O ) and V O H. Therefore, threshold voltage drift can be suppressed, thereby enabling transistors with low cutoff current and high on-state current. This allows for the creation of semiconductor devices that simultaneously achieve low power consumption and high performance.

[0254] FIG. 10A Examples showing the insulating layer 110 having a three-layer structure of insulating layer 110a, insulating layer 110b, and insulating layer 110c are provided, but the present invention is not limited to this. For example, as FIG. 11A and FIG. 11B As shown, insulating layer 110 may include insulating layers 110a, 110b, 110c, and 110e. Insulating layer 110e is more preferably made of a material that releases impurities that reduce the resistance of conductive layer 112b. This reduces the resistance of conductive layer 112b. For example, when a metal oxide is used in conductive layer 112b, the impurity more preferably contains hydrogen. This increases the carrier concentration in conductive layer 112b, reducing resistance. Conductive layer 112b can be used for wiring, enabling semiconductor devices with low wiring resistance. Furthermore, insulating layer 110 may also include insulating layer 110d. For example, insulating layer 110 may include insulating layers 110a, 110b, 110c, 110d, and 110e.

[0255] FIG. 12A As shown, the insulating layer 110 can contact the side surface of the insulating layer 109. Furthermore, the end of the insulating layer 109 can be aligned or substantially aligned with the end of the conductive layer 112a. For example, the insulating layer 109 and the conductive layer 112a can be formed by forming an insulating film that becomes the insulating layer 109 and a conductive film that becomes the conductive layer 112a, and then processing them. Processing the insulating film and the conductive film using the same steps can reduce manufacturing costs.

[0256] The end of the insulating layer 109 may not be aligned with the end of the conductive layer 112a. For example... FIG. 12B As shown, the insulating layer 109 may also have a portion that protrudes beyond the end of the conductive layer 112a. The end of the conductive layer 112a contacts the top surface of the insulating layer 109. By adopting this structure, the steps of the surfaces on which the layers (e.g., insulating layer 110) are formed on the conductive layer 112a and the insulating layer 109 are reduced, thereby improving the coverage of the layers. As a result, problems such as breaks or voids in the layers can be suppressed.

[0257] like FIG. 13A and FIG. 13B As shown, an insulating layer 110f may be included between insulating layer 110c and insulating layer 110e. FIG. 13A and FIG. 13B The insulating layer 110 shown includes insulating layer 110a, insulating layer 110b on insulating layer 110a, insulating layer 110c on insulating layer 110b, insulating layer 110f on insulating layer 110c, and insulating layer 110e on insulating layer 110f. The above description is available, so a detailed description of insulating layer 110f is omitted.

[0258] Note that the structure of insulating layer 109 shown in structural examples 1-4 can also be applied to other structural examples.

[0259] [Structure Examples 1-5] FIG. 14A and FIG. 14B A cross-sectional view of a semiconductor device 10D according to one embodiment of the present invention is shown. A top view of the semiconductor device 10D can be seen from [reference needed]. FIG. 1A . FIG. 14A It is along FIG. 1A A cross-sectional view of the section between the dotted line A1 and A2 in the diagram. FIG. 14B It is along FIG. 1A The cross-sectional view of the section between the dotted and dashed lines B1-B2 in the figure.

[0260] Semiconductor device 10D includes transistor 100B and insulating layer 110. Transistor 100B differs from others primarily in that the semiconductor layer 108 has a stacked structure. FIG. 1B The transistor 100 shown is different.

[0261] FIG. 14A and FIG. 14B The semiconductor layer 108 is shown to have a three-layer structure, including semiconductor layer 108a, semiconductor layer 108b on semiconductor layer 108a, and semiconductor layer 108c on semiconductor layer 108b.

[0262] Semiconductor layers 108a, 108b, and 108c can each be made of materials exemplified as semiconductor layer 108. Semiconductor layers 108a, 108b, and 108c preferably all contain metal oxides exhibiting semiconductor properties.

[0263] The band gaps of the first metal oxide contained in semiconductor layer 108a, the second metal oxide contained in semiconductor layer 108b, and the third metal oxide contained in semiconductor layer 108c are preferably 2.0 eV or more, and more preferably 2.5 eV or more.

[0264] The band gap of the first metal oxide is preferably larger than that of the second metal oxide. The band gap of the third metal oxide is preferably larger than that of the second metal oxide. Semiconductor layer 108b is sandwiched between semiconductor layer 108a and semiconductor layer 108c, both of which have band gaps larger than that of semiconductor layer 108b, and can employ an embedded channel structure. Thus, in semiconductor layer 108, the main current path is through semiconductor layer 108b.

[0265] For example, the difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, more preferably 0.3 eV or more, and more preferably 0.5 eV or more. The difference between the band gap of the third metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, more preferably 0.3 eV or more, and more preferably 0.5 eV or more.

[0266] The conduction band bottom of the first metal oxide is preferably closer to the vacuum level than the conduction band bottom of the second metal oxide. The conduction band bottom of the third metal oxide is preferably closer to the vacuum level than the conduction band bottom of the second metal oxide. In other words, the electron affinity of the first metal oxide is preferably less than the electron affinity of the second metal oxide. The electron affinity of the third metal oxide is preferably less than the electron affinity of the second metal oxide.

[0267] The band gaps of the first, second, and third metal oxides can be evaluated using optical methods such as spectrophotometry, spectral ellipsography, photoluminescence, X-ray photoelectron spectroscopy (XPS or ESCA), or X-ray absorption fine structure (XAFS). Alternatively, a combination of these methods can be used. The electron affinity or conduction band bottom can be calculated from the ionization potential, which is the difference between the vacuum level and the valence band top energy, and the band gap. The ionization potential can be evaluated, for example, using ultraviolet photoelectron spectroscopy (UPS).

[0268] Here, trap levels caused by impurities or defects may form at and near the interface between the insulating layer 110 and the semiconductor layer 108. Examples of such impurities include residual components of the etchant or etching gas used when forming the opening 141, and components of the conductive layers 112a and 112b that adhere to the side of the insulating layer 110 when forming the opening 141. By providing the semiconductor layer 108a between the semiconductor layer 108b and the insulating layer 110, the semiconductor layer 108b can be kept away from the trap levels.

[0269] Sometimes, the interface between the insulating layer 106 and the semiconductor layer 108, and its vicinity, is damaged during the formation of the insulating layer 106. This can potentially lead to the formation of trap levels at or near the interface between the insulating layer 106 and the semiconductor layer 108. By placing a semiconductor layer 108c between the semiconductor layer 108b and the insulating layer 106, the semiconductor layer 108b can be moved away from these trap levels.

[0270] By sandwiching semiconductor layer 108b, which serves as the main current path of semiconductor layer 108, between semiconductor layers 108a and 108c, the trap levels at and near the interface of semiconductor layer 108b can be reduced. This allows for the realization of transistors with high on-state current and high reliability. Consequently, semiconductor devices that simultaneously achieve high-speed operation and high reliability can be manufactured.

[0271] The composition of the first metal oxide is preferably different from that of the second metal oxide. The composition of the third metal oxide is also preferably different from that of the second metal oxide. By changing the composition of the metal oxides, the band gap can be adjusted. Specifically, the content of element M in both the first and third metal oxides is preferably higher than the content of element M in the second metal oxide. This allows the band gaps of both the first and third metal oxides to be larger than that of the second metal oxide.

[0272] The indium content in the second metal oxide is preferably higher than that in the first metal oxide and the third metal oxide. Therefore, a transistor with a large on-state current can be realized.

[0273] For example, when the first and second metal oxides are In-M-Zn oxides, the first metal oxide may have an In:M:Zn ratio of 1:1:1 or similar, and the second metal oxide may have an In:M:Zn ratio of 40:1:10 or similar. Alternatively, the first metal oxide may have an In:M:Zn ratio of 1:1:1 or similar, and the second metal oxide may have an In:M:Zn ratio of 10:1:10 or similar. Alternatively, the first metal oxide may have an In:M:Zn ratio of 1:1:1 or similar, and the second metal oxide may have an In:M:Zn ratio of 10:1:40 or similar. As element M, one or more of gallium, aluminum, and tin are particularly preferred. Furthermore, element M in the first metal oxide, the second metal oxide, and the third metal oxide may be the same, or some or all of them may be different. Furthermore, when one or more of the first metal oxide, the second metal oxide, and the third metal oxide contain multiple elements M, the elements of the element M may be the same as those of the elements M in the other metal oxides, or some or all of them may be different.

[0274] More specifically, the first metal oxide may suitably use an In:Ga:Zn ratio of 1:1:1 or similar, the second metal oxide may suitably use an In:Sn:Zn ratio of 40:1:10 or similar, and the third metal oxide may suitably use an In:Ga:Zn ratio of 1:1:1 or similar. Alternatively, the first metal oxide may suitably use an In:Ga:Zn ratio of 1:1:1 or similar, the second metal oxide may suitably use an In:Sn:Zn ratio of 10:1:10 or similar, and the third metal oxide may suitably use an In:Ga:Zn ratio of 1:1:1 or similar. Alternatively, the first metal oxide may appropriately use an In:Ga:Zn ratio of 1:1:1 or similar, the second metal oxide may appropriately use an In:Sn:Zn ratio of 10:1:40 or similar, and the third metal oxide may appropriately use an In:Ga:Zn ratio of 1:1:1 or similar.

[0275] The second metal oxide may not contain element M. For example, the second metal oxide may be an In-Zn oxide, and the first and third metal oxides may be In-M-Zn oxides. Specifically, the second metal oxide may be an In-Zn oxide, and the first and third metal oxides may be In-M-Zn oxides. More specifically, the first metal oxide may suitably use an In:Ga:Zn ratio of 1:1:1 or similar, the second metal oxide may suitably use an In:Zn ratio of 4:1 or similar, and the third metal oxide may suitably use an In:Ga:Zn ratio of 1:1:1 or similar. Alternatively, the first metal oxide may suitably use an In:Ga:Zn ratio of 1:1:1 or similar, the second metal oxide may suitably use an In:Zn ratio of 1:1:1 or similar, and the third metal oxide may suitably use an In:Ga:Zn ratio of 1:1:1 or similar. Alternatively, the first metal oxide may appropriately use an In:Ga:Zn ratio of 1:1:1 or similar, the second metal oxide may appropriately use an In:Zn ratio of 1:4 or similar, and the third metal oxide may appropriately use an In:Ga:Zn ratio of 1:1:1 or similar.

[0276] FIG. 15 An enlarged view of the side surface and surrounding area of ​​the insulating layer 110 is shown. FIG. 15 In the diagram, solid double arrows indicate the thicknesses T108a, T108b, and T108c of semiconductor layer 108a, semiconductor layer 108b, and semiconductor layer 108c, respectively. Here, the thickness of semiconductor layer 108 is defined as the shortest distance between insulating layer 110 and insulating layer 106 when viewed in cross-section. Specifically, the thicknesses of each layer of semiconductor layer 108 are shown at the midpoint between the height of the top surface and the height of the bottom surface of insulating layer 110.

[0277] By increasing the thickness T108b of the semiconductor layer 108b in the main current path, a transistor with a large on-state current can be realized. The thickness T108b is preferably greater than the thicknesses T108a and T108c. However, when the thickness T108b is too large, the oxygen vacancies (V0) in the semiconductor layer 108b... O ) and V O The amount of H may be greater than the oxygen vacancies repaired by oxygen supplied from the insulation layer 110 (V O ) and V OThe amount of H. The thickness T108b of the semiconductor layer 108b is preferably 1 nm or more and 50 nm or less, more preferably 3 nm or more and 30 nm or less, more preferably 3 nm or more and 20 nm or less, more preferably 5 nm or more and 20 nm or less, and more preferably 5 nm or more and 15 nm or less.

[0278] The thickness T108c of semiconductor layer 108c is preferably greater than the thickness T108a of semiconductor layer 108a. By increasing the thickness T108c, the semiconductor layer 108b can be moved away from trap energy levels that may form at and near the interface between insulating layer 106 and semiconductor layer 108. In addition, damage to semiconductor layer 108b during the formation of insulating layer 106 can be suppressed. When the thickness T108c is too large, the distance between the conductive layer 104, which is used as the gate electrode, and semiconductor layer 108b sometimes becomes longer, resulting in a smaller on-state current. The thickness T108c of semiconductor layer 108c is preferably 1 nm or more and 30 nm or less, more preferably 1 nm or more and 20 nm or less, more preferably 1 nm or more and 10 nm or less, and more preferably 2 nm or more and 10 nm or less.

[0279] Here, oxygen in the insulating layer 110 is supplied to the semiconductor layer 108b via the semiconductor layer 108a. Therefore, it is preferable that the semiconductor layer 108a facilitates oxygen permeation. By making the thickness T108a of the semiconductor layer 108a smaller than the thickness T108c of the semiconductor layer 108c, oxygen in the insulating layer 110 can be efficiently supplied to the semiconductor layer 108b. This reduces the number of oxygen vacancies (V0) in the semiconductor layer 108b, which serves as the main current path. O ) and V O H. When the thickness T108a is too small, the distance between the interface between the insulating layer 110 and the semiconductor layer 108, and the trap energy level near the interface, and the semiconductor layer 108b, which serves as the main current path, becomes shorter, resulting in a smaller on-state current. Furthermore, reliability may sometimes decrease. The thickness T108a of the semiconductor layer 108a is preferably 0.1 nm or more and 10 nm or less, more preferably 0.3 nm or more and 5 nm or less, more preferably 0.5 nm or more and 5 nm or less, and even more preferably 0.5 nm or more and 3 nm or less.

[0280] Semiconductor layers 108a, 108b, and 108c are preferably crystalline. By making semiconductor layer 108a crystalline, the crystallinity of semiconductor layer 108b formed thereon can sometimes be improved. Similarly, by making semiconductor layer 108b crystalline, the crystallinity of semiconductor layer 108c formed thereon can sometimes be improved.

[0281] The band gap of the first metal oxide can be different from that of the third metal oxide.

[0282] The band gap of the third metal oxide is more preferably larger than that of the first metal oxide. By using a material with a large band gap in the semiconductor layer 108c located on the side of the conductive layer 104 used as the gate electrode, the generation and induction of charge carriers in the semiconductor layer 108c and at the interface between the semiconductor layer 108c and the gate insulating layer (here, the insulating layer 106) can be suppressed, thereby enabling a transistor with high reliability. For example, by suppressing the generation and induction of charge carriers in the semiconductor layer 108c and at its interface due to light incident on the transistor, changes in the electrical characteristics of the transistor relative to light can be suppressed.

[0283] Semiconductor layer 108a has a region that contacts conductive layers 112a and 112b, which serve as source and drain electrodes, respectively. By making the band gap of the first metal oxide contained in semiconductor layer 108a smaller than the band gap of the third metal oxide, the contact resistance between semiconductor layer 108a and conductive layer 112a and the contact resistance between semiconductor layer 108a and conductive layer 112b can be reduced. Therefore, a transistor with a large on-state current can be realized.

[0284] The difference between the band gap of the first metal oxide and the band gap of the third metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more. The conduction band bottom of the third metal oxide is preferably closer to the vacuum level than the conduction band bottom of the first metal oxide. In other words, the electron affinity of the third metal oxide is preferably less than the electron affinity of the first metal oxide.

[0285] Furthermore, the content of element M in the third metal oxide is preferably higher than that in the first metal oxide. This allows the band gap of the third metal oxide to be larger than that of the first metal oxide.

[0286] For example, when the first, second, and third metal oxides use In-M-Zn oxides, the first metal oxide may appropriately use an In:M:Zn ratio of 1:1:1 or similar, the second metal oxide may appropriately use an In:M:Zn ratio of 40:1:10 or similar, and the third metal oxide may appropriately use an In:M:Zn ratio of 1:3:4 or similar. Alternatively, the first metal oxide may appropriately use an In:M:Zn ratio of 1:1:1 or similar, the second metal oxide may appropriately use an In:M:Zn ratio of 10:1:10 or similar, and the third metal oxide may appropriately use an In:M:Zn ratio of 1:3:4 or similar.

[0287] More specifically, the first metal oxide may suitably use an In:Ga:Zn ratio of 1:1:1 or similar, the second metal oxide may suitably use an In:Sn:Zn ratio of 40:1:10 or similar, and the third metal oxide may suitably use an In:Ga:Zn ratio of 1:3:4 or similar. Alternatively, the first metal oxide may suitably use an In:Ga:Zn ratio of 1:1:1 or similar, the second metal oxide may suitably use an In:Sn:Zn ratio of 10:1:10 or similar, and the third metal oxide may suitably use an In:Ga:Zn ratio of 1:3:4 or similar.

[0288] The second metal oxide may also not contain element M. For example, the second metal oxide may be an In-Zn oxide, and the first and third metal oxides may be In-M-Zn oxides. Specifically, the first metal oxide may suitably use an In:Ga:Zn ratio of 1:1:1 or similar, the second metal oxide may suitably use an In:Zn ratio of 4:1 or similar, and the third metal oxide may suitably use an In:Ga:Zn ratio of 1:3:4 or similar. Alternatively, the first metal oxide may suitably use an In:Ga:Zn ratio of 1:1:1 or similar, the second metal oxide may suitably use an In:Zn ratio of 1:1 or similar, and the third metal oxide may suitably use an In:Ga:Zn ratio of 1:3:4 or similar.

[0289] FIG. 14A Examples of semiconductor layer 108 having a three-layer structure of semiconductor layer 108a, semiconductor layer 108b, and semiconductor layer 108c are given, but one aspect of the invention is not limited to this. For example, a structure may be provided that does not include one or both of semiconductor layer 108a and semiconductor layer 108c. Specifically, as... FIG. 16A As shown, semiconductor layer 108 can have a two-layer structure consisting of semiconductor layer 108a and semiconductor layer 108b. Alternatively, as... FIG. 16B As shown, semiconductor layer 108 can have a two-layer structure of semiconductor layer 108b and semiconductor layer 108c. Alternatively, semiconductor layer 108 can also have a stacked structure of four or more layers.

[0290] Note that the structure of semiconductor layer 108 shown in structural examples 1-5 can also be applied to other structural examples.

[0291] [Structure Examples 1-6] FIG. 17A and FIG. 17B A cross-sectional view of a semiconductor device 10E according to one embodiment of the present invention is shown. A top view of the semiconductor device 10E can be seen by referring to... FIG. 1A . FIG. 17A It is along FIG. 1A A cross-sectional view of the section between the dotted line A1 and A2 in the diagram. FIG. 17B It is along FIG. 1A The cross-sectional view of the section between the dotted and dashed lines B1-B2 in the figure.

[0292] Semiconductor device 10E includes transistor 100C and insulating layer 110. The angle formed between the side surface of the conductive layer 112b on the side of opening 143 and the surface on which the conductive layer 112b is formed (here, the top surface of the insulating layer 110) differs from the angle formed between the side surface of the insulating layer 110 on the side of opening 141 and the surface on which the insulating layer 110 is formed (here, the top surface of the conductive layer 112a). This difference is primarily due to the fact that... FIG. 1B The transistor 100 shown is different.

[0293] FIG. 17C Show FIG. 17A An enlarged image. For example... FIG. 17C As shown, when viewed in cross-section, the angle θ112b between the side of the conductive layer 112b on the side of the opening 143 and the surface on which the conductive layer 112b is formed (here, the top surface of the insulating layer 110) is preferably smaller than the angle θ110b. By making the angle θ112b smaller than the angle θ110b, the step of the surface on which the layer (e.g., the semiconductor layer 108) is formed on the conductive layer 112b and the insulating layer 110 is reduced, thereby improving the coverage of the layer. This suppresses defects such as breaks or voids in the layer.

[0294] For example, by using different methods to form openings 141 and 143, the angle θ112b of the conductive layer 112b can be different from the angle θ110b of the insulating layer 110. For example, by forming opening 143 using a wet etching method and opening 141 using a dry etching method, the angle θ112b can be smaller than the angle θ110b.

[0295] Note that the structures of insulating layer 110 and conductive layer 112b shown in structural examples 1-6 can also be applied to other structural examples.

[0296] [Structure Examples 1-7] FIG. 18A A top view of a semiconductor device 10F according to one aspect of the present invention is shown. FIG. 18B Show along FIG. 18A A cross-sectional view of the section between the dotted line A1 and A2 in the diagram. FIG. 18CThis shows a cross-sectional view along the dashed line B1-B2.

[0297] Semiconductor device 10F includes transistor 100D and insulating layer 110. The main difference between transistor 100D and its counterpart lies in the top surface shape of opening 141 being different from that of opening 143. FIG. 1B The transistor 100 shown is different.

[0298] like FIG. 18A As shown, in a top view, opening 143 preferably includes opening 141. Furthermore, as... FIG. 18B and FIG. 18C As shown, when viewed in cross-section, the insulating layer 110 preferably has a region on the side of the opening 141 that protrudes beyond the conductive layer 112b. By employing this structure, the step of the formed surface of the layer (e.g., semiconductor layer 108) on the conductive layer 112b and the insulating layer 110 is reduced, thereby improving the coverage of the layer. As a result, defects such as breaks or voids in the layer can be suppressed.

[0299] Semiconductor layer 108 includes regions that contact the top and side surfaces of conductive layer 112b, the top and side surfaces of insulating layer 110, and the top surface of conductive layer 112a. Semiconductor layer 108 has a shape along the top and side surfaces of conductive layer 112b, the top and side surfaces of insulating layer 110, and the top surface of conductive layer 112a.

[0300] Note that when the top surface of openings 141 and 143 is circular, openings 141 and 143 may or may not be concentric circles.

[0301] Note that the structures of openings 141 and 143 shown in structural examples 1-7 can also be applied to other structural examples.

[0302] [Structure Examples 1-8] FIG. 19A A top view of a semiconductor device 10G according to one aspect of the present invention is shown. FIG. 19B Show along FIG. 19A A cross-sectional view of the section between the dotted line A1 and A2 in the diagram. FIG. 19C This shows a cross-sectional view along the dashed line B1-B2.

[0303] Semiconductor device 10G includes transistor 100E and insulating layer 110. Transistor 100E differs from others in that it includes conductive layer 103 and insulating layer 107. FIG. 1B The transistor 100 shown is different.

[0304] like FIG. 19B and FIG. 19CAs shown, transistor 100E includes a conductive layer 103 and an insulating layer 107 between the conductive layer 112a and the insulating layer 110.

[0305] The insulating layer 107 is located on the conductive layer 112a. The insulating layer 107 is provided in such a way that it covers the top surface and the side surface of the conductive layer 112a.

[0306] The conductive layer 103 is located on the insulating layer 107. The conductive layer 112a and the conductive layer 103 are electrically insulated from each other by the insulating layer 107. An opening 148 is provided in the region of the conductive layer 103 that overlaps with the conductive layer 112a, leading to the insulating layer 107.

[0307] An insulating layer 110 is disposed on an insulating layer 107 and a conductive layer 103. The insulating layer 110 is disposed such that it covers the top and side surfaces of the conductive layer 103 and the top surface of the insulating layer 107. An opening 141 is provided in the insulating layer 110 and the insulating layer 107 to reach the conductive layer 112a.

[0308] An insulating layer 110a is located on the insulating layer 107 and the conductive layer 103. The insulating layer 110a is provided such that it covers the top and side surfaces of the conductive layer 103. In addition, the insulating layer 110a is provided such that it covers a portion of the opening 148. The insulating layer 110a is in contact with the insulating layer 107 in the opening 148.

[0309] There are no particular restrictions on the shape of the top surface of opening 148. The top surface shape of opening 148 can be any shape that can be used for openings 141 and 143. For example... FIG. 19A As shown, the top surface shapes of openings 141, 143, and 148 are preferably circular. By making the top surface shape of the openings circular, the processing accuracy during opening formation can be improved, thus enabling the formation of fine openings.

[0310] In this specification, the top surface shape of the opening 148 refers to the shape of the top end or the bottom end of the opening 148 side of the conductive layer 103.

[0311] When the top surfaces of openings 141 and 148 are circular, openings 141 and 148 are preferably concentric circles. Therefore, the shortest distance between the semiconductor layer 108 and the conductive layer 103, viewed in cross-section, can be the same on both the left and right sides of opening 141. However, openings 141 and 148 are sometimes not concentric circles.

[0312] In transistor 100E, there is a region in semiconductor layer 108 that overlaps with conductive layer 104 separated by insulating layer 106 and with conductive layer 103 separated by a portion of insulating layer 110 (especially insulating layers 110a and 110b). In other words, there is a region in semiconductor layer 108 sandwiched between conductive layer 104 and conductive layer 103, wherein insulating layer 106 is sandwiched between semiconductor layer 108 and conductive layer 104 and a portion of insulating layer 110 (especially insulating layers 110a and 110b) is sandwiched between semiconductor layer 108 and conductive layer 103.

[0313] Conductive layer 104 is used as the gate electrode (also referred to as the first gate electrode) of transistor 100E. A portion of insulating layer 106 is used as a gate insulating layer (also referred to as the first gate insulating layer). Additionally, conductive layer 103 is used as the back gate electrode (also referred to as the second gate electrode). A portion of insulating layer 110 is used as the back gate insulating layer (also referred to as the second gate insulating layer). Conductive layer 103 can be made of materials suitable for conductive layers 112a, 112b, and 104. Note that conductive layer 103 may also be omitted.

[0314] By providing a back gate electrode in transistor 100E, the potential of the back gate electrode side (also known as the back channel side) of semiconductor layer 108 is fixed, thereby improving the saturation of Id-Vd characteristics.

[0315] Note that in this specification, the small change in current in the saturation region of the Id-Vd characteristic of a transistor is sometimes described as "high saturation".

[0316] Transistor 100E includes a back gate electrode, thus fixing the potential on the back channel side of semiconductor layer 108 and suppressing threshold voltage drift. Here, when the threshold voltage of the transistor drifts, the drain current (hereinafter also referred to as the cutoff current) flowing through it when the gate voltage is 0V sometimes increases. By suppressing threshold voltage drift, a transistor with low cutoff current can be realized. Therefore, a semiconductor device with low power consumption can be realized.

[0317] The insulating layer 107 can be made of a material suitable for the insulating layer 110. The insulating layer 107 in contact with the conductive layers 112a and 103 is preferably a nitrogen-containing insulating layer. The insulating layer 107 can suitably use a material suitable for the insulating layer 110a. For example, silicon nitride can suitably be used for the insulating layer 107. Note that this embodiment shows an insulating layer 107 with a single-layer structure, but the invention is not limited to this. The insulating layer 107 can also have a stacked structure of two or more layers.

[0318] The conductive layer 103 can also be electrically connected to the conductive layer 112a. For example, by providing an opening in the region of the insulating layer 107 that overlaps with the conductive layer 112a and then covering the opening, a structure can be formed in which the conductive layer 103 contacts the conductive layer 112a. By electrically connecting the conductive layer 112a, which serves as a source electrode or drain electrode, to the conductive layer 103, which serves as a back gate electrode, the source electrode or drain electrode and the back gate electrode can be made to have the same potential. For example, when the conductive layer 112a is used as a source electrode, threshold voltage drift of the transistor 100E can be suppressed. Furthermore, the reliability of the transistor 100E can be improved. Note that the conductive layer 103, which contacts the top surface of the conductive layer 112a, can also be formed without providing the insulating layer 107.

[0319] The conductive layer 103 can also be electrically connected to the conductive layer 112b. For example, by providing an opening in the region of the insulating layer 110 that overlaps with the conductive layer 103 and providing the conductive layer 112b in a manner that covers the opening, a structure in which the conductive layer 103 and the conductive layer 112b are in contact can be achieved.

[0320] The conductive layer 103 can also be electrically connected to the conductive layer 104. For example, by providing an opening in the region of the insulating layer 106 and the insulating layer 110 that overlaps with the conductive layer 103, and then covering the opening, a structure can be formed in which the conductive layer 103 and the conductive layer 104 are in contact. By electrically connecting the conductive layer 104, which serves as the gate electrode, to the conductive layer 103, which serves as the back gate electrode, the back gate electrode and the gate electrode can be made to have the same potential, thereby increasing the on-state current of the transistor 100E.

[0321] The thickness of the conductive layer 103 can also be greater than the thickness of the insulating layer 110. As a result, the potential on the back channel side of the semiconductor layer 108 can be fixed over a large area between the source region and the drain region in the semiconductor layer 108.

[0322] Transistor 100E has a region in which a conductive layer 103, an insulating layer 110, a semiconductor layer 108, an insulating layer 106, and a conductive layer 104 are sequentially stacked in one direction, without other layers in between. This direction can be exemplified by a direction perpendicular to the channel length direction. By expanding this region, the potential on the back channel side of the semiconductor layer 108 can be more reliably controlled.

[0323] The thickness of the conductive layer 103 is preferably greater than the sum of the thickness of the portion inside the opening 141 of the semiconductor layer 108 that contacts the conductive layer 112a and the thickness of the insulating layer 106 that contacts that portion.

[0324] Note that the structures of conductive layer 103 and insulating layer 107 shown in structural examples 1-8 can also be applied to other structural examples.

[0325] <Structure Example 2> FIG. 20A to FIG. 20I A circuit diagram of a semiconductor device according to one aspect of the present invention is shown. Figures 21 to 26 show a top view and a cross-sectional view of a semiconductor device according to one aspect of the present invention. Hereinafter, the transistor included in the semiconductor device according to one aspect of the present invention will be described primarily using transistor 100 as an example. The semiconductor device according to one aspect of the present invention is not limited thereto, and may also include one or more of the transistors 100A to 100E described above.

[0326] One aspect of the present invention includes a semiconductor device comprising at least two transistors, wherein any one of the gate, source, and drain of one transistor is electrically connected to any one of the gate, source, and drain of the other transistor.

[0327] For example, FIG. 20A The semiconductor device shown includes transistor 100 and transistor 200. One of the source and drain of transistor 200 is electrically connected to the gate of transistor 100.

[0328] Note that in FIG. 20A to FIG. 20C The illustration shows an example where transistors 100 and 200 are n-channel transistors, but one aspect of the invention is not limited thereto. One or both of transistors 100 and 200 may also be p-channel transistors.

[0329] [Structure Example 2-1] FIG. 21A A top view of a semiconductor device 20 according to one aspect of the present invention is shown. FIG. 21B Show along FIG. 21A A cross-sectional view of the section between the dotted line A1 and A2 in the diagram. FIG. 21C The cross-sectional view is shown along the dashed lines B1-B2 and B3-B4.

[0330] Semiconductor device 20 includes transistor 100 and transistor 150. In semiconductor device 20, any one of the gate, source, and drain of transistor 100 can be electrically connected to any one of the gate, source, and drain of transistor 150. Note that... FIG. 21A to FIG. 21C The electrical connection between transistors 100 and 150 is omitted.

[0331] Transistor 100 and transistor 150 are both disposed on substrate 102.

[0332] Since transistor 100 can be described in the above description, detailed instructions are omitted.

[0333] Transistor 150 includes conductive layer 202, insulating layer 110, insulating layer 120, semiconductor layer 208, insulating layer 106, conductive layer 204, conductive layer 212a, and conductive layer 212b. The layers constituting transistor 150 can have a single-layer structure or a stacked structure.

[0334] A conductive layer 202 is formed on a substrate 102. The conductive layer 202 serves as the back gate electrode of the transistor 150. The conductive layer 202 can be made of the same material as the conductive layer 112a included in the transistor 100. The conductive layer 202 can be formed using the same process as the conductive layer 112a. For example, the conductive layers 112a and 202 can be formed by forming a film that becomes the conductive layer 112a and 202 and processing that film. Alternatively, the conductive layer 202 can also be formed using a different process than the conductive layer 112a. When formed using different processes, the conductive layers 202 and 112a can use different materials. The conductive layer 202 does not have a region in contact with the semiconductor layer 108 and the semiconductor layer 208, therefore there are no particular limitations on the material used for the conductive layer 202. For example, the conductive layer 202 is preferably made of a material with lower resistance than the conductive layer 112a. This reduces the resistance of the conductive layer 202. For example, In-Sn-Si oxide (ITSO) can be appropriately used for conductive layer 112a and copper or tungsten can be used for conductive layer 202. FIG. 5A As shown, when the conductive layer 112a has a stacked structure, for example, In-Sn-Si oxide (ITSO) can be appropriately used for conductive layer 112a_2 and copper or tungsten can be used for conductive layer 112a_1 and conductive layer 202. Additionally, the transistor 150 can have a structure that does not include a back gate electrode.

[0335] An insulating layer 110 is provided to cover the conductive layer 202, and an insulating layer 120 is provided on the insulating layer 110. Insulating layers 110 and 120 serve as the back gate insulating layer of the transistor 150. Because the insulating layer 120 is a layer in contact with the channel formation region of the semiconductor layer 208, it is preferably an oxygen-containing insulating layer. The insulating layer 120 can, for example, use a material suitable for insulating layer 110b.

[0336] A semiconductor layer 208 is disposed on the insulating layer 120. The semiconductor layer 208 has a region that overlaps with the conductive layer 202, separated by the insulating layer 110 and the insulating layer 120. The semiconductor layer 208 can be made of the same material as the semiconductor layer 108. The semiconductor layer 208 can be formed by the same process as the semiconductor layer 108.

[0337] An insulating layer 106 is disposed such that it covers the insulating layer 120 and the semiconductor layer 208. The insulating layer 106 is used as the gate insulating layer of the transistor 150. In addition, the insulating layer 106 has openings 147a and 147b reaching the semiconductor layer 208.

[0338] Conductive layers 204, 212a, and 212b are disposed on the insulating layer 106. Conductive layers 204, 212a, and 212b can be made of the same material as conductive layer 104. Conductive layers 204, 212a, and 212b can be formed using the same process as conductive layer 104. For example, conductive layers 104, 204, 212a, and 212b can be formed by forming a film that becomes conductive layers 104, 204, 212a, and 212b and processing that film.

[0339] Conductive layer 212a is disposed such that it covers at least a portion of opening 147a, and conductive layer 212b is disposed such that it covers at least a portion of opening 147b. Conductive layers 212a and 212b have regions that contact semiconductor layer 208. Conductive layer 212a is electrically connected to semiconductor layer 208 through opening 147a. Conductive layer 212b is electrically connected to semiconductor layer 208 through opening 147b. Conductive layer 212a is used as one of the source and drain electrodes of transistor 150, and conductive layer 212b is used as the other of the source and drain electrodes of transistor 150.

[0340] The conductive layer 204 has a region that overlaps with the semiconductor layer 208 through the insulating layer 106. The conductive layer 204 is used as the gate electrode of the transistor 150.

[0341] like FIG. 21C As shown, conductive layer 204 can also contact conductive layer 202, and conductive layer 204 and conductive layer 202 are electrically connected. Therefore, conductive layer 204 and conductive layer 202 can be supplied with the same potential. By supplying conductive layer 204 and conductive layer 202 with the same potential, the current that can flow when transistor 150 is in the on state can be increased. Conductive layer 204 can be electrically connected to conductive layer 202 through openings 149 provided in insulating layer 106 and insulating layer 110.

[0342] Conductive layer 212a or conductive layer 212b can also be electrically connected to conductive layer 202. By supplying the source and back gate with the same potential, the back channel potential is stabilized, and the saturation of the Id-Vd characteristic of the transistor can be improved. Conductive layer 212a or conductive layer 212b can contact conductive layer 202 through openings provided in insulating layer 106 and insulating layer 110.

[0343] The conductive layer 202 may also not be electrically connected to the conductive layers 204, 212a, and 212b. For example, a constant potential can be supplied to the back gate and a signal for driving the transistor 150 can be supplied to the gate. Thus, the potential supplied to the back gate can be controlled at the threshold voltage when driving the transistor 150.

[0344] In semiconductor layer 208, the region between the source electrode and the drain electrode, where the gate insulating layer overlaps with the gate electrode, is used as a channel formation region. Semiconductor layer 208 has a pair of regions 208L that clamp the channel formation region and a pair of regions 208D outside of them.

[0345] Region 208D can also be described as a region with a higher carrier concentration or lower resistance than the channel formation region. The region in semiconductor layer 208 that contacts conductive layer 212a and the adjacent region 208D are used as one of the source and drain regions. The region in semiconductor layer 208 that contacts conductive layer 212b and the adjacent region 208D are used as the other of the source and drain regions.

[0346] Region 208L can also be described as a region with equal or lower resistance, equal or higher carrier concentration, equal or higher oxygen vacancy density, and equal or higher impurity concentration compared to the channel formation region. Furthermore, region 208L can also be described as a region with equal or higher resistance, equal or lower carrier concentration, equal or lower oxygen vacancy density, and equal or lower impurity concentration compared to region 208D.

[0347] Region 208L is used as a buffer region to mitigate the drain electric field. Since region 208L does not overlap with conductive layer 204, almost no channel is formed when a gate voltage is supplied to conductive layer 204. The carrier concentration in region 208L is preferably higher than that in the channel formation region. Therefore, region 208L can be used as an LDD (Lightly Doped Drain) region. By providing region 208L as an LDD region between the channel formation region and region 208D, a transistor 150 with a high drain breakdown voltage can be realized.

[0348] For example, after forming conductive layers 204, 212a, and 212b, impurity elements can be added to semiconductor layer 208 using these conductive layers as a mask to form regions 208L and 208D. Region 208L is a region in semiconductor layer 208 that overlaps with insulating layer 106 but not with conductive layer 204. Region 208D is a region in semiconductor layer 208 that does not overlap with insulating layer 106 or conductive layer 204.

[0349] like FIG. 21A and FIG. 21BAs shown, the ends of a portion of conductive layers 212a and 212b are preferably located inside openings 147a and 147b. In other words, in openings 147a and 147b, the ends of a portion of conductive layers 212a and 212b are preferably in contact with semiconductor layer 208. Therefore, the region in contact with conductive layer 212a can be adjacent to one of the pair of regions 208D, and similarly, the region in contact with conductive layer 212b can be adjacent to the other of the pair of regions 208D. Note that there are no particular limitations on the top surface shape of openings 147a and 147b.

[0350] Regions 208L and 208D contain impurity elements. These impurity elements can be one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, or noble gases. Typical examples of noble gases include helium, neon, argon, krypton, and xenon. One or more of boron, phosphorus, aluminum, magnesium, and silicon are particularly preferred as impurity elements.

[0351] When adding impurity elements to semiconductor layer 208 to form regions 208L and 208D, conductive layer 104 can be used as a mask and the impurity elements can be supplied to semiconductor layer 108 through insulating layer 106. Thus, a region containing the impurity element is formed in a region of semiconductor layer 108 that does not overlap with conductive layer 104. Here, in transistor 100, the region of semiconductor layer 108 that contacts conductive layer 112b is used as a source region or drain region. Therefore, the region containing the impurity element is formed in a portion of the source region or drain region.

[0352] Transistor 150 is a so-called top-gate transistor having a gate electrode above semiconductor layer 208. For example, by using the conductive layer 204, which serves as the gate electrode, as a mask and adding impurity elements to semiconductor layer 208, the source and drain regions can be formed in a self-aligned manner. Transistor 150 can be described as a TGSA (Top Gate Self-Aligned) type transistor.

[0353] The channel length of transistor 150 can be controlled by the width of the conductive layer 204 in the channel length direction. Thus, the channel length of transistor 150 is a value greater than the minimum dimension exposed by the exposure apparatus used in transistor manufacturing. By increasing the channel length, transistors with high saturation can be achieved.

[0354] An insulating layer 195 is provided to cover transistors 100 and 150. The insulating layer 195 serves as a protective layer. The insulating layer 195 is preferably made of a material from which impurities do not easily diffuse. By providing the insulating layer 195, the diffusion of impurities from the outside into the transistor can be effectively suppressed, thereby improving the reliability of the semiconductor device. Examples of impurities include water and hydrogen. For example, the insulating layer 195 comprises one or both of an inorganic insulating layer and an organic insulating layer. The insulating layer 195 may also have a stacked structure of inorganic and organic insulating layers.

[0355] The inorganic insulating layer 195 can be made of materials that are also suitable for insulating layer 110. Specifically, insulating layer 195 can be one or more of silicon nitride, silicon oxynitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate. For example, one or more of acrylic resin and polyimide resin can be used as the organic insulating layer of insulating layer 195.

[0356] In the manufacture of semiconductor device 20, some processes can be shared to form short-channel transistor 100 and long-channel transistor 150 on the same substrate. For example, by using transistor 100 as a transistor requiring high on-state current and transistor 150 as a transistor requiring high saturation, a high-performance semiconductor device can be realized.

[0357] Here, the conductive layers 212a and 212b are shown as being formed using the same process as conductive layers 104 and 204; however, the present invention is not limited to this. For example, conductive layers 212a and 212b may be formed after the insulating layer 195 is formed. Specifically, after the insulating layer 195 is provided to cover the conductive layers 104 and 204, an opening leading to the semiconductor layer 208 may be provided in the insulating layers 195 and 106, and conductive layers 212a and 212b may be provided to cover this opening, thereby allowing conductive layers 212a and 212b to be electrically connected to the semiconductor layer 208. Furthermore, by using the conductive layer 204 as a mask to add impurity elements to the semiconductor layer 208 after the conductive layer 204 is formed, a region with low resistance can be formed in the semiconductor layer 208.

[0358] [Structure Example 2-2] FIG. 22A and FIG. 22B A cross-sectional view of a semiconductor device 20A according to one embodiment of the present invention is shown. A top view of the semiconductor device 20A can be seen in [reference needed]. FIG. 21A . FIG. 22A It is along FIG. 21A A cross-sectional view of the section between the dotted line A1 and A2 in the diagram. FIG. 22B It is along FIG. 21ACross-sectional views of the dashed lines B1-B2 and B3-B4 in the diagram.

[0359] Semiconductor device 20A includes transistor 100 and transistor 150A. Transistor 150A is mainly distinguished from transistor 120 by the point where the conductive layer 202 is disposed between the insulating layer 110 and the insulating layer 120. FIG. 21B The transistor 150 shown is different.

[0360] A conductive layer 202 is provided on the insulating layer 110. The conductive layer 202 can be made of the same material as the conductive layer 112b. The conductive layer 202 can be formed by the same process as the conductive layer 112b.

[0361] An insulating layer 120 is disposed on the conductive layer 202. The insulating layer 120 is disposed such that it covers a portion of the top and side surfaces of the conductive layer 202. The insulating layer 120 is disposed at least in the region where the semiconductor layer 208 overlaps with the conductive layer 204. In the transistor 150A, a portion of the insulating layer 120 is used as a back gate insulating layer. By disposing the conductive layer 202 between the insulating layers 110 and 120, the thickness of the back gate insulating layer of the transistor 150A can be reduced. This enhances the electric field of the back gate electrode. Furthermore, the saturation of the Id-Vd characteristic of the transistor 150A can be improved. In addition, threshold voltage drift can be suppressed, and a transistor with low cutoff current can be realized.

[0362] The insulating layer 120 preferably has a laminated structure. FIG. 22A Examples are shown, such as the example of an insulating layer 120 having a laminated structure of an insulating layer 120a and an insulating layer 120b on the insulating layer 120a.

[0363] The insulating layer 120a, which is disposed in contact with the conductive layer 202, is preferably made of a material from which the metal elements in the conductive layer 202 do not easily diffuse. This suppresses the diffusion of the metal elements in the conductive layer 202 into the channel formation region in the semiconductor layer 208. The insulating layer 120a can suitably use a material suitable for the insulating layer 110a. For example, silicon nitride is preferably used for the insulating layer 120a.

[0364] The insulating layer 120b that contacts the channel formation region of the semiconductor layer 208 is preferably an oxygen-containing insulating layer. The insulating layer 120b can use a material suitable for the insulating layer 110b. For example, silicon oxynitride is preferably used for the insulating layer 120b.

[0365] For details regarding transistor 100, please refer to the above description; therefore, detailed explanations are omitted.

[0366] [Structure Examples 2-3] FIG. 20B A circuit diagram of a semiconductor device 20B according to one aspect of the present invention is shown. FIG. 23AA top view of semiconductor device 20B is shown. FIG. 23B Show along FIG. 23A A cross-sectional view of the section between the dotted line A1 and A2 in the diagram. FIG. 23C The cross-sectional view is shown along the dashed lines B1-B2 and B3-B4.

[0367] Semiconductor device 20B includes transistor 100 and transistor 200. One of the source and drain of transistor 200 is electrically connected to the other of the source and drain of transistor 100.

[0368] Transistor 100 and transistor 200 are both formed on substrate 102.

[0369] Since transistor 100 can be described in the above description, detailed instructions are omitted.

[0370] Transistor 200 includes conductive layer 112b, conductive layer 112c, semiconductor layer 208, insulating layer 106, and conductive layer 204. Transistor 200 may have the same structure as transistor 100.

[0371] Conductive layer 112c is used as one of the source and drain electrodes of transistor 200. Conductive layer 112b is used as the other of the source and drain electrodes of transistor 100 and transistor 200. When transistors 100 and 200 share conductive layer 112b, the footprint of the semiconductor device can be reduced. A portion of insulating layer 106 is used as the gate insulating layer of transistor 200. Conductive layer 204 is used as the gate electrode of transistor 200.

[0372] Conductive layer 112c can use the same material as conductive layer 112a. Conductive layer 112c can be formed using the same process as conductive layer 112a. Insulating layer 110 includes an opening 241 reaching conductive layer 112c. Opening 241 can be formed using the same process as opening 141. Conductive layer 112b includes an opening 243 in the region overlapping with opening 241. Opening 243 can be formed using the same process as opening 143. There are no limitations on the top surface shape of openings 241 and 243, but they are preferably circular. Furthermore, a structure is shown here where the top surface shape of opening 241 is consistent with the top surface shape of opening 243, but one aspect of the invention is not limited to this. The top surface shape of opening 241 and the top surface shape of opening 243 may also be different.

[0373] Alternatively, the width of opening 141 can be different from the width of opening 241. By making the opening widths different, two transistors with different channel widths can also be manufactured.

[0374] A semiconductor layer 208 is provided to cover openings 241 and 243. The semiconductor layer 208 can be formed using the same process as the semiconductor layer 108. An insulating layer 106 is provided on the semiconductor layer 208, and a conductive layer 204 is provided on the insulating layer 106. The conductive layer 204 can be formed using the same process as the conductive layer 104.

[0375] Notice, FIG. 23A The diagram shows a structure where the semiconductor layers between transistors 100 and 200 are separated into semiconductor layer 108 and semiconductor layer 208, but one aspect of the invention is not limited to this. Transistors 100 and 200 may also share the same semiconductor layer.

[0376] [Structure Examples 2-4] FIG. 20C A circuit diagram of a semiconductor device 20C according to one aspect of the present invention is shown. FIG. 24A A top view of semiconductor device 20C is shown. FIG. 24B Show along FIG. 24A A cross-sectional view of the section between the dotted line A1 and A2 in the diagram. FIG. 24C The cross-sectional view is shown along the dashed lines B1-B2 and B3-B4.

[0377] Semiconductor device 20C includes transistor 100 and transistor 200. One of the source and drain of transistor 200 is electrically connected to one of the source and drain of transistor 100.

[0378] Transistor 100 and transistor 200 are both formed on substrate 102.

[0379] Since transistor 100 can be described in the above description, detailed instructions are omitted.

[0380] The transistor 200 includes a conductive layer 112a, a conductive layer 112c, a semiconductor layer 208, an insulating layer 106, and a conductive layer 204.

[0381] Conductive layer 112c is used as one of the source and drain electrodes of transistor 200. Conductive layer 112a is used as the other of the source and drain electrodes of transistor 100 and transistor 200. When transistors 100 and 200 share conductive layer 112a, the footprint of the semiconductor device can be reduced.

[0382] The conductive layer 112c can be made of the same material as the conductive layer 112b. The conductive layer 112c can be formed by the same process as the conductive layer 112b.

[0383] [Structure Examples 2-5] FIG. 20DA circuit diagram of a semiconductor device 20D according to one aspect of the present invention is shown. FIG. 25A A top view of semiconductor device 20D is shown. FIG. 25B Show along FIG. 25A The cross-sectional view of the section between the dotted and dashed lines A1-A2 in the figure.

[0384] Semiconductor device 20D includes transistor 100 and transistor 250. One of the source and drain of transistor 250 is electrically connected to one of the source and drain of transistor 100.

[0385] Transistor 100 and transistor 250 are both disposed on substrate 102.

[0386] Semiconductor device 20D includes a conductive layer 259 on a substrate 102, an insulating layer 252 on the substrate 102 and the conductive layer 259, and a semiconductor layer 253 on the insulating layer 252. Additionally, an insulating layer 254 is included on the insulating layer 252 and the semiconductor layer 253, and a conductive layer 255 is included on the insulating layer 254. The semiconductor layer 253 and the conductive layer 255 have overlapping regions. The conductive layer 259 serves as the back gate electrode of transistor 250, and the insulating layer 252 serves as the back gate insulating layer. The insulating layer 254 serves as the gate insulating layer, and the conductive layer 255 serves as the gate electrode.

[0387] An insulating layer 256 is provided on the insulating layer 254 and the conductive layer 255. Furthermore, an opening 257a is provided in the insulating layer 254 and the insulating layer 256 in a region that overlaps with a portion of the semiconductor layer 253. Additionally, an opening 257b is provided in the insulating layer 254 and the insulating layer 256 in another region that overlaps with a portion of the semiconductor layer 253.

[0388] A conductive layer 258a is provided on the insulating layer 256 and the opening 257a, and a conductive layer 258b is provided on the insulating layer 256 and the opening 257b. The conductive layer 258a is electrically connected to the semiconductor layer 253 in the opening 257a. The conductive layer 258b is electrically connected to the semiconductor layer 253 in the opening 257b.

[0389] In semiconductor layer 253, the region overlapping with conductive layer 255 is used as a channel formation region. Semiconductor layer 253 has a pair of regions 253D that clamp the channel formation region. One of the pair of regions 253D is used as one of the source and drain regions and is electrically connected to conductive layer 258a. The other of the pair of regions 253D is used as the other of the source and drain regions and is electrically connected to conductive layer 258b.

[0390] An insulating layer 110 is disposed on the insulating layer 256, the conductive layer 258a and the conductive layer 258b, and a conductive layer 112b is disposed on the insulating layer 110.

[0391] The conductive layer 112b and the insulating layer 110 include an opening 146 in the region overlapping a portion of the conductive layer 258a. FIG. 25A A semiconductor layer 108 is provided in such a way that it covers the opening 146.

[0392] An insulating layer 106 is provided on the insulating layer 110, the conductive layer 112b, and the semiconductor layer 108, and a conductive layer 104 is provided on the insulating layer 106. In addition, an insulating layer 195 is provided on the insulating layer 106 and the conductive layer 104.

[0393] The conductive layer 259 preferably overlaps with the channel formation region and extends beyond the end of the channel formation region. In other words, the conductive layer 259 is preferably larger than the channel formation region. Furthermore, the conductive layer 259 preferably extends beyond the end of the semiconductor layer 253. In other words, the conductive layer 259 is preferably larger than the semiconductor layer 253.

[0394] The gate electrode and back gate electrode are configured such that a channel forming region sandwiching the semiconductor layer is formed. Furthermore, the threshold voltage of the transistor can be changed by altering the potential of the back gate electrode. The potential of the back gate electrode can be ground potential or any potential.

[0395] The back gate electrode can be formed using the same materials and methods as the gate, source, and drain electrodes. Furthermore, since the gate and back gate electrodes are conductive layers, they prevent external electric fields from affecting the semiconductor layer forming the channel (especially providing electrostatic discharge shielding). In other words, they prevent changes in the transistor's electrical characteristics due to external electric fields such as electrostatic discharge. Additionally, by providing a back gate electrode, the change in the transistor's threshold voltage before and after BT (Bias Temperature) stress testing can be reduced. By providing a back gate electrode, transistor characteristic non-uniformity is reduced, improving the reliability of the semiconductor device.

[0396] like FIG. 20E As shown, the back gate and gate of transistor 250 can be electrically connected. Additionally, as... FIG. 20F As shown, the back gate of transistor 250 can be electrically connected to either the source or the drain. Additionally, as... FIG. 20G As shown, transistor 250 may have a structure that does not include a back gate.

[0397] FIGS. 20D-20H The transistor 100 shown is an n-channel transistor and the transistor 250 is a p-channel transistor, but this is not the only embodiment of the invention. Both transistor 100 and transistor 250 can be either n-channel or p-channel transistors. Alternatively, transistor 100 can be a p-channel transistor and transistor 250 can be an n-channel transistor.

[0398] Similar to transistor 100, an OS transistor can also be used as transistor 250.

[0399] Here, semiconductor layer 108 and semiconductor layer 253 may be made of the same material or different materials. The structure of semiconductor layer 108 and semiconductor layer 253 can be referred to the description of semiconductor layer 108 and semiconductor layer 208 in semiconductor device 20.

[0400] Transistor 250 can also be a transistor that uses silicon in the channel forming region (hereinafter also referred to as a Si transistor).

[0401] Examples of silicon include monocrystalline silicon, polycrystalline silicon, and amorphous silicon. In particular, transistors containing LTPS in the semiconductor layer (hereinafter also referred to as LTPS transistors) can be used. LTPS transistors have high field-effect mobility and good frequency characteristics.

[0402] Transistor 100 includes a conductive layer 258a instead of conductive layer 112a, and its structure is otherwise the same as described above (see Figure 1).

[0403] The conductive layer 258a is used as one of the source and drain electrodes of transistor 100, and as one of the source and drain electrodes of transistor 250. When transistors 100 and 250 share the conductive layer 258a, the footprint of the semiconductor device can be reduced.

[0404] As described above, transistor 100 is a vertical channel transistor. On the other hand, in transistor 250, the current flowing through the semiconductor layer flows in the lateral direction, that is, in a direction parallel or substantially parallel to the surface of substrate 102. This type of transistor can be called a lateral channel transistor or a lateral transistor.

[0405] Thus, in addition to vertical channel transistors, a semiconductor device according to one aspect of the present invention may also include lateral channel transistors.

[0406] Furthermore, the transistor 100 can also be formed in the region overlapping with the opening 257a. Specifically, a structure can be adopted in which an opening 146 is provided in the region overlapping with the opening 257a, and the conductive layer 258a contacts the semiconductor layer 108 in the opening 257a. Alternatively, a structure can be adopted in which the conductive layer 258a is not provided, and the semiconductor layer 108 is contacted in region 253D of the opening 257a. By adopting this structure, a semiconductor device with a smaller footprint can be realized.

[0407] [Structure Examples 2-6] FIG. 20H A circuit diagram of a semiconductor device 20E according to one aspect of the present invention is shown.FIG. 26A A top view of semiconductor device 20E is shown. FIG. 26B Show along FIG. 26A The cross-sectional view of the section between the dotted and dashed lines A1-A2 in the figure.

[0408] Semiconductor device 20E includes transistor 100 and transistor 250. The gate of transistor 250 is electrically connected to one of the source and drain of transistor 100.

[0409] Semiconductor device 20E differs from semiconductor device 20D primarily in that the opening 146 is arranged to overlap with the conductive layer 255, which serves as the gate electrode of transistor 250. Therefore, in semiconductor device 20D, transistor 100 is arranged to overlap the gate electrode of transistor 250.

[0410] exist FIG. 26A and FIG. 26B In the present invention, the opening 146 is provided in a manner that overlaps with the channel forming region, but is not limited thereto. The opening 146 may also be provided in a manner that does not overlap with the channel forming region but overlaps with the conductive layer 255. In the semiconductor device 20E, the conductive layer 255 is used as the gate electrode of the transistor 250, and is used as one of the source electrode and drain electrode of the transistor 100.

[0411] By overlapping transistors 100 and 250, a semiconductor device with a further reduced footprint can be realized.

[0412] The difference between semiconductor device 20E and semiconductor device 20D lies in the structure of opening 257a, opening 257b, conductive layer 258a, and conductive layer 258b.

[0413] Openings 257a and 257b are formed in the region overlapping with region 253D of semiconductor layer 253 by selectively removing a portion of insulating layer 254 and insulating layer 110, respectively. Conductive layers 258a and 258b are disposed on insulating layer 110 and electrically connected to region 253D through openings 257a and 257b.

[0414] In semiconductor device 20E, conductive layers 258a and 258b can also be formed through the same process as conductive layer 112b. Because conductive layers 258a and 258b do not need to be formed through different processes than conductive layer 112b, the manufacturing process of semiconductor device can be shortened to improve the productivity of semiconductor device.

[0415] One aspect of the present invention includes a semiconductor device comprising at least one transistor and at least one capacitor element, wherein the source or drain of the transistor is electrically connected to one of a pair of electrodes of the capacitor element. FIG. 20IAn example is shown where the source or drain of transistor 100 is electrically connected to one electrode of capacitor element 190.

[0416] One embodiment of the transistor in this invention is a vertical transistor, which, because the source electrode, semiconductor layer, and drain electrode can be stacked, can significantly reduce the occupied area compared to a planar transistor. Furthermore, by using a p-channel Si transistor as a planar transistor and an n-channel OS transistor as a vertical transistor, a CMOS (Complementary Metal Oxide Semiconductor) circuit can be constructed. Additionally, by employing this structure and stacking the planar and vertical transistors, the occupied area of ​​the CMOS circuit can be reduced.

[0417] [Structure Examples 2-7] FIG. 27A An equivalent circuit diagram of a semiconductor device 30 according to one embodiment of the present invention is shown. The semiconductor device 30 includes transistors 100_1 to 100_p (p is an integer greater than or equal to 2). Transistors 100_1 to 100_p are connected in parallel, and the semiconductor device 30 can be regarded as a single transistor.

[0418] The gate electrodes of transistors 100_1 to 100_p are electrically connected to each other. The source electrodes of transistors 100_1 to 100_p are electrically connected to each other. The drain electrodes of transistors 100_1 to 100_p are electrically connected to each other.

[0419] Note that in FIG. 27A In this embodiment, transistors 100_1 to 100_p are n-channel transistors, but one embodiment of the invention is not limited to this. Transistors 100_1 to 100_p can also be p-channel transistors.

[0420] Let's take the case where p is 4 as an example for a specific explanation. FIG. 27B An equivalent circuit diagram of a semiconductor device 30 according to one aspect of the present invention is shown. FIG. 27C A top view of semiconductor device 30 is shown. FIG. 28 Show along FIG. 27C The cross-sectional view of the section between the dotted and dashed lines A3-A4 in the figure. FIG. 29 A perspective view of semiconductor device 30 is shown.

[0421] Semiconductor device 30 includes transistors 100_1 to 100_4. Transistors 100_1 to 100_4 can all employ the structure of transistor 100 described above. Note that transistor 100 is used as an example here, but the invention is not limited to this. Any of transistors 100A to 100E can also be used with transistors 100_1 to 100_4.

[0422] FIG. 27C The diagram shows a configuration of transistors 100_1 to 100_4 in a 2-row, 2-column arrangement, but there are no particular restrictions on the arrangement of the transistors. For example, transistors 100_1 to 100_4 could also be configured in a 1-row, 4-column arrangement.

[0423] Transistors 100_1 to 100_4 all include a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. The conductive layer 104 serves as the gate electrode of transistors 100_1 to 100_4. A portion of the insulating layer 106 serves as the gate insulating layer of transistors 100_1 to 100_4. The conductive layer 112a serves as one of the source and drain electrodes of transistors 100_1 to 100_4, and the conductive layer 112b serves as the other of the source and drain electrodes.

[0424] FIG. 30A This is a perspective view of the conductive layer 112a.

[0425] FIG. 30B This is a perspective view summarizing the conductive layers 112a and 112b, and openings 141_1 to 141_4 and 143_1 to 143_4. Note that openings 141_1 to 141_4 provided in the insulating layer 110 are shown in dashed lines. For details regarding openings 141_1 to 141_4 and openings 143_1 to 143_4, please refer to the description of openings 141 and 143; therefore, detailed descriptions are omitted.

[0426] When the semiconductor device 30 is considered as a transistor, the channel width of the transistor is the sum of the channel widths of transistors 100_1 to 100_4. For example, when the top surface shape of openings 141_1 to 141_4 is circular and the width of each opening 141_1 to 141_4 is recorded as width D141, the semiconductor device 30 can be considered as a transistor with a channel width of "D141×π×4" (see reference). FIG. 3A and FIG. 3B The semiconductor device 30, composed of p transistors, can be considered as a transistor with a channel width of "D141×π×p". Furthermore, the semiconductor device 30 can be considered as a transistor with a channel length L100 (see reference).FIG. 3B By connecting multiple transistors in parallel, the channel width is increased, thereby increasing the on-state current. Furthermore, the channel width can be varied by adjusting the number (p) of transistors connected in parallel. The number (p) of transistors connected in parallel is determined to achieve the desired on-state current.

[0427] FIG. 30C This is a perspective view illustrating the conductive layer 112a and the semiconductor layer 108. The semiconductor layer 108 is disposed such that it covers openings 141_1 to 141_4 and openings 143_1 to 143_4. Note that in FIG. 30C The diagram shows the structure of transistors 100_1 to 100_4 sharing a common semiconductor layer 108, but one aspect of the invention is not limited thereto. The semiconductor layer 108 may also be separated for transistors 100_1 to 100_4.

[0428] FIG. 30D This is a perspective view showing the conductive layer 112a and the conductive layer 104. The conductive layer 104 is provided in such a way that it covers openings 141_1 to 141_4 and openings 143_1 to 143_4.

[0429] Furthermore, the structure of the semiconductor device 30 shown in structural examples 2-7 can be used in other structural examples. For example, the semiconductor device 30 can also be applied to... FIGS. 20A-20I One or more of the transistors included in the semiconductor device shown.

[0430] [Structure Examples 2-8] FIG. 31A An equivalent circuit diagram of a semiconductor device 40 according to one embodiment of the present invention is shown. The semiconductor device 40 includes transistors 100_1 to 100_q (q being an integer greater than or equal to 2). Transistors 100_1 to 100_q are connected in series, and the semiconductor device 40 can be considered as a single transistor.

[0431] Note that in FIG. 31A In this embodiment, transistors 100_1 to 100_q are n-channel transistors, but one embodiment of the invention is not limited to this. Transistors 100_1 to 100_q can also be p-channel transistors.

[0432] Let's take the case where q is 4 as an example for a specific explanation. FIG. 31B An equivalent circuit diagram of a semiconductor device 40 according to one aspect of the present invention is shown. FIG. 31C A top view of semiconductor device 40 is shown. FIG. 32 Show along FIG. 31C The cross-sectional view of the section with dotted lines A5-A6 in the figure. FIG. 33 A perspective view of semiconductor device 40 is shown.

[0433] Semiconductor device 40 includes transistors 100_1 to 100_4. Transistors 100_1 to 100_4 can all employ the structure of transistor 100 described above. Note that this description uses transistor 100 as an example, but the invention is not limited to this. Any of transistors 100A to 100E can also be used with transistors 100_1 to 100_4.

[0434] FIG. 31C The diagram shows a configuration of transistors 100_1 to 100_4 in a 2-row, 2-column arrangement, but there are no particular restrictions on the arrangement of the transistors. For example, transistors 100_1 to 100_4 could also be configured in a 1-row, 4-column arrangement.

[0435] Transistor 100_1 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_1, a conductive layer 112a, and a conductive layer 112b. Conductive layer 112a is used as one of the source electrode and the drain electrode of transistor 100_1, and conductive layer 112b is used as the other of the source electrode and the drain electrode.

[0436] Transistor 100_2 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_2, a conductive layer 112a, and a conductive layer 112c. Conductive layer 112a is used as one of the source and drain electrodes of transistor 100_2, and conductive layer 112c is used as the other. Conductive layer 112a is shared by transistors 100_1 and 100_2.

[0437] Transistor 100_3 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_3, a conductive layer 112c, and a conductive layer 112d. Conductive layer 112c is used as one of the source and drain electrodes of transistor 100_3, and conductive layer 112d is used as the other. Conductive layer 112c is shared by transistors 100_2 and 100_3.

[0438] Transistor 100_4 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_4, a conductive layer 112d, and a conductive layer 112e. Conductive layer 112d is used as one of the source and drain electrodes of transistor 100_4, and conductive layer 112e is used as the other. Conductive layer 112d is shared by transistors 100_3 and 100_4.

[0439] FIG. 34A This is a perspective view illustrating conductive layer 112a and conductive layer 112d. Conductive layer 112a and conductive layer 112d can be formed in the same process.

[0440] FIG. 34B This is a perspective view illustrating conductive layers 112a, 112b, 112c, 112d, 112e, and openings 141_1 to 141_4 and 143_1 to 143_4. Conductive layers 112a to 112e can be formed in the same process. Opening 143_1 is provided in conductive layer 112b, openings 143_2 and 143_3 are provided in conductive layer 112c, and opening 143_4 is provided in conductive layer 112e.

[0441] FIG. 34C This is a perspective view illustrating conductive layer 112a, conductive layer 112d, and semiconductor layers 108_1 to 108_4. Semiconductor layers 108_1 to 108_4 can be formed in the same process.

[0442] FIG. 34D This is a perspective view illustrating conductive layers 112a, 112d, and 104. Conductive layer 104 is used as the gate electrode of transistors 100_1 to 100_4.

[0443] One of the source and drain electrodes of transistor 100_1 is electrically connected to one of the source and drain electrodes of transistor 100_2. The other of the source and drain electrodes of transistor 100_2 is electrically connected to one of the source and drain electrodes of transistor 100_3. The other of the source and drain electrodes of transistor 100_3 is electrically connected to one of the source and drain electrodes of transistor 100_4.

[0444] When semiconductor device 40 is considered as a transistor, the channel length of that transistor is the sum of the channel lengths of transistors 100_1 to 100_4. For example, when the channel length of each of transistors 100_1 to 100_4 is denoted as channel length L100, semiconductor device 40 can be considered as a transistor with a channel length of "L100×4" (see reference). FIG. 3B The semiconductor device 40, consisting of q transistors, can be considered as a transistor with a channel length of "L100×q". Furthermore, the semiconductor device 40 can be considered as a transistor with a channel width W100 (see reference). FIG. 3A and FIG. 3B By connecting multiple transistors in series, the channel length is increased, thereby improving saturation. Furthermore, the channel length can be varied by adjusting the number (q) of transistors connected in series. The number (q) of transistors connected in series can be determined in a way that achieves the desired saturation.

[0445] Note that the structure of the semiconductor device 40 shown in structural examples 2-8 can be used in other structural examples. For example, the semiconductor device 40 can be applied to... FIGS. 20A-20I One or more of the transistors included in the semiconductor device shown.

[0446] Semiconductor device 40 can be used for each transistor in semiconductor device 30. That is, groups of transistors connected in parallel can also be connected in series (hereinafter also referred to as series-parallel connection).

[0447] This embodiment can be appropriately combined with other embodiments. Furthermore, in this specification, where multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0448] (Implementation Method 2) In this embodiment, refer to FIGS. 35A-39 A method for manufacturing a semiconductor device according to one aspect of the present invention will be described. Note that, regarding the materials and forming methods of each constituent element, some parts that are the same as those described in Embodiment 1 above are sometimes omitted.

[0449] Thin films (insulating films, semiconductor films, and conductive films, etc.) constituting semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), and alumina deposition (ALD). CVD methods include PECVD and thermal CVD. Furthermore, metal-organic chemical vapor deposition (MOCVD) is one type of thermal CVD method.

[0450] Thin films (insulating films, semiconductor films, and conductive films, etc.) constituting semiconductor devices can be formed using wet deposition methods such as spin coating, dip coating, spray coating, inkjet coating, dispenser coating, screen printing, offset printing, doctor knife coating, slot coating, roller coating, curtain coating, or doctor blade coating.

[0451] When processing thin films that constitute semiconductor devices, photolithography and other methods can be used. Alternatively, nanoimprinting, sandblasting, and lift-off methods can also be used to process the thin films. In addition, island-shaped thin films can be directly formed by deposition methods that use metal masks or other masking methods.

[0452] Photolithography typically involves two methods. One method involves forming a resist mask on the thin film to be processed, processing the film by etching, and then removing the resist mask. The other method involves depositing a photosensitive thin film, exposing it to light, and then developing it to form the desired shape.

[0453] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365nm), g-line (wavelength 436nm), h-line (wavelength 405nm), or a mixture of these. Additionally, ultraviolet light, KrF lasers, or ArF lasers can also be used. Furthermore, immersion lithography can be employed. Extreme ultraviolet (EUV) light or X-rays can also be used as the light for exposure. Alternatively, an electron beam can be used instead of the light for exposure. Extreme ultraviolet light, X-rays, or electron beams are preferred because they allow for extremely fine processing. Note that when exposure is performed by scanning with a beam such as an electron beam, a photomask is not required.

[0454] As a method for etching thin films, one or more of the following methods can be used: dry etching, wet etching, and sandblasting.

[0455] <Example 1 of Manufacturing Method> Here, refer to FIGS. 35A-38 illustrate FIG. 11A and 11B An example of a method for manufacturing the semiconductor device 10C shown. FIGS. 35A-38 Show side by side along FIG. 1A The cross-sectional view along the dotted-dash line A1-A2 and the cross-sectional view along the dotted-dash line B1-B2.

[0456] First, an insulating layer 109 is formed on the substrate 102. When forming the insulating layer 109, sputtering or PECVD can be appropriately used.

[0457] First, a conductive film, which becomes a conductive layer 112a, is formed on the insulating layer 109, and the conductive film is processed to form the conductive layer 112a. FIG. 35A When forming this conductive film, sputtering can be appropriately used.

[0458] Next, an insulating film 110af, which becomes an insulating layer 110a, and an insulating film 110bf, which becomes an insulating layer 110b, are formed on the conductive layer 112a. FIG. 35B ).

[0459] When forming insulating films 110af and 110bf, sputtering or PECVD methods can be appropriately used. Preferably, insulating film 110bf is formed after insulating film 110af in a manner that prevents the surface of insulating film 110af from being exposed to the atmosphere. This suppresses the adhesion of atmospheric impurities to the surface of insulating film 110af. Examples of such impurities include water and organic matter. For example, it is preferable to continuously form insulating film 110bf using the same apparatus after forming insulating film 110af.

[0460] The substrate temperature during the formation of insulating films 110af and 110bf is preferably 180°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, more preferably 300°C or higher and 400°C or lower, and more preferably 350°C or higher and 400°C or lower. By keeping the substrate temperature during the formation of insulating films 110af and 110bf within the above range, the amount of impurities (e.g., water and hydrogen) released from the insulating films 110af and 110bf themselves can be reduced, thereby suppressing impurity diffusion into the semiconductor layer 108. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be realized.

[0461] Note that since insulating films 110af and 110bf are formed before semiconductor layer 108, there is no need to worry about oxygen being removed from semiconductor layer 108 due to the heat applied during the formation of insulating films 110af and 110bf.

[0462] Furthermore, heat treatment can be performed after the insulating films 110af and 110bf are formed. By performing heat treatment, impurities (such as water and hydrogen) can be removed from the film of insulating film 110af, the film of insulating film 110bf, and the surface.

[0463] Oxygen can be supplied to the insulating film 110bf after its formation. Methods for supplying oxygen include, for example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment. For plasma treatment, a device that plasma-plasmizes oxygen gas at high-frequency power can be appropriately used. Examples of devices that plasma-plasmize gas at high-frequency power include PECVD devices, plasma etching devices, and plasma ashing devices. Plasma treatment is preferably performed in an oxygen-containing atmosphere. For example, plasma treatment is preferably performed in an atmosphere containing one or more of oxygen, nitrous oxide (N₂O), nitrogen dioxide (NO₂), carbon monoxide, and carbon dioxide.

[0464] Note that the plasma treatment can also be performed after the formation of the insulating film 110bf in a manner that prevents the surface of the insulating film 110bf from being exposed to the atmosphere. For example, if a PECVD apparatus is used when forming the insulating film 110bf, it is preferable to use the PECVD apparatus for the plasma treatment. This can improve productivity. Specifically, after the insulating film 110bf is formed using a PECVD apparatus, N2O plasma treatment can be performed continuously.

[0465] Next, preferably a film 130 is formed on the insulating film 110bf. FIG. 35D When forming film 130, sputtering can be appropriately utilized. By forming film 130 in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110bf. FIG. 35C The arrows in the diagram schematically indicate the supply of oxygen to the insulating film 110bf.

[0466] There are no limitations on the conductivity of the film 130. The film 130 can be at least one of insulating films, semiconductor films, and conductive films. For example, the film 130 can be made of alumina, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO).

[0467] As the film 130, it is preferable to use an oxide material containing one or more elements that are the same as those in the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor that can be applied to the semiconductor layer 108.

[0468] When film 130 is formed, the higher the oxygen flow rate ratio of the deposition gas introduced into the processing chamber of the deposition apparatus, or the higher the oxygen partial pressure in the processing chamber, the greater the amount of oxygen supplied to the insulating film 110bf. The oxygen flow rate ratio or oxygen partial pressure is preferably 50% or more and 100% or less, more preferably 60% or more and 100% or less, further preferably 70% or more and 100% or less, even more preferably 80% or more and 100% or less, and even more preferably 90% or more and 100% or less. In particular, it is preferable to set the oxygen flow rate ratio to 100% so that the oxygen partial pressure is as close as possible to 100%.

[0469] Thus, by forming film 130 using sputtering in an oxygen-containing atmosphere, oxygen can be supplied to insulating film 110bf while preventing oxygen from escaping from insulating film 110bf during film formation. As a result, more oxygen can be confined within insulating film 110bf. Furthermore, more oxygen can be supplied to semiconductor layer 108 through subsequent heat treatment. Consequently, oxygen vacancies and Vo in semiconductor layer 108 can be reduced. O H, which can realize transistors that exhibit good electrical characteristics and high reliability.

[0470] Heat treatment can also be performed after film 130 is formed. By performing heat treatment after film 130 is formed, oxygen can be effectively supplied from film 130 to insulating film 110bf.

[0471] The heat treatment temperature is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, more preferably 300°C or higher and 400°C or lower, and more preferably 350°C or higher and 400°C or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, and oxygen. Clean dry air (CDA) can be used as the nitrogen-containing or oxygen-containing atmosphere. Note that the content of hydrogen, water, etc., in this atmosphere is preferably as low as possible. As this atmosphere, a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, is preferred. By using an atmosphere with the lowest possible content of hydrogen, water, etc., the absorption of hydrogen, water, etc., by the insulating films 110af and 110bf can be prevented as much as possible. This heat treatment can be performed using an oven, a rapid thermal annealing (RTA) apparatus, etc. Using an RTA apparatus can shorten the heat treatment time.

[0472] Oxygen can also be supplied to the insulating film 110bf through the film 130 after the formation of film 130 or after the above-described heat treatment. As a method of supplying oxygen, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used, for example. Regarding plasma treatment, please refer to the above description, so its detailed explanation is omitted.

[0473] Next, remove membrane 130 ( FIG. 35E While there are no particular restrictions on the method for removing film 130, wet etching can be appropriately employed. By using wet etching, etching of the insulating film 110bf during the removal of film 130 can be suppressed. Therefore, the reduction in the thickness of the insulating film 110bf can be suppressed, and the thickness of the insulating layer 110b can be made uniform.

[0474] The oxygen supply process for the insulating film 110bf is not limited to the methods described above. For example, oxygen free radicals, oxygen atoms, oxygen atom ions, or oxygen molecular ions can be supplied to the insulating film 110bf using ion doping, ion implantation, or plasma treatment. Alternatively, oxygen can be supplied to the insulating film 110bf after a film for inhibiting oxygen desorption is formed on the insulating film 110bf. Preferably, the film is removed after oxygen supply. As the aforementioned film for inhibiting oxygen desorption, conductive or semiconductor films containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten can be used.

[0475] Next, an insulating film 110cf, which becomes an insulating layer 110c, is formed on the insulating film 110bf. FIG. 36B When forming the insulating film 110cf, sputtering can be appropriately utilized. Oxygen can be supplied to the insulating film 110bf by forming the insulating film 110cf in an oxygen-containing atmosphere. FIG. 36A The arrows in the diagram schematically indicate the supply of oxygen to the insulating film 110bf.

[0476] When forming the insulating film 110cf, the higher the oxygen flow rate ratio or oxygen partial pressure of the deposition gas introduced into the processing chamber of the deposition apparatus, the greater the amount of oxygen supplied to the insulating film 110bf. The oxygen flow rate ratio or oxygen partial pressure is preferably 50% or more and 100% or less, more preferably 60% or more and 100% or less, further preferably 70% or more and 100% or less, even more preferably 80% or more and 100% or less, and even more preferably 90% or more and 100% or less. In particular, it is preferable to set the oxygen flow rate ratio to 100% so that the oxygen partial pressure is as close as possible to 100%.

[0477] Thus, by forming the insulating film 110cf in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110bf while preventing oxygen from escaping from the insulating film 110bf during its formation. As a result, more oxygen can be confined within the insulating film 110bf. Furthermore, a greater amount of oxygen can be supplied to the semiconductor layer 108 through subsequent heat treatment. Consequently, oxygen vacancies and Vo in the semiconductor layer 108 can be reduced. O H, which can realize transistors that exhibit good electrical characteristics and high reliability.

[0478] Heat treatment can also be performed after the insulating film 110cf is formed. By performing heat treatment after the insulating film 110cf is formed, oxygen can be effectively supplied from the insulating film 110cf to the insulating film 110bf.

[0479] Next, an insulating film 110ef (which becomes the insulating layer 110e) is formed on the insulating film 110cf. FIG. 36C When forming the insulating film 110ef, sputtering or PECVD methods can be appropriately used.

[0480] Next, a conductive film 112bf, which becomes a conductive layer 112b, is formed on the insulating film 110ef. FIG. 36D When forming the conductive film 112bf, sputtering can be appropriately utilized.

[0481] Next, conductive film 112bf is processed to form conductive layer 112B. FIG. 37A The conductive layer 112B will later become the conductive layer 112b. The formation of the conductive layer 112B can be, for example, suitably utilizing a wet etching method.

[0482] Next, a portion of the conductive layer 112B is removed to form a conductive layer 112b including the opening 143. A wet etching method can be appropriately used when forming the conductive layer 112b.

[0483] Next, a portion of insulating films 110af, 110bf, and 110cf is removed to form an insulating layer 110 including the opening 141. FIG. 37B An opening 141 is provided in the region overlapping with an opening 143. By forming an opening 141, the conductive layer 112a is exposed. When forming the insulating layer 110, a dry etching method can be appropriately used.

[0484] Opening 141 can be formed, for example, using a photoresist mask used to form opening 143. Specifically, a photoresist mask can be formed on conductive layer 112B, and a portion of conductive layer 112B can be removed using the photoresist mask to form opening 143, and portions of insulating films 110af, 110bf, and 110cf can be removed using the same photoresist mask to form opening 141. Opening 141 can also be formed using a different photoresist mask than the one used to form opening 143.

[0485] Next, a metal oxide film 108f, which forms the semiconductor layer 108, is formed in such a way that it covers openings 141 and 143. FIG. 37C The metal oxide film 108f is disposed in contact with the top and side surfaces of the conductive layer 112b, the top and side surfaces of the insulating layer 110, and the top surface of the conductive layer 112a.

[0486] The metal oxide film 108f is preferably formed using a sputtering method with a metal oxide target. Alternatively, the metal oxide film 108f is preferably formed using an ALD method. Because of its high coverage, the ALD method can be appropriately used when forming the metal oxide film 108f that covers the openings 141 and 143. By using the ALD method, a metal oxide film can also be formed with high coverage on the side of the insulating layer 110. Furthermore, the ALD method allows for easy control of the deposition rate, thus enabling the formation of thin films with high yield. Therefore, the ALD method is particularly suitable when the thickness of the metal oxide film 108f is small. Alternatively, when forming the metal oxide film 108f, a CVD method can be used instead of sputtering and the ALD method.

[0487] The metal oxide film 108f is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film 108f is preferably a high-purity film, wherein impurities containing hydrogen are minimized. In particular, a crystalline metal oxide film is preferably used as the metal oxide film 108f.

[0488] When forming the metal oxide film 108f, oxygen gas is preferably used. By using oxygen gas, oxygen can be suitably supplied to the insulating layer 110. For example, when an oxide or oxynitride is used as the insulating layer 110b, oxygen can be suitably supplied to the insulating layer 110b.

[0489] By supplying oxygen to the insulating layer 110b, and then supplying oxygen to the semiconductor layer 108 in subsequent processes, the oxygen vacancies and Vo in the semiconductor layer 108 can be reduced. O H.

[0490] When forming the metal oxide film 108f, oxygen gas and inert gas (e.g., helium, argon, xenon, etc.) can also be mixed. Note that the higher the oxygen flow rate ratio or oxygen partial pressure of the deposition gas during the formation of the metal oxide film, the higher the crystallinity of the metal oxide film can be, enabling the realization of highly reliable transistors. On the other hand, the lower the oxygen flow rate ratio or oxygen partial pressure, the more likely a metal oxide film with low crystallinity and high conductivity can be achieved, thereby enabling the realization of transistors with large on-state current.

[0491] Here, when the oxygen flow ratio or oxygen partial pressure is high, the metal oxide film sometimes exhibits a polycrystalline structure. In a polycrystalline metal oxide film, grain boundaries become recombination centers and trap charge carriers, thus sometimes reducing the on-state current of the transistor. Therefore, it is preferable to adjust the oxygen flow ratio or oxygen partial pressure to prevent the metal oxide film 108f from exhibiting a polycrystalline structure. Since the composition of the metal oxide film varies, it is preferable to adjust the oxygen flow ratio or oxygen partial pressure according to the composition of the metal oxide film 108f.

[0492] At higher substrate temperatures during metal oxide film formation, more crystalline and denser metal oxide films can be formed. This allows for the development of transistors with high reliability. Conversely, as the substrate temperature decreases, less crystalline metal oxide films with higher conductivity can be formed. This allows for the development of transistors with high on-state current.

[0493] The substrate temperature for forming the metal oxide film 108f is preferably above room temperature and below 250°C, more preferably above room temperature and below 200°C, and even more preferably above room temperature and below 140°C. For example, the substrate temperature is preferably above room temperature and below 140°C, which can improve productivity. In addition, crystallinity can be reduced by setting the substrate temperature to room temperature or forming the metal oxide film without heating the substrate.

[0494] Note that at high substrate temperatures, metal oxide films sometimes exhibit a polycrystalline structure. It is preferable to vary the substrate temperature according to the composition of the material used in the metal oxide film 108f.

[0495] When using ALD methods, thermal ALD or PEALD (Plasma Enhanced ALD) deposition methods are preferred. Thermal ALD is preferred because it offers extremely high coverage. Furthermore, PEALD not only offers high coverage but also allows for low-temperature deposition, making it a preferred method as well.

[0496] Metal oxide films can be formed, for example, using precursors containing constituent metal elements and oxidants, and employing the ALD method.

[0497] For example, when forming In-Ga-Zn oxide, three precursors can be used: one containing indium, one containing gallium, and one containing zinc. Alternatively, two precursors can be used: one containing indium, and one containing both gallium and zinc.

[0498] Examples of indium-containing precursors include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptadecanoic acid)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amide]-indium.

[0499] Examples of gallium-containing precursors include trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamide)gallium(III), gallium acetylacetonate(III), tris(2,2,6,6-tetramethyl-3,5-heptadecanoate)gallium, dimethylgallium chloride, and diethylgallium chloride.

[0500] As aluminum-containing precursors, aluminum chloride and trimethylaluminum can be used, for example.

[0501] Examples of tin-containing precursors include tin(IV) chloride and tetra(dimethylamide)tin.

[0502] Examples of zinc-containing precursors include dimethyl zinc, diethyl zinc, bis(2,2,6,6-tetramethyl-3,5-heptadecanoic acid) zinc, and zinc chloride.

[0503] Examples of oxidizing agents include ozone, oxygen, and water.

[0504] As a method for controlling the composition of the obtained membrane, one or more of the following can be adjusted: the type of source gas, the flow rate ratio of the source gas, the time during which the source gas flows through, and the order in which the source gas flows through. By adjusting these parameters, the composition of the metal oxide film 108f can be controlled. Furthermore, by adjusting these parameters, a metal oxide film 108f whose composition continuously varies can be formed.

[0505] Before depositing the metal oxide film 108f, it is preferable to perform at least one of the following: a treatment to remove water, hydrogen, and organic matter adsorbed on the surface of the insulating layer 110, and a treatment to supply oxygen to the insulating layer 110. For example, a heating treatment can be performed at a temperature of 70°C or higher and 200°C or lower under a reduced pressure atmosphere. Alternatively, a plasma treatment in an oxygen-containing atmosphere can be performed. Alternatively, oxygen can be supplied to the insulating layer 110 by performing a plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (N₂O). When performing a plasma treatment containing nitrous oxide gas, organic matter on the surface of the insulating layer 110 can be appropriately removed and oxygen can be supplied to the insulating layer 110. Preferably, after such treatment, the metal oxide film 108f is continuously deposited in a manner that does not expose the surface of the insulating layer 110 to the atmosphere.

[0506] Note that when the semiconductor layer 108 has a stacked structure, it is preferable to deposit the upper metal oxide film continuously after depositing the lower metal oxide film in a manner that does not expose its surface to the atmosphere.

[0507] When the semiconductor layer 108 has a stacked structure, all layers constituting the semiconductor layer 108 can be formed using the same deposition method (e.g., sputtering or ALD). Alternatively, different deposition methods can be used depending on the layer. For example, a first metal oxide layer can be deposited using sputtering, and a second metal oxide layer can be deposited using ALD.

[0508] Next, the metal oxide film 108f is processed into islands, thereby forming the semiconductor layer 108. FIG. 37D ).

[0509] When forming the semiconductor layer 108, a wet etching method can be appropriately used. Sometimes, a portion of the conductive layer 112b in a region that does not overlap with the semiconductor layer 108 is etched, resulting in a reduced thickness. Similarly, sometimes a portion of the insulating layer 110 in a region that does not overlap with either the semiconductor layer 108 or the conductive layer 112b is etched, resulting in a reduced thickness. For example, sometimes the insulating layer 110c in the insulating layer 110 disappears due to etching, exposing the surface of the insulating layer 110b. Note that in the etching of the metal oxide film 108f, by using a material with a high selectivity as the insulating layer 110c, the reduction in the thickness of the insulating layer 110c can be suppressed.

[0510] Preferably, the heat treatment is performed after depositing the metal oxide film 108f or after processing the metal oxide film 108f into a semiconductor layer 108. Heat treatment can remove hydrogen and water contained in the metal oxide film 108f or the semiconductor layer 108 or adsorbed on its surface. Furthermore, heat treatment can sometimes improve the film quality of the metal oxide film 108f or the semiconductor layer 108 (e.g., reduce defects or increase crystallinity).

[0511] Oxygen can be supplied from the insulating layer 110b to the metal oxide film 108f or the semiconductor layer 108 through heat treatment. More preferably, the heat treatment is performed before processing into the semiconductor layer 108. Details regarding the heat treatment can be found above, so further explanation is omitted.

[0512] Note that this heat treatment can be omitted if not required. Alternatively, a heat treatment performed in a later process can be used instead of this heat treatment. Sometimes, a heat treatment performed in a later process (e.g., a deposition process) can be used as the heat treatment for this process.

[0513] Next, an insulating layer 106 is formed in such a manner that it covers the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110. FIG. 38 When forming the insulating layer 106, methods such as PECVD, sputtering, or ALD can be appropriately used.

[0514] When an oxide semiconductor is used in the semiconductor layer 108, the insulating layer 106 is preferably used as a barrier film to suppress oxygen diffusion. By giving the insulating layer 106 the function of suppressing oxygen diffusion, the diffusion of oxygen from the upper side of the insulating layer 106 to the conductive layer 104 can be suppressed, thereby suppressing the oxidation of the conductive layer 104. As a result, a transistor exhibiting good electrical characteristics and high reliability can be realized.

[0515] By increasing the temperature at which the insulating layer 106 is formed to serve as the gate insulating layer, an insulating layer with fewer defects can be formed. However, at higher temperatures when the insulating layer 106 is formed, oxygen escapes from the semiconductor layer 108, and sometimes oxygen vacancies and V in the semiconductor layer 108... O H increases. The substrate temperature during the formation of the insulating layer 106 is preferably 180°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, and even more preferably 300°C or higher and 400°C or lower. By keeping the substrate temperature during the formation of the insulating layer 106 within the above range, defects in the insulating layer 106 can be reduced while oxygen detachment from the semiconductor layer 108 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be realized.

[0516] Plasma treatment can be performed on the surface of the semiconductor layer 108 before forming the insulating layer 106. This plasma treatment reduces impurities such as water adsorbed on the surface of the semiconductor layer 108. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 106 can be reduced, resulting in a transistor with high reliability. In particular, plasma treatment is preferred when the surface of the semiconductor layer 108 is exposed to the atmosphere between the formation of the semiconductor layer 108 and the formation of the insulating layer 106. The plasma treatment can be performed, for example, in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, or argon. The plasma treatment and the deposition of the insulating layer 106 are preferably performed continuously without exposure to the atmosphere.

[0517] Next, a conductive layer 104 is formed on the insulating layer 106. FIG. 11A and FIG. 11B When forming the conductive film that becomes the conductive layer 104, sputtering, thermal CVD (including MOCVD), or ALD can be appropriately used, for example.

[0518] The semiconductor device 10C of one aspect of the present invention can be manufactured through the above-described process.

[0519] <Example 2 of Manufacturing Method> illustrate FIG. 7A and FIG. 7B An example of a method for manufacturing the semiconductor device 10A shown. FIG. 39 Show side by side along FIG. 1A The cross-sectional view along the dotted-dash line A1-A2 and the cross-sectional view along the dotted-dash line B1-B2.

[0520] First, the formation of the insulating layer 106 is performed in the same manner as in <Manufacturing Method Example 1>. The method for forming the insulating layer 106 can be referred to the method shown in Manufacturing Method Example 1 above. FIGS. 35A-38 The explanation is as described above, so detailed instructions are omitted.

[0521] Next, impurity element 189 is added to semiconductor layer 108. FIG. 39 Region 108D was formed by adding impurity element 189.

[0522] It is preferable to add impurity element 189 along a direction perpendicular to or substantially perpendicular to the top surface of substrate 102. In this case, as described above, the amount of impurity element added in the region of semiconductor layer 108 inclined to the top surface of substrate 102 is less than that in the region parallel to or substantially parallel to the top surface of substrate 102. In other words, the amount of impurity element added in the source and drain regions of semiconductor layer 108 is greater than that in the channel formation region. Therefore, the resistance of the source and drain regions can be preferentially reduced. When impurity element 189 is added to semiconductor layer 108, oxygen vacancies (V0) are sometimes generated in semiconductor layer 108.O Alternatively, when impurity element 189 is added to semiconductor layer 108, sometimes impurity element 189 interacts with oxygen vacancies (V) in semiconductor layer 108. O ) bond.

[0523] Furthermore, impurity element 189 is preferably added to semiconductor layer 108 via insulating layer 106. The thickness of insulating layer 106 in the direction of impurity element 189 addition varies depending on its location. Therefore, regions with a high amount of impurity element 189 and regions with a low amount of impurity element 189 are formed in semiconductor layer 108. Specifically, the amount of impurity element added in the region disposed along the top surface of conductive layer 112a or the top surface of conductive layer 112b in semiconductor layer 108 is higher than that in the region disposed along the side surface of insulating layer 110. In this way, the addition of impurity element to the channel formation region of semiconductor layer 108 can be suppressed, and the resistance of the source and drain regions can be preferentially reduced. At this time, impurity element 189 is also supplied to insulating layer 106.

[0524] FIG. 39 An example is shown in which region 108D is formed in the semiconductor layer 108, the region disposed along the top surface of the conductive layer 112a and the region disposed along the top surface of the conductive layer 112b.

[0525] The elements that can be used as impurity element 189 are as described above.

[0526] Impurity element 189 can be supplied using plasma ion doping or ion implantation. By using these methods, the concentration distribution in the depth direction can be controlled with high precision based on factors such as ion acceleration voltage and dosage.

[0527] By using ion implantation, which involves mass separation of the ionized source gas, the purity of the supplied impurity element can be improved. When using ion implantation, the aforementioned first element is preferably used as impurity element 189, and boron or phosphorus is more preferably used. By using an element that is stable by bonding with oxygen as impurity element 189, a stable region 108D under low electrical resistance can be achieved.

[0528] Furthermore, productivity can be improved by utilizing plasma ion doping, which involves adding elements without mass separation of the ionized source gas. When using plasma ion doping, the impurity element 189 is preferably a combination of the first element and hydrogen, and more preferably a combination of boron or phosphorus and hydrogen. By using a combination of an element stable by bonding with oxygen and hydrogen as impurity element 189, the resistance of region 108D is easily reduced, and a stable low resistance state can be maintained.

[0529] The ion implantation or ion doping equipment used to supply impurity element 189 is also used in the manufacture of Si transistors such as LTPS transistors. Therefore, it is preferred to use equipment from existing LTPS production lines without requiring new equipment investment. This reduces the initial equipment investment cost when manufacturing semiconductor devices.

[0530] In the supply processing of impurity element 189, it is preferable to control the processing conditions so that the concentration of the impurity element in the portion of the semiconductor layer 108 overlapping with the conductive layer 112a or conductive layer 112b is higher than the concentration of the impurity element in other regions. This allows for the supply of an optimal concentration of impurity element 189 to the source and drain regions of the semiconductor layer 108.

[0531] As the source gas for impurity element 189, a gas containing the aforementioned impurity element can be used. When supplying boron, B₂H₆ gas or BF₃ gas is typically used. Furthermore, when supplying phosphorus, PH₃ gas is typically used. Alternatively, a mixture of these source gases diluted with hydrogen or a rare gas can also be used.

[0532] In addition to the above, source gases can include CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and rare gases. Furthermore, the ion source is not limited to gases; solids or liquids can also be heated to vaporize them.

[0533] For example, it is preferable to use a gas supply containing boron and hydrogen as impurity element 189. In this case, impurity element 189 can be added without mass separation, and the resistance of semiconductor layer 108 can be easily reduced, thus improving the productivity and characteristics of the semiconductor device, which is therefore preferred.

[0534] By setting conditions such as accelerating voltage and dosage according to the composition, density, and thickness of insulating layer 106 and semiconductor layer 108, the supply of impurity element 189 can be controlled.

[0535] Note that there are no restrictions on the method of supplying impurity element 189; for example, plasma treatment or treatment using thermal diffusion caused by heating can also be performed. In the case of plasma treatment, the impurity element can be supplied by first generating plasma in a gas atmosphere containing the supplied halogen, and then performing plasma treatment. As the apparatus for generating the plasma, dry etching apparatus, ashing apparatus, plasma CVD apparatus, or high-density plasma CVD apparatus can be used, etc.

[0536] In one embodiment of the invention, impurity element 189 can be supplied to semiconductor layer 108 through insulating layer 106. This suppresses the decrease in crystallinity of semiconductor layer 108 when impurity element 189 is supplied. Therefore, the increase in resistance caused by decreased crystallinity can be suppressed.

[0537] Furthermore, there is a concern about contamination of the deposition chamber of the insulation layer 106 when the impurity element 189 is deposited after its addition. Therefore, it is preferable to add the impurity element 189 after the insulation layer 106 is deposited.

[0538] Alternatively, an insulating layer 106 can be deposited on the semiconductor layer 108 after the impurity element 189 is directly added to the semiconductor layer 108. This can suppress damage to the insulating layer 106 caused by the addition of the impurity element 189.

[0539] Preferably, the impurity element 189 is supplied simultaneously with heating the substrate 102. This allows for the repair of damage to the semiconductor layer 108 caused by the addition of the impurity element 189. In other words, the addition of the impurity element 189 and the repair of any damage resulting from this addition can be performed on the semiconductor layer 108 in parallel. Furthermore, damage to the insulating layer 106 caused by the addition of the impurity element 189 can also be repaired. Note that one aspect of the invention is not limited to this; the impurity element 189 supply process can be performed without heating the substrate 102.

[0540] The substrate temperature in the supply process of impurity element 189 is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and lower than 500°C, more preferably 200°C or higher and lower than 450°C, more preferably 250°C or higher and lower than 400°C, more preferably 250°C or higher and lower than 350°C, or preferably 300°C or higher and lower than 400°C, more preferably 300°C or higher and lower than 350°C.

[0541] Alternatively, a heat treatment can be performed after the supply of impurity element 189. This heat treatment can repair any damage to the semiconductor layer 108 and the insulating layer 106 that occurred during the supply process of impurity element 189.

[0542] Note that if the heat treatment temperature is too high, the resistance of region 108D, the contact resistance between region 108D and conductive layer 112a, and the contact resistance between region 108D and conductive layer 112b may increase. Therefore, the heat treatment temperature after adding impurity element 189 is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and lower than 500°C, more preferably 200°C or higher and lower than 450°C, more preferably 250°C or higher and lower than 400°C, more preferably 250°C or higher and lower than 350°C, or preferably 300°C or higher and lower than 400°C, more preferably 300°C or higher and lower than 350°C.

[0543] By using an element that becomes stable through bonding with oxygen as impurity element 189, the detachment of impurity element 189 during the heating process can be suppressed. Therefore, even after a heating process following the addition of impurity element 189, the resistance of region 108D can be kept low.

[0544] Next, a conductive layer 104 is formed on the insulating layer 106. FIG. 7A and FIG. 7B Since the formation of the conductive layer 104 can be referred to in <Example 1 of Manufacturing Method> above, detailed description is omitted.

[0545] The semiconductor device 10A of one aspect of the present invention can be manufactured through the above-described process.

[0546] This implementation method can be appropriately combined with other implementation methods.

[0547] (Implementation Method 3) In this embodiment, refer to FIGS. 40-4 8. A display device according to one aspect of the present invention.

[0548] The display device in this embodiment can be a high-resolution display device or a large-screen display device. Therefore, the display device in this embodiment can be used as a display unit for devices such as: electronic devices with large screens, such as televisions, desktop or laptop computers, monitors for computers, digital signage, large game machines such as pinball machines, etc.; digital cameras; digital video cameras; digital photo frames; mobile phones; portable game consoles; portable information terminals; and sound reproduction devices.

[0549] The display device in this embodiment can be a high-definition display device. Therefore, for example, the display device in this embodiment can be used as the display unit of information terminal devices (wearable devices) such as watch-type and bracelet-type devices, as well as the display unit of wearable devices that can be worn on the head, such as VR devices such as head-mounted displays (HMDs) and AR devices such as glasses-type devices.

[0550] One aspect of the semiconductor device of the present invention can be used in a display device or a module including the display device. Examples of modules including the display device include modules in which the display device is mounted with connectors such as flexible printed circuit boards (FPC) or TCP (Tape Carrier Package), and modules in which integrated circuits (ICs) are mounted via COG (Chip On Glass) or COF (Chip On Film) methods.

[0551] The display device of this embodiment can also have the function of a touch panel. For example, various detection elements (or sensor elements) capable of detecting the approach or contact of a detection object such as a finger can also be used in the display device.

[0552] Examples of sensor types include capacitive, resistive film, surface acoustic wave, infrared, optical, and pressure-sensitive types.

[0553] As electrostatic capacitive types, there are surface-type electrostatic capacitive types and projection-type electrostatic capacitive types. Furthermore, as projection-type electrostatic capacitive types, there are self-capacitance types and mutual-capacitance types. Mutual-capacitance types are preferred because they allow for simultaneous multi-point sensing.

[0554] Examples of touch panels include Out-Cell, On-Cell, and In-Cell types. Note that an In-Cell type touch panel refers to a structure in which electrodes constituting the detection element are provided on one or both of the substrate supporting the display element and the opposing substrate.

[0555] <Display Device 50A> FIG. 40 A perspective view of the display device 50A is shown.

[0556] The display device 50A has a structure that bonds substrate 152 and substrate 151. FIG. 40 In the image, substrate 152 is represented by a dashed line.

[0557] The display device 50A includes a display section 162, a connection section 140, a circuit section 164, a conductive layer 165, etc. FIG. 40 An example is shown where display device 50A is equipped with IC173 and FPC172. Therefore, it is also possible to... FIG. 40 The structure shown is called a display module, which includes display device 50A, IC, and FPC.

[0558] The connecting portion 140 is disposed on the outer side of the display portion 162. The connecting portion 140 may be disposed along one or more edges of the display portion 162. There may also be one or more connecting portions 140. FIG. 40 An example is shown in which the connecting portions 140 are arranged around the four sides of the display portion 162. In the connecting portions 140, the common electrode of the display element is electrically connected to the conductive layer, and a potential can be supplied to the common electrode.

[0559] The circuit section 164 may include, for example, a scan line driving circuit (also known as a gate driver). Alternatively, the circuit section 164 may include both a scan line driving circuit and a signal line driving circuit (also known as a source driver).

[0560] The conductive layer 165 has the function of supplying signals and power to the display unit 162 and the circuit unit 164. The signals and power are input to the conductive layer 165 from the outside via FPC 172 or from IC 173.

[0561] FIG. 40 An example is shown where IC 173 is mounted on substrate 151 using a COG or COF method. IC 173 can be, for example, an IC that includes one or both of a scan line drive circuit and a signal line drive circuit. Note that the display device 50A and the display module do not necessarily need to have an IC mounted on them. Alternatively, the IC can also be mounted on an FPC using a COF method or the like.

[0562] One aspect of the semiconductor device of the present invention can be used, for example, in one or both of the display section 162 and the circuit section 164 of the display device 50A. The channel forming region of the transistors included in the display device can suitably use oxide semiconductor (OS) transistors. By using OS transistors, a low-power display device can be realized. Alternatively, the semiconductor device of one aspect of the present invention can be used in both the display section 162 and the circuit section 164, that is, all transistors included in the display device can be OS transistors. Thus, by using OS transistors as all transistors included in the display device, the effect of reducing manufacturing costs is achieved.

[0563] For example, when the semiconductor device of one aspect of the present invention is used in the pixel circuit of a display device, the occupied area of ​​the pixel circuit can be reduced, and a high-definition display device can be realized. Furthermore, for example, when the semiconductor device of one aspect of the present invention is used in the driving circuit of a display device (e.g., one or both of a gate line driving circuit and a source line driving circuit), the occupied area of ​​the driving circuit can be reduced, thus enabling a display device with a narrow bezel. Additionally, the semiconductor device of one aspect of the present invention has excellent electrical characteristics; by using this semiconductor device in a display device, the reliability of the display device can be improved.

[0564] Display unit 162 is an image display area in display device 50A, and includes a plurality of pixels 201 arranged periodically. FIG. 40 The image shown is a magnified view of pixel 201.

[0565] There are no particular limitations on the arrangement of pixels in the display device of this embodiment, and various methods can be used. Examples of pixel arrangements include stripe arrangement, S-stripe arrangement, matrix arrangement, Delta arrangement, Bayer arrangement, and Pentile arrangement.

[0566] FIG. 40 The pixel 201 shown includes a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light. Note that there is no particular limitation on the number of sub-pixels included in a pixel.

[0567] Subpixels 11R, 11G, and 11B all include a display element and a circuit that controls the driving of the display element.

[0568] Various components can be used as display elements, such as liquid crystal elements and light-emitting elements. In addition, MEMS (Micro Electro Mechanical Systems) elements using shutter-based or optical interference methods, as well as display elements employing microencapsulation, electrophoresis, electrowetting, or electronic powder fluid methods (registered trademark), can be used. Furthermore, QLEDs (Quantum-dot LEDs) can also be used, utilizing light sources and color conversion technology based on quantum dot materials.

[0569] Examples of display devices using liquid crystal elements include transmissive liquid crystal displays, reflective liquid crystal displays, and transflective liquid crystal displays.

[0570] Examples of display device modes that can be used with liquid crystal elements include Vertical Alignment (VA) mode, FFS (Fringe Field Switching) mode, IPS (In-Plane-Switching) mode, TN (Twisted Nematic) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Anti-Ferroelectric Liquid Crystal) mode, ECB (Electrically Controlled Birefringence) mode, and guest-host mode. Examples of VA modes include MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, and ASV (Advanced Super View) mode.

[0571] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low-molecular-weight liquid crystals, high-molecular-weight liquid crystals, polymer-dispersed liquid crystals (PDLCs), polymer network liquid crystals (PNLCs), ferroelectric liquid crystals, and antiferroelectric liquid crystals. These liquid crystal materials exhibit cholesteric, smectic, cubic, chiral nematic, isotropic, and blue phases, depending on the conditions. Furthermore, either positive or negative liquid crystals can be used as liquid crystal materials, and the choice can be made based on the mode or design used.

[0572] Examples of light-emitting elements include self-emissive light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers. For example, small LEDs and micro LEDs can be used as LEDs.

[0573] Light-emitting materials contained in light-emitting elements include, for example, substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials), and inorganic compounds (quantum dot materials, etc.).

[0574] The light-emitting element can emit colors such as infrared, red, green, blue, cyan, magenta, yellow, or white. Furthermore, when the light-emitting element has a microcavity structure, the color purity can be further improved.

[0575] In a light-emitting element, one electrode is used as the anode and the other electrode is used as the cathode.

[0576] In addition, the display device of one aspect of the present invention may also adopt any of the following structures: top surface emission type that emits light in the direction opposite to the substrate on which the light-emitting element is formed, bottom surface emission type that emits light in the direction on which the light-emitting element is formed, and dual emission type that emits light in both directions.

[0577] FIG. 41A An example of a cross-section of a portion of the display device 50A including the region of FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the region including the end is shown.

[0578] FIG. 41A The display device 50A shown includes transistors 205D, 205R, 205G, 205B, light-emitting elements 130R, 130G, and 130B, etc., between substrates 151 and 152. Light-emitting element 130R is a display element included in sub-pixel 11R that emits red light, light-emitting element 130G is a display element included in sub-pixel 11G that emits green light, and light-emitting element 130B is a display element included in sub-pixel 11B that emits blue light.

[0579] The display device 50A adopts an SBS structure. In the SBS structure, the materials and structures of each light-emitting element can be optimized separately, increasing the freedom of material and structure selection, thereby making it easier to improve brightness and reliability.

[0580] The display device 50A adopts a top-emitting type. In the top-emitting type, transistors and the like can be arranged in a manner that overlaps with the light-emitting area of ​​the light-emitting element, so the pixel aperture ratio can be further improved compared with the bottom-emitting type.

[0581] Transistors 205D, 205R, 205G, and 205B are all formed on substrate 151. These transistors can be manufactured using the same process. Alternatively, transistors 205D, 205R, 205G, and 205B can also be transistors with different structures.

[0582] In this embodiment, an example of using OS transistors as transistors 205D, 205R, 205G, and 205B is shown. Transistors 205D, 205R, 205G, and 205B can be transistors according to one aspect of the present invention. That is, in the display device 50A, both the display unit 162 and the circuit unit 164 include transistors according to one aspect of the present invention. By using transistors according to one aspect of the present invention in the display unit 162, pixel size can be reduced, thereby achieving high definition. Furthermore, by using transistors according to one aspect of the present invention in the circuit unit 164, the area occupied by the circuit unit 164 can be reduced, thereby achieving narrow bezels. For details regarding transistors according to one aspect of the present invention, please refer to the description of the above embodiment.

[0583] Specifically, transistors 205D, 205R, 205G, and 205B all include a conductive layer 104 serving as a gate, an insulating layer 106 serving as a gate insulating layer, conductive layers 112a and 112b serving as source and drain, a semiconductor layer 108 comprising a metal oxide, and an insulating layer 110. Here, the multiple layers obtained by processing the same conductive film are shaded with the same lines. The insulating layer 110 is located between conductive layers 112a and 112b. The insulating layer 106 is located between conductive layer 104 and semiconductor layer 108.

[0584] Note that the transistors included in the display device of this embodiment are not limited to the transistors of one aspect of the present invention. For example, transistors including one aspect of the present invention and transistors with other structures may also be combined.

[0585] The display device of this embodiment may include, for example, any one or more of planar transistors, interleaved transistors, and anti-interleaved transistors. The transistors included in the display device of this embodiment have either a top-gate or bottom-gate structure. Alternatively, gates may be disposed above and below the semiconductor layer forming the channel.

[0586] The display device in this embodiment may also include Si transistors.

[0587] To increase the luminous brightness of the light-emitting element included in a pixel circuit, it is necessary to increase the current flowing through the light-emitting element. This requires increasing the source-drain voltage of the driving transistor included in the pixel circuit. Because the source-drain breakdown voltage of an OS transistor is higher than that of a Si transistor, a higher voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor in the pixel circuit, the current flowing through the light-emitting element can be increased, thereby improving the luminous brightness of the light-emitting element.

[0588] When a transistor operates in the saturation region, an OS transistor, compared to a Si transistor, allows for a smaller change in the source-drain current in response to changes in the gate-source voltage. Therefore, by using an OS transistor as the driving transistor in a pixel circuit, the current flowing through the source-drain can be precisely determined based on the gate-source voltage change, thus controlling the amount of current flowing through the light-emitting element. This, in turn, increases the grayscale level of the pixel circuit.

[0589] Regarding the saturation of current flowing through a transistor when it operates in the saturation region, compared to a Si transistor, an OS transistor can maintain a stable current (saturation current) even when the source-drain voltage is gradually increased. Therefore, by using an OS transistor as a driving transistor, a stable current can flow through the light-emitting element even if the current-voltage characteristics of the element, for example, become non-uniform. In other words, when an OS transistor operates in the saturation region, the source-drain current remains almost constant even when the source-drain voltage is changed, thus stabilizing the brightness of the light-emitting element.

[0590] The transistors included in the circuit section 164 and the transistors included in the display section 162 can have the same structure or different structures. The multiple transistors included in the circuit section 164 can have the same structure or two or more different structures. Similarly, the multiple transistors included in the display section 162 can have the same structure or two or more different structures.

[0591] All transistors included in the display unit 162 can be OS transistors, all transistors included in the display unit 162 can be Si transistors, some transistors included in the display unit 162 can be OS transistors and the remaining transistors can be Si transistors.

[0592] For example, by using both LTPS transistors and OS transistors in the display section 162, a display device with low power consumption and high driving capability can be realized. Furthermore, the structure combining LTPS transistors and OS transistors is sometimes referred to as LTPO. Moreover, as a more preferred example, a structure can be described in which the OS transistor is used as a transistor having a switching function that controls the conduction and non-conduction between wirings, and the LTPS transistor is used as a transistor for controlling current.

[0593] For example, one of the transistors included in the display unit 162 can also be used as a transistor to control the current flowing through the light-emitting element, and is referred to as a driving transistor. One of the source and drain of the driving transistor is electrically connected to the pixel electrode of the light-emitting element. An LTPS transistor is preferably used as this driving transistor. This increases the current flowing through the light-emitting element in the pixel circuit.

[0594] On the other hand, one of the other transistors included in the display unit 162 can also be used as a switch to control the selection and non-selection of pixels, and is referred to as a selection transistor. The gate of the selection transistor is electrically connected to the gate line, and one of the source and drain is electrically connected to the source line (signal line). An OS transistor is preferably used as the selection transistor. Therefore, even with a significantly low frame rate (e.g., below 1 fps), the grayscale of the pixels can be maintained, thereby reducing power consumption by stopping the driver when displaying static images.

[0595] An insulating layer 218 is provided to cover transistors 205D, 205R, 205G, and 205B, and an insulating layer 235 is provided on the insulating layer 218.

[0596] The insulating layer 218 is preferably used as a protective layer for the transistor. The insulating layer 218 is preferably made of a material from which impurities such as water and hydrogen do not easily diffuse. Therefore, the insulating layer 218 can be used as a barrier film. By employing this structure, the diffusion of impurities from the outside into the transistor can be effectively suppressed, thereby improving the reliability of the display device.

[0597] The insulating layer 218 preferably comprises one or more inorganic insulating layers. The insulating layer 218 may be made of a material that is also suitable for the insulating layer 110.

[0598] The insulating layer 235 is preferably used as a planarization layer, and an organic insulating film is appropriately used. Materials suitable for use as organic insulating films include, for example, acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimide amide resin, silicone resin, benzocyclobutene resin, phenolic resin, and precursors of these resins. Furthermore, the insulating layer 235 can also be a laminated structure of organic and inorganic insulating films. The outermost layer of the insulating layer 235 is preferably used as an etching protection layer. Therefore, when processing the pixel electrodes 111R, 111G, 111B, etc., the formation of recesses in the insulating layer 235 can be suppressed. Alternatively, recesses can be formed in the insulating layer 235 during the processing of the pixel electrodes 111R, 111G, 111B, etc. Additionally, pixel electrodes 111R, 111G, and 111B are sometimes collectively referred to as pixel electrode 111.

[0599] Light-emitting elements 130R, 130G, and 130B are disposed on the insulating layer 235.

[0600] The light-emitting element 130R includes a pixel electrode 111R on an insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R. FIG. 41A The light-emitting element 130R shown emits red light (R). The EL layer 113R includes a light-emitting layer that emits red light.

[0601] The light-emitting element 130G includes a pixel electrode 111G on an insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G. FIG. 41A The light-emitting element 130G shown emits green light (G). The EL layer 113G includes a light-emitting layer that emits green light.

[0602] The light-emitting element 130B includes a pixel electrode 111B on an insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B. FIG. 41A The light-emitting element 130B shown emits blue light (B). The EL layer 113B includes a light-emitting layer that emits blue light.

[0603] Note that in FIG. 41A The EL layers 113R, 113G, and 113B are shown with the same thickness, but this is not a limitation. The thicknesses of the EL layers 113R, 113G, and 113B can also be different. For example, it is preferable to set the thickness to enhance the optical path of the light emitted by the EL layers 113R, 113G, and 113B. This allows for the realization of a microcavity structure to improve the color purity of the light emitted from each light-emitting element.

[0604] Pixel electrode 111R is electrically connected to the conductive layer 112b of transistor 205R through openings provided in insulating layers 106, 218, and 235. Similarly, pixel electrode 111G is electrically connected to the conductive layer 112b of transistor 205G, and pixel electrode 111B is electrically connected to the conductive layer 112b of transistor 205B.

[0605] Each end of pixel electrodes 111R, 111G, and 111B is covered by an insulating layer 237. The insulating layer 237 serves as a partition wall. The insulating layer 237 can be configured as a single layer or a multilayer structure using one or both of inorganic and organic insulating materials. For example, the insulating layer 237 can use materials suitable for insulating layer 218 and insulating layer 235. The insulating layer 237 electrically insulates the pixel electrodes from the common electrode. Furthermore, the insulating layer 237 electrically insulates adjacent light-emitting elements.

[0606] An insulating layer 237 is provided at least in the display section 162. The insulating layer 237 can be provided not only in the display section 162, but also in the connecting section 140 and the circuit section 164. Furthermore, the insulating layer 237 can also be provided at the end of the display device 50A.

[0607] The common electrode 115 is a continuous film shared by the light-emitting elements 130R, 130G, and 130B. The common electrode 115 shared by multiple light-emitting elements is electrically connected to the conductive layer 123 disposed in the connection portion 140. The conductive layer 123 is preferably a conductive layer formed using the same material and process as the pixel electrodes 111R, 111G, and 111B.

[0608] In one aspect of the display device of the present invention, a conductive film that transmits visible light is used as the electrode on the light-extracting side of both the pixel electrode and the common electrode. Furthermore, a conductive film that reflects visible light is preferably used as the electrode on the non-light-extracting side.

[0609] The electrode on the side that does not extract light can also be a conductive film that transmits visible light. In this case, it is preferable to place the electrode between the reflective layer and the EL layer. In other words, the light emitted from the EL layer can also be reflected by the reflective layer and extracted from the display device.

[0610] Metals, alloys, conductive compounds, and mixtures thereof can be appropriately used as materials for the pair of electrodes forming the light-emitting element. Specifically, examples of such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, as well as alloys appropriately combined with them. Additionally, examples of such materials include indium tin oxide (In-Sn oxide, also known as ITO), In-Si-Sn oxide (also known as ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Furthermore, examples of such materials include aluminum alloys such as aluminum-nickel-lanthanum alloys (Al-Ni-La), silver alloys such as silver-magnesium alloys, and silver-palladium-copper alloys such as silver-Pd-Cu alloys (Ag-Pd-Cu, also abbreviated as APC). In addition, as materials, examples include elements belonging to Group 1 or Group 2 of the periodic table (e.g., lithium, cesium, calcium, strontium), rare earth metals such as europium and ytterbium, alloys of these elements in appropriate combinations, and graphene.

[0611] The light-emitting element preferably employs a mi...

Claims

1. A semiconductor device, comprising: transistor; as well as First insulating layer, The transistor includes a semiconductor layer, a first conductive layer, and a second conductive layer. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer. The first insulating layer includes a first opening leading to the first conductive layer. The second conductive layer includes a second opening in the region overlapping with the first opening. The semiconductor layer has regions in the first opening and the second opening that contact the top surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer. The first insulating layer includes a second insulating layer and a third insulating layer on the second insulating layer. The second insulating layer comprises silicon and oxygen. Furthermore, the third insulating layer comprises one or both of aluminum and hafnium, as well as oxygen.

2. The semiconductor device according to claim 1, The semiconductor layer comprises a metal oxide.

3. The semiconductor device according to claim 1 or 2, The first insulating layer includes a fourth insulating layer. The fourth insulating layer is located between the first conductive layer and the second insulating layer. Furthermore, the fourth insulating layer comprises silicon and nitrogen.

4. The semiconductor device according to claim 3, The first insulating layer includes a fifth insulating layer and a sixth insulating layer. The fifth insulating layer is located between the first conductive layer and the fourth insulating layer. The sixth insulating layer is located between the second conductive layer and the third insulating layer. The fifth insulating layer comprises silicon and nitrogen. The sixth insulating layer comprises silicon and nitrogen. Furthermore, the fifth insulating layer has a region with a higher hydrogen content than the fourth insulating layer.

5. The semiconductor device according to claim 3, further comprising: The fifth insulating layer, The first insulating layer includes a sixth insulating layer. The top surface of the fifth insulating layer has a region that contacts the bottom surface of the first conductive layer. The sixth insulating layer is located between the second conductive layer and the third insulating layer. The fifth insulating layer comprises silicon and nitrogen. The sixth insulating layer comprises silicon and nitrogen. Furthermore, the fifth insulating layer has a region with a higher hydrogen content than the fourth insulating layer.

6. The semiconductor device according to claim 1 or 2, The semiconductor layer has a first region that contacts the top surface of the first conductive layer and a second region that contacts the top surface of the second conductive layer. Both the first region and the second region contain the first element. And the first element is boron or phosphorus.

7. The semiconductor device according to claim 1 or 2, The semiconductor layer includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The second semiconductor layer is located on the first semiconductor layer. The third semiconductor layer is located on the second semiconductor layer. The first semiconductor layer comprises a first metal oxide. The second semiconductor layer comprises a second metal oxide. The third semiconductor layer comprises a third metal oxide. The band gap of the first metal oxide is larger than that of the second metal oxide. Furthermore, the band gap of the third metal oxide is greater than that of the second metal oxide.

8. The semiconductor device according to claim 7, The band gap of the third metal oxide is larger than that of the first metal oxide. The thickness of the third semiconductor layer is greater than the thickness of the first semiconductor layer. Furthermore, the thickness of the second semiconductor layer is greater than the thickness of the third semiconductor layer.

9. The semiconductor device according to claim 1 or 2, The semiconductor layer includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The second semiconductor layer is located on the first semiconductor layer. The third semiconductor layer is located on the second semiconductor layer. The first semiconductor layer comprises a first metal oxide. The second semiconductor layer comprises a second metal oxide. The third semiconductor layer comprises a third metal oxide. The first metal oxide contains indium, a second element, and zinc. The second metal oxide contains indium. The third metal oxide comprises indium, a third element, and zinc. The second element is one or more of gallium, aluminum, and tin. The third element is one or more of gallium, aluminum, and tin. The content of the second element in the first metal oxide is higher than the sum of the contents of gallium, aluminum, and tin in the second metal oxide. Furthermore, the content of the third element in the third metal oxide is higher than the sum of the contents of gallium, aluminum, and tin in the second metal oxide.

10. The semiconductor device according to claim 9, The content of the third element in the third metal oxide is higher than the content of the second element in the first metal oxide. The thickness of the third semiconductor layer is greater than the thickness of the first semiconductor layer. Furthermore, the thickness of the second semiconductor layer is greater than the thickness of the third semiconductor layer.

11. A method for manufacturing a semiconductor device, comprising the following steps: Form the first conductive layer; A first insulating film is formed on the first conductive layer; A second insulating film is formed on the first insulating film; A first conductive film is formed on the second insulating film; The first conductive film is processed to form a second conductive layer including a first opening in the region overlapping with the first conductive layer; Processing the first insulating film and the second insulating film to form a first insulating layer and a second insulating layer including a second opening in the region overlapping with the first opening; and A semiconductor layer is formed on the first conductive layer, the second conductive layer, the first insulating layer, and the second insulating layer. in, The first insulating layer comprises silicon and oxygen. Furthermore, the second insulating layer comprises one or both of aluminum and hafnium, as well as oxygen.

12. The method for manufacturing a semiconductor device according to claim 11, The second insulating film is formed by sputtering in an oxygen-containing atmosphere.

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