Semiconductor integrated circuit device

Abstract

In a semiconductor integrated circuit device, an output transistor section (30N) including a transistor (N1) connected between a VSS and an output terminal (PAD) includes an active region (31) having a nanosheet (32) as a channel. The power supply wiring (25) and the output wiring (26) are arranged in a wiring layer on the rear surface side of the transistor (N1) so as to overlap the active region (31) in plan view. The power supply wiring (25) is connected to a lower surface of a portion of the active region (31) that serves as a source via a through hole, and the output wiring (26) is connected to a lower surface of a portion of the active region (31) that serves as a drain via a through hole.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor integrated circuit device, and particularly relates to a layout structure of an IO unit including an input / output circuit for receiving and transmitting signals between the semiconductor integrated circuit device and the outside of the semiconductor integrated circuit device. BACKGROUND

[0002] In an IO unit that constitutes a semiconductor integrated circuit device and that receives and transmits signals with the outside, an output buffer and an electrostatic discharge (ESD) protection circuit are generally provided. In addition, along with the miniaturization of semiconductor integrated circuit devices in recent years, the demand for high-speed operation of semiconductor integrated circuit devices is also increasing.

[0003] Patent Document 1 discloses a technique in which, in order to achieve high integration of a semiconductor integrated circuit device, a wiring is provided on the back surface of a substrate directly below a transistor, and the source / drain of the transistor is connected to the wiring.

[0004] PRIOR ART DOCUMENTS

[0005] PATENT DOCUMENTS

[0006] Patent Document 1: U.S. Patent Application Publication No. 2021 / 0375853 SUMMARY

[0007] -Technical Problem to be Solved by the Invention-

[0008] However, Patent Document 1 does not disclose a specific layout structure of a circuit that carries a large current, such as an output circuit in an input / output circuit, with respect to a structure in which a wiring is provided directly below a transistor. In addition, a specific layout structure of an ESD protection circuit is also not disclosed.

[0009] The present disclosure provides a specific layout structure of a circuit that carries a large current and an ESD protection circuit with respect to a semiconductor integrated circuit device having a structure in which a wiring is provided directly below a transistor.

[0010] -Technical Solution to the Technical Problem-

[0011] In a first aspect of this disclosure, a semiconductor integrated circuit device includes a first output transistor portion, a first power supply wiring, and an output wiring. The first output transistor portion includes a first transistor of a first conductivity type connected between a first power supply supplying a first power supply voltage and an output terminal. The first power supply wiring supplies the first power supply voltage. The output wiring is connected to the output terminal. The first output transistor portion includes a first active region of the first conductivity type, which constitutes the channel, source, and drain of the first transistor and has a nanosheet serving as the channel. The first power supply wiring is arranged in a wiring layer located on the back side of the first transistor, overlapping the first active region in a top view, and is connected to the lower surface of the portion of the first active region that becomes the source of the first transistor via a via. The output wiring is arranged in the same wiring layer as the first power supply wiring, overlapping the first active region in a top view, and is connected to the lower surface of the portion of the first active region that becomes the drain of the first transistor via a via.

[0012] According to this aspect, a first output transistor portion, including a first transistor connected between a first power supply and an output terminal, includes a first active region that forms the channel, source, and drain of the first transistor. The first active region has a nanosheet serving as the channel. A first power supply wiring and an output wiring are arranged in a wiring layer on the back side of the first transistor, overlapping the first active region in a top view. The first power supply wiring is connected via a via to the lower surface of the portion of the first active region that becomes the source of the first transistor, and the output wiring is connected via a via to the lower surface of the portion of the first active region that becomes the drain of the first transistor. This allows the output terminal to carry a large current without increasing the layout area.

[0013] In a second aspect of this disclosure, a semiconductor integrated circuit device includes: an electrostatic discharge protection diode connected between a first power supply supplying a first power supply voltage and an output terminal, a first power supply wiring supplying the first power supply voltage, and an output wiring connected to the output terminal. The electrostatic discharge protection diode includes a first active region of a first conductivity type and a second active region of a second conductivity type. The first active region of the first conductivity type forms a terminal of one of an anode and a cathode and has a first nanosheet. The second active region of the second conductivity type forms a terminal of the other of an anode and a cathode and has a second nanosheet. The first power supply wiring is arranged in a wiring layer located on the back side of the first active region and the second active region in a manner that overlaps with the first active region when viewed from above, and is connected to the lower surface of the portion of the first active region containing the first nanosheet via a via. The output wiring is arranged in the same wiring layer as the first power supply wiring in a manner that overlaps with the second active region when viewed from above, and is connected to the lower surface of the portion of the second active region containing the second nanosheet via a via.

[0014] According to this aspect, the ESD protection diode connected between the first power supply and the output terminal includes a first active region of a first conductivity type and a second active region of a second conductivity type. The first active region of the first conductivity type constitutes a terminal of one of the anode and cathode, and the second active region of the second conductivity type constitutes a terminal of the other of the anode and cathode. The first and second active regions have nanosheets. A first power supply wiring and an output wiring are arranged in a wiring layer on the back side of the first and second active regions. The first power supply wiring is connected via a via to the lower surface of the portion of the first active region containing the nanosheet, and the output wiring is connected via a via to the lower surface of the portion of the second active region containing the nanosheet. Therefore, the characteristics and performance of the ESD protection diode can be improved without increasing the layout area.

[0015] In a third aspect of this disclosure, a semiconductor integrated circuit device includes a first output transistor portion, a protection resistor, and a first power supply wiring. The first output transistor portion includes a first transistor of a first conductivity type connected between a first power source supplying a first power supply voltage and a first node. The protection resistor is connected between an output terminal and the first node. The first power supply wiring supplies the first power supply voltage. The first output transistor portion includes a first active region of the first conductivity type, which constitutes the channel, source, and drain of the first transistor and has nanosheets serving as the channel. The first power supply wiring is arranged in a wiring layer located on the back side of the first transistor, overlapping the first active region in a top view, and is connected via a via to the lower surface of the portion of the first active region that becomes the source of the first transistor. The protection resistor is formed on the upper layer of the first active region, one end of which is connected to the portion of the first active region that becomes the drain of the first transistor, and the other end of which is connected to the output wiring, which is connected to the output terminal.

[0016] According to this aspect, a first output transistor portion, including a first transistor connected between a first power supply and a first node, includes a first active region that forms the channel, source, and drain of the first transistor. The first active region has a nanosheet serving as the channel. A first power supply wiring is disposed in a wiring layer located on the back side of the first transistor and connected via a via to the lower surface of the portion of the first active region that becomes the source of the first transistor. A resistive element connected between the output terminal and the first node is formed on the upper layer of the first active region. One end of the resistive element is connected to the portion of the first active region that becomes the drain of the first transistor, and the other end of the resistive element is connected to the output wiring, which is connected to the output terminal. Thus, a large current can be carried at the output terminal without increasing the layout area.

[0017] The effect of an invention

[0018] According to this disclosure, in a semiconductor integrated circuit device having a structure in which wiring is located directly below the transistor, circuits that carry large currents and ESD protection circuits can be implemented in a small area. Attached Figure Description

[0019] Figure 1 This is a top view schematically illustrating the overall structure of the semiconductor integrated circuit device involved in the embodiment.

[0020] Figure 2 This is a circuit structure diagram of the output circuit involved in the first embodiment.

[0021] Figure 3This is an example of an overview of the IO cell layout in the first implementation.

[0022] Figure 4 It is shown Figure 3 A top view of the layout of the output transistor N1.

[0023] Figure 5 It is shown Figure 3 A top view of the layout of the output transistor N1.

[0024] Figure 6 (a) and (b) are Figure 4 and Figure 5 A cross-sectional view of the map in the document.

[0025] Figure 7 (a) and (b) are other structural examples of the semiconductor integrated circuit device involved in the implementation.

[0026] Figure 8 It is shown Figure 3 A top view of the layout of the output transistor P1.

[0027] Figure 9 It is shown Figure 3 A top view of the layout of the output transistor P1.

[0028] Figure 10 It is shown Figure 3 A top view of the layout of diode 1a in the image.

[0029] Figure 11 It is shown Figure 3 A top view of the layout of diode 1a in the image.

[0030] Figure 12 (a) and (b) are Figure 10 and Figure 11 A cross-sectional view of the map in the document.

[0031] Figure 13 It is shown Figure 3 A top view of the layout of diode 1b in the image.

[0032] Figure 14 It is shown Figure 3 A top view of the layout of diode 1b in the image.

[0033] Figure 15 This is a circuit structure diagram of the output circuit involved in the second embodiment.

[0034] Figure 16 This is an example of the overview of the IO cell layout in the second embodiment.

[0035] Figure 17 It is shown Figure 16A top view of the layout of the output transistor N1.

[0036] Figure 18 It is shown Figure 16 A top view of the layout of the output transistor N1.

[0037] Figure 19 It is shown Figure 16 A top view of the layout of the output transistor P1.

[0038] Figure 20 It is shown Figure 16 A top view of the layout of the output transistor P1.

[0039] Figure 21 It is shown Figure 16 A top view of the layout of diode 1a in the image.

[0040] Figure 22 It is shown Figure 16 A top view of the layout of diode 1b in the image.

[0041] Figure 23 This is a circuit structure diagram of the output circuit of a modified example of the second embodiment.

[0042] Figure 24 This is an example of the general layout of the IO cell in a variant of the second embodiment. Detailed Implementation

[0043] The embodiments will now be described with reference to the accompanying drawings. It should be noted that in the following description, "VDDIO" and "VSS" refer to the power supply voltage or the power supply itself. Furthermore, it is assumed that the transistor is formed on a P-type substrate and an N-type well. It should be noted that the transistor can also be formed on a P-type well or on an N-type substrate.

[0044] (First Implementation)

[0045] Figure 1 This is a top view schematically illustrating the overall structure of the semiconductor integrated circuit device involved in the embodiment. Figure 1 The semiconductor integrated circuit device 1 shown includes a core region 2 and an I / O region 3. An internal core circuit is formed in the core region 2, and an interface circuit (I / O circuit) is formed in the I / O region 3, located between the core region 2 and the chip edge. In the I / O region 3, an I / O cell row 10A is arranged in a ring surrounding the periphery of the semiconductor integrated circuit device 1. Figure 1 The design has been simplified, but multiple I / O units 10 constituting the interface circuit are arranged in I / O unit column 10A. Additionally, in... Figure 1The details are omitted, but multiple external connection pads are arranged in the semiconductor integrated circuit device 1. These external connection pads are located on the back side of the semiconductor chip. It should be noted that the I / O cell row 10A can also be located in a portion of the periphery of the semiconductor integrated circuit device 1.

[0046] The I / O unit 10 includes signal I / O units and power I / O units. The signal I / O units include, for example, level shifting circuits, output buffer circuits, and ESD protection circuits. These circuits are required for receiving and transmitting signals between the semiconductor integrated circuit device 1 and the outside, or between the device and the core region 2. The power I / O units supply power from the external connection pads to the inside of the semiconductor integrated circuit device 1. The power I / O units include ESD protection circuits, etc.

[0047] Figure 2 This is a circuit diagram of the output circuit 11 included in the IO unit 10. It should be noted that the actual output circuit also includes... Figure 2 Elements other than the circuit elements shown, but... Figure 2 The record is omitted.

[0048] Figure 2 The output circuit 11 shown includes an external output terminal PAD, output transistors P1 and N1, and ESD (Electro-Static Discharge) protection diodes 1a and 1b. Output transistor P1 is a P-type transistor, and output transistor N1 is an N-type transistor.

[0049] Output transistors P1 and N1 output signals to the external output terminal PAD based on the signals received at their gates. The source of output transistor P1 is connected to VDDIO, and the drain of output transistor P1 is connected to the external output terminal PAD. The source of output transistor N1 is connected to VSS, and the drain of output transistor N1 is connected to the external output terminal PAD.

[0050] ESD protection diode 1a is positioned between VSS and the external output terminal PAD. The anode of ESD protection diode 1a is connected to VSS, and the cathode of ESD protection diode 1a is connected to the external output terminal PAD. ESD protection diode 1b is positioned between VDDIO and the external output terminal PAD. The anode of ESD protection diode 1b is connected to the external output terminal PAD, and the cathode of ESD protection diode 1b is connected to VDDIO. When high-voltage noise is input to the external output terminal PAD, current flows into VDDIO and VSS through ESD protection diodes 1a and 1b. This protects output transistors P1 and N1.

[0051] Figure 3 This is one example of the layout overview of an I / O unit. Figure 3 The layout in the diagram corresponds to IO unit 10a, which is arranged in... Figure 1 One of the I / O units 10 at the lower edge of the semiconductor integrated circuit device 1. Here, the X direction (equivalent to the first direction) is the direction along the outer edge of the semiconductor integrated circuit device 1, and is the direction in which the plurality of I / O units 10 are arranged. The Y direction (equivalent to the second direction) is the direction perpendicular to the X direction.

[0052] I / O units typically have a high-supply-voltage region and a low-supply-voltage region. The high-supply-voltage region contains ESD protection circuitry, output buffers for outputting signals to the outside of the semiconductor integrated circuit device, etc., while the low-supply-voltage region contains circuitry for inputting and outputting signals to the inside of the semiconductor integrated circuit device, etc. Furthermore, Figure 3 The IO unit 10a is divided into a low power supply voltage region 6 and a high power supply voltage region 7 in the Y direction. The low power supply voltage region 6 is located on the core region 2 side, and the high power supply voltage region 7 is located on the chip edge side.

[0053] The low power supply voltage region 6 is located near the output transistors N1 and P1, and includes, for example, circuitry for generating signals that are input to the gates of the output transistors N1 and P1.

[0054] Figure 3 The IO unit 10a shown constitutes Figure 2 The output circuit 11 is shown. In the high power supply voltage region 7, ESD protection diodes 1a and 1b, output transistor P1, and output transistor N1 are arranged sequentially from the edge of the chip. It should be noted that the arrangement of ESD protection diodes 1a and 1b and output transistors P1 and N1 is not limited to... Figure 3 The arrangement is shown below. For example, the positions of output transistor P1 and output transistor N1 can be interchanged, and the positions of ESD protection diode 1a and ESD protection diode 1b can also be interchanged.

[0055] <Output transistor N1>

[0056] Figure 4 and Figure 5 All are shown Figure 3 A top view showing the detailed layout of the output transistor N1. Figure 4The diagram shows the structure of the wiring layers disposed on the back side of the semiconductor chip for forming transistors, namely the BM0 (Backside Metal 0) layer, the BM1 (Backside Metal 1) layer, and the BM2 (Backside Metal 2) layer. The BM1 layer is located below the BM0 layer, i.e., at a distance from the transistor. The BM2 layer is located below the BM1 layer, i.e., at a distance from the transistor. Figure 5 The structure of the BM0 wiring layer and its upper layers is shown. Figure 6 yes Figure 4 and Figure 5 The cross-sectional views of the layout are shown in Figure (a), which shows the cross-sectional structure cut along the X1-X1' line, and (b), which shows the cross-sectional structure cut along the Y1-Y1' line. It should be noted that the direction perpendicular to the substrate surface is defined as the Z direction.

[0057] like Figure 5 As shown, the output transistor section 30N is formed in the central part of the figure, and the protective ring section 40A is formed in a ring around it.

[0058] like Figure 4 As shown, power supply wiring 21 and output wiring 22 extending in the Y direction are arranged on layer BM2. Power supply wiring 21 supplies power supply voltage VSS. Output wiring 22 is connected to external output terminal PAD. The spacing between power supply wiring 21 and output wiring 22 is the minimum value constrained by the manufacturing process.

[0059] Power supply wiring 23 and output wiring 24 extending in the X direction are arranged on layer BM1. Power supply wiring 23 is connected to power supply wiring 21 on layer BM2 via vias. Output wiring 24 is connected to output wiring 22 on layer BM2 via vias. The spacing between power supply wiring 23 and output wiring 24 is the minimum value constrained by the manufacturing process.

[0060] A power supply line 25 and an output line 26 extending in the Y direction are arranged on the BM0 layer. The power supply line 25 is connected to the power supply line 23 of the BM1 layer via a via. The power supply line 25 is formed in the guard ring portion 40A and is formed to pass through the output transistor portion 30N. The output line 26 is connected to the output line 24 of the BM1 layer via a via. The output line 26 is formed in the output transistor portion 30N.

[0061] An N-type active region 31 extending in the X direction is formed in the output transistor section 30N. The active region is the region that constitutes the channel, source, and drain of the transistor. The active region constituting the nanosheet FET has a nanosheet that serves as the channel. The portions of the active region that become the source and drain located on both sides of the nanosheet are formed, for example, by epitaxial growth starting from the nanosheet. It should be noted that, as will be described later, there are times when the active region does not form a transistor.

[0062] exist Figure 5 In order to form transistor N1, five active regions 31 are arranged in the Y direction, and each active region 31 contains six nanosheets 32. Each nanosheet 32 ​​is composed of three overlapping sheet structures when viewed from above, and extends in the X direction.

[0063] In the active region 31, the portion that becomes the source of the transistor overlaps with the power supply wiring 25 of the BMO layer when viewed from above, and is connected to the power supply wiring 25 via a via. In the active region 31, the portion that becomes the drain of the transistor overlaps with the output wiring 26 of the BMO layer when viewed from above, and is connected to the output wiring 26 via a via.

[0064] A gate wiring 33 extending in the Y direction is formed to span five active regions 31. The gate wiring 33 surrounds the outer periphery of the nanosheet 32 ​​in the Y and Z directions through a gate insulating film (not shown). The gate wiring 33 corresponds to the gate of transistor N1.

[0065] On the metal wiring layer M0, located above the transistor, a signal wiring 34 extending in the X direction is arranged. The signal wiring 34 is connected to the gate wiring 33 of the output transistor section 30N via a via. The signal wiring 34 supplies the signal INN to the gate of the transistor N1.

[0066] A P-type active region 41 is formed in the guard ring portion 40A. The active region 41 includes nanosheets 42. Each nanosheet 42 consists of a three-sheet structure that overlaps when viewed from above, and extends in the X direction. However, the active region 41 does not function as a transistor.

[0067] In the active region 41, the portion sandwiching the nanosheet 42 (corresponding to the source and drain of the transistor) overlaps with the power supply wiring 25 of the BMO layer when viewed from above, and is connected to the power supply wiring 25 via vias. That is, the active region 41 supplies the power supply voltage VSS from the power supply wiring 25 to the P-type substrate or P-type well. Furthermore, the guard ring 40A can suppress noise transmission and latch-up effects between the output transistor portion 30N and surrounding transistors.

[0068] A gate wiring 43 extending in the Y direction is formed in the active region 41. The gate wiring 43 surrounds the outer periphery of the nanosheet 42 in the Y and Z directions through a gate insulating film (not shown). However, the gate wiring 43 does not function as the gate of the transistor.

[0069] A local wiring (LI) 44 extending in the Y direction is arranged. The local wiring 44 is formed on the upper surface of the active region 41. A power supply wiring 45 extending in the X direction is arranged in the M0 layer. The power supply wiring 45 is connected to the local wiring 44 and to the gate wiring 43. As a result, the power supply voltage VSS is supplied to the gate wiring 43 of the guard ring portion 40A.

[0070] The above structure achieves the following effects: The wiring on the back of the transistor consists only of power supply wiring to VSS and output wiring connected to the external output terminal PAD. Furthermore, power supply and output wiring are maximized on the BM1 and BM2 layers. Therefore, it can carry large currents and also suppress wiring resistance.

[0071] The power and output wiring of the BMO layer is connected to the active region 31 that constitutes the output transistor N1 only through vias. Therefore, the resistance value can be reduced, thereby enabling it to carry a large current.

[0072] As described above, the output transistor portion 30N, which includes the transistor N1 connected between the power supply VSS and the external output terminal PAD, includes an active region 31 constituting the channel, source, and drain of the transistor N1. The active region 31 has a nanosheet 32 ​​serving as the channel. The power supply wiring 25 and the output wiring 26 are arranged in a wiring layer on the back side of the transistor N1, overlapping the active region 31 when viewed from above. The power supply wiring 25 is connected via a via to the lower surface of the portion of the active region 31 that serves as the source of the transistor N1, and the output wiring 26 is connected via a via to the lower surface of the portion of the active region 31 that serves as the drain of the transistor N1. This allows the output terminal to carry a large current without increasing the layout area.

[0073] It should be noted that although the power supply wirings 21, 23, 25 and the output wirings 22, 24, 26 are formed on a wiring layer disposed on the back side of the semiconductor chip, this is not a limitation. In this disclosure, the power supply wirings and output wirings can be formed on the back side of the transistor (active region). The back side of the transistor refers to the side opposite to the stacked side of the local wiring, metal wiring, etc., connected to the transistor, with reference to the transistor.

[0074] Power wiring 21, 23, 25 and output wiring 22, 24, 26 can also be formed in multiple wiring layers.

[0075] Alternatively, the routing layer can be placed below the BM2 layer, forming back-side routing. In this case, preferably, the routing directions in each routing layer are alternating, for example, such as X-direction in the BM3 layer and Y-direction in the BM4 layer.

[0076] (Other structural examples)

[0077] It is permissible to use a different semiconductor chip than the one used to form the power supply wiring and output wiring on the back side of the transistor.

[0078] Figure 7 (a) illustrates another structural example of the semiconductor integrated circuit device involved in the embodiment. Figure 7 The semiconductor integrated circuit device 100 shown in (a) is constructed by stacking a first semiconductor chip 101 (chip A) and a second semiconductor chip 102 (chip B). The aforementioned I / O units are arranged on chip A. Power supply wiring and output wiring are formed on a wiring layer disposed on the surface of chip B. Chip B is attached to the back side of chip A using bumps or the like.

[0079] Figure 7 (b) shows the structure in this example, along Figure 4 and Figure 5 The sectional view of the map along line Y1-Y1'. For example... Figure 7 As shown in (b), a power supply line for supplying VSS and an output line connected to the external output terminal PAD are formed in the wiring layer disposed on the surface of chip B. The power supply line 25 of the BMO layer is connected to the portion of the active region 31 of chip A that becomes the source of a transistor via a via. The output line 26 of the BMO layer is connected to the portion of the active region 31 of chip A that becomes the drain of a transistor via a via.

[0080] This structural example achieves the same effect as the aforementioned IO unit. It should be noted that in this structural example, power and output wiring can also be formed on chip B at a lower layer than BM2.

[0081] This structural example can also be applied to the layout to be described later.

[0082] <Output transistor P1>

[0083] Figure 8 and Figure 9 All are shown Figure 3 A top view showing the detailed layout of the output transistor P1. Figure 8 The structure of the BM0-BM2 layers is shown. Figure 9 The structure of the BM0 wiring layer and its upper layers is shown.

[0084] Compared with the layout of Figure 4 and Figure 5 , in the layout of Figure 8 and Figure 9 , the conductivity type of the active region 36 in the output transistor section 30P is P-type, and the conductivity type of the active region 46 in the guard ring section 40B is N-type. Also, the power supply voltage supplied to the part of the active region 36 that becomes the source of the transistor P1 is VDDIO, and the signal applied to the gate of the transistor P1 is INP. It can be easily understood from the description of the layout of Figure 4 and Figure 5 the layout of Figure 8 and Figure 9 , so the detailed description of the layout of Figure 8 and Figure 9 is omitted here.

[0085] It should be noted that the output wiring 27 of the BM2 layer is connected to the output wiring 22 of the BM2 layer of the output transistor N1.

[0086] The output transistor section 30P including the transistor P1 connected between the power supply VDDIO and the external output terminal PAD includes the active region 36 that constitutes the channel, source, and drain of the transistor P1. The active region 36 has nanosheets as the channel. The power supply wiring 28 and the output wiring 29 are arranged in the wiring layer on the back side of the transistor P1 so as to overlap the active region 36 in a top view. The power supply wiring 28 is connected to the lower surface of the part of the active region 36 that becomes the source of the transistor P1 via a via hole, and the output wiring 29 is connected to the lower surface of the part of the active region 36 that becomes the drain of the transistor P1 via a via hole. Thus, a large current can be carried by the output terminal without increasing the layout area.

[0087] <ESD protection diode 1a>

[0088] Figure 10 and Figure 11 are both top views showing the detailed layout of the ESD protection diode 1a in Figure 3 . Figure 10 Shows the structure of the BM0 - BM2 layers. Figure 11 Shows the structure of the BM0 wiring layer and its upper layer. Figure 12 Is Figure 10 and Figure 11 a cross-sectional view of the layout in , (a) shows the cross-sectional structure cut along the X1 - X1' line, and (b) shows the cross-sectional structure cut along the Y1 - Y1' line.

[0089] As Figure 11As shown, a cathode portion 60 is formed in the upper, central and lower parts of the figure, and an anode portion 70 is formed in a manner that surrounds the cathode portion 60.

[0090] like Figure 10 As shown, power supply wiring 51 and output wiring 52 extending in the Y direction are arranged on layer BM2. Power supply wiring 51 supplies power supply voltage VSS. Output wiring 52 is connected to external output terminal PAD. The spacing between power supply wiring 51 and output wiring 52 is the minimum value constrained by the manufacturing process.

[0091] Power supply wiring 53 and output wiring 54 extending in the X direction are arranged on layer BM1. Power supply wiring 53 is connected to power supply wiring 51 on layer BM2 via vias. Output wiring 54 is connected to output wiring 52 on layer BM2 via vias. The spacing between power supply wiring 53 and output wiring 54 is the minimum value constrained by the manufacturing process.

[0092] A power supply wiring 55 and an output wiring 56 extending in the Y direction are arranged in the BM0 layer. The power supply wiring 55 is connected to the power supply wiring 53 in the BM1 layer via a through-hole. The power supply wiring 55 is formed in the anode portion 70. The output wiring 56 is connected to the output wiring 54 in the BM1 layer via a through-hole. The output wiring 56 is formed in the cathode portion 60.

[0093] An N-type active region 61 extending in the X direction is formed in the cathode portion 60. Each active region 61 contains six nanosheets 62. Each nanosheet 62 is composed of a three-sheet structure overlapping when viewed from above, and extends in the X direction. However, the active regions 61 do not function as transistors.

[0094] In the active region 61, the portion sandwiching the nanosheet 62 (equivalent to the source and drain of the transistor) overlaps with the output wiring 56 of the BMO layer when viewed from above, and is connected to the output wiring 56 via a via.

[0095] A gate wiring 63 extending in the Y direction is formed in the active region 61. The gate wiring 63 surrounds the outer periphery of the nanosheet 62 in the Y and Z directions through a gate insulating film (not shown). However, the gate wiring 63 does not function as the gate of the transistor. The gate wiring 63 is connected to the active region 61 via local wiring 64 and MO wiring 65.

[0096] A P-type active region 71 is formed in the anode portion 70. Each active region 71 contains a nanosheet 72. Each nanosheet 72 consists of three overlapping sheet structures when viewed from above and extends in the X direction. However, the active region 71 does not function as a transistor.

[0097] In the active region 71, the portion sandwiching the nanosheet 72 (the portion corresponding to the source and drain of the transistor) overlaps with the power supply wiring 55 of the BM0 layer when viewed from above, and is connected to the power supply wiring 55 via a via hole.

[0098] In the active region 71, a gate wiring 73 extending in the Y direction is formed. The gate wiring 73 surrounds the outer peripheries of the nanosheet 72 in the X and Z directions with a gate insulating film (not shown) interposed therebetween. However, the gate wiring 73 is not the gate of the transistor. The gate wiring 73 is connected to the active region 71 via a local wiring 74 and an M0 wiring 75. That is, the potential of the gate wiring 73 is fixed at VSS.

[0099] Under the above structure, the following effects can be obtained. The wirings arranged on the back surface of the active regions 61 and 71 constituting the ESD protection diode 1a are only the power supply wiring for supplying VSS and the output wiring connected to the external output terminal PAD. Also, in the BM1 layer and the BM2 layer, power supply wirings and output wirings are laid out to the maximum extent. Therefore, the wiring resistance can be reduced, and thus the characteristics and performance of the ESD protection diode 1a can be improved.

[0100] The power supply wiring and the output wiring in the BM0 layer are only connected to the active regions 61 and 71 constituting the ESD protection diode 1a via via holes. Therefore, the resistance value can be reduced, and thus the characteristics and performance of the ESD protection diode 1a can be improved.

[0101] As described above, the ESD protection diode 1a connected between the power supply VSS and the external output terminal PAD includes a P-type active region 71 constituting the anode portion 70 and an N-type active region 61 constituting the cathode portion 60. The active region 61 has a nanosheet 62, and the active region 71 has a nanosheet 72. The power supply wiring 55 and the output wiring 56 are arranged in the wiring layer on the back side of the active regions 61 and 71. The power supply wiring 55 is connected to the lower surface of the portion sandwiching the nanosheet 72 in the active region 71 via a via hole, and the output wiring 56 is connected to the lower surface of the portion sandwiching the nanosheet 62 in the active region 61 via a via hole. Thereby, the characteristics and performance of the ESD protection diode 1a can be improved without increasing the layout area.

[0102] The power supply wirings 51, 53, 55 and the output wirings 52, 54, 56 may also be formed in multiple wiring layers.

[0103] It is also possible to provide a wiring layer in a lower layer than the BM2 layer and form a back surface wiring. In this case, preferably, the wiring directions in each wiring layer alternate, for example, the wiring direction in the BM3 layer is in the X direction and the wiring direction in the BM4 layer is in the Y direction.

[0104] <ESD protection diode 1b>

[0105] Figure 13 and Figure 14 All are shown Figure 3 A top view showing the detailed layout of the ESD protection diode 1b in the diagram. Figure 13 The structure of the BM0-BM2 layers is shown. Figure 14 The structure of the BM0 wiring layer and its upper layers is shown.

[0106] exist Figure 13 and Figure 14 In the territory, with Figure 10 and Figure 11 Compared to the previous layout, the positions of the anode and cathode portions have been interchanged. That is, the anode portion 70A is formed in the upper, central, and lower parts of the diagram, and the cathode portion 60A is formed surrounding the anode portion 70A. The active region 77 in the anode portion 70A has a P-type conductivity, and the active region 67 in the cathode portion 60A has an N-type conductivity. Furthermore, the power supply voltage supplied to the portion of the active region 67 of the cathode portion 60A containing the nanosheet is VDDIO.

[0107] From the relevant Figure 10 and Figure 11 The map description makes it easy to understand. Figure 13 and Figure 14 The territory is omitted here. Figure 13 and Figure 14 A detailed description of the territory.

[0108] It should be noted that the output wiring 57 of the BM2 layer is connected to the output wiring 52 of the BM2 layer of the ESD protection diode 1a. In addition, the output wirings 52 and 57 are also connected to the output wirings 22 and 27 of the BM2 layer of the output transistors N1 and P1.

[0109] The ESD protection diode 1b, connected between the power supply VSS and the external output terminal PAD, includes an N-type active region 67 constituting the cathode portion 60A and a P-type active region 77 constituting the anode portion 70A. Power supply wiring 58 and output wiring 59 are arranged in the wiring layer on the back side of the active regions 67 and 77. Power supply wiring 58 is connected via a via to the lower surface of the portion of the active region 67 containing the nanosheet, and output wiring 59 is connected via a via to the lower surface of the portion of the active region 77 containing the nanosheet. This allows for improved characteristics and performance of the ESD protection diode 1b without increasing the layout area.

[0110] (Second Implementation)

[0111] Figure 15 This is a circuit structure diagram of the output circuit included in the IO unit 10 in the second embodiment. It should be noted that the actual output circuit also includes...Figure 15 Elements other than the circuit elements shown, but... Figure 15 The record is omitted.

[0112] Figure 15 The output circuit shown includes, in addition to Figure 2 In addition to the external output terminals PAD, output transistors P1 and N1, and ESD protection diodes 1a and 1b, the output circuit 11 shown also includes protection resistors Rsn and Rsp.

[0113] The source of output transistor P1 is connected to VDDIO, and the drain of output transistor P1 is connected to the external output terminal PAD via a protection resistor Rsp. The source of output transistor N1 is connected to VSS, and the drain of output transistor N1 is connected to the external output terminal PAD via a protection resistor Rsn. In this embodiment, the protection resistors Rsp and Rsn are composed of multiple resistive elements formed in a wiring layer, which is formed in a BEOL (Back End of Line) wiring process. It should be noted that the node between output transistor N1 and protection resistor Rsn is called node A, and the node between output transistor P1 and protection resistor Rsp is called node B.

[0114] Figure 16 This is one example of the layout overview of the IO unit in this embodiment. In the high power supply voltage region 7, in the region where ESD protection diodes 1a and 1b are arranged, resistor elements RU are arranged in an array in the XY direction. The resistor elements RU are formed on an upper layer above the MO wiring layer. The resistor elements RU arranged on the ESD protection diode 1b are connected to each other to form a protection resistor Rsp. The resistor elements RU arranged on the ESD protection diode 1a are connected to each other to form a protection resistor Rsn.

[0115] A protection resistor Rsp is connected between the external output terminal PAD and node B, which means that the wiring of node B extends from the area forming the protection resistor Rsp towards the area where the output transistor P1 is located. A protection resistor Rsn is connected between the external output terminal PAD and node A, which means that the wiring of node A extends from the area forming the protection resistor Rsn towards the area where the output transistor N1 is located.

[0116] It should be noted that the positions of the protective resistors Rsp and Rsn on the plane are not limited to... Figure 16 The location shown.

[0117] <Output transistors N1, P1>

[0118] Figure 17 and Figure 18 All are shown Figure 16A top view showing the detailed layout of the output transistor N1. Figure 17 The structure of the BM0-BM2 layers is shown. Figure 18 This shows the structure of the BM0 wiring layer and its upper layers. It should be noted that this is for... Figure 4 and Figure 5 The version shown Figure 1 Such a structure sometimes omits or simplifies the explanation.

[0119] like Figure 17 As shown, a power supply trace 121 extending in the Y direction is arranged on the BM2 layer. The power supply trace 121 supplies the power supply voltage VSS. The spacing of the power supply trace 121 is the minimum value constrained by the manufacturing process.

[0120] A power supply trace 122 extending in the X direction is arranged on layer BM1. The power supply trace 122 is connected to the power supply trace 121 on layer BM2 via vias, supplying the power supply voltage VSS. The spacing of the power supply trace 122 is the minimum value constrained by the manufacturing process.

[0121] A power supply trace 123 extending in the Y direction is arranged on the BM0 layer. The power supply trace 123 is connected to the power supply trace 122 on the BM1 layer via a via, supplying the power supply voltage VSS.

[0122] In other words, all the wiring laid on the BM0-BM2 layers is power supply wiring for the VSS.

[0123] like Figure 18 As shown, an N-type active region 131 extending in the X direction is formed in the output transistor section 130N. In the active region 131, the portion that becomes the source of transistor N1 overlaps with the power supply wiring 123 of the MO layer when viewed from above, and is connected to the power supply wiring 123 via a via. On the other hand, in the active region 131, the portion that becomes the drain of transistor N1 is connected to wiring 135 formed in the MO wiring layer via a via. Wiring 135 corresponds to node A. Wiring 135 is connected to a protection resistor Rsn via wiring and a via (not shown). That is, one end of the protection resistor Rsn is connected to the portion in the active region 131 that becomes the drain of transistor N1. Furthermore, the other end of the protection resistor Rsn is connected to an output wiring (not shown), which is connected to an external output terminal PAD.

[0124] Figure 19 and Figure 20 All are shown Figure 16 A top view showing the detailed layout of the output transistor P1. Figure 19 The structure of the BM0-BM2 layers is shown. Figure 20 This shows the structure of the BM0 wiring layer and its upper layers. It should be noted that this is for... Figure 8and Figure 9 The version shown Figure 1 Such a structure sometimes omits or simplifies the explanation.

[0125] like Figure 19 As shown, power traces 126 extending in the Y direction are arranged on the BM2 layer. Power traces 126 supply power supply voltage VDDIO. The spacing of the power traces 126 is the minimum value constrained by the manufacturing process.

[0126] A power supply trace 127 extending in the X direction is arranged on layer BM1. The power supply trace 127 is connected to the power supply trace 126 on layer BM2 via a via, supplying the power supply voltage VDDIO. The spacing of the power supply trace 127 is the minimum value constrained by the manufacturing process.

[0127] A power supply trace 128 extending in the Y direction is arranged on the BM0 layer. The power supply trace 128 is connected to the power supply trace 127 on the BM1 layer via a via, supplying the power supply voltage VDDIO.

[0128] In other words, all the wiring arranged on the BM0-BM2 layers is power supply wiring for VDDIO.

[0129] like Figure 20 As shown, a P-type active region 136 extending in the X direction is formed in the output transistor section 130P. The portion of the active region 136 that serves as the source of transistor P1 overlaps with the power supply wiring 128 of the MO layer when viewed from above, and is connected to the power supply wiring 128 via a via. On the other hand, the portion of the active region 136 that serves as the drain of transistor P1 is connected to wiring 139 formed in the MO wiring layer via a via. Wiring 139 corresponds to node B. Wiring 139 is connected to a protection resistor Rsp via wiring and a via (not shown). That is, one end of the protection resistor Rsp is connected to the portion of the active region 136 that serves as the drain of transistor P1. The other end of the protection resistor Rsp is connected to an output wiring (not shown), which is connected to an external output terminal PAD.

[0130] The above structure achieves the following effects: The wiring arranged on the back of the transistor is solely for power supply to VSS and VDDIO. Furthermore, power wiring is maximized in the BM1 and BM2 layers. Therefore, compared to the structure shown in the first embodiment, it can carry a larger current and further suppress wiring resistance.

[0131] As described above, the output transistor section 130N including the transistor N1 connected between the power supply VSS and the node A includes an active region 131 that constitutes the channel, source, and drain of the transistor N1. The active region 131 has a nanosheet as the channel. The power supply wiring 123 is arranged in the wiring layer on the back side of the transistor N1 and is connected via a via to the lower surface of the portion in the active region 131 that becomes the source of the transistor N1. The protection resistor Rsn connected between the external output terminal PAD and the node A is formed on the upper layer of the active region 131. One end of the protection resistor Rsn is connected to the portion in the active region 131 that becomes the drain of the transistor N1, and the other end of the protection resistor Rsn is connected to the output wiring, which is connected to the external output terminal PAD.

[0132] The output transistor section 130P including the transistor P1 connected between the power supply VDDIO and the node B includes an active region 136 that constitutes the channel, source, and drain of the transistor P1. The active region 136 has a nanosheet as the channel. The power supply wiring 128 is arranged in the wiring layer on the back side of the transistor P1 and is connected via a via to the lower surface of the portion in the active region 136 that becomes the source of the transistor P1. The protection resistor Rsp connected between the external output terminal PAD and the node B is formed on the upper layer of the active region 136. One end of the protection resistor Rsp is connected to the portion in the active region 136 that becomes the drain of the transistor P1, and the other end of the protection resistor Rsp is connected to the output wiring, which is connected to the external output terminal PAD.

[0133] With the above structure, it is possible to make the output terminal carry a large current without expanding the layout area.

[0134] <ESD protection diodes 1a, 1b>

[0135] Figure 21 is a top view showing Figure 16 the details of the layout of the ESD protection diode 1a in Figure 22 is a top view showing Figure 16 the details of the layout of the ESD protection diode 1b in

[0136] The layout structure of the ESD protection diodes 1a, 1b of the present embodiment is the same as Figures 10 to 14 the layout structure of the ESD protection diodes 1a, 1b of the first embodiment shown in

[0137] Figure 21 shows the same as Figure 11With the same structure, the M0 wiring 65 in the cathode section 60 is labeled "PAD". The M0 wiring 65 is connected to the protection resistor Rsn via wiring and through-hole (not shown). Figure 22 Showing with Figure 14 With the same structure, the M0 wiring 78 in the anode section 70A is labeled "PAD". The M0 wiring 78 is connected to the protection resistor Rsp via wiring and through-hole (not shown).

[0138] This embodiment also achieves the same effect as the ESD protection diodes 1a and 1b in the first embodiment. Furthermore, since it eliminates the need for a region to connect the protection resistors Rsn and Rsp to the external output terminal PAD, area increase can be suppressed.

[0139] It should be noted that other structural examples described in the first embodiment can also be applied to this embodiment.

[0140] (Modified Example)

[0141] Figure 23 This is a circuit structure diagram of the output circuit involved in a variation of the second embodiment. Figure 23 The circuit structure in the second embodiment Figure 15 The circuit structures are roughly the same, but the insertion positions of the protective resistors differ. That is to say, in Figure 23 In the output circuit shown, a protective resistor Rs is used to replace... Figure 15 The protective resistors Rsn and Rsp are used in the process. Figure 23 In this configuration, the drains of output transistors P1 and N1 are connected to each other, and a protection resistor Rs is placed between the external output terminal PAD and the drains of output transistors P1 and N1. It should be noted that the node between the drains of output transistors P1 and N1 and the protection resistor Rs is called node C.

[0142] Figure 24 This is one example of the layout overview of the IO cell in this variant. The protection resistor Rs is formed by connecting the resistor elements RU arranged on the ESD protection diodes 1a and 1b to each other.

[0143] In this modified example, the MO wiring 135 in output transistor N1 corresponding to node A and the MO wiring 139 in output transistor P1 corresponding to node B, both in the second embodiment, correspond to node C. The layout structures of output transistors N1 and P1 and ESD protection diodes 1a and 1b are the same as in the second embodiment. Therefore, the same effects as in the second embodiment can be obtained.

[0144] It should be noted that in the output circuit of the above embodiments, both the P-type and N-type output transistors are single-stage transistors, but are not limited to this. For example, they can also be structures composed of multiple stages of transistors, such as two-stage or three-stage transistors connected in series. Furthermore, the output circuit of the above embodiments can also be an input-output circuit that includes an input circuit.

[0145] Industrial practicality

[0146] This disclosure enables high-current-carrying circuits and ESD protection circuits for semiconductor integrated circuit devices with wiring located directly below transistors. Therefore, this disclosure is useful for improving the performance of, for example, system-on-chip (SoC) devices.

[0147] -Symbol Explanation-

[0148] 1. Semiconductor integrated circuit device

[0149] 1a, 1b ESD protection diodes

[0150] 10, 10a IO units

[0151] 25 Power cabling

[0152] 26 Output wiring

[0153] 30N, 30P output transistors

[0154] 31, 36 Active regions

[0155] 32 nanosheets

[0156] 40A, 40B Protective Ring Section

[0157] 41, 46 Active regions

[0158] 42 nanosheets

[0159] 43 Gate wiring

[0160] 55, 58 Power wiring

[0161] Output wiring for 56 and 59

[0162] 60, 60A Cathode Section

[0163] Active regions 61 and 67

[0164] 62 nanosheets

[0165] 70, 70A Anode Section

[0166] 71, 77 Active regions

[0167] 72 nanosheets

[0168] 100 Semiconductor integrated circuit devices

[0169] 101 First Semiconductor Chip

[0170] 102 Second Semiconductor Chip

[0171] 123, 128 Power wiring

[0172] 130N, 130P output transistor section

[0173] 131, 136 active regions

[0174] P1 and N1 output transistors

[0175] Rsn, Rsp, Rs protection resistors

[0176] PAD external output terminals

[0177] VDDIO and VSS power supplies.

Claims

1. A semiconductor integrated circuit device, characterized in that, The semiconductor integrated circuit device includes a first output transistor section, a first power supply wiring, and an output wiring. The first output transistor section includes a first transistor of a first conductivity type connected between a first power supply supplying a first power supply voltage and an output terminal. The first power supply wiring supplies the first power supply voltage. The output wiring is connected to the output terminal. The first output transistor section includes a first active region of the first conductivity type, which constitutes the channel, source, and drain of the first transistor, and has nanosheets serving as the channel. The first power supply wiring is arranged in a wiring layer located on the back side of the first transistor, overlapping with the first active region when viewed from above, and is connected to the lower surface of the portion of the first active region that becomes the source of the first transistor via a via. The output wiring is arranged in the same wiring layer as the first power wiring, overlapping the first active region when viewed from above, and is connected to the lower surface of the portion in the first active region that becomes the drain of the first transistor via vias.

2. The semiconductor integrated circuit device according to claim 1, characterized in that, The semiconductor integrated circuit device includes a protective ring formed around the first output transistor portion. The protective ring portion includes a second active region having a second conductivity type with a second nanosheet. The first power wiring is connected via a via to the lower surface of the portion of the second active region that contains the second nanosheet.

3. The semiconductor integrated circuit device according to claim 2, characterized in that, The protective ring includes gate wiring formed in a manner that surrounds the second nanosheet. The gate wiring is supplied with the first power supply voltage.

4. The semiconductor integrated circuit device according to claim 1, characterized in that, The first power supply wiring and the output wiring are formed in a wiring layer disposed on the first semiconductor chip, and the first active region is formed in the first semiconductor chip.

5. The semiconductor integrated circuit device according to claim 1, characterized in that, The first power supply wiring and the output wiring are formed in the wiring layer disposed on the second semiconductor chip, and the second semiconductor chip is attached to the back side of the first semiconductor chip on which the first active region is formed.

6. A semiconductor integrated circuit device, characterized in that, The semiconductor integrated circuit device includes: An electrostatic discharge protection diode connected between the first power supply supplying the first power voltage and the output terminal. The first power supply wiring that supplies the first power supply voltage, and The output wiring connected to the output terminal, The electrostatic discharge protection diode includes a first active region of a first conductivity type and a second active region of a second conductivity type. The first active region of the first conductivity type constitutes a terminal of one of the anode and cathode, and has a first nanosheet. The second active region of the second conductivity type constitutes a terminal of the other of the anode and cathode, and has a second nanosheet. The first power supply wiring is arranged in a wiring layer located on the back side of the first active region and the second active region, overlapping with the first active region when viewed from above. It is connected to the lower surface of the portion of the first active region that contains the first nanosheet via a via. The output wiring is arranged in the same wiring layer as the first power wiring in a manner that overlaps with the second active region when viewed from above, and is connected to the lower surface of the portion of the second active region that contains the second nanosheet via a via.

7. The semiconductor integrated circuit device according to claim 6, characterized in that, The semiconductor integrated circuit device includes a first wiring and a resistive element, wherein the first wiring is arranged in a wiring layer above the first active region and the second active region in a manner that overlaps with the second active region when viewed from above. The resistive element is formed on the upper layer of the first wiring. The resistive element is connected via the first wiring to the upper surface of the portion of the second active region that sandwiches the second nanosheet.

8. The semiconductor integrated circuit device according to claim 6, characterized in that, The first power supply wiring and the output wiring are formed in a wiring layer disposed on the first semiconductor chip, and the first active region is formed in the first semiconductor chip.

9. The semiconductor integrated circuit device according to claim 6, characterized in that, The first power supply wiring and the output wiring are formed in the wiring layer disposed on the second semiconductor chip, and the second semiconductor chip is attached to the back side of the first semiconductor chip on which the first active region is formed.

10. A semiconductor integrated circuit device, characterized in that, The semiconductor integrated circuit device includes a first output transistor section, a protection resistor, and a first power supply wiring. The first output transistor section includes a first transistor of a first conductivity type connected between a first power source supplying a first power supply voltage and a first node. The protective resistor is connected between the output terminal and the first node, and the first power supply wiring supplies the first power supply voltage. The first output transistor section includes a first active region of the first conductivity type, which constitutes the channel, source, and drain of the first transistor, and has nanosheets serving as the channel. The first power supply wiring is arranged in a wiring layer located on the back side of the first transistor, overlapping with the first active region when viewed from above, and is connected to the lower surface of the portion of the first active region that becomes the source of the first transistor via a via. The protection resistor is formed on the upper layer of the first active region. One end of the protection resistor is connected to the portion of the first active region that becomes the drain of the first transistor, and the other end of the protection resistor is connected to the output wiring, which is connected to the output terminal.

11. The semiconductor integrated circuit device according to claim 10, characterized in that, The semiconductor integrated circuit device includes a protective ring formed around the first output transistor portion. The protective ring portion includes a second active region having a second conductivity type with a second nanosheet. The first power wiring is connected via a via to the lower surface of the portion of the second active region that contains the second nanosheet.

12. The semiconductor integrated circuit device according to claim 11, characterized in that, The protective ring includes gate wiring formed in a manner that surrounds the second nanosheet. The gate wiring is supplied with the first power supply voltage.

13. The semiconductor integrated circuit device according to claim 10, characterized in that, The first power supply wiring and the output wiring are formed in a wiring layer disposed on the first semiconductor chip, and the first active region is formed in the first semiconductor chip.

14. The semiconductor integrated circuit device according to claim 10, characterized in that, The first power supply wiring and the output wiring are formed in the wiring layer disposed on the second semiconductor chip, and the second semiconductor chip is attached to the back side of the first semiconductor chip on which the first active region is formed.

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