Improved materials and methods for complementary field effect transistors with intermediate dielectric isolation layer

Abstract

Embodiments of the present disclosure advantageously provide semiconductor devices, in particular, CFETs, and methods of making such devices having fully strained superlattice structures and having the channel layer substantially free of defects and the release layer protected from material loss during removal of the intermediate sacrificial layer. A CFET described herein comprises a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; an intermediate sacrificial layer on a top surface of the first hGAA structure, the intermediate sacrificial layer comprising silicon germanium (SiGe); and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprises alternating layers of a nanosheet channel layer comprising silicon (Si) and a nanosheet release layer comprising silicon germanium (SiGe). The intermediate sacrificial layer and the nanosheet release layers may comprise silicon germanium (SiGe) having the same or substantially the same germanium content.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the field of electronic device manufacturing, and in particular, to transistors. More particularly, embodiments of the present disclosure relate to complementary field-effect transistors (CFETs) and methods of forming the same. BACKGROUND

[0002] Transistors are a key component of most integrated circuits. Because the drive current and thus speed of a transistor is proportional to the gate width of the transistor, faster transistors generally require larger gate widths. Thus, there is a tradeoff between transistor size and speed, and “fin” field-effect transistors (finFETs) have been developed to address the conflicting goals of having a transistor with maximum drive current and minimum size. FinFETs feature a fin-shaped channel region that substantially increases the size of the transistor without significantly increasing the footprint of the transistor, and are now used in many integrated circuits. However, finFETs have their own drawbacks.

[0003] As transistor devices continue to shrink in feature size to achieve greater circuit density and higher performance, transistor device structures need to be improved to improve electrostatic coupling and reduce adverse effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, fin field-effect transistor (FinFET) structures, and gate-all-around (GAA) structures. GAA device structures include several lattice-matched channels suspended in a stacked configuration and connected by source / drain regions. GAA structures provide good electrostatic control and can be widely used for complementary metal oxide semiconductor (CMOS) wafer fabrication.

[0004] One example of a gate-all-around (GAA) technology is a complementary field-effect transistor (CFET), in which nFET and pFET nanowires / nanosheets are stacked vertically on top of each other. CFET transistors have increased on-device density and reduced area consumption compared to GAA transistors. When stacking nFETs and pFETs in a monolithic fashion, n and p superlattices are deposited sequentially with an intermediate sacrificial layer, which is selectively removed and replaced with a middle dielectric isolation (MDI) layer during processing. The MDI layer is used to electrically isolate the lower-level GAA from the higher-level GAA.

[0005] Each n or p superlattice of the CFET includes alternating layers of channel and release layers. The release layers typically include silicon germanium (SiGe) with a lower germanium (Ge) concentration. For etch contrast of the intermediate sacrificial layer compared to the channel and release layers, the intermediate sacrificial layer includes SiGe with a high Ge concentration.

[0006] However, when providing structures with such a high Ge concentration in the intermediate sacrificial layer, the superlattice relaxes and the strain and mobility decrease, resulting in poor transistor performance due to reduced drive current. Further, while providing an intermediate sacrificial layer with a relatively high Ge concentration provides etch contrast and selective removal of the intermediate sacrificial layer, undesirable loss of SiGe occurs within the release layer, resulting in the release layer becoming rough and damaged. Additionally, the Si channel layer can round during removal of the intermediate sacrificial layer. As a result, the superlattice has a non-uniform distribution, which adversely affects device performance and causes device variability.

[0007] Accordingly, there is a need for semiconductor devices, particularly CFETs, and methods of manufacturing such devices, that have fully strained superlattice structures and channel layers that are uniform and free or substantially free of defects. There is a further need for semiconductor devices, particularly CFETs, and methods of manufacturing such devices, that have channel and release layers that are protected from damage and loss during removal of the intermediate sacrificial layer. SUMMARY

[0008] Aspects of the disclosure are directed to a method of forming a semiconductor device, the method including: forming a vertical stack of superlattice structures on a substrate by forming a first horizontal gate all around (hGAA) structure on the substrate, the first hGAA structure including alternating layers of nanosheet channel layers and nanosheet release layers; forming an intermediate sacrificial layer on a top surface of the first hGAA structure; forming a second horizontal gate all around (hGAA) structure on a top surface of the sacrificial layer, the second hGAA structure including alternating layers of nanosheet channel layers and nanosheet release layers; depositing a packaging material to fill one or more trenches in the vertical stack of superlattice structures and surround the vertical stack of superlattice structures; removing a portion of the packaging material to expose the second hGAA structure; depositing a protective liner on the second hGAA structure; removing a portion of the packaging material to expose the intermediate sacrificial layer; and removing the intermediate sacrificial layer, wherein the first hGAA structure is covered by the packaging material and the second hGAA structure is covered by the protective liner during removal of the intermediate sacrificial layer.

[0009] Another aspect of the disclosure is directed to a method of forming a semiconductor device, the method comprising: forming a first horizontal gate-all-around (hGAA) structure on a substrate by forming a vertically stacked superlattice structure on the substrate, the first hGAA structure comprising alternating layers of nanosheet channel layers and nanosheet release layers; forming an intermediate sacrificial layer on a top surface of the first hGAA structure; forming a second horizontal gate-all-around (hGAA) structure on a top surface of the sacrificial layer, the second hGAA structure comprising alternating layers of nanosheet channel layers and nanosheet release layers; and etching the intermediate sacrificial layer, wherein the alternating layers of nanosheet release layers in the first hGAA structure and the second hGAA structure and the intermediate sacrificial layer comprise a same material, wherein the second hGAA structure is shielded by a protective liner while etching the intermediate sacrificial layer, and the first hGAA structure is shielded by an encapsulation material while etching the intermediate sacrificial layer, and wherein etching the intermediate sacrificial layer results in no material loss when forming the alternating layers of nanosheet release layers in the first hGAA structure and the second hGAA structure. BRIEF DESCRIPTION OF DRAWINGS

[0010] So that the features that are exemplified by the above-recited aspects of the disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, can be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure can admit to other equally effective embodiments. The embodiments described herein are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. The following description and drawings are illustrative of the disclosure and are not to be construed as limiting the disclosure.

[0011] Figure 1 A process flow diagram illustrating a method of fabricating a complementary field effect transistor (CFET) in accordance with one or more embodiments;

[0012] Figure 2 A schematic cross-sectional view of a vertically stacked superlattice structure on a semiconductor substrate in accordance with one or more embodiments;

[0013] Figures 3A to 3E A sequence of process operations illustrating fabrication of a CFET with an intermediate dielectric isolation (MDI) layer in accordance with prior art;

[0014] Figure 4 A double cross-sectional view of a vertically stacked superlattice structure after back gate spacer deposition in accordance with one or more embodiments;

[0015] Figure 5A A desired vertically stacked superlattice structure after selective removal of an intermediate sacrificial layer;

[0016] Figure 5BFIG. illustrates a double cross-sectional view of a vertically stacked superlattice structure after deposition of a gate-last spacer, according to one or more embodiments;

[0017] Figure 6 FIG. illustrates a double cross-sectional view of a vertically stacked superlattice structure after deposition of a gate-last spacer, according to one or more embodiments;

[0018] Figure 7 FIG. illustrates a double cross-sectional view of a vertically stacked superlattice structure after deposition of a gate-last spacer, according to one or more embodiments;

[0019] Figure 8 FIG. illustrates a double cross-sectional view of a vertically stacked superlattice structure after deposition of a gate-last spacer, according to one or more embodiments;

[0020] Figure 9 FIG. illustrates a double cross-sectional view of a vertically stacked superlattice structure after deposition of a gate-last spacer, according to one or more embodiments;

[0021] Figure 10 FIG. illustrates a double cross-sectional view of a vertically stacked superlattice structure after deposition of a gate-last spacer, according to one or more embodiments;

[0022] Figure 11 FIG. illustrates a double cross-sectional view of a vertically stacked superlattice structure after deposition of a gate-last spacer, according to one or more embodiments;

[0023] Figure 12 FIG. illustrates a double cross-sectional view of a vertically stacked superlattice structure after deposition of a gate-last spacer, according to one or more embodiments;

[0024] Figure 13 FIG. illustrates a double cross-sectional view of a vertically stacked superlattice structure after deposition of a gate-last spacer, according to one or more embodiments;

[0025] Figure 14 FIG. illustrates a double cross-sectional view of a vertically stacked superlattice structure after deposition of a gate-last spacer, according to one or more embodiments;

[0026] Figure 15 FIG. illustrates a double cross-sectional view of a vertically stacked superlattice structure after deposition of a gate-last spacer, according to one or more embodiments;

[0027] Figure 16 FIG. 2 illustrates a double cross-sectional view of a bottom stack of a CFET after a carbon spin-on or CVD gap fill to expose a lower horizontal gate all around (hGAA) structure and a vertical stack of superlattice structures according to one or more embodiments;

[0028] Figure 17 FIG. 3 illustrates a double cross-sectional view of a vertical stack of superlattice structures after removal of a protective liner according to one or more embodiments;

[0029] Figure 18 FIG. 4 illustrates a double cross-sectional view of a CFET with a top stack isolated from a bottom stack with a fabricated MDI layer according to one or more embodiments. DETAILED DESCRIPTION

[0030] Before describing several exemplary embodiments of the disclosure, it is to be understood that the disclosure is not limited to the details of construction or process steps set forth in the following description. The disclosure is capable of other embodiments and of being practiced or being carried out in various ways.

[0031] The term“about” as used herein means approximate or nearly and in the context of a stated numerical value or range means a variation of ± 15% or less of the numerical value. For example, a value that differs by ± 14%, ± 13%, ± 12%, ± 11%, ± 10%, ± 9%, ± 8%, ± 7%, ± 6%, ± 5%, ± 4%, ± 3%, ± 2%, or ± 1% from the stated value would meet the definition of“about.”

[0032] Spatially relative terms such as“beneath,”“below,”“lower,”“above,”“upper” and similar terms, can be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device is inverted or flipped over, a bottom surface or feature that was described as below or beneath another surface or feature would then be oriented above the other surface or feature. Thus, the example term“below” can encompass both an orientation of below and above. The device can be oriented in other ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0033] The use of the terms "a" and "an" and "the" and similar referents in the context of describing the materials and methods discussed herein (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein unless otherwise indicated herein or otherwise clearly contradicted by context. Unless otherwise stated, the use of any and all examples, or exemplary language (e.g., "such as") provided herein, is intended to be non-exhaustive. The language of the specification should not be interpreted to mean that any unclaimed element is an essential element of the disclosed materials and methods.

[0034] Reference throughout this specification to "one embodiment", "certain embodiments", "one or more embodiments" or "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, appearances of the phrases such as "in one or more embodiments", "in certain embodiments", "in one embodiment", or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment. In one or more embodiments, the particular feature, structure, material, or characteristic is combined in any suitable manner.

[0035] As used in the present specification and throughout the claims that follow, the term "substrate" or "wafer" refers to a surface, or portions of a surface, upon which processing is performed. Those skilled in the art will appreciate that references to a substrate are intended to include both a bare substrate and a substrate having one or more films or features formed thereon. As used herein, "substrate" refers to any substrate or material surface upon which film processing is performed during fabrication. For example, a substrate surface on which processing is performed can include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxides, amorphous silicon, doped silicon, germanium, gallium arsenide, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, without limitation, semiconductor wafers. Substrates can be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the film processing steps disclosed can also be performed on an underlayer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlayer as the context dictates. Thus, for example, where a film / layer or partial film / layer has been deposited onto a substrate surface, the exposed surface of the most recently deposited film / layer becomes the substrate surface.

[0036] The term "on" indicates that there is direct contact between devices. The term "directly on" indicates that there is direct contact between devices without intervening devices.

[0037] As used in the present specification and throughout the claims that follow, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gas species that can react with a substrate surface.

[0038] "Epitaxy" is a process that forces the deposited film to highly crystalline align with the substrate. Epitaxial growth is broadly defined as condensing a gas precursor to form a film on a substrate. Liquid precursors can also be used. Gas phase precursors can be obtained by chemical vapor deposition (CVD) and laser ablation. Now several epitaxy techniques are available, such as molecular beam epitaxy (MBE), epitaxial CVD, or atomic layer epitaxy (ALE).

[0039] Transistors are circuit components or devices that are typically formed on a semiconductor device. Depending on the circuit design, transistors are formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other devices. Generally, a transistor includes a gate formed between source and drain regions. In one or more embodiments, the source and drain regions include doped regions of a substrate and exhibit a doping profile suitable for a particular application. The gate is positioned over a channel region and includes a gate dielectric interposed between the gate electrode and the channel region in the substrate.

[0040] As used herein, the term "field-effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. A field-effect transistor is a voltage-controlled device in which the current-carrying capacity of the field-effect transistor is changed by applying an electric field. Field-effect transistors typically exhibit very high input impedance at low temperatures. The conductivity between the drain terminal and the source terminal is controlled by the electric field in the device, which is generated by the voltage difference between the body and the gate of the device. The three terminals of a FET are: the source (S), through which carriers enter the channel; the drain (D), through which carriers leave the channel; and the gate (G), the terminal that modulates the conductivity of the channel. Conventionally, the current entering the channel at the source (S) is denoted as IS, while the current entering the channel at the drain (D) is denoted as ID. The voltage from drain to source is denoted as VDS. By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., ID) can be controlled.

[0041] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET) and is used in integrated circuits and high-speed switching applications. MOSFETs have an insulating gate whose voltage determines the conductivity of the device. This ability to vary the conductivity with the amount of applied voltage is used to amplify or switch electronic signals. MOSFETs are based on the modulation of the charge concentration between the body electrode and the gate electrode above the body, which is insulated from all other device regions by a gate dielectric layer. In contrast to MOS capacitors, MOSFETs include two additional terminals (source and drain), each connected to a separate highly doped region that is separated by a body region. These regions can be p- or n-type, but both have the same type or opposite type as the body region. The source and drain (unlike the body) are highly doped, as indicated by the "+" symbol after the doping type.

[0042] If the MOSFET is an n-channel or nMOS FET, the source and drain are n+ regions, and the body is a p-type substrate region. If the MOSFET is a p-channel or pMOS FET, the source and drain are p+ regions, and the body is an n-type substrate region. The source is so named because it is the source of charge carriers (electrons for n-channel, holes for p-channel) that flow through the channel; similarly, the drain is where the charge carriers exit the channel.

[0043] An nMOS FET consists of n-type source and drain and a p-type substrate. When a voltage is applied to the gate, holes in the body (p-type substrate) are driven away from the gate. This allows an n-type channel to form between the source and the drain, and current is carried by electrons from the source through the induced n-type channel to the drain. Logic gates and other digital devices implemented using NMOS are said to have NMOS logic. There are three modes of operation in NMOS, which are cut-off, triode, and saturation. A circuit with NMOS logic gates dissipates static power when the circuit is idle, because DC current flows through the logic gates when the output is low.

[0044] A pMOS FET consists of p-type source and drain and an n-type substrate. When a positive voltage is applied between the source and the gate (a negative voltage between the gate and the source), a p-type channel forms between the source and the drain with opposite polarity. Current is carried by holes from the source through the induced p-type channel to the drain. Logic gates and other digital devices implemented using PMOS are said to have PMOS logic. PMOS technology is inexpensive and has good noise immunity.

[0045] In NMOS, the charge carriers are electrons, and in PMOS, the charge carriers are holes. When a high voltage is applied to the gate, NMOS will conduct, and PMOS will not conduct. Also, when a low voltage is applied in the gate, NMOS will not conduct, and PMOS will conduct. NMOS is considered faster than PMOS because the charge carriers in NMOS are electrons, and in PMOS, the charge carriers are holes, and electrons travel twice as fast as holes. But PMOS devices have higher noise immunity than NMOS devices. Also, NMOS ICs can be smaller (given the same functionality) than PMOS ICs because NMOS can provide half the impedance provided by PMOS (with the same geometry and operating conditions).

[0046] As used herein, the term "fin field effect transistor (FinFET)" refers to a MOSFET transistor built on a substrate with the gate placed on two, three, or four sides of the channel or wrapped around the channel, forming a dual-gate structure. FinFET devices have been given the generic name "FinFET" because the source / drain regions form "fins" on the substrate. FinFET devices have fast switching times and high current densities.

[0047] As used herein, the term "gate-all-around (GAA)" is used to refer to an electronic device, such as a transistor, in which the gate material surrounds the channel region on all sides. The channel region of a GAA transistor can include nanowires or nanosheets or nanoribbons, strip-like channels, or other suitable channel configurations known to those of skill. In one or more embodiments, the channel region of a GAA device has a plurality of horizontally spaced apart horizontal nanowires or horizontal strips, such that the GAA transistor is a stacked horizontal gate-all-around (hGAA) transistor.

[0048] As used herein, the term "complementary field effect transistor (CFET)" refers to a transistor that includes a NMOS FET device and a PMOS FET device stacked on top of each other. Each of the NMOS FET device and the PMOS FET device forming the CFET is a GAA transistor or a hGAA transistor.

[0049] As used herein, the term "nanowire" refers to a nanostructure with a diameter on the order of a nanometer (10 -9 A nanowire can also be defined as having an aspect ratio greater than 1000. Alternatively, a nanowire can be defined as a structure with a thickness or diameter limited to tens of nanometers or less but with no limit on length. Nanowires are used in transistors and some laser applications, and in one or more embodiments, nanowires are made of semiconductor materials, metallic materials, insulating materials, superconductor materials, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPUs, GPUs, MPUs, as well as non-volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. As used herein, the term "nanosheet" refers to a two-dimensional nanostructure with a thickness on the scale of from about 0.1 nm to about 1000 nm, or from 0.5 nm to 500 nm, or from 0.5 nm to 100 nm, or from 1 nm to 500 nm, or from 1 nm to 100 nm, or from 1 nm to 50 nm.

[0050] As used herein, "material loss" in a layer, particularly "material loss" in a nanosheet release layer and / or a nanosheet channel layer, refers to the loss or removal of a portion of the material forming such layer. In particular, "material loss" in a nanosheet release layer and / or a nanosheet release layer is described herein in connection with the loss or removal of a portion of the material forming such layer during removal of the intervening sacrificial layer. For example, in embodiments of an intervening sacrificial layer formed of SiGe, a nanosheet release layer formed of SiGe (same or different concentration of Ge), and a nanosheet channel layer formed of Si, the removal process (such as etching or another appropriate removal process) performed for removal of the intervening sacrificial layer results in unintended loss or removal of a portion of the SiGe forming the nanosheet release layer and / or loss or removal of a portion of the Si forming the nanosheet channel layer.

[0051] Generally, to remove the intervening sacrificial layer within a CFET superlattice by an etching process without etching the nanosheet release layer, a three-color selectivity of >10: 1 is required. In a typical patterned wafer, the selectivity is extremely high for SiGe versus Si (e.g., a nanosheet channel layer formed of Si versus an intervening sacrificial layer and a nanosheet release layer formed of SiGe), satisfying the >10: 1 requirement. However, for SiGe with high germanium content (i.e., higher than 30% in atomic) versus SiGe with low germanium content (i.e., higher than 15-20% in atomic), the selectivity is much lower and does not satisfy the >10: 1 requirement. Thus, monolithic CFETs have been fabricated by relying on a relatively high germanium content within the intervening sacrificial layer relative to the germanium content in the nanosheet release layer.

[0052] Without intending to be bound by any particular theory of operation, it is believed that reliance on a selective etch process based on a relatively high germanium content in the intermediate sacrificial layer relative to the germanium content in the nanosheet release layer of the vertically stacked superlattice structure can result in defects due to some material loss also occurring in the nanosheet release layer. Without intending to be bound by any particular theory of operation, it is further believed that the selective etch process can result in loss of material forming the nanosheet channel layer, resulting in a circular distribution of the nanosheet channel layer after etching the intermediate sacrificial layer. Embodiments of the disclosure advantageously provide a vertically stacked superlattice structure in which loss of material forming the nanosheet release layer and the nanosheet channel layer is minimized or prevented when removing the intermediate sacrificial layer. In some embodiments, loss of material forming the nanosheet release layer and the nanosheet channel layer is minimized or prevented by etching the exposed intermediate sacrificial layer while protecting both the upper hGAA structure and the lower hGAA structure, such as by using a protective liner to coat the upper hGAA structure and a protective gap fill material to surround the lower hGAA structure. In some embodiments, the selective etching of the intermediate sacrificial layer can be accomplished without relying on the etch selectivity of the material forming the intermediate sacrificial layer relative to the material forming the nanosheet release layer.

[0053] According to one or more embodiments, any material can be used to form the intermediate sacrificial layer and the nanosheet release layer, and the selective etching of the intermediate sacrificial layer can be performed while minimizing or preventing etching of the nanosheet release layer. According to one or more embodiments, the material forming the intermediate sacrificial layer can have a higher etch selectivity than the material forming the nanosheet release layer. According to one or more embodiments, the material forming the intermediate sacrificial layer can have the same or substantially the same etch selectivity as the material forming the nanosheet release layer. According to one or more embodiments, the same or substantially the same material can be used to form the intermediate sacrificial layer and the nanosheet release layer. According to one or more embodiments, the nanosheet channel layer comprises Si and the intermediate sacrificial layer and the nanosheet release layer independently comprise SiGe. According to one or more embodiments, a stack of alternating nanosheet channel layers comprising Si and nanosheet release layers comprising SiGe, and an intermediate sacrificial layer comprising SiGe, is capable of forming a vertically stacked superlattice structure that is strained and free of crystalline lattice defects. According to one or more embodiments, the material forming the intermediate sacrificial layer is the same as the material forming the nanosheet release layer, and the fabrication of the vertical superlattice structure is simplified because fewer material compositions are needed when forming the various layers. Furthermore, without being bound by theory, it is believed that using the same material composition (e.g., the same SiGe material) to form the intermediate sacrificial layer and the nanosheet release layer not only allows for a more simplified fabrication process, but also reduces potential defects that can arise during fabrication processes that use different materials.

[0054] Embodiments of the present disclosure are described herein with reference to the accompanying drawings, which illustrate devices (e.g., transistors) and processes for forming transistors according to one or more embodiments of the present disclosure. The processes shown are merely illustrative of possible uses of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the illustrated applications.

[0055] Figure 1 A process flow diagram depicting a method 100 of fabricating a complementary field effect transistor (CFET) according to one or more embodiments of the present disclosure. The method 100 includes forming a vertically stacked superlattice structure on a substrate at operation 102. In one or more embodiments, the superlattice is strained and free of crystalline lattice defects. At operation 104, the vertically stacked superlattice structure is formed on the substrate by disposing a first or lower horizontal gate all around (hGAA) structure on the substrate. The first or lower hGAA is formed of alternating layers of nanosheet channel layers and nanosheet release layers. At operation 106, an intermediate sacrificial layer is formed on a top surface of the first or lower hGAA structure. At operation 108, a second or upper horizontal gate all around (hGAA) structure is formed on a top surface of the sacrificial layer. The second hGAA is formed of alternating layers of nanosheet channel layers and nanosheet release layers. After forming the gate structure on a top surface of the second hGAA, a spacer layer is deposited on outer surfaces of the gate structure and on top surfaces of the hGAA not covered by the gate structure at operation 110. At operation 112, a series of trenches are etched in the vertically stacked superlattice structure and source / drain regions are formed. At operation 114, a spin-on, CVD carbon gap fill, or other suitable process is performed to surround the entire vertical superlattice structure with an encapsulation material from a top surface of the substrate to a top of the gate structure, followed by planarization. At operation 116, the encapsulation material is etched to expose the gate structure and the second hGAA. At operation 118, a protective liner is deposited on the exposed top surfaces of the gate structure, the second hGAA, and the etched encapsulation material. At operation 120, the protective liner is removed from the top surface of the etched encapsulation material. At operation 122, the method 100 includes etching the encapsulation material to expose the intermediate sacrificial layer. At operation 124, the intermediate sacrificial layer is removed so that an intermediate spacer layer can be formed during subsequent processing.

[0056] Figure 2A simplified diagram of a CFET device 200 including a substrate 210 having a top surface 212. The substrate 210 can be any suitable substrate material known to those of skill in the art. In one or more embodiments, the substrate 210 includes a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphide (InP), indium gallium arsenide (InGaAs), aluminum indium arsenide (InAlAs), germanium (Ge), silicon germanium (SiGe), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 210 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), indium (In), phosphorus (P), or selenium (Se). Although several examples of materials that can form the substrate 210 are described herein, any material that can be used as a foundation upon which passive and active electronic devices (e.g., transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic device) can be built upon fall within the spirit and scope of the present disclosure.

[0057] In one or more embodiments, the substrate 210 is a p-type or n-type substrate. As used herein, the term "n-type" refers to a semiconductor that is produced by doping an intrinsic semiconductor with an electron donor element during fabrication. The term n-type comes from the negative charge of the electron. In an n-type semiconductor, electrons are the majority carriers, and holes are the minority carriers. As used herein, the term "p-type" refers to a positive charge of holes (or electron holes). In contrast to n-type semiconductors, the hole concentration is greater than the electron concentration in p-type semiconductors. In a p-type semiconductor, holes are the majority carriers, and electrons are the minority carriers.

[0058] In one or more embodiments, the vertically-stacked superlattice structure 260 includes one or more horizontal fully-encircling gate (hGAA) structures on the substrate 210. In some embodiments, the vertically-stacked superlattice structure 260 includes a first or lower horizontal fully-encircling gate (hGAA) structure 215 on the top surface 212 of the substrate 210. In some embodiments, the vertically-stacked superlattice structure 260 includes a second or upper horizontal fully-encircling gate (hGAA) structure 255. Without being bound by any particular theory of operation, the first or lower hGAA 215 and the second or upper hGAA 255 can independently include the same structure with the same layers. According to one or more embodiments, the vertically-stacked superlattice structure 260 includes a first hGAA structure 215 on the top surface 212 of the substrate 210, an intermediate sacrificial layer 240 on a top surface 225 of the first hGAA structure 215, and a second hGAA structure 255 on a top surface 245 of the intermediate sacrificial layer 240.

[0059] In some embodiments, each of the first hGAA 215 and the second hGAA 255 includes alternating layers of nanosheet channel layers 230 and nanosheet release layers 220. In some embodiments, the plurality of nanosheet release layers 220 and the plurality of nanosheet channel layers 230 can include any number of lattice-matched material pairs suitable for forming a vertical stack of superlattice structures 260. In some embodiments, each of the first hGAA 215 and the second hGAA 255 has a range of 1 to 5 pairs of alternating nanosheet channel layers 230 and nanosheet release layers 220.

[0060] The nanosheet release layers 220 can have any appropriate thickness. In one or more embodiments, each nanosheet release layer 220 has a thickness ranging from about 5 nm to about 15 nm. The nanosheet channel layers 230 can have any appropriate thickness. In one or more embodiments, each nanosheet channel layer 230 has a thickness ranging from about 4 nm to about 15 nm.

[0061] In some embodiments, each of the nanosheet channel layers 230 independently includes silicon (Si). In some embodiments, each of the nanosheet release layers 220 independently includes silicon germanium (SiGe). In one or more embodiments, the nanosheet release layers 220 include silicon germanium (SiGe) having a germanium content ranging from greater than 0% to about 50% by atom. In specific embodiments, the nanosheet release layers 220 include silicon germanium (SiGe) having a germanium content ranging from about 10% to about 40% by atom, including 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, 29%, 30%, 31%, 32%, 33%, 34%, 35%, 36%, 37%, 38%, 39%, and 40% by atom of silicon germanium (SiGe).

[0062] In one or more embodiments, a sacrificial layer 240 is formed between the first or lower hGAA 215 and the second or upper hGAA 255. In one or more embodiments, the intermediate sacrificial layer 240 is selectively removed and replaced with an intermediate dielectric isolation (MDI) layer 340 during later processing. The intermediate dielectric isolation (MDI) layer 340 serves to electrically isolate the source / drain regions of the lower hGAA 215 from the source / drain regions of the upper hGAA 255. In one or more embodiments, the intermediate sacrificial layer 240 includes silicon germanium (SiGe) having a germanium content greater than 0% to about 65% by atom. In specific embodiments, the intermediate sacrificial layer 240 includes silicon germanium (SiGe) having a germanium content in a range of about 10% to about 65% by atom, including 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, 29%, 30%, 31%, 32%, 33%, 34%, 35%, 36%, 37%, 38%, 39%, 40%, 41%, 42%, 43%, 44%, 45%, 46%, 47%, 48%, 49%, 50%, 51%, 52%, 53%, 54%, 55%, 56%, 57%, 58%, 59%, 60%, 61%, 62%, 63%, 64%, and 65% by atom of silicon germanium (SiGe).

[0063] According to one or more embodiments, the intermediate sacrificial layer 240 is fabricated from silicon germanium (SiGe) having a relatively higher germanium content than the germanium content in the nanosheet release layer 220. According to one or more embodiments, the nanosheet release layer 220 and the intermediate sacrificial layer 240 each individually include silicon germanium (SiGe) having substantially the same germanium content. By “substantially the same” content, it is meant that the germanium content in the nanosheet release layer 220 is within about ±1% to 5% of the germanium content in the intermediate sacrificial layer 240 by atom. According to one or more embodiments, the nanosheet release layer 220 and the intermediate sacrificial layer 240 each individually include silicon germanium (SiGe) having the same germanium content.

[0064] In one or more embodiments, the sacrificial layer 240 can have any suitable thickness. In some embodiments, the sacrificial layer 240 has a thickness within a range of about 15 nm to about 90 nm, including a range of about 15 nm to about 80 nm, a range of about 20 nm to about 75 nm, a range of about 15 nm to about 60 nm, a range of about 15 nm to about 50 nm, a range of about 15 nm to about 75 nm, and a range of about 20 nm to about 50 nm.

[0065] As recognized by one of skill in the art, during subsequent processing, the intermediate sacrificial layer 240 can be removed and replaced with an intermediate dielectric isolation (MDI) layer 340. Selectively removing the intermediate sacrificial layer 240 can be performed by any suitable means known to one of skill in the art. In some embodiments, selectively removing the intermediate sacrificial layer 240 includes an etch process that removes the intermediate sacrificial layer 240 without causing material loss in the nanosheet release layer 220. In some embodiments, the etch process includes one or more of a wet etch process or a dry etch process. In some embodiments, the etch process is a directional etch.

[0066] As Figures 3A to 3E depicted, a general process for forming the CFET 200 is depicted, in which a vertically stacked superlattice structure 260 is provided, including a first or lower hGAA 215 on a substrate 210, an intermediate sacrificial layer 240 disposed on the lower hGAA 215, and a second or upper hGAA 255 stacked on top of the intermediate sacrificial layer 240, with a gate structure 270 on a top surface of the second or upper hGAA 255, and a spacer layer 280 deposited on an outer surface of the gate structure 270. A series of trenches 290 are etched in the vertically stacked superlattice structure 260 to a top surface 212 of the substrate, and source / drain regions are formed. Next, the intermediate sacrificial layer 240 is selectively removed, e.g., via an etch process. Then, an intermediate dielectric isolation (MDI) material is deposited over the entire structure, and fills the cavities left by the removed intermediate sacrificial layer 240. Finally, the MDI material is removed, such that the MDI material remains only within the cavities left by the removed intermediate sacrificial layer 240, thus forming an intermediate dielectric isolation (MDI) layer 340.

[0067] Figure 4 An enlarged view of an embodiment of the vertically stacked superlattice structure 260 is depicted after deposition of the spacer layer 280 corresponding to the Figure 3A As shown, the first or lower hGAA 215 and the second or upper hGAA 255 each include alternating layers of nanosheet channel layers 230 and nanosheet release layers 220. In this embodiment, each nanosheet channel layer 230 includes silicon (Si), and each nanosheet release layer 220 includes silicon germanium (SiGe). The intermediate sacrificial layer 240 includes silicon germanium (SiGe). As Figures 3A to 3E and Figure 4 depicted in the embodiment shown, to selectively remove the intermediate sacrificial layer 240 while at the same time maintaining the nanosheet release layer 220, the intermediate sacrificial layer 240 is fabricated from silicon germanium (SiGe) having a relatively higher germanium content than the germanium content in the nanosheet release layer 220.

[0068] As Figure 5AAs shown, the desired superlattice profile after selective removal of the intermediate sacrificial layer 240 is smooth and uniform. As depicted, the surface of the alternating layers of nanosheet channel layers 230 and nanosheet release layers 220 is flat and level with a defect-free surface along the stack. However, it has been found that selective removal based on the relatively high germanium content within the intermediate sacrificial layer 240 results in undesirable material loss in one or more additional material layers. For example, as shown Figure 5B As shown, selective etching of the intermediate sacrificial layer 240 having a relatively high germanium content compared to the nanosheet release layers 220 results in material loss of the nanosheet release layers 220. Rather than providing the desired smooth and uniform superlattice profile via selective removal of only the intermediate sacrificial layer 240, portions of the nanosheet release layers 220 are also removed. Thus, the superlattice profile of alternating nanosheet channel layers 230 and nanosheet release layers 220 is provided, where the outer surface of the nanosheet release layers 220 is recessed, sloped inward, and / or otherwise has surface roughness due to the removed portions of material. As a result, the nanosheet release layers 220 are not otherwise level with the outer surface of the nanosheet channel layers 230 after selective removal of the intermediate sacrificial layer 240. This material loss from the nanosheet release layers 220 adversely affects subsequent removal processes of the nanosheet release layers 220. For example, the material loss from the nanosheet release layers 220 results in a rough and uneven surface of the nanosheet release layers 220. This can result in random and uneven spacer cavities between the nanosheet channel layers 230, which can cause variations in Vt control. Additionally, it has been found that material loss (i.e., loss of Si) also occurs in the nanosheet channel layers 220, which creates smaller (relative to the size of the nanosheet channel layers 230 prior to selective etching of the intermediate sacrificial layer 240) and rounded shapes, as shown Figure 5B As shown. This material loss in the nanosheet channel layers 230 adversely affects source / drain growth and device performance.

[0069] Referring to Figures 6 to 17According to one or more embodiments, a CFET is provided having a vertically stacked superlattice structure 260, which has a smooth distribution along upper and lower stacked hGAA structures 215, 255 after removal of the intermediate sacrificial layer 240, and wherein the nanosheet channel layers 230 are spaced apart from each other by uniform spacer cavities after subsequent removal of the nanosheet release layer 220. According to one or more embodiments, a CFET and a method of manufacturing such a device are provided, wherein the nanosheet release layer 220 and the channel layer 230 are protected from damage and material loss during removal of the intermediate sacrificial layer 240. Furthermore, according to one or more embodiments, the removal of the intermediate sacrificial layer 240 is achieved without material loss in the nanosheet channel layer 230 or the nanosheet release layer 220, regardless of the materials used to form the intermediate sacrificial layer 240, the nanosheet channel layer 230, and the nanosheet release layer 220.

[0070] like Figure 6 As shown, according to one or more embodiments, a vertically stacked superlattice structure 260 is provided on a substrate 210. The vertically stacked superlattice structure 260 includes a first or lower horizontal hGAA structure 215 on the top surface 212 of the substrate, an intermediate sacrificial layer 240 disposed on the top surface 225 of the first or lower hGAA structure 215, and a second or upper hGAA structure 255 disposed on the top surface 245 of the sacrificial layer 240. According to one or more embodiments, the first or lower hGAA structure 215 and the second or upper hGAA structure 255 each individually include alternating layers of nanosheet channel layer 230 and nanosheet release layer 220. A gate structure 270 is disposed on the top surface of the second or upper hGAA structure 255. Furthermore, a spacer layer 280 is deposited on the outer surface of the gate structure 270 and the exposed top surface (i.e., the surface not covered by the gate structure 270) of the second or upper hGAA structure 255. It should be noted that, although Figures 6 to 17 The illustrated embodiment depicts six gates, but the method and structure are not limited to this number.

[0071] According to one or more embodiments, a series of vertical trenches 290 are etched along the sidewalls of the gate structure 270 in the vertically stacked superlattice structure 260. The trenches extend through the second or upper hGAA structure 255, the intermediate sacrificial layer 240, and the first or lower hGAA structure 215, stopping at the top surface 212 of the substrate. Source / drain regions are further formed. Figure 7 The structure obtained from the icon.

[0072] like Figure 8 As shown, a material deposition process has been performed, followed by planarization. According to one or more embodiments, encapsulation material 300 is deposited to surround the structure (e.g., Figure 7The encapsulation material is any suitable material capable of protecting the underlying first or lower hGAA structure 255 during subsequent removal of the intermediate sacrificial layer 240 (e.g., by etching or other suitable removal process). According to one or more embodiments, the encapsulation material 300 includes carbon. As shown, according to one or more embodiments, the encapsulation material 300 is deposited to fill the voids (including the trench 290) in the entire vertical superlattice structure from the substrate top surface 212 to the top of the gate structure 270, as well as around the vertically stacked superlattice structure 260 and the gate structure 270. The encapsulation material 300 can be deposited by using spin-on, CVD carbon gap fill, or other suitable process.

[0073] According to one or more embodiments, portions of the encapsulation material 300 are removed, such as by etching, as shown. Figure 9 As depicted, the encapsulation material 300 has been removed around the gate structure 270 and the second or upper hGAA structure 255. As a result, only the substrate 210, the first or lower hGAA structure 215, and the intermediate sacrificial layer 240 remain surrounded by the encapsulation material 300, as depicted by the dashed line. Figure 9

[0074] Figure 10 A protective liner 310 is deposited on the exposed top surface of the gate structure 270, the second or upper hGAA structure 255, and the encapsulation material 300, according to one or more embodiments. The protective liner 310 can be formed of any suitable material capable of protecting the underlying upper or second hGAA structure 255 during subsequent removal of the intermediate sacrificial layer 240 (e.g., by etching or other suitable removal process). According to one or more embodiments, the protective liner 310 includes a layer of A10x or SiN having a thickness of at least about 0.5 nm and up to about 4 nm, including a range from about 0.6 nm to about 3.9 nm, about 0.7 nm to about 3.8 nm, about 0.8 nm to about 3.7 nm, about 0.9 nm to about 3.6 nm, and about 1 nm to about 3.5 nm. In particular embodiments, the protective liner 310 includes a layer of A10x or SiN having a thickness in a range from about 1 nm to about 3 nm, including 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm, 2 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, 2.6 nm, 2.7 nm, 2.8 nm, 2.9 nm, and 3 nm.

[0075] After deposition of the protective liner 310, a bottom opening etch process is performed to remove the protective liner 310 from the top surface of the encapsulation material 300. As Figure 11 ​As shown, according to one or more embodiments, a bottom opening etch process exposes a top surface of the encapsulation material 300, which is disposed on the sidewalls of and within the trenches 290 of the vertically stacked superlattice structure 260 above the top surface 245 of the intermediate sacrificial layer.

[0076] Then, a portion of the encapsulation material 300 is removed to expose the intermediate sacrificial layer 240, as Figure 12 depicted. According to one or more embodiments, a carbon pullback etch is performed to reveal the intermediate sacrificial layer 240. As Figure 12 depicted, a vertically stacked superlattice structure 260 is now provided, wherein (a) the substrate 210 and the first or lower hGAA structure 215 are completely surrounded and protected by the encapsulation material 300, (b) the gate structure 270 and the second or upper hGAA structure 255 are surrounded and protected by the protective liner 310, and (c) the intermediate sacrificial layer 240 is exposed for subsequent etch or removal processes.

[0077] As Figure 13 shown, according to one or more embodiments, the intermediate sacrificial layer 240 has been removed using an etch or other suitable process. When the intermediate sacrificial layer 240 is removed, the substrate 210, the first or lower hGAA structure 215, the gate structure 270, and the second or upper hGAA structure 255 are protected from the removal process (e.g., etch) and material loss.

[0078] In Figure 14 the intermediate dielectric isolation (MDI) material 320 is deposited over the entire structure to fill the cavities left by the removed intermediate sacrificial layer 240, the trenches 290, and to cover the outer surface of the device upward from the encapsulation material 300. Advantageously, depositing the MDI material 320 when the encapsulation material 300 covers the first or lower hGAA structure 215 provides a lower aspect ratio, which facilitates the deposition process.

[0079] According to one or more embodiments as Figure 15 shown, the MDI material 320 is trimmed back so that it remains only in the cavities left by the removed intermediate sacrificial layer 240. Again, the reduced aspect ratio provided by the encapsulation material 300 facilitates this trimming back process. Then, densification of the MDI material 320 is performed to form the intermediate dielectric isolation (MDI) layer 340.

[0080] As Figure 16 shown, according to one or more embodiments, the remaining portion of the encapsulation material 300 is removed. For example, in embodiments in which the encapsulation material 300 is carbon, a radical ashing can be performed to remove the carbon material and expose the first or lower hGAA structure 215.

[0081] In Figure 17In some embodiments, the protective liner 310 is removed to expose the gate structure 270 and the second or upper hGAA structure 255.

[0082] With the now exposed first hGAA structure 215 and second hGAA structure 255, additional processing steps can be performed, including a selective etch process to remove the nanosheet release layer 220 and form uniform cavities that separate the nanosheet channel layers 230. For example, Figure 18 A CFET formed according to one or more embodiments is illustrated in FIG. 3B after additional processing steps.

[0083] According to one or more embodiments, methods and structures for forming electronic devices, and in particular, CFETs, are provided in which STI oxide loss is reduced or prevented. In particular, during typical etch and clean procedures, STI loss is induced that can lead to the Si fin base becoming fully exposed. Subsequent epitaxial growth of the source / drain can lead to growth from the bottom Si fin sidewalls, which can induce electrical failure. Without being bound by theory, according to one or more embodiments, the encapsulation material 300 provides shielding of the underlying components from clean, removal, and etch steps throughout the process, including during the repair of the sacrificial layer 240 and MDI layer 340 in between etches. According to one or more embodiments, the encapsulation material 300 shields the underlying components, and thus reduces or even prevents STI loss.

[0084] While this disclosure has been described in reference to particular embodiments, it should be recognized that such embodiments are merely illustrative of the principles and applications of this disclosure. Numerous modifications and adaptations will be readily apparent to those skilled in the art without departing from the spirit and scope of the disclosure. Therefore, the disclosure intends to cover modifications and variations of the described methods and devices provided they come within the scope of the appended claims and their equivalents.

Claims

1. A method for forming a semiconductor device, the method comprising the following steps: The following steps are used to form a vertically stacked superlattice structure on a substrate. A first horizontal all-around gate (hGAA) structure is formed on the substrate, the first hGAA structure comprising alternating layers of nanosheet channel layers and nanosheet release layers; An intermediate sacrificial layer is formed on the top surface of the first hGAA structure; A second horizontal all-around gate (hGAA) structure is formed on the top surface of the intermediate sacrificial layer. The second hGAA structure includes alternating layers of nanosheet channel layers and nanosheet release layers. Deposit encapsulation material to fill one or more trenches in the vertically stacked superlattice structure and around the vertically stacked superlattice structure; Remove a portion of the encapsulation material to expose the second hGAA structure; A protective liner is deposited on the second hGAA structure; Remove a portion of the encapsulation material to expose the intermediate sacrificial layer; as well as Remove the intermediate sacrificial layer. During the removal of the intermediate sacrificial layer, the first hGAA structure is covered by the encapsulation material, and the second hGAA structure is covered by the protective pad.

2. The method of claim 1, wherein the step of depositing the encapsulation material to fill one or more trenches in the vertically stacked superlattice structure and around the vertically stacked superlattice structure comprises the step of performing a spin-coating or chemical vapor deposition (CVD) carbon interstitial filling process.

3. The method of claim 1, wherein the protective liner comprises a layer of AlOx or SiN.

4. The method of claim 3, wherein the step of depositing the protective liner comprises the step of depositing an AlOx or SiN layer having a thickness ranging from about 0.5 nm to about 4 nm.

5. The method of claim 1, wherein the step of removing the intermediate sacrificial layer comprises the step of etching the intermediate sacrificial layer.

6. The method of claim 5, wherein the encapsulation material and the protective liner shield the first hGAA structure and the second hGAA structure and prevent material loss in the alternating layers of the nanosheet release layer and the nanosheet channel layer during etching.

7. The method of claim 1, further comprising the steps of: after removing the intermediate sacrificial layer, depositing an intermediate dielectric isolation (MDI) material within at least one cavity formed by removing the intermediate sacrificial layer; removing an excess of the deposited MDI material so that the MDI material remains only within the cavity; and densifying the MDI material to form an MDI layer.

8. The method of claim 7, further comprising the steps of: after densifying the MDI material, removing the encapsulation material and the protective liner to expose the first hGAA structure and the second hGAA structure; and performing selective etching to remove the alternating layers of the nanosheet release layer from the first hGAA structure and the second hGAA structure.

9. The method of claim 1, wherein the alternating layers of the nanosheet channel layer comprise silicon (Si), the alternating layers of the nanosheet release layer comprise silicon-germanium (SiGe), and the intermediate sacrificial layer comprises silicon-germanium (SiGe).

10. The method of claim 9, wherein the alternating layers of the nanosheet release layer comprise silicon germanium (SiGe) having a germanium content of from about 10% to about 40% on an atomic basis, and the intermediate sacrificial layer comprises silicon germanium (SiGe) having a germanium content of from about 10% to about 65% on an atomic basis.

11. The method of claim 10, wherein the alternating layers of the nanosheet release layer comprise silicon germanium (SiGe) having a germanium content of about 15% to about 35% on an atomic basis, and the intermediate sacrificial layer comprises silicon germanium (SiGe) having a germanium content of about 15% to about 35% on an atomic basis.

12. The method of claim 9, wherein the alternating layers of the nanosheet release layer and the intermediate sacrificial layer are made of the same material.

13. The method of claim 1, wherein the etch selectivity of the material forming the alternating layers of the nanosheet release layer is the same as the etch selectivity of the material forming the intermediate sacrificial layer.

14. The method of claim 7, wherein the excess of deposited MDI material and removal of deposited MDI material when the first hGAA structure is covered by the encapsulation material provides a lower aspect ratio for depositing and removing the MDI material.

15. The method of claim 7, wherein densifying the MDI material when the first hGAA structure is covered by the encapsulation material and when the second hGAA structure is covered by the protective liner contributes to the densification of the MDI material.

16. A method of forming a semiconductor device, the method comprising the steps of: The following steps are used to form a vertically stacked superlattice structure on a substrate. A first horizontal all-around gate (hGAA) structure is formed on the substrate, the first hGAA structure comprising alternating layers of nanosheet channel layers and nanosheet release layers; An intermediate sacrificial layer is formed on the top surface of the first hGAA structure; A second horizontal all-around gate (hGAA) structure is formed on the top surface of the sacrificial layer. This second hGAA structure comprises alternating layers of nanosheet channel layers and nanosheet release layers; and Etch the intermediate sacrificial layer. The alternating layers of the nanosheet release layer and the intermediate sacrificial layer in the first hGAA structure and the second hGAA structure contain the same material. During the etching of the intermediate sacrificial layer, the second hGAA structure is shielded by a protective pad, and during the etching of the intermediate sacrificial layer, the first hGAA structure is shielded by encapsulation material. Etching the intermediate sacrificial layer results in no material loss in the alternating layers of the nanosheet release layers in the first hGAA structure and the second hGAA structure.

17. The method of claim 16, wherein the encapsulation material is carbon, and is deposited on the first hGAA structure using a spin-coating or chemical vapor deposition (CVD) carbon interstitial filling process.

18. The method of claim 16, wherein the protective liner comprises a layer of AlOx or SiN.

19. The method of claim 16, wherein the alternating layers of the nanosheet channel layer comprise silicon (Si), the alternating layers of the nanosheet release layer comprise silicon-germanium (SiGe), and the intermediate sacrificial layer comprises silicon-germanium (SiGe).

20. The method of claim 19, wherein the alternating layers of the nanosheet release layer and the intermediate sacrificial layer individually comprise silicon germanium (SiGe) having the same germanium content.

Images