A method of making a high thermal conductivity silicon carbide coating

Abstract

This invention relates to the technical field of semiconductor material preparation, and provides a method for preparing a high thermal conductivity silicon carbide coating. The method employs a two-stage chemical vapor deposition process to sequentially deposit a first silicon carbide coating and a second silicon carbide coating on a substrate surface. The silicon carbide grain size in the first coating is A μm, and the silicon carbide grain size in the second coating is B μm, where A and B satisfy: A ≥ 70; B ≥ 70; 1 < B / A ≤ 2.2. Simultaneously, combined with a post-deposition heat treatment process, the bonding strength, thermal conductivity, and etching resistance can be improved at the same time.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor material preparation, and specifically to a method for preparing a high thermal conductivity silicon carbide coating. Background Technology

[0002] Silicon carbide, as an important wide-bandgap semiconductor material, possesses excellent electrical properties such as high electron saturation drift velocity and high breakdown field strength. It also has good mechanical properties, thermal properties and chemical stability, which enables it to adapt to extreme service conditions such as high temperature, high pressure and high frequency. It plays an irreplaceable role in key semiconductor device fields such as semiconductor effect transistors and ultra-high power semiconductor devices.

[0003] Silicon carbide (SiC) relies on phonon transfer for thermal conductivity. Poor thermal conductivity leads to heat accumulation in the etching environment, exacerbating phonon scattering, causing stress cracking in the coating, and resulting in etchant penetration and loss, thus shortening its lifespan. Conversely, good thermal conductivity allows for timely heat dissipation and maintains coating stability. Therefore, its thermal conductivity is one of the key factors determining whether it can operate at high speeds in an etching environment for extended periods. However, in existing technologies, when preparing SiC coatings using chemical vapor deposition (CVD), the SiC coating exhibits dispersed crystal orientations (such as multiple crystal plane orientations like (111), (220), (311), and (222)). The numerous grain boundaries exacerbate phonon scattering, leading to a significant decrease in thermal conductivity and reduced etching resistance. Consequently, it cannot operate continuously for extended periods in high-temperature etching environments, resulting in short lifespans for downstream devices. Therefore, a CVD process solution is urgently needed to address these technical bottlenecks. Summary of the Invention

[0004] The purpose of this invention is to overcome the aforementioned problems in the prior art and provide a method for preparing a high thermal conductivity silicon carbide coating. The method provided by this invention achieves simultaneous improvement in bonding strength, thermal conductivity, and etching resistance through two chemical vapor deposition (CVD) processes.

[0005] To achieve the above objectives, a first aspect of the present invention provides a method for preparing a silicon carbide coating with high thermal conductivity, comprising the following steps:

[0006] (1) After pretreatment of the substrate, it is placed in a chemical vapor deposition equipment, the chemical vapor deposition equipment is evacuated, and then the air in the chemical vapor deposition equipment is replaced with inert gas and heated.

[0007] (2) The mixture of the first silicon carbide source gas, the first carrier gas and the first dilution gas is introduced into the chemical vapor deposition equipment, the first deposition temperature is controlled at 1350℃-1600℃ and the first deposition pressure is 5KPa-50KPa, and the first silicon carbide coating is obtained by first deposition on the surface of the substrate using the chemical vapor deposition process.

[0008] (3) Place the first silicon carbide coating obtained in step (2) into the chemical vapor deposition equipment again, introduce a mixture of second silicon carbide source gas, second carrier gas and second dilution gas, control the second deposition temperature to 1350℃-1600℃, the second deposition pressure to 5KPa-50KPa, and perform a second deposition on the surface of the first silicon carbide coating using the chemical vapor deposition process to obtain the second silicon carbide coating.

[0009] (4) After cooling, heat treatment is performed at a temperature of 1400℃-1600℃ for 3h-6h.

[0010] Wherein, the grain size of silicon carbide in the first silicon carbide coating is denoted as A μm, and the grain size of silicon carbide in the second silicon carbide coating is denoted as B μm, and A and B satisfy: A≥70; B≥70; 1<B / A≤2.2.

[0011] The second aspect of the present invention provides a semiconductor material prepared by the method provided in the first aspect of the present invention.

[0012] The third aspect of the present invention provides an application of the semiconductor material provided in the second aspect in a semiconductor etching process.

[0013] The present invention, by adopting the above technical solution, has the following beneficial effects:

[0014] The method provided by this invention uses two chemical vapor deposition (CVD) processes to first generate a first silicon carbide coating with large-sized grains on the substrate surface, and then generate a second silicon carbide coating with grains slightly larger than the first layer using the first silicon carbide coating as a substrate. Combined with subsequent high-temperature heat treatment processes, this method can not only ensure the bonding strength between the silicon carbide coating and the substrate, and between the two coating layers, avoiding coating cracking or peeling under high-temperature conditions, but also further improve the thermal conductivity and etching resistance of the silicon carbide coating, ultimately obtaining a high-performance silicon carbide coating suitable for high-temperature and etching service scenarios of semiconductors.

[0015] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and should be understood to include values ​​close to those ranges or values. For numerical ranges, endpoint values ​​of various ranges, endpoint values ​​of various ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. In this document, unless otherwise specified, data ranges include endpoints. Attached Figure Description

[0016] Figure 1 The image shown is an electron microscope image of a silicon carbide coating in an example of the present invention.

[0017] Figure 2 The image shown is an electron microscope image of the silicon carbide coating in Comparative Example 1 of the present invention. Detailed Implementation

[0018] The following provides a detailed description of specific embodiments of the present invention. It should be understood that the specific embodiments described herein are for illustrative and explanatory purposes only and are not intended to limit the scope of the invention.

[0019] Unless otherwise defined, all scientific and technical terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art.

[0020] The first aspect of this invention provides a method for preparing a silicon carbide coating with high thermal conductivity, comprising the following steps:

[0021] (1) After pretreatment of the substrate, it is placed in a chemical vapor deposition equipment, the chemical vapor deposition equipment is evacuated, and then the air in the chemical vapor deposition equipment is replaced with inert gas and heated.

[0022] (2) The mixture of the first silicon carbide source gas, the first carrier gas and the first dilution gas is introduced into the chemical vapor deposition equipment, the first deposition temperature is controlled at 1350℃-1600℃ and the first deposition pressure is 5KPa-50KPa, and the first silicon carbide coating is obtained by first deposition on the surface of the substrate using the chemical vapor deposition process.

[0023] (3) Place the first silicon carbide coating obtained in step (2) into the chemical vapor deposition equipment again, introduce a mixture of second silicon carbide source gas, second carrier gas and second dilution gas, control the second deposition temperature to 1350℃-1600℃, the second deposition pressure to 5KPa-50KPa, and perform a second deposition on the surface of the first silicon carbide coating using the chemical vapor deposition process to obtain the second silicon carbide coating.

[0024] (4) After cooling, heat treatment is performed at a temperature of 1400℃-1600℃ for 3h-6h.

[0025] Wherein, the grain size of silicon carbide in the first silicon carbide coating is denoted as A μm, and the grain size of silicon carbide in the second silicon carbide coating is denoted as B μm, and A and B satisfy: A≥70; B≥70; 1<B / A≤2.2.

[0026] Among different silicon carbide morphologies, 3C-SiC (tetrahedral cubic silicon carbide) better meets the core requirements of semiconductor applications. It not only has a relatively lower coefficient of thermal expansion but also better thermal conductivity compared to other SiC crystal forms. These two characteristics give it significant advantages in semiconductor applications, making it an ideal material for the extreme service environments of related semiconductor devices. Currently, most silicon carbide coatings prepared by CVD methods are tetrahedral 3C-SiC. However, it is difficult to achieve a uniform morphology, and there are regions without tetrahedral morphology. These regions perform poorly in high-temperature etching environments and have weak etching resistance.

[0027] The method provided by this invention involves forming a first silicon carbide coating and a second silicon carbide coating sequentially on the substrate surface through two CVD depositions. Both coatings exhibit a layered structure with large grain sizes on a macroscopic scale (e.g., Figure 1 The structure shown in the figure has a larger grain size, which reduces the number of grain boundaries inside the coating. According to the principle of phonon thermal conductivity, grain boundaries are the main scattering source of phonon transmission. Reducing the number of grain boundaries can significantly reduce the phonon scattering probability, extend the phonon mean free path, and thus effectively improve the thermal conductivity of the silicon carbide coating. The plate-like structure can improve the compactness between grains through orderly stacking, fill the internal pores that are easily generated during the growth of large grains, and avoid the formation of etchant penetration channels due to pores, thereby strengthening the etching resistance of the silicon carbide coating from the structure. In terms of microstructure control, both the first and second silicon carbide coatings are 3C-SiC with a high (111) crystal orientation. The high (111) orientation can significantly reduce the proportion of non-target crystal planes such as (220) and (311), ensuring that the grains grow in an orderly manner along a uniform direction, thereby improving the structural stability and performance uniformity of the coating from the microscopic level. It avoids the disordered arrangement of grains caused by orientation dispersion. An increase in non-target orientations will aggravate grain boundary scattering, which will not only weaken the thermal conductivity, but also generate internal stress due to the orientation difference between grains. Furthermore, this invention controls the grain size ratio of the first and second silicon carbide coatings (satisfying 1 < B / A ≤ 2.2), and combines it with a high-temperature heat treatment process of 1400℃-1600℃ for 3h-6h. The size control and interface strengthening work together. The second deposition uses the first silicon carbide coating as a homogeneous substrate. Compared with the first deposition on a substrate (such as a graphite substrate), the lattice matching is better, and it is easier to achieve the same (111) orientation as the first layer. The slightly larger grain size can also fill the interface between the first layer and the substrate, or the tiny gaps that may exist inside the first layer. Then, the high-temperature heat treatment activates the activity of interface atoms, which promotes the formation of stable valence bonds between the silicon carbide coating and the substrate, and between the two silicon carbide coatings. This solves the problem of insufficient bonding strength caused by larger grain size, thereby achieving a simultaneous improvement in bonding strength, thermal conductivity and etching resistance.

[0028] It should be noted that (111), (220), (311), and (222) all refer to the "crystal plane indices" in silicon carbide crystallography, which are symbols used by Miller index method to identify planes with different atomic packing patterns in a crystal. Based on the face-centered cubic lattice of 3C-SiC, the intercepts of the atomic planes with the axes are determined along the x, y, and z coordinate axes. The inverse of the intercept is taken and simplified to the smallest positive integer ratio to obtain these indices. Among them, (111) is the core crystal plane that is targeted for control in this invention. It has a high atomic packing density, which can reduce phonon scattering to improve thermal conductivity and enhance etching resistance. (220), (311), and (222) are secondary crystal planes that need to be suppressed. If their orientation ratio is too high, it will lead to disordered crystal orientation, an increase in the number of grain boundaries, aggravated phonon scattering (reduced thermal conductivity), and damage to the uniformity of coating morphology, thus weakening the etching resistance.

[0029] For example, the value of B / A can be 1.001, 1.01, 1.05, 1.2, 1.4, 1.6, 1.8, 2, 2.1, 2.2 or any value between any of the above pairs of values, preferably 1 < B / A ≤ 1.5, and more preferably 1.2 < B / A ≤ 1.4. If B / A > 2.2, the excessive size difference will disrupt the consistency of the lattice orientation of the two silicon carbide coatings. Even if the secondary deposition is based on a homogeneous substrate, grains much larger than the first layer will have difficulty maintaining a high (111) orientation and are prone to an increase in non-target orientations such as (220) and (311), which will instead exacerbate grain boundary scattering and weaken thermal conductivity. On the other hand, excessive size difference will lead to a sharp increase in internal stress between the two silicon carbide coatings. Especially during the subsequent high-temperature heat treatment of 1400℃-1600℃ in this invention, the internal stress cannot be released through valence bond bonding, which can easily cause coating cracking. At the same time, excessively large grains are prone to problems such as loose grains and increased porosity during growth. Etching agents can penetrate into the interior of the coating through the pores, leading to a deterioration in etching resistance.

[0030] In some embodiments, the grains in both the first and second silicon carbide coatings have a lamellar structure. This was determined by observation using a scanning electron microscope (SEM).

[0031] In some embodiments, the peak percentage of the (111) crystal plane orientation in the first silicon carbide coating and the second silicon carbide coating is independently 70%-90%.

[0032] In this invention, the peak percentage of the (111) crystal plane orientation is tested by X-ray diffraction (XRD).

[0033] In some embodiments, before the heat treatment in step (4), the temperature is lowered to 20℃-100℃, for example, it can be 20℃, 30℃, 40℃, 50℃, 60℃, 70℃, 80℃, 90℃, 100℃ or any value between any two of the above points.

[0034] For example, in step (4) heat treatment, the temperature of the heat treatment can be, for example, 1400℃, 1420℃, 1440℃, 1460℃, 1480℃, 1500℃, 1520℃, 1540℃, 1560℃, 1580℃, 1600℃ or any value between any two of the above points; the time can be, for example, 3h, 3.5h, 4h, 4.5h, 5h, 5.5h, 6h or any value between any two of the above points. The temperature and time of high-temperature post-treatment need to be strictly controlled. If the temperature is below 1400℃, the atomic activity is insufficient, making it difficult to promote the formation of stable valence bonds between the coating and the substrate, and between the two coating layers. The bonding strength cannot be effectively improved, and the grain structure cannot be fully optimized. The improvement of thermal conductivity and etching resistance is limited. If the temperature is above 1600℃, it is easy to induce silicon carbide phase transformation (such as the transformation of 3C-SiC to other crystal forms), destroying the high (111) crystal plane orientation, causing disorder in the crystal structure, resulting in a sharp drop in thermal conductivity and deterioration in etching resistance. If the time is less than 3h, the heat treatment is insufficient, the interface reaction is incomplete, and there are many residual defects. If the time is longer than 6h, it may lead to abnormal grain growth, generating internal stress that causes coating cracking. It may also increase the risk of phase transformation, prolong the production cycle, and reduce process efficiency.

[0035] For example, the first deposition pressure can be 5 kPa, 10 kPa, 20 kPa, 30 kPa, 40 kPa, 50 kPa, or any value between any two of the above.

[0036] In some implementations, the deposition pressures for the first and second depositions are each independently between 5 kPa and 20 kPa, for example, 5 kPa, 6 kPa, 8 kPa, 10 kPa, 12 kPa, 14 kPa, 16 kPa, 18 kPa, 20 kPa, or any value between any of the above two points.

[0037] The core of deposition pressure is to regulate the gas distribution and reaction rate in the CVD reaction environment to ensure the stable growth of silicon carbide grains. On the one hand, appropriate pressure can make the silicon carbon source and carrier gas diffuse evenly in the reaction chamber, avoiding excessively low pressure leading to excessively fast gas diffusion and uneven nucleation density, or excessively high pressure leading to excessively violent reaction and small grains, thereby ensuring that the first and second coatings form large-sized grains of more than 70μm. On the other hand, stable pressure can maintain a high (111) crystal orientation, avoid pressure fluctuations causing grain orientation dispersion, and at the same time ensure the density of the coating, reduce porosity, and enhance the etching resistance.

[0038] In some embodiments, the deposition times for the first and second depositions are each independently 4-6 hours, for example, 4, 4.5, 5, 5.5, 6 hours, or any value between any two of these values, preferably 4.5-5.5 hours. The deposition time primarily serves the goals of coating thickness and structural integrity. Sufficient deposition time ensures the coating reaches the target thickness; insufficient time results in a thin coating that cannot effectively perform its thermal conductivity and etching resistance functions; excessive time can lead to overgrowth of grains, increasing internal stress and reducing production efficiency. Simultaneously, by coordinating deposition temperature and pressure, appropriate time ensures uniform grain growth, preventing uneven coating structure due to improper timing, and further guaranteeing stable coating performance.

[0039] In some embodiments, the substrate is a graphene substrate. Graphene itself has extremely high thermal conductivity. Choosing graphene as the substrate can form a synergistic thermal conductivity system between the silicon carbide coating and the substrate with the high thermal conductivity silicon carbide coating prepared in this invention, avoiding the accumulation of heat dissipated by the coating at the substrate interface due to insufficient thermal conductivity of the substrate, and further ensuring the overall thermal conductivity efficiency. From the perspective of lattice matching and coating growth, the lattice structure of the graphene substrate can provide excellent orientation guidance for the first silicon carbide deposition, reduce lattice mismatch during initial deposition, reduce internal stress in the coating, and lay the structural foundation for the subsequent formation of large-size, highly (111) oriented silicon carbide grains, avoiding the accumulation of heat due to lattice differences between the substrate and the coating. Excessive size can lead to coating cracking or peeling. In addition, the two-dimensional sheet structure of graphene can provide a larger contact area, allowing the silicon carbide coating to adhere more tightly to the substrate surface during the first deposition. Subsequent high-temperature heat treatment can also promote the formation of stable valence bonds between graphene and silicon carbide, further improving the bonding strength. At the same time, graphene has excellent chemical stability and high temperature resistance, and can withstand the high temperature and chemical corrosion of semiconductor etching environment. It will not react chemically with etchants or silicon carbide coatings, ensuring the stability of the substrate structure during long-term service. Together with silicon carbide coatings, it can adapt to the extreme service scenarios of high temperature and etching in semiconductors.

[0040] In some embodiments, A satisfies 70≤A≤120, meaning that the grain size of silicon carbide in the first silicon carbide coating can be, for example, 70μm, 80μm, 90μm, 100μm, 110μm, 120μm, or any value between any two of the above. If A < 70μm, it will lead to an increase in the number of grain boundaries, exacerbating phonon scattering and resulting in a decrease in thermal conductivity; at the same time, small grains are prone to insufficient coating density, increasing the weak areas for etching resistance, and failing to provide a stable homogeneous growth substrate for the second deposition, weakening the subsequent interlayer bonding strength; if A > 120μm, due to the nucleation limitation of the first deposition substrate, excessively large grains are prone to uneven growth, accompanied by increased internal stress, and are prone to cracking during subsequent high-temperature heat treatment (1400℃-1600℃); and it is difficult to precisely control the deposition temperature in the process, which may introduce porosity, thereby reducing the bonding strength between the coating and the substrate.

[0041] In some embodiments, B satisfies 90≤B≤150, that is, the grain size of silicon carbide in the second silicon carbide coating can be, for example, 90μm, 100μm, 110μm, 120μm, 130μm, 140μm, 150μm or any value between the above two points. If B < 90μm, it will lead to an increase in the number of grain boundaries in the second coating, which will intensify phonon scattering and will not significantly improve the overall thermal conductivity and etching resistance of the coating. If B > 150μm, the large difference in grain size between the first and second silicon carbide coatings will lead to inconsistent lattice orientations between the two layers, and an increase in non-target orientations (such as (220) and (311)), which will intensify phonon scattering. At the same time, excessive internal stress will cause the coating to crack during high-temperature heat treatment, and excessively large grain growth is prone to loosening and porosity, which will degrade the etching resistance.

[0042] In this invention, the grain size of silicon carbide can be tested by a 3D profilometer or a scanning electron microscope. For example, 50 silicon carbide grains can be selected, and the grain size can be measured separately and then the average value can be taken.

[0043] In some embodiments, the molar ratio of the first silicon carbide source gas to the first carrier gas, and the molar ratio of the second silicon carbide source gas to the second carrier gas, each independently satisfy 1:(40-100), for example, it can be 1:40, 1:50, 1:60, 1:70, 1:80, 1:90, 1:100, or any ratio within the range defined by this invention. Controlling the molar ratio of the first silicon carbide source gas to the first carrier gas, and the second silicon carbide source gas to the second carrier gas, at 1:(40-100 is primarily about controlling the concentration of the silicon carbide source gas and the interaction of the carrier gas in the reaction system to ensure that the CVD deposition process and the performance of the silicon carbide coating meet the standards. On the one hand, the carrier gas can fully utilize the ratio to transport silicon-carbon source and remove by-products, which can stably transport silicon-carbon source to the substrate / first coating surface and timely remove by-products such as chloride generated by the deposition reaction, avoiding by-product residues forming defects, while maintaining a clean reaction environment. On the other hand, the ratio can control the concentration of silicon-carbon source within a suitable range, avoiding both excessively high silicon-carbon source ratio (molar ratio less than 1:40) leading to a sudden increase in nucleation density and an increase in small grains, and excessively low silicon-carbon source ratio (molar ratio greater than 1:100) leading to insufficient nucleation, weak growth momentum, and difficulty in forming highly (111) oriented lamellar grains. In addition, a stable ratio of silicon-carbon source to carrier gas can also ensure a balanced CVD reaction rate, enabling the first and second coatings to grow uniformly to the target thickness, and ensuring the coating density meets the standard, reducing porosity, and laying the foundation for subsequent improvement of etching resistance and bonding strength.

[0044] In some embodiments, the first silicon-carbon source gas and the second silicon-carbon source gas are each independently selected from at least one of trichloromethylsilane, trichlorosilane, and tetrachlorosilane.

[0045] In some embodiments, the first carrier gas and the second carrier gas are each independently selected from hydrogen.

[0046] In some embodiments, the first diluent gas and the second diluent gas are each independently selected from at least one of argon and nitrogen.

[0047] In some embodiments, the thickness of the first silicon carbide coating is denoted as m1, and the thickness of the second silicon carbide coating is denoted as m2; m1 and m2 satisfy: 0.8 ≤ m1 / m2 ≤ 1.5, and the value of m1 / m2 can be, for example, 0.8, 0.9, 1, 1.2, 1.3, 1.4, 1.5, or any value between any two of the above points, preferably 0.8 ≤ m1 / m2 ≤ 1.2. On the one hand, a balanced thickness ratio can avoid internal stress caused by excessive thickness difference between the two layers (especially during subsequent high-temperature heat treatment at 1400℃-1600℃), ensuring the overall structural stability of the coating; on the other hand, a suitable thickness ratio allows the second layer to fully cover and fill any small gaps that may exist in the first layer, while jointly constructing a continuous heat conduction path, improving etching resistance. If m1 / m2 < 0.8, the first layer is too thin and cannot serve as a stable homogeneous substrate to support the growth of the second layer. This can easily lead to the dispersion of the grain orientation in the second layer (such as an increase in non-target orientations of (220) and (311), thus destroying the high (111) orientation advantage. Furthermore, the large difference in thickness between the two layers can cause a sudden increase in internal stress, making it prone to cracking during high-temperature heat treatment. This can reduce both the etching resistance and the bonding strength. If m1 / m2 > 1.5, the second layer is too thin and cannot fully fill the gaps in the first layer or cover the weak etching areas. This results in a lot of residual pores and easy penetration of the etchant. At the same time, the heat conduction paths of the two layers are unbalanced, and the overall heat conduction performance is limited by the thin second layer, which cannot meet the design expectations.

[0048] In some implementations, m1 and m2 satisfy: 100 ≤ m1 + m2 ≤ 120, where the value of m1 + m2 can be, for example, 100, 105, 110, 115, 120, or any value between any two of these values. On the one hand, sufficient total thickness can form an effective protective layer to resist continuous losses under high-temperature etching conditions; on the other hand, this thickness range can balance thermal conductivity. Too thick a layer will prolong the phonon transmission path, while too thin a layer will provide insufficient protection. This range allows for efficient phonon transmission while ensuring the durability of the coating.

[0049] In some implementations, m1 satisfies 50μm≤m1≤60μm, that is, the thickness of the first silicon carbide coating can be, for example, 51μm, 52μm, 53μm, 54μm, 55μm, 56μm, 57μm, 58μm, 59μm, 60μm or any value between any of the above two points.

[0050] In some implementations, m2 satisfies: 50μm≤m2≤60μm, that is, the thickness of the second silicon carbide coating can be, for example, 51μm, 52μm, 53μm, 54μm, 55μm, 56μm, 57μm, 58μm, 59μm, 60μm or any value between any two of the above points.

[0051] In some embodiments, a surface treatment step is also included between step (2) and step (3): the first silicon carbide coating obtained in step (2) is removed from the chemical vapor deposition equipment, acid-washed and polished, and then a second deposition is performed.

[0052] In this invention, the thickness of the silicon carbide coating can be obtained by conventional testing methods in the art, such as using a 3D profilometer or non-destructive film thickness measurement.

[0053] The second aspect of the present invention provides a semiconductor material prepared by the method provided in the first aspect of the present invention.

[0054] The third aspect of the present invention provides an application of the semiconductor material provided in the second aspect in a semiconductor etching process.

[0055] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0056] Unless otherwise specified, all materials and reagents used in the following examples are commercially available.

[0057] The present invention will now be described in detail with reference to specific embodiments, which are intended to understand rather than limit the invention.

[0058] Example 1

[0059] Preparation of silicon carbide coating:

[0060] (1) After the substrate is pretreated by acid washing to remove impurities, it is placed in the CVD furnace, the CVD furnace is evacuated, and then the air in the chemical vapor deposition equipment is replaced with argon and heated.

[0061] (2) A mixture of trichloromethylsilane (MTS), hydrogen and argon is introduced into the chemical vapor deposition equipment, and the first deposition temperature is controlled at 1450°C, the first deposition pressure is 20000 Pa, the deposition time is 300 min, and the flow ratio of MTS to hydrogen is 1:90. The first silicon carbide coating is obtained by first deposition on the surface of the substrate using chemical vapor deposition process. Then, acid washing and polishing are performed, and surface impurities are removed by ultrasonication.

[0062] (3) Place the first silicon carbide coating obtained in step (2) into the chemical vapor deposition equipment again, introduce a mixture of MTS, hydrogen and argon, control the second deposition temperature to be 1450℃, the second deposition pressure to be 20000pa, the deposition time to be 300min, and the flow ratio of MTS and hydrogen to be 1:90; use chemical vapor deposition process to perform a second deposition on the surface of the first silicon carbide coating to obtain the second silicon carbide coating;

[0063] (4) Perform heat treatment at a temperature of 1550°C for 4 hours.

[0064] According to XRD testing, the peak percentage of the silicon carbide coating (111) in Example 1 was 87%.

[0065] Example 2 group

[0066] Example 2 was performed in the same manner as Example 1, with the main differences as follows:

[0067] Example 2-1:

[0068] In the first deposition: the first deposition temperature was controlled at 1400℃, the first deposition pressure at 20000pa, the deposition time at 300min, and the flow ratio of MTS to hydrogen at 1:110.

[0069] In the second deposition: the second deposition temperature was controlled at 1450℃, the second deposition pressure at 20000pa, the deposition time at 300min, and the flow ratio of MTS to hydrogen at 1:90.

[0070] Example 2-2:

[0071] In the first deposition: the first deposition temperature was controlled at 1450℃, the first deposition pressure at 16000pa, the deposition time at 300min, and the flow ratio of MTS to hydrogen at 1:60.

[0072] In the second deposition: the second deposition temperature was controlled at 1500℃, the second deposition pressure at 16000pa, the deposition time at 300min, and the flow ratio of MTS to hydrogen at 1:60.

[0073] Comparative Example 1

[0074] In the first deposition: the first deposition temperature was controlled at 1250℃, the first deposition pressure at 10000pa, the deposition time at 300min, and the flow rate ratio of MTS to hydrogen at 1:8.

[0075] In the second deposition: the second deposition temperature was controlled at 1250℃, the second deposition pressure at 10000pa, the deposition time at 300min, and the flow ratio of MTS to hydrogen at 1:8.

[0076] Comparative Example 2

[0077] Comparative Example 2 was carried out in accordance with Example 1, with the main differences as follows:

[0078] In the first deposition: the first deposition temperature was controlled at 1400℃, the first deposition pressure at 20000pa, the deposition time at 300min, and the flow ratio of MTS to hydrogen at 1:110.

[0079] In the second deposition: the second deposition temperature was controlled at 1550℃, the second deposition pressure at 16000pa, the deposition time at 300min, and the flow ratio of MTS to hydrogen at 1:60.

[0080] Comparative Example 3

[0081] The procedure is the same as in Example 1, with the main differences being as follows:

[0082] In the first deposition: the first deposition temperature was controlled at 1450℃, the first deposition pressure at 20000pa, the deposition time at 250min, and the flow ratio of MTS to hydrogen at 1:90.

[0083] In the second deposition: the second deposition temperature was controlled at 1450℃, the second deposition pressure at 20000pa, the deposition time at 360min, and the flow ratio of MTS to hydrogen at 1:90.

[0084] Comparative Example 4 Groups

[0085] The four comparative groups were conducted in accordance with Example 1, with the main differences as follows:

[0086] Comparative Example 4-1: The heat treatment temperature was 1450℃. Too low a temperature will result in insufficient densification of the material, thus affecting the bonding strength, porosity, and density.

[0087] Comparative Example 4-2: The heat treatment temperature was 1650℃. Above 1600℃, the phase structure of silicon carbide will change.

[0088] Performance testing

[0089] i) Etching resistance test: The silicon carbide materials prepared in the above examples and comparative examples are placed in the sample chamber of a plasma etching device, etching gas is introduced, and the gas is excited by a radio frequency power source to generate plasma and start the etching program. The ions and free radicals in the plasma begin to react with the S1C surface. The time for introducing etching gas once is 10 hours. After etching is completed, the silicon carbide material is taken out to observe whether cracks are generated. If there are no visible cracks, the above operation is repeated until obvious visible cracks are generated on the material surface and the number of etchings until cracks are generated is recorded.

[0090] ii) Thermal conductivity test: Thermal conductivity test shall be conducted using a laser thermal conductivity meter in accordance with GB / T 22588-2008.

[0091] iii) Bond strength test: The bond strength is tested using a microcomputer-controlled electronic universal testing machine in accordance with the national standard GB / T 31541-2015.

[0092] Table 1

[0093]

[0094] Note: In Table 1, the data for A, B, m1, and m2 are the actual data obtained and rounded to the nearest integer; the values ​​of B / A and m1 / m2 are rounded to two decimal places.

[0095] Table 2

[0096]

[0097] As can be seen, the method provided by the present invention uses two chemical vapor deposition (CVD) processes to first generate a first silicon carbide coating with large-sized grains on the substrate surface, and then generate a second silicon carbide coating with grains slightly larger than the first layer using the first silicon carbide coating as a substrate; unlike the tetrahedral structure of Comparative Example 1 ( Figure 2 The silicon carbide coating formed by this invention has a sheet-like structure. Figure 1 By orderly stacking, the density between grains can be improved, filling the internal pores that are easily generated during the growth of large grains, avoiding the formation of etchant penetration channels due to pores. Combined with subsequent high-temperature heat treatment processes, it can not only ensure the bonding strength between the silicon carbide coating and the substrate, and between the two coating layers, avoiding coating cracking or peeling under high-temperature conditions, but also further improve the thermal conductivity and etching resistance of the silicon carbide coating, ultimately obtaining a high-performance silicon carbide coating suitable for high-temperature and etching service scenarios of semiconductors.

[0098] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of the present invention is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0099] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications or equivalent substitutions made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for preparing a high thermal conductivity silicon carbide coating, characterized in that, Includes the following steps: (1) After pretreatment of the substrate, it is placed in a chemical vapor deposition equipment, the chemical vapor deposition equipment is evacuated, and then the air in the chemical vapor deposition equipment is replaced with inert gas and heated. (2) The mixture of the first silicon carbide source gas, the first carrier gas and the first dilution gas is introduced into the chemical vapor deposition equipment, the first deposition temperature is controlled at 1350℃-1600℃ and the first deposition pressure is 5KPa-50KPa, and the first silicon carbide coating is obtained by first deposition on the surface of the substrate using the chemical vapor deposition process. (3) Place the first silicon carbide coating obtained in step (2) into the chemical vapor deposition equipment again, introduce a mixture of second silicon carbide source gas, second carrier gas and second dilution gas, control the second deposition temperature to 1350℃-1600℃, the second deposition pressure to 5KPa-50KPa, and perform a second deposition on the surface of the first silicon carbide coating using the chemical vapor deposition process to obtain the second silicon carbide coating. (4) After cooling, heat treatment is performed at a temperature of 1500℃-1600℃ for 3h-6h. Wherein, the grain size of silicon carbide in the first silicon carbide coating is denoted as A μm, and the grain size of silicon carbide in the second silicon carbide coating is denoted as B μm. A satisfies: 70≤A≤120; B satisfies: 90≤B≤150; 1<B / A≤2.2; The thickness of the first silicon carbide coating is denoted as m1, and the thickness of the second silicon carbide coating is denoted as m2; m1 and m2 satisfy: 0.8≤m1 / m2≤1.5; The molar ratio of the first silicon carbide source gas to the first carrier gas, and the molar ratio of the second silicon carbide source gas to the second carrier gas, each independently satisfy 1:(40-100); The deposition times for the first and second deposits were each 4-6 hours.

2. The method according to claim 1, characterized in that, The first and second deposition pressures were each independently between 5 kPa and 20 kPa.

3. The method according to claim 1, characterized in that, The grains in both the first and second silicon carbide coatings are lamellar structures, and the peak percentage of the (111) crystal plane orientation in both the first and second silicon carbide coatings is independently 70%-90%. And / or, the matrix is ​​a graphene matrix.

4. The method according to claim 1, characterized in that, m1 and m2 satisfy: 100≤m1+m2≤120; And / or, m1 satisfies: 50 μm ≤ m1 ≤ 60 μm; And / or, m2 satisfies: 50 μm ≤ m2 ≤ 60 μm.

5. The method according to any one of claims 1-4, characterized in that, The first silicon-carbon source gas and the second silicon-carbon source gas are each independently selected from at least one of trichloromethylsilane, trichlorosilane, and tetrachlorosilane; And / or, the first carrier gas and the second carrier gas are each independently selected from hydrogen; And / or, the first diluting gas and the second diluting gas are each independently selected from at least one of argon and nitrogen.

6. The semiconductor material prepared by the method according to any one of claims 1-5.

7. The application of the semiconductor material according to claim 6 in a semiconductor etching process.

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