Power cycle test circuit and method of SiC power semiconductor device

Abstract

The invention relates to the technical field of power semiconductor devices, and discloses a power cycle test circuit and method for a SiC power semiconductor device, and the circuit is characterized in that the AC side of a rectification circuit is connected with an AC power supply, and the DC side of the rectification circuit is connected with the first end of a DC boost circuit; the second end of the direct-current booster circuit is connected with the direct-current side of the inverter circuit; the alternating-current side of the inverter circuit is connected with an alternating-current power supply; part of power semiconductor devices in the rectifying circuit, the direct-current booster circuit and the inverter circuit are SiC power semiconductor devices to be tested. The active power cycle test circuit comprises a rectification circuit, a direct current boost circuit and an inversion circuit which are connected in series. The AC power supply provides energy for the test circuit. No load exists in the test loop, a power circulation loop is formed, and a circuit is provided for characteristic test of the SiC power semiconductor device. In the working process of the circuit, the power supply loop only needs to provide loss energy of the test loop.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, and specifically to a power cycle testing circuit and method for SiC power semiconductor devices. Background Technology

[0002] Using novel wide-bandgap materials with high ionization energy, such as silicon carbide, it is possible to fabricate classic MOSFET devices with fast switching times and breakdown voltages exceeding 1000 volts. Furthermore, they can withstand high temperatures, ensuring stable operation and extended lifespan. New materials require new testing techniques, especially in the field of thermal transient testing, where robust methods are needed to inspect device integrity, identify fault mechanisms, and determine thermal resistance.

[0003] Common testing methods include active power cycling, which involves powering on the device to heat it and then powering it off to cool it; this is the most common method. Another method is passive cycling, such as water cooling or air cooling to control temperature changes.

[0004] Power cycling testing of semiconductor devices is a critical reliability test for evaluating their ability to withstand thermomechanical stress during repeated switching. This method examines the degradation mechanism of semiconductor components by switching high currents through the device. By repeating power cycling until the component fails, a lifespan curve can be plotted. Its core principle is to simulate the junction temperature fluctuations and average junction temperature caused by power dissipation in real-world applications. This leads to cyclic stress in different materials (chip, solder, substrate, bonding wires, etc.) due to differences in their coefficients of thermal expansion, which can ultimately result in solder fatigue, bonding wire detachment / breakage, chip cracking, and other failures.

[0005] Currently, power cycling tests for SiC devices are mostly based on direct current (DC) power cycling. This means that the applied current excitation is DC, and during the device heating phase of each cycle, an appropriate gate voltage is applied to turn on the device. The flowing DC test current causes conduction losses, thus heating the device to its maximum junction temperature. In this case, the heat generated by the device under test originates solely from conduction losses, without any switching losses. Summary of the Invention

[0006] In view of this, the present invention provides a power cycle test circuit and method for SiC power semiconductor devices to solve the problem that the heat generation of the device under test in power cycle testing is only caused by conduction loss, and there is no switching loss.

[0007] In a first aspect, the present invention provides a power cycle test circuit for SiC power semiconductor devices. The test circuit is applied to SiC power semiconductor devices and includes: a rectifier circuit, a DC boost circuit, and an inverter circuit. The AC side of the rectifier circuit is connected to an AC power supply, and the DC side of the rectifier circuit is connected to a first terminal of the DC boost circuit. The second terminal of the DC boost circuit is connected to the DC side of the inverter circuit. The AC side of the inverter circuit is connected to an AC power supply. Some of the power semiconductor devices in the rectifier circuit, the DC boost circuit, and the inverter circuit are the SiC power semiconductor devices under test.

[0008] This invention relates to an active power cycle test circuit comprising three parts: rectification, DC boost, and inversion, connected in series. An AC power supply provides energy to the test circuit. This test loop has no load, forming a power cycle loop to provide a circuit for testing the characteristics of SiC power semiconductor devices. During circuit operation, the power supply loop only needs to supply the energy lost in the test loop.

[0009] In one optional implementation, the rectifier circuit includes three bridge arms, each bridge arm consisting of two first power semiconductor devices connected in series, wherein any one of the six first power semiconductor devices is a first SiC power semiconductor device under test, and the remaining first power semiconductor devices are silicon-based power semiconductor devices.

[0010] In one alternative implementation, the first SiC power semiconductor device under test is a SiC diode; the silicon-based power semiconductor device is a silicon-based diode.

[0011] In one optional embodiment, the DC boost circuit includes: a first capacitor, a first inductor, a second SiC power semiconductor device under test, and a third SiC power semiconductor device under test. A first terminal of the first capacitor is connected to a first terminal of the first inductor and the DC side of the rectifier circuit. A second terminal of the first capacitor is connected to a second terminal of the second SiC power semiconductor device under test and the DC side of the inverter circuit. A second terminal of the first inductor is connected to a first terminal of both the second and third SiC power semiconductor devices under test. A second terminal of the third SiC power semiconductor device under test is connected to the DC side of the inverter circuit.

[0012] In one optional implementation, the second SiC power semiconductor device under test is a SiC MOS transistor; the third SiC power semiconductor device under test is a SiC diode.

[0013] In one optional embodiment, the inverter circuit includes: a second capacitor, a third capacitor, and three bridge arms. Each bridge arm includes: a second power semiconductor device, a third power semiconductor device, a fourth power semiconductor device, a fifth power semiconductor device, a sixth power semiconductor device, and a seventh power semiconductor device. The first terminal of the second power semiconductor device is connected to the second terminal of the DC-DC boost circuit and the first terminal of the second capacitor. The second terminal of the second power semiconductor device is connected to the first terminals of the third and sixth power semiconductor devices. The second terminal of the third power semiconductor device is connected to the first terminal of the fourth power semiconductor device, and the second terminal of the third power semiconductor device is the AC side of this bridge arm. The second terminal of the fourth power semiconductor device is connected to the first terminals of the fifth and seventh power semiconductor devices. The second terminal of the fifth power semiconductor device is connected to the second terminal of the DC-DC boost circuit and the second terminal of the third capacitor. The second terminal of the sixth power semiconductor device is connected to the first terminal of the seventh power semiconductor device, the second terminal of the second capacitor, and the first terminal of the third capacitor. The sixth and seventh power semiconductor devices are fourth SiC power semiconductor devices under test, and the second, third, fourth, and fifth power semiconductor devices are silicon-based power semiconductor devices.

[0014] In one optional implementation, the sixth and seventh power semiconductor devices are SiCIGBT transistors; the second, third, fourth, and fifth power semiconductor devices are silicon-based SiCIGBT transistors.

[0015] In one alternative implementation, the power cycle test circuit for the SiC power semiconductor device further includes an output filter circuit, wherein the DC side of the inverter circuit is connected to an AC power supply through the output filter circuit.

[0016] In one alternative implementation, the power cycle test circuit for the SiC power semiconductor device further includes an input filter circuit, wherein an AC power supply is connected to the input filter circuit.

[0017] Secondly, the present invention provides a power cycle testing method for SiC power semiconductor devices, based on the power cycle testing circuit for SiC power semiconductor devices according to the first aspect and any optional embodiment thereof. The method includes: determining the model and testing requirements of the power semiconductor device under test; determining, according to the device testing requirements, some power semiconductor devices in the rectifier circuit, DC boost circuit, and inverter circuit as the SiC power semiconductor devices under test; starting the AC power supply; recording the electrical parameters of the SiC power semiconductor device under test; and generating a test report based on the electrical parameters of the SiC power semiconductor device under test. Attached Figure Description

[0018] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is a composition diagram of a power cycle test circuit according to an embodiment of the present invention;

[0020] Figure 2 This is a detailed circuit structure diagram of the rectifier circuit according to an embodiment of the present invention;

[0021] Figure 3 This is a detailed circuit structure diagram of the DC boost circuit according to an embodiment of the present invention;

[0022] Figure 4 This is a detailed circuit structure diagram of the inverter circuit according to an embodiment of the present invention;

[0023] Figure 5 This is a detailed circuit structure diagram of the output filter circuit according to an embodiment of the present invention;

[0024] Figure 6 This is the series connection configuration of the SiC power semiconductor devices under test according to an embodiment of the present invention;

[0025] Figure 7 This is the parallel connection configuration of the SiC power semiconductor devices under test according to an embodiment of the present invention;

[0026] Figure 8 This is a flowchart of a power cycling test method according to an embodiment of the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] This embodiment provides a power cycle testing circuit for SiC power semiconductor devices, such as... Figure 1 As shown, the test circuit includes: a rectifier circuit, a DC-DC boost circuit, and an inverter circuit, wherein...

[0029] The AC side of the rectifier circuit is connected to the AC power supply, and the DC side of the rectifier circuit is connected to the first terminal of the DC boost circuit; the second terminal of the DC boost circuit is connected to the DC side of the inverter circuit; the AC side of the inverter circuit is connected to the AC power supply; some power semiconductor devices in the rectifier circuit, DC boost circuit and inverter circuit are SiC power semiconductor devices under test.

[0030] Specifically, the rectifier circuit, as the front-end processing stage of the circuit, has its AC side directly connected to the AC power source, responsible for converting the input AC power into DC power, providing the basic DC power supply for subsequent circuits. The DC side of the rectifier circuit is connected to the first terminal of the DC boost circuit, realizing the transfer and subsequent processing of electrical energy.

[0031] Specifically, the DC boost circuit receives DC power from the rectifier circuit, and its core function is to boost the input DC voltage to meet the requirements of different voltage levels during testing. The second terminal of this circuit is connected to the DC side of the inverter circuit, delivering the boosted DC power to the inverter circuit.

[0032] Specifically, the AC side of the inverter circuit is connected to the AC power supply. Its function is to convert the DC power that has been boosted back into AC power, forming a complete closed circuit loop, ensuring that energy can be rationally circulated and utilized, and also providing a guarantee for the stable operation of the test environment.

[0033] Specifically, in the three key components of the rectifier circuit, DC boost circuit, and inverter circuit, some power semiconductor devices are designated as SiC power semiconductor devices under test. This design allows the test circuit to directly apply specific test conditions to these SiC devices, simulating their operating state in real-world applications, thereby accurately assessing their reliability and performance changes during power cycling.

[0034] In practical applications, SiC power semiconductor devices are often placed in circuit systems that include rectification, transformation, and inversion, undergoing AC-DC conversion and voltage fluctuations. The test circuit structure in this embodiment simulates such a real-world circuit environment. The current and voltage changes experienced by the SiC device under test within this environment closely match their actual application conditions, allowing the test to more accurately reflect the device's performance.

[0035] Since the circuit covers rectification, DC boost, and inversion stages, the SiC device under test in this embodiment can be tested in different circuit stages, and its performance under different working scenarios such as rectification, boost, and inversion can be comprehensively tested, covering a variety of working conditions that the device may encounter, thereby comprehensively evaluating its reliability.

[0036] In this embodiment, since the rectifier circuit converts AC to DC, the DC boost circuit adjusts the voltage as needed, and the inverter circuit converts DC back to AC and feeds it back to the power supply, an energy cycle is formed, which reduces energy waste and makes the energy loss in the entire testing process low.

[0037] Compared to traditional power cycling circuits, this embodiment has higher aging efficiency. Traditional circuits may struggle to fully simulate the operating states of devices in multiple circuit stages, while this test circuit, due to its realistic structure, subjects the SiC device under test to stresses more closely to actual use conditions during rectification, boosting, and inversion. This allows for faster detection of aging signs, shortens the time required to obtain device aging patterns, and thus improves aging efficiency.

[0038] The high power utilization rate in this embodiment is due to the inverter circuit feeding the processed electrical energy back to the AC power source, achieving energy recycling. In traditional circuits, more energy may be consumed, while this circuit design significantly improves power utilization efficiency and reduces dependence on external power sources.

[0039] The simplicity of the control method in this embodiment stems from the systematic nature of the circuit structure and the clear definition of the functions of each part. The connection methods of the rectification, DC boost, and inverter circuits are clear, and the control of each part of the circuit can be targeted without the need for complex coordination mechanisms. Operators can more easily control the testing process, reducing the difficulty of control.

[0040] In some alternative implementations, the rectifier circuit includes: three bridge arms, each bridge arm consisting of two first power semiconductor devices connected in series, wherein any one of the six first power semiconductor devices is a first SiC power semiconductor device under test, and the remaining first power semiconductor devices are silicon-based power semiconductor devices.

[0041] Specifically, among the six primary power semiconductor devices included in the entire rectifier circuit, there are clear device distinctions and configurations. One of these primary power semiconductor devices is designated as the first SiC power semiconductor device under test. This configuration allows the SiC device to be directly placed in the operating environment of the rectifier circuit and subjected to testing under actual rectification conditions. The remaining five primary power semiconductor devices are silicon-based power semiconductor devices. As mature and stable semiconductor components, silicon-based devices primarily serve to assist rectification and maintain the normal operating state of the circuit, providing the SiC device under test with a circuit environment close to practical applications.

[0042] This design, consisting of three bridge arms, each containing two first power semiconductor devices connected in series, and with only one of the six devices designated as the first SiC device under test and the rest as silicon-based devices, ensures the basic functionality of the rectifier circuit while accurately testing the performance and reliability of specific SiC devices under rectifier conditions. At the same time, it leverages mature silicon-based devices to maintain circuit stability, making the testing process more controllable and effective.

[0043] Optionally, the first SiC power semiconductor device under test is a SiC diode; the silicon-based power semiconductor device is a silicon-based diode. For example... Figure 2 As shown, the rectifier circuit adopts a three-phase uncontrolled diode bridge rectification method. The three-phase uncontrolled diode bridge includes six power semiconductor devices. One of the power semiconductor devices is selected as a test point using a SiC diode, while the other five are silicon-based diodes. The DC boost circuit provides two test points: one for the SiC diode and one for the MOSFET.

[0044] For example, a rectifier circuit such as Figure 2 As shown, Figure 2 In this configuration, D6 can be configured as a SiC power semiconductor device, and D1 to D5 can be configured as silicon-based power semiconductor devices.

[0045] In some alternative implementations, such as Figure 3 As shown, the DC boost circuit includes: a first capacitor C1, a first inductor L1, a second SiC power semiconductor device under test Q1, and a third SiC power semiconductor device under test D7. The first terminal of the first capacitor C1 is connected to the first terminal of the first inductor L1 and the DC side of the rectifier circuit; the second terminal of the first capacitor C1 is connected to the second terminal of the second SiC power semiconductor device under test Q1 and the DC side of the inverter circuit; the second terminal of the first inductor L1 is connected to the first terminal of the second SiC power semiconductor device under test Q1 and the first terminal of the third SiC power semiconductor device under test D7; and the second terminal of the third SiC power semiconductor device under test D7 is connected to the DC side of the inverter circuit.

[0046] Optionally, the second SiC power semiconductor device under test, Q1, is a SiC MOS transistor; the third SiC power semiconductor device under test, D7, is a SiC diode.

[0047] Specifically, the second tested SiC power semiconductor device Q1 acts as a switching element. Its on / off state directly controls the charging and discharging process of the inductor, thus determining the operating state of the boost circuit. When Q1 is on, current flows through L1 and Q1, and L1 begins to store energy. When Q1 is off, the energy stored in L1 is released to the load (in this case, the inverter circuit) through D7, resulting in a voltage increase. During this process, Q1 experiences conduction losses, switching losses, etc., and the electrical and thermal stresses it endures are highly similar to those experienced when it acts as a switching device in actual applications, facilitating accurate testing of its reliability and performance in boost scenarios.

[0048] The third SiC power semiconductor device under test, D7, serves as both a freewheeling diode and a rectifier. When Q1 is off, D7 conducts, providing a path for the inductor to release energy and ensuring that energy can be smoothly transferred to the inverter circuit. Simultaneously, D7 also experiences some losses and bears corresponding stress during conduction, which is consistent with the operating state of a freewheeling diode in a real circuit, thus enabling effective testing of its performance in the boost circuit.

[0049] This structural design enables the DC boost circuit to not only stably achieve voltage boosting and provide the required DC voltage for the entire test circuit, but more importantly, it allows the second and third SiC power semiconductor devices under test, Q1 and D7, to operate under conditions close to actual applications. This facilitates a comprehensive evaluation of their reliability in boost scenarios and, in conjunction with the testing of the SiC devices under test in the rectifier circuit, further enhances the overall functionality of the test circuit.

[0050] In some alternative implementations, the inverter circuit includes: a second capacitor C2, a third capacitor C3, and three bridge arms, such as... Figure 4 As shown, each bridge arm includes: a second power semiconductor device Q2, a third power semiconductor device Q3, a fourth power semiconductor device Q4, a fifth power semiconductor device Q5, a sixth power semiconductor device Q6, and a seventh power semiconductor device Q7.

[0051] like Figure 4As shown, the first terminal of the second power semiconductor device Q2 is connected to the second terminal of the DC-DC boost circuit and the first terminal of the second capacitor C2. The second terminal of the second power semiconductor device Q2 is connected to the first terminal of the third power semiconductor device Q3 and the first terminal of the sixth power semiconductor device Q6. The second terminal of the third power semiconductor device Q3 is connected to the first terminal of the fourth power semiconductor device Q4, and the second terminal of the third power semiconductor device Q3 is the AC side of this bridge arm. The second terminal of the fourth power semiconductor device Q4 is connected to the first terminal of the fifth power semiconductor device Q5 and the second terminal of the seventh power semiconductor device Q7. The second terminal of the fifth power semiconductor device Q5 is connected to the second terminal of the DC-DC boost circuit and the second terminal of the third capacitor C3. The second terminal of the sixth power semiconductor device Q6 is connected to the first terminal of the seventh power semiconductor device Q7, the second terminal of the second capacitor C2, and the first terminal of the third capacitor C3. The sixth power semiconductor device Q6 and the seventh power semiconductor device Q7 are the fourth SiC power semiconductor devices under test, and the second power semiconductor device Q2, the third power semiconductor device Q3, the fourth power semiconductor device Q4, and the fifth power semiconductor device Q5 are silicon-based power semiconductor devices.

[0052] Specifically, the sixth and seventh power semiconductor devices, Q6 and Q7, are the fourth tested SiC power semiconductor devices. Leveraging the excellent high-frequency characteristics and high-voltage withstand capability of SiC material, they can significantly improve the switching frequency and efficiency of the circuit. The second, third, fourth, and fifth power semiconductor devices, Q2, Q3, Q4, and Q5, are traditional silicon-based power semiconductor devices. Their mature manufacturing processes and stable operating characteristics provide a reliable foundation for the circuit's operation. Through this structural design, the inverter circuit can achieve efficient power conversion under different operating conditions, while simultaneously addressing the dual requirements of performance improvement and cost control.

[0053] This embodiment of the inverter circuit provides SiC diode test points. The inverter circuit is not limited to using a three-phase two-level, three-phase three-level, or modular multilevel converter (MMC).

[0054] Optionally, the sixth power semiconductor device Q6 and the seventh power semiconductor device Q7 are SiC IGBT transistors; the second power semiconductor device Q2, the third power semiconductor device Q3, the fourth power semiconductor device Q4, and the fifth power semiconductor device Q5 are silicon-based SiC IGBT transistors.

[0055] In some alternative implementations, the power cycle test circuit further includes an output filter circuit, wherein the DC side of the inverter circuit is connected to an AC power supply via the output filter circuit.

[0056] Specifically, the DC side of the inverter circuit is electrically connected to the AC power supply through an output filter circuit. When the AC power input is processed and enters the inverter circuit, after the inverter circuit completes the DC-AC conversion, its output power first flows through the output filter circuit. The output filter circuit effectively filters out high-order harmonics generated during the inverter process, making the output current or voltage waveform closer to a sine wave, thus improving power quality. Simultaneously, it can suppress electromagnetic interference (EMI) in the circuit, reducing mutual interference between the inverter circuit and the AC power supply, ensuring the stable operation of the entire power cycle test circuit. Furthermore, the output filter circuit also acts as an energy buffer. When fluctuations occur in the load or power supply in the circuit, it can mitigate these fluctuations through the charging and discharging of energy storage elements (such as capacitors), protecting the inverter circuit and AC power supply from impacts, providing a stable and reliable electrical environment for power cycle testing, and ensuring the accuracy and reliability of the test results.

[0057] Optionally, the output filter circuit consists of three output filter units, each configured in one phase of the inverter circuit, such as... Figure 5 As shown, the output filtering unit is an LC filter circuit.

[0058] In some alternative implementations, the power cycle test circuit further includes an input filter circuit, wherein an AC power supply is connected to the input filter circuit.

[0059] Specifically, the AC power supply is directly connected to the input filter circuit, and the electrical energy output from the AC power supply first passes through the input filter circuit. The input filter circuit effectively filters out high-frequency interference and harmonic components in the AC power supply, making the waveform of the electrical energy input to subsequent circuits (such as rectifier circuits) smoother and more stable. This not only improves the anti-interference capability of the entire power cycle test circuit but also protects the components in subsequent circuits from power supply noise damage, extending their lifespan. Simultaneously, the input filter circuit can also suppress interference signals generated inside the circuit from propagating outwards through the AC power supply, preventing interference to other electrical equipment and ensuring the electromagnetic compatibility of the entire power system.

[0060] Alternatively, the input filter circuit is also mostly composed of passive components such as inductors and capacitors, commonly including π-type filter circuits and LC filter circuits. Its main function is to preprocess the electrical energy input by AC power supply, because AC power supply may be affected by external electromagnetic interference during transmission, introducing various harmonic components and noise. If these adverse factors directly enter subsequent circuit stages, they will have an adverse effect on the normal operation of the circuit.

[0061] In some alternative implementations, such as Figure 6 , Figure 7As shown, the test points in this test circuit can be used to test whether the devices are connected in parallel or in series, in order to verify the voltage equalization characteristics under series operation and the current equalization characteristics under parallel operation.

[0062] According to an embodiment of the present invention, a power cycle testing method for SiC power semiconductor devices is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0063] This embodiment provides a power cycling test method for SiC power semiconductor devices, such as... Figure 8 As shown, the power cycle test circuit based on the above SiC power semiconductor device includes the following methods:

[0064] Step S1: Determine the model and test requirements of the power semiconductor device under test.

[0065] Specifically, the core parameters of the SiC power semiconductor device under test need to be clearly defined, including but not limited to rated voltage (e.g., 1200V, 1700V), rated current (e.g., 50A, 100A), package type (e.g., TO-247, D2PAK), gate threshold voltage range, and maximum junction temperature (Tj_max). These parameters are crucial for matching the load capacity of the test circuit and designing the drive signal. For example, for a 1200V / 100A SiCIGBT, it is necessary to ensure that the output voltage of the DC boost circuit of the test circuit does not exceed its withstand voltage limit to avoid device damage.

[0066] Step S2: Based on the device testing requirements, identify some of the power semiconductor devices in the rectifier circuit, DC boost circuit, and inverter circuit as the SiC power semiconductor devices under test.

[0067] Specifically, priority is given to SiC power semiconductor devices that undertake the main power conversion task and withstand high electrical and thermal stresses in the circuit. For example, the sixth and seventh power semiconductor devices Q6 and Q7 in the inverter circuit, as SiC IGBTs, withstand large voltage change rates (dv / dt) and current stresses during high-frequency switching, making them the core objects for evaluating the high-frequency performance of SiC devices; SiC devices in DC boost circuits, on the other hand, need to cope with the high voltage stress during the boost process, making them suitable for withstand voltage and efficiency testing.

[0068] Step S3: Turn on the AC power.

[0069] Step S4: Record the electrical parameters of the SiC power semiconductor device under test.

[0070] Step S5: Generate a test report based on the electrical parameters of the SiC power semiconductor device under test.

[0071] Optionally, the core content of the report may include the following:

[0072] (1) Test Overview: Includes basic information such as the model of the SiC device under test, test requirements (e.g., number of cycles, junction temperature range), test circuit parameters (e.g., input voltage, switching frequency), and test duration;

[0073] (2) Data presentation: The changing trends of key parameters are displayed in the form of charts, such as "the curve of the change of on-state voltage drop with the number of cycles" and "the relationship between junction temperature fluctuation and switching loss", which intuitively reflects the performance degradation law of the device;

[0074] (3) Failure analysis (if it occurs): If the device under test fails during the test, the failure time and parameter mutation before failure (such as a sudden increase in leakage current) should be recorded. Combined with the circuit waveform (such as the switching waveform captured by the oscilloscope at the moment of failure) to analyze the cause of failure (such as thermal runaway, gate oxide layer breakdown).

[0075] (4) Conclusions and recommendations: Summarize the reliability level of the tested SiC devices, evaluate their applicable scenarios (such as new energy vehicle inverters and photovoltaic inverters), and propose optimization suggestions for the problems found in the test (such as improving the heat dissipation design to reduce junction temperature fluctuations).

[0076] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A power cycle testing circuit for a SiC power semiconductor device, characterized in that, The test circuit includes: a rectifier circuit, a DC boost circuit, and an inverter circuit, wherein... The AC side of the rectifier circuit is connected to an AC power source, and the DC side of the rectifier circuit is connected to the first terminal of the DC boost circuit. The second terminal of the DC boost circuit is connected to the DC side of the inverter circuit; The AC side of the inverter circuit is connected to the AC power supply; Some of the power semiconductor devices in the rectifier circuit, DC boost circuit, and inverter circuit are SiC power semiconductor devices under test.

2. The power cycle test circuit for SiC power semiconductor devices according to claim 1, characterized in that, The rectifier circuit includes three bridge arms, each bridge arm consisting of two first power semiconductor devices connected in series. In the six first power semiconductor devices, any one of the first power semiconductor devices is the first SiC power semiconductor device under test, and the remaining first power semiconductor devices are silicon-based power semiconductor devices.

3. The power cycle test circuit for SiC power semiconductor devices according to claim 2, characterized in that, The first SiC power semiconductor device under test is a SiC diode; Silicon-based power semiconductor devices are silicon-based diodes.

4. The power cycle test circuit for SiC power semiconductor devices according to claim 1, characterized in that, The DC boost circuit includes: a first capacitor, a first inductor, a second SiC power semiconductor device under test, and a third SiC power semiconductor device under test, wherein... The first terminal of the first capacitor is connected to the first terminal of the first inductor and the DC side of the rectifier circuit, and the second terminal of the first capacitor is connected to the second terminal of the second SiC power semiconductor device under test and the DC side of the inverter circuit. The second end of the first inductor is connected to the first end of the second SiC power semiconductor device under test and the first end of the third SiC power semiconductor device under test. The second terminal of the third SiC power semiconductor device under test is connected to the DC side of the inverter circuit.

5. The power cycle test circuit for SiC power semiconductor devices according to claim 4, characterized in that, The second SiC power semiconductor device under test is a SiC MOS transistor; The third SiC power semiconductor device under test is a SiC diode.

6. The power cycle test circuit for SiC power semiconductor devices according to claim 1, characterized in that, The inverter circuit includes: a second capacitor, a third capacitor, and three bridge arms. Each bridge arm includes: a second power semiconductor device, a third power semiconductor device, a fourth power semiconductor device, a fifth power semiconductor device, a sixth power semiconductor device, and a seventh power semiconductor device. The first terminal of the second power semiconductor device is connected to the second terminal of the DC boost circuit and the first terminal of the second capacitor, and the second terminal of the second power semiconductor device is connected to the first terminal of the third power semiconductor device and the first terminal of the sixth power semiconductor device. The second end of the third power semiconductor device is connected to the first end of the fourth power semiconductor device, and the second end of the third power semiconductor device is the AC side of the bridge arm. The second end of the fourth power semiconductor device is connected to the first end of the fifth power semiconductor device and the second end of the seventh power semiconductor device. The second terminal of the fifth power semiconductor device is connected to the second terminal of the DC boost circuit and the second terminal of the third capacitor; The second terminal of the sixth power semiconductor device is connected to the first terminal of the seventh power semiconductor device, the second terminal of the second capacitor, and the first terminal of the third capacitor. The sixth and seventh power semiconductor devices are the fourth SiC power semiconductor devices under test, while the second, third, fourth, and fifth power semiconductor devices are silicon-based power semiconductor devices.

7. The power cycle test circuit for SiC power semiconductor devices according to claim 6, characterized in that, The sixth and seventh power semiconductor devices are SiCIGBT transistors. The second, third, fourth, and fifth power semiconductor devices are silicon-based SiC IGBT transistors.

8. The power cycle test circuit for SiC power semiconductor devices according to claim 1, characterized in that, Also includes: Output filter circuit, wherein, The DC side of the inverter circuit is connected to the AC power supply through the output filter circuit.

9. The power cycle test circuit for SiC power semiconductor devices according to claim 1, characterized in that, Also includes: Input filter circuit, wherein, The AC power supply is connected to the input filter circuit.

10. A power cycling test method for SiC power semiconductor devices, characterized in that, Based on the power cycle test circuit of the SiC power semiconductor device according to any one of claims 1-9, the method includes: Determine the model and testing requirements of the power semiconductor device under test; According to the device testing requirements, some power semiconductor devices in the rectifier circuit, DC boost circuit and inverter circuit are identified as the SiC power semiconductor devices under test. Turn on the AC power; Record the electrical parameters of the SiC power semiconductor device under test; A test report is generated based on the electrical parameters of the SiC power semiconductor device under test.

Images