Implementation method of side lobe cancellation algorithm based on FPGA and HLS

Abstract

The invention relates to the technical field of digital signal processing, in particular to an implementation method of a sidelobe cancellation algorithm based on an FPGA and an HLS. Complex operations such as matrix inversion in the sidelobe cancellation algorithm are realized through the HLS, and the HLS adopts a C / C + + programming mode, so that the development efficiency is high, and iteration and upgrading of IP configuration can be quickly realized. Other operations in the sidelobe cancellation algorithm are realized through the FPGA, so that the relationship between resources consumed by large data volume processing and processing delay is balanced. Through cooperative work of the FPGA and the HLS, the development efficiency can be improved while the requirements for high processing performance and high real-time performance are met, parameters such as the number of channels, the number of sampling points and the matrix inversion dimension can be controlled through parameter configuration in the implementation process of the sidelobe cancellation algorithm, and the method has the advantages of being high in real-time performance, high in universality and high in development efficiency and has wide application prospects. The digital array signal processor can be widely applied to radar digital array signal processor products.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of digital signal processing, in particular to an implementation method of sidelobe cancellation algorithm based on FPGA and HLS. BACKGROUND

[0002] Sidelobe cancellation is a technology that increases several auxiliary antennas near the main antenna, and uses the weighted sum of the interference signals received by multiple antennas to form a zero point in the interference direction, so as to cancel the sidelobe interference of the antenna. For a multi-functional and multi-task array radar, considering that different functions and tasks may bring multiple main channels and auxiliary channels, and in addition to the real-time requirements of different radar frequency cycles, the sidelobe cancellation algorithm can be implemented by FPGA. FPGA has strong real-time and parallel processing capability, which can improve the speed of sidelobe cancellation.

[0003] However, in the implementation process of the sidelobe cancellation algorithm, complex operations such as matrix inversion are involved. If pure FPGA is used to develop multi-functional and multi-task radar equipment, the development process will inevitably face problems such as long development cycle and difficulty in upgrading. In the face of scenarios with a large number of channels, large data volume, and high real-time processing requirements, the traditional implementation method using DSP or CPU + GPU usually cannot meet the requirements of strong processing performance and strong real-time performance at the same time. Therefore, in view of the future development needs, how to improve the development efficiency while having strong real-time performance and strong processing performance is the key point of radar algorithm design research. SUMMARY

[0004] Therefore, embodiments of the present application propose an implementation method of sidelobe cancellation algorithm based on FPGA and HLS, which can improve the development efficiency while meeting the requirements of strong processing performance and strong real-time performance. In the implementation process of the sidelobe cancellation algorithm, the number of channels, the number of sampling points, and the dimension of matrix inversion can be controlled by parameters, which has the characteristics of high real-time performance, strong universality, and fast development efficiency, and can be widely applied to radar digital array signal processing machine products.

[0005] In order to achieve the above object, the embodiment of the present application proposes an implementation method of sidelobe cancellation algorithm based on FPGA and HLS, which is suitable for multi-functional and multi-task array radar, and the method comprises the following steps: receiving and buffering the main channel array manifold data and the auxiliary channel array manifold data sent by a digital beam forming unit, generating the required sampling point number according to the configured sub-channel number and weight coefficient, rearranging and intercepting the array manifold data based on the required sampling point number, and then sending the data into the buffer interval of each sub-channel; reading out the intercepted data of all sub-channels in the auxiliary channel and the main channel in a time division multiplexing manner, then reading out the intercepted data of all sub-channels in the auxiliary channel in parallel circulation according to the time division multiplexing number, performing matrix multiplication operation on the twice read sub-channel data to obtain autocorrelation processing result and cross-correlation processing result; generating a matrix inversion module based on Cholesky decomposition through HLS tool, inputting the autocorrelation processing result and the matrix inversion dimension into the matrix inversion module to obtain autocorrelation matrix inversion result; wherein the maximum dimension matrix inversion processing time is less than the radar repetition frequency cycle; latching each element in each row of the autocorrelation matrix inversion result, reading out the cross-correlation result when the latching of the last element in each row is completed, multiplying each element in each row of the autocorrelation matrix inversion result with each element in each column of the cross-correlation matrix to obtain weight coefficient formation result; reading out the auxiliary channel array manifold data from the buffer interval, performing secondary latching on the elements of each channel according to the number of sub-channels in the auxiliary channel, reading out the weight coefficient when the latching of the elements of the last channel is completed, and the reading-out number is equal to the total number of sampling points of the array manifold data, so as to realize the matrix multiplication operation of the data of the auxiliary channel under all sampling points and the weight coefficient formation result, and finally reading out the main channel array manifold data from the buffer interval and performing difference processing to obtain sidelobe cancellation formation result.

[0006] To achieve the above object, the embodiment of the present application also proposes an implementation system of sidelobe cancellation algorithm based on FPGA and HLS, which is suitable for multi-functional and multi-task array radar, and the system comprises: a data caching and rearrangement interception module, which is used for receiving and caching main channel array manifold data and auxiliary channel array manifold data sent by a digital beam forming unit, generating required sampling point number according to configured sub-channel number and weight coefficient, rearranging and intercepting the array manifold data based on the required sampling point number, and sending the array manifold data into the cache interval of each sub-channel; a self-correlation and cross-correlation processing module, which is used for reading out the intercepted data of all sub-channels in the auxiliary channel and the main channel in a time division multiplexing manner, reading out the intercepted data of all sub-channels in the auxiliary channel in parallel circulation according to the time division multiplexing number, performing matrix multiplication operation on the twice read sub-channel data, and obtaining self-correlation processing result and cross-correlation processing result; a self-correlation matrix inversion module, which is used for generating a matrix inversion module based on Cholesky decomposition through an HLS tool, inputting the self-correlation processing result and matrix inversion dimension into the matrix inversion module, and obtaining self-correlation matrix inversion result, wherein the processing time of the matrix inversion with the maximum dimension is less than the radar repetition frequency cycle; a weight coefficient forming module, which is used for latching each element of each row in the self-correlation matrix inversion result, reading out the cross-correlation result when the latching of the last element of each row is completed, multiplying the elements of each row of the self-correlation matrix inversion result with the elements of each column of the cross-correlation matrix, and obtaining weight coefficient forming result; and a sidelobe cancellation forming module, which is used for reading out the auxiliary channel array manifold data from the cache interval, latching the elements of each channel twice according to the number of sub-channels in the auxiliary channel, reading out the weight coefficient when the latching of the elements of the last channel is completed, reading out the number of times equal to the total number of sampling points of the array manifold data, performing matrix multiplication operation on the data of the auxiliary channel under all sampling points and the weight coefficient forming result, and finally reading out the main channel array manifold data from the cache interval and performing difference processing to obtain sidelobe cancellation forming result.

[0007] To achieve the above object, the embodiment of the present application also proposes an electronic device, which comprises: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions capable of being executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the implementation method of sidelobe cancellation algorithm based on FPGA and HLS as described above.

[0008] To achieve the above object, the embodiment of the present application also proposes a computer readable storage medium, which stores a computer program, and the computer program can implement the implementation method of sidelobe cancellation algorithm based on FPGA and HLS as described above when executed by a processor.

[0009] The application provides an implementation method of a sidelobe cancellation algorithm based on FPGA and HLS. In the sidelobe cancellation algorithm, complex operations such as matrix inversion are implemented through HLS, and other operations are implemented through FPGA, so as to balance the relationship between resource consumption and processing delay in large data processing. FPGA and HLS work cooperatively, can meet the requirements of strong processing performance and strong real-time performance, improve development efficiency, and can be widely applied to radar digital array signal processing machine products.

[0010] Optionally, the working clock frequencies of the FPGA and the HLS are both F, the data rate of a single channel is S, the maximum number of sub-channels of the maximum transmission is U=F / S, the number of effective sub-channels in the main channel is M, the number of effective sub-channels in the auxiliary channel is N, M and N are both not greater than U, the radar frequency period is T, the number of data transmitted by a single channel is L, the number of sampling points required for weight coefficient generation is K, and the maximum matrix inversion dimension in the HLS is V. The FPGA receives the main channel array manifold data and the auxiliary channel array manifold data sent by the digital beam forming unit, the main channel array manifold data includes U sub-channel data of L transmitted data, and the number of effective sub-channels is M; the auxiliary channel array manifold data includes U sub-channel data of L transmitted data, and the number of effective sub-channels is N. The main channel array manifold data and the auxiliary channel array manifold data are respectively stored in the corresponding DDR memories, at the same time, the array manifold data is rearranged according to the maximum channel number U and the number L of data transmitted by a single channel, and the data corresponding to the number of effective sub-channels and the number K of sampling points required for weight coefficient generation are intercepted and stored in the BRAM cache of each sub-channel, that is, K data corresponding to the first sub-channel in the main channel are sent to the first dual-port RAM, and the processing mode of the sub-channels in the auxiliary channel is the same as that of the sub-channels in the main channel. The number of BRAMs required for instantiation of the main channel and the auxiliary channel is based on the maximum number of channels generated by the minimum data rate of a single channel.

[0011] Optionally, the intercepted data of all sub-channels in the main channel and all sub-channels in the auxiliary channel are read out at the same time, that is, the auxiliary channel and the auxiliary channel autocorrelation processing, and the auxiliary channel and the main channel cross-correlation processing can be realized, and in the case of a large number of channels, the internal operation unit of the device is consumed, and the processing mode of time division multiplexing is adopted; When cross-correlation processing is performed, the time division multiplexing times are P, P=M / n, n is the number of sub-channels in the main channel read in parallel in a single time division multiplexing, P satisfies (P x K) / F < T, so as to realize the flow processing of the radar repetition frequency period level, and the cycle reading times of the N auxiliary sub-channels are also P times, in each time division multiplexing period, the first row of the multiplier module is multiplied by the corresponding elements of the first row to the nth row of the multiplicand module and is accumulated, and the same is true for the subsequent rows, until the Nth row of the multiplier module is multiplied by the corresponding elements of the first row to the nth row of the multiplicand module and is accumulated, so as to obtain the cross-correlation processing result, and the cross-correlation processing result is stored in the cache area; The implementation mode of the autocorrelation processing result is the same as that of the cross-correlation processing result.

[0012] Optionally, the HLS tool adopts C / C++ programming development, calls the Cholesky inverse function in the mathematical function library, inputs the original data, the data type and the matrix inversion dimension, and then the inversion result of the input data can be obtained, after optimizing the interface, array, function and loop, the processing delay is checked through the synthesis implementation function of the HLS tool, the matrix inversion IP core is generated, and the FPGA is allowed to call; The matrix inversion operation realized based on the HLS tool needs to be mapped to the hardware resource, and the size of the inversion matrix cannot be dynamically changed each time, therefore, the matrix inversion dimension needs to be set according to the radar repetition frequency period T, the maximum matrix inversion dimension that can be realized in T is V, so as to realize the flow processing of the repetition frequency period level, the input matrix inversion dimension is not greater than V, and when the input matrix inversion dimension is less than V, 1 is filled in the remaining matrix main diagonal line, so as to satisfy the correctness of the inversion operation.

[0013] Optionally, the weight coefficient formation is realized by the FPGA, taking the first row of the autocorrelation matrix inversion result as an example, each element of the first row is subjected to register latching processing, after the last element of the first row is latched, the cross-correlation processing result is read out in parallel, in the longitudinal direction at each moment, the corresponding multiplication and accumulation of all elements of the first row of the autocorrelation matrix inversion result and each column element of the cross-correlation processing result are realized, and the same is true for the subsequent rows, until the corresponding multiplication and accumulation of all elements of the Nth row of the autocorrelation matrix inversion result and each column element of the cross-correlation result are realized, so as to obtain the weight coefficient formation result, and the weight coefficient formation result is stored in the cache area; The multiplication and accumulation of the N rows of data of the autocorrelation matrix inversion result and the corresponding correlation processing result is also implemented by using time division multiplexing.

[0014] Optionally, the auxiliary channel array manifold data is sequentially read out from the DDR memory and smoothed output through the FIFO cache. According to the number N of valid sub-channels in the auxiliary channel, the L downlink data corresponding to each sub-channel in the N channels are latched. When the latching of the Nth sub-channel in each downlink data ends, the L downlink data corresponding to the N sub-channels are latched again, so that the N sub-channels are output in parallel at the same time. At the same time, the weight coefficient formation result is output in parallel at the same time. The number of times of outputting the same group of weight coefficient formation result is equal to the number L of downlink data of a single channel. In the longitudinal direction, the N effective auxiliary sub-channel data of the first downlink data point number are multiplied and accumulated with each column data of the weight coefficient formation result. Similarly, the N effective auxiliary sub-channel data of the Lth downlink data point number are multiplied and accumulated with each column data of the weight coefficient formation result. Finally, the cancellation factor result of the product of the L downlink data corresponding to the N auxiliary sub-channels and the weight coefficient formation result is obtained. At the same time, the main channel array manifold data in the DDR memory is sequentially read out and smoothed output through the FIFO cache. The sidelobe cancellation formation result is obtained by subtracting the cancellation factor result.

[0015] Optionally, when the radar repetition frequency period is short, the array manifold data stored in the radar repetition frequency period of the previous stage or multiple stages also needs to be read out when the main channel array manifold data and the auxiliary channel array manifold data are stored in the DDR memory, that is, the DDR memory needs to be read and written arbitrated; In order to have the real-time processing effect of the radar repetition frequency period, the time consumed by the autocorrelation processing and the cross-correlation processing, the autocorrelation matrix inversion, and the weight coefficient formation needs to be less than the radar repetition frequency period T. When the maximum channel number, the effective channel number, the number of downlink data of a single channel, and the number of sampling points required for weight coefficient generation corresponding to the data rate change, real-time configuration of parameters is used to complete different forms of sidelobe cancellation processing. When the maximum inversion dimension of the matrix changes, the iteration and upgrade of IP configuration need to be realized quickly through HLS. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the drawings needed to be used in the description of the embodiments of the present application or the related art will be briefly introduced. Obviously, the following drawings are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor based on these drawings, and the drawings described herein are only used to explain the present application, and not to limit the present application.

[0017] Figure 1 is a flow chart of an implementation method of a sidelobe cancellation algorithm based on FPGA and HLS provided in an embodiment of the present application; Figure 2 is a schematic diagram of the implementation method of the sidelobe cancellation algorithm based on FPGA and HLS provided in an embodiment of the present application; Figure 3 is a schematic diagram of an array manifold rearrangement process provided in an embodiment of the present application; Figure 4 is a schematic diagram of an autocorrelation process and a cross-correlation process provided in an embodiment of the present application; Figure 5 is a schematic diagram of a matrix inversion process provided in an embodiment of the present application; Figure 6 is a schematic diagram of a weight coefficient formation process provided in an embodiment of the present application; Figure 7 is a schematic diagram of a cancellation factor generation process provided in an embodiment of the present application; Figure 8 is a schematic diagram of a DDR memory read-write arbitration process provided in an embodiment of the present application; Figure 9 is a schematic diagram of a sidelobe cancellation pipeline process provided in an embodiment of the present application; Figure 10 is a structural schematic diagram of an implementation system of a sidelobe cancellation algorithm based on FPGA and HLS provided in another embodiment of the present application; Figure 11 is a structural schematic diagram of an electronic device provided in another embodiment of the present application. DETAILED DESCRIPTION

[0018] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the drawings. Those skilled in the art can understand that, in the embodiments of the present application, many technical details are proposed in order to make the readers better understand. However, the technical solutions claimed by the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments. The following embodiments are classified for the convenience of description, and should not constitute any limitation on the specific implementation modes of the present application, and the following embodiments can be combined and referenced with each other without contradiction.

[0019] One embodiment of the present application proposes an implementation method of a sidelobe cancellation algorithm based on FPGA and HLS. The implementation details of the implementation method of the sidelobe cancellation algorithm based on FPGA and HLS proposed by the present embodiment will be described in detail below. The following content is only the implementation details provided for the convenience of understanding, and is not necessary for implementing the present solution.

[0020] The specific process of the implementation method of the sidelobe cancellation algorithm based on FPGA and HLS proposed by the present embodiment can be as shown in Figure 1 The specific process of the implementation method of the sidelobe cancellation algorithm based on FPGA and HLS proposed by the present embodiment can be as shown in Figure 2 The method comprises the following steps. In step 11, the main channel array manifold data and the auxiliary channel array manifold data sent by the digital beam forming unit are received and buffered, the required sampling point number is generated according to the configured sub-channel number and weight coefficient, the array manifold data is rearranged and intercepted based on the required sampling point number, and then sent to the buffer interval of each sub-channel.

[0021] In the specific implementation, the implementation method of the sidelobe cancellation algorithm proposed by the present embodiment is realized based on the FPGA processing platform and the HLS processing platform. First, the FPGA receives the main channel array manifold data and the auxiliary channel array manifold data sent by the digital beam forming unit and buffers them, generates the required sampling point number according to the configured sub-channel number and weight coefficient, rearranges and intercepts the array manifold data based on the required sampling point number, and then sends them to the buffer interval of each sub-channel.

[0022] In one example, the working clock frequencies of the FPGA and the HLS processing platform are both F, the data rate of a single channel under transmission is S, the number of maximum under-transmission sub-channels is U, U=F / S, the number of effective sub-channels in the main channel is M, the number of effective sub-channels in the auxiliary channel is N, M and N are both not greater than U, the radar repetition frequency period is configured as T, the number of data under transmission of a single channel is L, the required sampling point number for weight coefficient generation is set as K, and the maximum matrix inversion dimension in the HLS processing platform is V.

[0023] In one example, the FPGA receives the main channel array manifold data and the auxiliary channel array manifold data sent by the digital beam forming unit, as shown in FIG. 1. Figure 3 As shown in FIG. 1, the main channel array manifold data contains U sub-channel data of L downlink data, and the effective sub-channel number is M; the auxiliary channel array manifold data contains U sub-channel data of L downlink data, and the effective sub-channel number is N. The main channel array manifold data and the auxiliary channel array manifold data are respectively stored in the corresponding DDR memories. At the same time, the array manifold data is rearranged according to the maximum channel number U and the number L of downlink data of a single channel, and the data corresponding to the effective sub-channel number and the sampling point number K required for generating the weight coefficient are cut off and stored in the BRAM cache of each sub-channel, that is, the K data corresponding to the first sub-channel in the main channel are sent to the first dual-port RAM, the K data corresponding to the second sub-channel in the main channel are sent to the second dual-port RAM, and so on, and the K data corresponding to the Mth sub-channel in the main channel are sent to the Mth dual-port RAM. The processing mode of the sub-channels in the auxiliary channel is the same as that of the sub-channels in the main channel. The number of BRAMs required for instantiation of the main channel and the auxiliary channel is based on the maximum number of channels that can be generated at the minimum data rate of a single channel, so as to increase the versatility of processing.

[0024] In step 12, the cut-off data of all sub-channels in the auxiliary channel and the main channel are read out in a time division multiplexing manner, and the cut-off data of all sub-channels in the auxiliary channel are read out in parallel according to the number of time division multiplexing. The sub-channel data read out twice are subjected to matrix multiplication to obtain the autocorrelation processing result and the cross-correlation processing result.

[0025] In a specific implementation, after the array manifold data is rearranged and cut off and sent to the cache area of each sub-channel, the cut-off data of all sub-channels in the auxiliary channel and the main channel are read out in a time division multiplexing manner, and the cut-off data of all sub-channels in the auxiliary channel are read out in parallel according to the number of time division multiplexing. Then, the sub-channel data read out twice are subjected to matrix multiplication to obtain the autocorrelation processing result and the cross-correlation processing result.

[0026] In one example, the cut-off data of all sub-channels in the main channel and all sub-channels in the auxiliary channel are read out at the same time, so as to realize the autocorrelation processing of the auxiliary channel and the auxiliary channel and the cross-correlation processing of the auxiliary channel and the main channel. In the case of a large number of channels and a large number of internal operation units consumed in complete parallel processing, a time division multiplexing processing mode can be used to save resources.

[0027] As shown in FIG. 1, Figure 4As shown, when the cross-correlation processing is performed, the time-division multiplexing number is P, P=M / n, n is the number of sub-channels in the main channel of the single time-division multiplexing parallel reading, and P satisfies (P×K) / F < T, so as to realize the flow processing of the radar repetition frequency period level, and the cycle reading number of the N auxiliary sub-channels is also P. In each time-division multiplexing period, the first row of the multiplier module is multiplied by the corresponding elements of the first row to the nth row of the multiplicand module and accumulated, then the second row of the multiplier module is multiplied by the corresponding elements of the first row to the nth row of the multiplicand module and accumulated, and so on, until the Nth row of the multiplier module is multiplied by the corresponding elements of the first row to the nth row of the multiplicand module and accumulated, so as to obtain the cross-correlation processing result, and the cross-correlation processing result is stored in the buffer area. The implementation manner of the autocorrelation processing result is the same as that of the cross-correlation processing result.

[0028] In step 13, a Cholesky decomposition-based matrix inversion module is generated by an HLS tool, the autocorrelation processing result and the matrix inversion dimension are input into the matrix inversion module, and an autocorrelation matrix inversion result is obtained, wherein the processing time of the matrix inversion with the maximum dimension is less than the radar repetition frequency period.

[0029] In a specific implementation, complex operations such as matrix inversion in the sidelobe cancellation algorithm are implemented by HLS, a Cholesky decomposition-based matrix inversion module is generated by an HLS tool, the autocorrelation processing result and the matrix inversion dimension are input into the matrix inversion module, and an autocorrelation matrix inversion result is obtained; wherein the processing time of the matrix inversion with the maximum dimension is less than the radar repetition frequency period.

[0030] In one example, before performing the matrix inversion operation on the autocorrelation processing result, in order to increase the matrix inversion precision, a fixed-point to floating-point operation can be performed, the matrix operation module is relatively complex, and in order to improve the development efficiency, the embodiment is selected to be implemented by an HLS tool. The HLS tool adopts C / C++ programming development, calls the Cholesky inversion function in the mathematical function library, inputs the original data, the data type and the matrix inversion dimension, and then the inversion result of the input data can be obtained. After the interface, array, function and loop are optimized, the processing delay is viewed through the synthesis implementation function of the HLS tool, the matrix inversion IP core is generated, and the FPGA is allowed to call.

[0031] The matrix inversion operation implemented based on the HLS tool needs to be mapped to the hardware resources, and the size of the inversion matrix cannot be dynamically changed each time, therefore the matrix inversion dimension needs to be set according to the radar repetition frequency period T, the maximum matrix inversion dimension that can be implemented within T is V, so as to realize the flow processing of the repetition frequency period level, the input matrix inversion dimension is not greater than V, and when the input matrix inversion dimension is less than V, 1 is filled in the remaining matrix main diagonal line, such as Figure 5The inverse operation is correct.

[0032] Step 14, latch each element of each row in the autocorrelation matrix inversion result, read out the cross-correlation result when the last element of each row is latched, multiply each element of each row in the autocorrelation matrix inversion result with each element of each column in the cross-correlation matrix to obtain the weight coefficient formation result.

[0033] In a specific implementation, after obtaining the autocorrelation matrix inversion result, each element of each row in the autocorrelation matrix inversion result needs to be latched, the cross-correlation result is read out when the last element of each row is latched, and each element of each row in the autocorrelation matrix inversion result is multiplied with each element of each column in the cross-correlation matrix to obtain the weight coefficient formation result.

[0034] In an example, in order to better balance the relationship between resources and delay, the weight coefficient formation process is still implemented by FPGA. As shown in Figure 6 The first row of the autocorrelation matrix inversion result is taken as an example, each element of the first row is registered and latched, the cross-correlation processing result is read out in parallel after the last element of the first row is latched, and at each moment, the corresponding multiplication and accumulation of all elements of the first row of the autocorrelation matrix inversion result and each column element of the cross-correlation processing result are implemented in the vertical direction. Similarly, the corresponding multiplication and accumulation of all elements of the Nth row of the autocorrelation matrix inversion result and each column element of the cross-correlation result are implemented until the weight coefficient formation result is obtained, and the weight coefficient formation result is stored in the cache area.

[0035] In order to save the multiplier resource, the corresponding multiplication and accumulation of the N rows of the autocorrelation matrix inversion result and the cross-correlation processing result can also be implemented by using time division multiplexing.

[0036] Step 15, read out the auxiliary channel array manifold data from the cache area, perform secondary latching on the elements of each channel according to the number of sub-channels in the auxiliary channel, read out the weight coefficient when the element latching of the last channel is completed, the reading-out time is equal to the total number of sampling points of the array manifold data, implement the matrix multiplication operation of the data of the auxiliary channel under all sampling points and the weight coefficient formation result, and finally read out the main channel array manifold data from the cache area and perform difference processing to obtain the sidelobe cancellation formation result.

[0037] In a specific implementation, after the weight coefficients (weight coefficient matrix) are generated, the auxiliary channel array manifold data needs to be read out from the buffer area, the elements of each channel are latched twice according to the number of sub-channels in the auxiliary channel, and when the element latching of the last channel is completed, the weight coefficients are read out, the number of readouts is equal to the total number of sampling points of the array manifold data, the matrix multiplication operation of the data of the auxiliary channel and the weight coefficient formation result under all sampling points is realized, and finally the main channel array manifold data is read out from the buffer area and difference processing is performed to obtain the sidelobe cancellation formation result.

[0038] In one example, after the weight coefficient matrix is generated, the auxiliary channel array manifold data is sequentially read out from the DDR memory, and the data is smoothly output through the FIFO buffer, according to the number N of valid sub-channels in the auxiliary channel, the L downlink data corresponding to each sub-channel in the N channels are latched, and when the latching of the Nth sub-channel in each downlink data is completed, the L downlink data corresponding to the N sub-channels are latched again, so that the N sub-channels output in parallel at the same time, as shown in Figure 7 Meanwhile, the weight coefficient formation result is output in parallel at the same time, and the number of times of output of the same group of weight coefficient formation results is equal to the number L of downlink data of a single channel.

[0039] Then, in the longitudinal direction, the N valid auxiliary sub-channel data of the first downlink data point number are multiplied by each column data of the weight coefficient formation result and accumulated, and so on, until the N valid auxiliary sub-channel data of the Lth downlink data point number are multiplied by each column data of the weight coefficient formation result and accumulated, and finally the cancellation factor result of the product of the L downlink data corresponding to the N auxiliary sub-channels and the weight coefficient formation result is obtained, and at the same time, the main channel array manifold data in the DDR memory is sequentially read out at the same time, and the data is smoothly output through the FIFO buffer, and is subtracted from the cancellation factor result to obtain the sidelobe cancellation formation result.

[0040] In one example, when the radar repetition frequency period is short, when the main channel array manifold data and the auxiliary channel array manifold data are stored in the DDR memory, the array manifold data stored in the previous stage or multiple stages of radar repetition frequency period also needs to be read out, that is, the DDR memory needs to be read and written arbitrated, as shown in Figure 8 In order to have the real-time processing effect of the radar repetition frequency period, the time consumed by the autocorrelation processing and the cross-correlation processing, the autocorrelation matrix inversion, and the weight coefficient formation needs to be less than the radar repetition frequency period T, as shown in Figure 9When the maximum number of channels corresponding to the data rate, the effective number of channels, the number of data transmitted by a single channel, and the number of sampling points required for generating the weight coefficient change, they can be configured in real time through parameters to complete different forms of sidelobe cancellation processing. When the maximum inversion dimension of the matrix changes, the iteration and upgrade of IP configuration need to be realized quickly through HLS.

[0041] The implementation method of the sidelobe cancellation algorithm based on FPGA and HLS proposed in the embodiment can balance the relationship between the resources consumed by large data processing and the processing delay. The cooperative work of FPGA and HLS can meet the requirements of strong processing performance and strong real-time performance at the same time, improve the development efficiency, and control the parameters such as the number of channels, the number of sampling points, and the inversion dimension of the matrix through parameter configuration in the implementation process of the sidelobe cancellation algorithm. The sidelobe cancellation algorithm has the characteristics of high real-time performance, strong versatility, and fast development efficiency, and can be widely applied to the digital array signal processor products of radar.

[0042] The step division of the above various methods is only for the purpose of clear description. In the implementation, one step can be combined or some steps can be divided into multiple steps, as long as the same logical relationship is included, which is within the protection scope of the present application. Adding irrelevant modifications or introducing irrelevant designs in the algorithm or the flow, but not changing the core design of the algorithm and the flow, are within the protection scope of the present application.

[0043] Another embodiment of the present application proposes an implementation system of the sidelobe cancellation algorithm based on FPGA and HLS, which is suitable for multi-functional and multi-task array radars. The details of the implementation system of the sidelobe cancellation algorithm based on FPGA and HLS proposed in the embodiment will be specifically described below. The following content only provides implementation details for the convenience of understanding, and is not necessary for implementing the embodiment.

[0044] The specific structure of the implementation system of the sidelobe cancellation algorithm based on FPGA and HLS proposed in the embodiment can be as follows Figure 10As shown, it comprises: a data buffering and rearrangement intercepting module 21, an autocorrelation and cross-correlation processing module 22, an autocorrelation matrix inversion module 23, a weight coefficient forming module 24 and a sidelobe cancellation forming module 25.

[0045] The data buffering and rearrangement intercepting module 21 is configured to receive and buffer the main channel array manifold data and the auxiliary channel array manifold data sent by the digital beamforming unit, generate the required sampling point number according to the configured subchannel number and weight coefficient, rearrange and intercept the array manifold data based on the required sampling point number, and then send the array manifold data to the buffer interval of each subchannel.

[0046] The autocorrelation and cross-correlation processing module 22 is configured to read out the intercepted data of all subchannels in the auxiliary channel and the main channel in a time division multiplexing manner, read out the intercepted data of all subchannels in the auxiliary channel in parallel circulation according to the time division multiplexing number, and perform matrix multiplication on the twice read subchannel data to obtain autocorrelation processing results and cross-correlation processing results.

[0047] The autocorrelation matrix inversion module 23 is configured to generate a matrix inversion module based on Cholesky decomposition through an HLS tool, input the autocorrelation processing results and the matrix inversion dimension into the matrix inversion module, and obtain autocorrelation matrix inversion results, wherein the processing time of the matrix inversion with the maximum dimension is less than the radar repetition frequency period.

[0048] The weight coefficient forming module 24 is configured to latch each element in each row of the autocorrelation matrix inversion results, read out the cross-correlation results when the latching of the last element in each row is completed, multiply the elements in each row of the autocorrelation matrix inversion results with the elements in each column of the cross-correlation matrix, and obtain weight coefficient forming results.

[0049] The sidelobe cancellation forming module 25 is configured to read out the auxiliary channel array manifold data from the buffer interval, perform secondary latching on the elements of each channel according to the number of subchannels in the auxiliary channel, read out the weight coefficients when the latching of the elements of the last channel is completed, read out the weight coefficients a number of times equal to the total number of sampling points of the array manifold data, perform matrix multiplication of the data of the auxiliary channel under all sampling points and the weight coefficient forming results, finally read out the main channel array manifold data from the buffer interval and perform difference processing to obtain sidelobe cancellation forming results.

[0050] It can be found that the embodiment is a system embodiment corresponding to the above-mentioned method embodiment, and the embodiment can be implemented in cooperation with the above-mentioned method embodiment. The related technical details and technical effects mentioned in the above-mentioned method embodiment are still valid in the embodiment. In order to reduce repetition, they will not be described here. Correspondingly, the related technical details mentioned in the embodiment can also be applied to the above-mentioned method embodiment.

[0051] It is worth mentioning that each module and module involved in the embodiment is a logical module. In actual application, one logical unit can be one physical unit, or a part of one physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of the present application, units not closely related to solving the technical problems proposed in the present application are not introduced in the embodiment, but this does not mean that there are no other units in the embodiment.

[0052] Another embodiment of the present application provides an electronic device, such as Figure 11 As shown in the figure, comprising: at least one processor 31;And, the memory 32 connected with the at least one processor 31;Wherein, the memory 32 stores the instruction capable of being executed by the at least one processor 31, the instruction is executed by the at least one processor 31, to enable the at least one processor 31 can execute as described in the above method embodiment one kind based on FPGA and HLS's sidelobe cancellation algorithm implementation method.

[0053] Wherein, the memory and the processor are connected in a bus mode, the bus includes any number of interconnected buses and bridges, and the bus connects various circuits of one or more processors and memories together. The bus can also connect various other circuits such as peripheral devices, voltage regulators and power management circuits together, which are well known in the art, and therefore will not be further described herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be one element or multiple elements, such as multiple receivers and transmitters, which provide units for communicating with various other devices on the transmission medium.

[0054] The processor is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interface, voltage regulation, power management and other control functions. And the memory can be used to store the data used by the processor in the execution operation.

[0055] Another embodiment of the present application provides a computer readable storage medium, the computer readable storage medium stores a computer program, the computer program is executed by the processor, and can realize the implementation method of the sidelobe cancellation algorithm based on FPGA and HLS as described in the above method embodiment.

[0056] That is, a person skilled in the art can understand that all or part of the steps in the above method embodiments can be completed by programs instructing relevant hardware, the programs are stored in a storage medium, and the programs include a plurality of instructions for causing a device (such as a single-chip microcomputer, a chip, etc.) or a processor to execute all or part of the steps of the method described in the method embodiments of the present application. The foregoing storage medium includes a U disk, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk, and various media that can store program codes.

[0057] A person skilled in the art can understand that each of the above embodiments is a specific embodiment for implementing the present application, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the present application. For those skilled in the art, a number of improvements and refinements can be made without departing from the principles of the present application, and these improvements and refinements are also considered within the protection scope of the present application.

Claims

1. A method for implementing a sidelobe cancellation algorithm based on FPGA and HLS, suitable for multi-functional and multi-task array radars, characterized in that, The method comprises: Receiving and buffering the main channel array manifold data and the auxiliary channel array manifold data sent by the digital beam forming unit, generating the required sampling point number according to the configured subchannel number and weight coefficient, rearranging and intercepting the array manifold data based on the required sampling point number, and then sending into the buffer interval of each subchannel; Reading out the intercepted data of all subchannels in the auxiliary channel and the main channel in a time division multiplexing manner, then reading out the intercepted data of all subchannels in the auxiliary channel in parallel circulation according to the time division multiplexing number, performing matrix multiplication operation on the subchannel data read out twice to obtain the autocorrelation processing result and the cross-correlation processing result; Generating a matrix inversion module based on Cholesky decomposition through the HLS tool, inputting the autocorrelation processing result and the matrix inversion dimension into the matrix inversion module to obtain the autocorrelation matrix inversion result; wherein the processing time of the matrix inversion with the maximum dimension is less than the radar repetition frequency period; Latching each element in each row of the autocorrelation matrix inversion result, reading out the cross-correlation result when the latching of the last element in each row is completed, multiplying each element in each row of the autocorrelation matrix inversion result with each element in each column of the cross-correlation matrix to obtain the weight coefficient formation result; Reading out the auxiliary channel array manifold data from the buffer interval, performing secondary latching on the elements of each channel according to the number of subchannels in the auxiliary channel, reading out the weight coefficient when the latching of the elements of the last channel is completed, and the reading out number is equal to the total number of sampling points of the array manifold data, so as to realize the matrix multiplication operation of the data of the auxiliary channel under all sampling points and the weight coefficient formation result, and finally reading out the main channel array manifold data from the buffer interval and performing difference processing to obtain the sidelobe cancellation formation result.

2. The implementation method of sidelobe cancellation algorithm based on FPGA and HLS according to claim 1, characterized in that, The working clock frequency of the configured FPGA and HLS is F, the data rate of the single channel under transmission is S, the maximum number of subchannels under transmission is U=F / S, the number of effective subchannels in the main channel is M, the number of effective subchannels in the auxiliary channel is N, M and N are not greater than U, the radar repetition frequency period is T, the number of data under transmission of the single channel is L, the required sampling point number for weight coefficient generation is K, and the maximum matrix inversion dimension in HLS is V; The FPGA receives the main channel array manifold data and the auxiliary channel array manifold data sent by the digital beam forming unit, the main channel array manifold data contains U subchannel data of L under-transmission data, and the number of effective subchannels is M, and the auxiliary channel array manifold data contains U subchannel data of L under-transmission data, and the number of effective subchannels is N. The main channel array manifold data and the auxiliary channel array manifold data are respectively stored in the corresponding DDR memories, at the same time, according to the maximum channel number U and the number L of the single channel downlink data, the array manifold data is rearranged, and the effective subchannel number and the data corresponding to the weight coefficient generated sampling point number K are cut off and stored in the BRAM cache of the corresponding subchannel, that is, the K data corresponding to the first subchannel in the main channel are sent to the first dual-port RAM, and so on, the K data corresponding to the Mth subchannel in the main channel are sent to the Mth dual-port RAM, the processing mode of the subchannel in the auxiliary channel is the same as that of the subchannel in the main channel, and the number of BRAMs required to be instantiated in the main channel and the auxiliary channel is based on the maximum number of channels that can be generated by the minimum data rate of the single channel downlink.

3. The implementation method of sidelobe cancellation algorithm based on FPGA and HLS according to claim 2, characterized in that, The cut-off data of all subchannels in the main channel and all subchannels in the auxiliary channel are read out at the same time, that is, the autocorrelation processing of the auxiliary channel and the auxiliary channel, and the cross-correlation processing of the auxiliary channel and the main channel are realized, in the case of a large number of channels and a large number of internal operation units consumed by completely parallel processing, a time division multiplexing processing mode is adopted; When performing cross-correlation processing, the time division multiplexing times are P, P=M / n, n is the number of subchannels in the main channel read in parallel in a single time division multiplexing, P satisfies (P*K) / F < T, so as to realize the pipeline processing of the radar repetition frequency period level, the cycle reading times of the N auxiliary subchannels are also P times, in each time division multiplexing period, the first row of the multiplier module is multiplied by the corresponding elements of the first row to the nth row of the multiplicand module and accumulated, and so on, until the Nth row of the multiplier module is multiplied by the corresponding elements of the first row to the nth row of the multiplicand module and accumulated, so as to obtain the cross-correlation processing result, and store the cross-correlation processing result in the cache area; The implementation mode of the autocorrelation processing result is the same as that of the cross-correlation processing result.

4. The implementation method of sidelobe cancellation algorithm based on FPGA and HLS according to claim 2, characterized in that, The HLS tool adopts C / C++ programming development, calls the Cholesky inverse function in the mathematical function library, inputs the original data, the data type and the matrix inversion dimension, and then the inversion result of the input data is obtained, after optimizing the interface, array, function and loop, the processing delay is checked through the synthesis implementation function of the HLS tool, the matrix inversion IP core is generated, and the FPGA is allowed to call; The matrix inversion operation realized based on the HLS tool needs to be mapped to the hardware resources, and the size of the inversion matrix cannot be dynamically changed each time, therefore, the matrix inversion dimension needs to be set according to the radar repetition frequency period T, the maximum matrix inversion dimension that can be realized in T is V, so as to realize the pipeline processing of the repetition frequency period level, the input matrix inversion dimension is not greater than V, when the input matrix inversion dimension is less than V, 1 is filled in the remaining matrix main diagonal line, so as to satisfy the correctness of the inversion operation.

5. The implementation method of sidelobe cancellation algorithm based on FPGA and HLS according to claim 1, characterized in that, The weight coefficient formation is realized by the FPGA, and the first row of the autocorrelation matrix inversion result is taken as an example. Each element of the first row is subjected to register latching processing. After the last element of the first row is latched, the cross-correlation processing result is read out in parallel. In the longitudinal direction at each moment, the corresponding multiplication and accumulation of all elements of the first row of the autocorrelation matrix inversion result and each column element of the cross-correlation processing result are implemented. Similarly, the corresponding multiplication and accumulation of all elements of the Nth row of the autocorrelation matrix inversion result and each column element of the cross-correlation result are implemented, so as to obtain the weight coefficient formation result, and the weight coefficient formation result is stored in the buffer area. The corresponding multiplication and accumulation of the N rows of the autocorrelation matrix inversion result and the cross-correlation processing result is also realized by the time division multiplexing method.

6. The implementation method of sidelobe cancellation algorithm based on FPGA and HLS according to claim 5, characterized in that, The auxiliary channel array manifold data is sequentially read out from the DDR memory, and the data is smoothly output through the FIFO buffer. According to the number N of effective sub-channels in the auxiliary channel, the L downlink data corresponding to each sub-channel in the N channels are latched. When the latching of the Nth sub-channel in each downlink data ends, the L downlink data corresponding to the N sub-channels are latched again, so that the N sub-channels output in parallel at the same moment. At the same time, the weight coefficient formation result is output in parallel at the same moment. The number of times of outputting the same group of weight coefficient formation results is equal to the number L of downlink data of a single channel. In the longitudinal direction, the corresponding multiplication and accumulation of the N effective auxiliary sub-channel data of the first downlink data point number and each column data of the weight coefficient formation result are implemented. Similarly, the corresponding multiplication and accumulation of the N effective auxiliary sub-channel data of the Lth downlink data point number and each column data of the weight coefficient formation result are implemented, so as to finally obtain the cancellation factor result of the product of the L downlink data corresponding to the N auxiliary sub-channels and the weight coefficient formation result. At the same moment, the main channel array manifold data in the DDR memory is sequentially read out and smoothly output through the FIFO buffer, and the sidelobe cancellation formation result is obtained by subtracting the cancellation factor result.

7. The implementation method of sidelobe cancellation algorithm based on FPGA and HLS according to claim 6, characterized in that, When the radar repetition frequency period is short, the array manifold data stored in the radar repetition frequency period of the previous stage or multiple stages needs to be read out when the main channel array manifold data and the auxiliary channel array manifold data are stored in the DDR memory, that is, the read-write arbitration processing of the DDR memory is needed. In order to have the real-time processing effect of the radar repetition frequency period, the time consumed by the autocorrelation processing and the cross-correlation processing, the autocorrelation matrix inversion, and the weight coefficient formation needs to be less than the radar repetition frequency period T. When the maximum channel number, the effective channel number, the number of downlink data of a single channel, and the number of sampling points required for weight coefficient generation corresponding to the data rate change, real-time configuration is needed through parameters to complete different forms of sidelobe cancellation processing. When the maximum inversion dimension of the matrix changes, the iteration and upgrade of the IP configuration need to be realized quickly through the HLS.

8. An implementation system of FPGA and HLS based sidelobe cancellation algorithm, suitable for multi-functional and multi-task array radar, characterized in that, The system comprises: The data buffer and rearrangement interception module is configured to receive and buffer the main channel array manifold data and the auxiliary channel array manifold data sent by the digital beam forming unit, generate the required sampling point number according to the configured sub-channel number and weight coefficient, rearrange and intercept the array manifold data based on the required sampling point number, and then send the array manifold data into the buffer interval of each sub-channel; The autocorrelation and cross-correlation processing module is configured to read out the intercepted data of all the sub-channels in the auxiliary channel and the main channel in a time division multiplexing manner, read out the intercepted data of all the sub-channels in the auxiliary channel in parallel circulation according to the time division multiplexing number, perform matrix multiplication on the twice read sub-channel data, and obtain the autocorrelation processing result and the cross-correlation processing result; The autocorrelation matrix inversion module is configured to generate a matrix inversion module based on Cholesky decomposition through an HLS tool, input the autocorrelation processing result and the matrix inversion dimension into the matrix inversion module, and obtain the autocorrelation matrix inversion result, wherein the maximum dimension matrix inversion processing time is less than the radar repetition frequency period; The weight coefficient forming module is configured to latch each element in each row of the autocorrelation matrix inversion result, read out the cross-correlation result when the latching of the last element in each row is completed, multiply each element in each row of the autocorrelation matrix inversion result with each element in each column of the cross-correlation matrix, and obtain the weight coefficient forming result; The sidelobe cancellation forming module is configured to read out the auxiliary channel array manifold data from the buffer interval, perform secondary latching on the elements of each channel according to the number of sub-channels in the auxiliary channel, read out the weight coefficient when the latching of the elements of the last channel is completed, read out the weight coefficient a number of times equal to the total number of sampling points of the array manifold data, perform matrix multiplication of the data of the auxiliary channel under all sampling points and the weight coefficient forming result, finally read out the main channel array manifold data from the buffer interval and perform difference processing to obtain the sidelobe cancellation forming result.

9. An electronic device, comprising: Comprise: At least one processor; And The memory is in communication connection with the at least one processor; wherein The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the implementation method of the sidelobe cancellation algorithm based on FPGA and HLS according to any one of claims 1 to 7.

10. A computer readable storage medium storing a computer program, characterized in that, The computer program is executed by the processor to implement the implementation method of the sidelobe cancellation algorithm based on FPGA and HLS according to any one of claims 1 to 7.

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