Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. According to the display panel, every two adjacent sub-pixel units in the same row of sub-pixel units are connected with the same data line, and every two adjacent sub-pixel units located on the same side of the data line are connected with the same data line, so that the number of required chip on films is reduced; a main sub-pixel and an auxiliary sub-pixel are arranged on the same side of a corresponding transistor region, a first pixel electrode with four display domains is arranged in the main sub-pixel, and a second pixel electrode with four display domains is arranged in the auxiliary sub-pixel, so that each sub-pixel unit has eight display domains, and the visual angle is increased; one electrode of the main transistor is connected with the first pixel electrode, and one electrode of the auxiliary transistor is connected with the second pixel electrode, so that normal display of the sub-pixel unit is realized; therefore, the visual angle of the display panel is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] TFT-LCD (thin film transistor-liquid crystal display) is widely used due to its long service life, mature technology and low price. Liquid crystal display devices include twisted nematic (TN) or super twisted nematic (STN) type, in-plane switching (IPS) type and vertical alignment (VA) type. Among them, the VA type liquid crystal display is widely used due to its high contrast ratio and color accuracy compared with other types of liquid crystal displays. In order to reduce the number of COF (chip on film), the DLS (data line sharing) architecture is used in the liquid crystal display device. Compared with the current 1G1D (one scan line and one data line) architecture, the DLS architecture can reduce half of the COF, but the viewing angle of the DLS architecture is poor, which leads to poor use effect in large size display devices. Some VA type liquid crystal display devices use DLS architecture, but due to the complex wiring of DLS architecture, the liquid crystal display device can only be set to 4 domains, and the viewing angle of the liquid crystal display device is small.

[0003] Therefore, the existing VA type liquid crystal display device using DLS architecture has the technical problem of small viewing angle. SUMMARY

[0004] The embodiments of the present application provide a display panel and a display device to alleviate the technical problem of small viewing angle of the existing VA type liquid crystal display device using DLS architecture.

[0005] In order to achieve the above-mentioned purpose, according to the first aspect of the present application, a display panel is provided, which comprises a plurality of scan lines, a plurality of data lines and a plurality of sub-pixel units arranged in an array. Two scan lines are arranged between two adjacent rows of the sub-pixel units. Two adjacent sub-pixel units in a row of the sub-pixel units are connected to two adjacent scan lines, respectively. Every two adjacent sub-pixel units in the same row of the sub-pixel units are connected to the same data line. Two adjacent sub-pixel units located on the same side of the data line are connected to the same data line.

[0006] The sub-pixel unit comprises a main sub-pixel and a secondary sub-pixel, the main sub-pixel is provided with a first pixel electrode with four display domains, and the secondary sub-pixel is provided with a second pixel electrode with four display domains.

[0007] The display panel further comprises a transistor region, and the main sub-pixel and the secondary sub-pixel are arranged on the same side of the corresponding transistor region.

[0008] The transistor region is provided with a main transistor and a secondary transistor, one electrode of the main transistor is connected with the first pixel electrode, and one electrode of the secondary transistor is connected with the second pixel electrode.

[0009] According to a second aspect of the present application, a display device is provided, which comprises the display panel according to any one of the above embodiments.

[0010] The display panel and the display device are provided in the embodiments of the present application. By connecting every two adjacent sub-pixel units in the same row of sub-pixel units with the same data line, and connecting adjacent two sub-pixel units on the same side of the data line with the same data line, the number of required chip-on-film is reduced. By arranging the main sub-pixel and the secondary sub-pixel on the same side of the corresponding transistor region, and arranging the first pixel electrode with four display domains in the main sub-pixel and the second pixel electrode with four display domains in the secondary sub-pixel, each sub-pixel unit has eight display domains, the viewing angle is improved, and one electrode of the main transistor is connected with the first pixel electrode, one electrode of the secondary transistor is connected with the second pixel electrode, the normal display of the sub-pixel unit is realized, and the viewing angle of the display panel is improved.

[0011] Other features and advantages of the present application will be described in detail in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0013] In order to more completely understand the present application and its advantages, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0014] Figure 1 The pixel arrangement diagram of the display panel provided in the embodiments of the present application.

[0015] Figure 2 The cross-sectional schematic diagram of the display panel provided in the embodiments of the present application.

[0016] Figure 3 A pixel circuit diagram of the display panel provided in the embodiment of the present application.

[0017] Figure 4 A stack diagram of some film layers of the display panel provided in the embodiment of the present application.

[0018] Figure 5 A decomposition diagram of a gate layer of the display panel in the embodiment of the present application. Figure 4

[0019] Figure 6 A decomposition diagram of an active layer of the display panel in the embodiment of the present application. Figure 4

[0020] Figure 7 A decomposition diagram of a source-drain layer of the display panel in the embodiment of the present application. Figure 4

[0021] Figure 8 A decomposition diagram of a pixel electrode layer of the display panel in the embodiment of the present application. Figure 4

[0022] A timing diagram of input signals of different data lines in one display frame of the display panel provided in the embodiment of the present application. Figure 9 DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort belong to the protection scope of the present application.

[0024] The embodiments of the present application aim at the technical problem of small viewing angle of the existing VA type liquid crystal display device applying DLS architecture, and provide a display panel and a display device to alleviate the above technical problem.

[0025] Figure 1 A pixel arrangement diagram of the display panel provided in the embodiment of the present application. Figure 2 A cross-sectional schematic diagram of the display panel provided in the embodiment of the present application. Figure 3 A pixel circuit diagram of the display panel provided in the embodiment of the present application. Figure 4 A stack diagram of some film layers of the display panel provided in the embodiment of the present application. Figure 5 A decomposition diagram of a gate layer of the display panel in the embodiment of the present application. Figure 4 A decomposition diagram of an active layer of the display panel in the embodiment of the present application. Figure 6 A decomposition diagram of a source-drain layer of the display panel in the embodiment of the present application. Figure 4 A decomposition diagram of a pixel electrode layer of the display panel in the embodiment of the present application. Figure 7 A decomposition diagram of a pixel electrode layer of the display panel in the embodiment of the present application.​​​​Figure 4 exploded view of a source-drain layer of the display panel in Figure 8 is Figure 4 exploded view of a pixel electrode layer of the display panel in

[0026] As Figure 1 shown, the display panel 1 includes a plurality of scan lines Scan, a plurality of data lines Data and a plurality of sub-pixel units 11 arranged in an array. Two scan lines Scan are arranged between two adjacent rows of the sub-pixel units 11. One row of the sub-pixel units 11 is connected to two adjacent scan lines Scan. Every two adjacent sub-pixel units 11 in the same row of the sub-pixel units 11 are connected to the same data line Data.

[0027] As Figure 1 shown, it can be seen that the scan lines Scan include a first scan line G1, a second scan line G2, a third scan line G3, a fourth scan line G4, a fifth scan line G5, a sixth scan line G6, a seventh scan line G7, an eighth scan line G8 and a ninth scan line G9. The data lines Data include a first data line D1, a second data line D2, a third data line D3 and a fourth data line D4.

[0028] Specifically, the fourth scan line G4, the fifth scan line G5 and the subsequent scan lines can have the same pattern as the second scan line G2 and the third scan line G3, respectively.

[0029] Specifically, as Figure 1 shown, it can be seen that the second scan line G2 and the third scan line G3 are arranged between the first row of the sub-pixel units 11 and the second row of the sub-pixel units 11. The fourth scan line G4 and the fifth scan line G5 are arranged between the second row of the sub-pixel units 11 and the third row of the sub-pixel units 11. The sixth scan line G6 and the seventh scan line G7 are arranged between the third row of the sub-pixel units 11 and the fourth row of the sub-pixel units 11, i.e., two scan lines Scan are arranged between two adjacent rows of the sub-pixel units 11.

[0030] Specifically, as Figure 1As shown in FIG. 1, it can be seen that the sub-pixel unit 11 includes the first type of sub-pixel 101, the second type of sub-pixel 102 and the third type of sub-pixel 103, and the light-emitting colors of the adjacent sub-pixel units 11 in the same row are different, the light-emitting colors of the adjacent sub-pixel units 11 in the same column are the same, for example, every three adjacent sub-pixel units 11 in the first row of the sub-pixel units 11 are the first type of sub-pixel 101, the second type of sub-pixel 102 and the third type of sub-pixel 103 in turn; the sub-pixel units 11 in the first column are all the first type of sub-pixel 101, the sub-pixel units 11 in the second column are all the second type of sub-pixel 102, and the sub-pixel units 11 in the third column are all the third type of sub-pixel 103, so that the display uniformity can be improved.

[0031] Specifically, as shown in FIG. 1, Figure 1 It can be understood that the sub-pixels of different light-emitting colors constitute a pixel unit, for example, a third type of sub-pixel 103, a second type of sub-pixel 102 and a first type of sub-pixel 101 constitute a pixel unit.

[0032] Specifically, as shown in FIG. 1, Figure 1 As shown in FIG. 1, Figure 1 In FIG. 1, "+" represents that the polarity of the input signal on the data line is positive, "-" represents that the polarity of the input signal on the data line is negative, and Figure 1 As shown in FIG. 1, the polarities of the adjacent data lines are opposite, so that the display effect can be improved and the power consumption can be reduced.

[0033] Specifically, as shown in FIG. 1, Figure 1 As shown in FIG. 1, in the first row of the sub-pixel units 11, the first sub-pixel unit (i.e., the first type of sub-pixel 101) and the second sub-pixel unit (i.e., the second type of sub-pixel 102) are connected to the first scanning line G1 and the second scanning line G2 respectively, the third sub-pixel unit (i.e., the third type of sub-pixel 103) and the fourth sub-pixel unit (i.e., the first type of sub-pixel 101) are connected to the first scanning line G1 and the second scanning line G2 respectively, and the fifth sub-pixel unit (i.e., the second type of sub-pixel 102) and the sixth sub-pixel unit (i.e., the third type of sub-pixel 103) are connected to the first scanning line G1 and the second scanning line G2 respectively, so that two adjacent sub-pixel units 11 in a row are connected to two adjacent scanning lines respectively.

[0034] Specifically, as shown in FIG. 1, Figure 1As shown, it can be seen that in the first row of the sub-pixel units 11, the first sub-pixel unit (i.e. the first type of sub-pixel 101) and the second sub-pixel unit (i.e. the second type of sub-pixel 102) are both connected to the first data line D1, the third sub-pixel unit (i.e. the third type of sub-pixel 103) and the fourth sub-pixel unit (i.e. the first type of sub-pixel 101) are both connected to the second data line D2, and the fifth sub-pixel unit (i.e. the second type of sub-pixel 102) and the sixth sub-pixel unit (i.e. the third type of sub-pixel 103) are both connected to the third data line D3. As can be seen, every two adjacent sub-pixel units in a row of the sub-pixel units 11 are connected to the same data line.

[0035] Specifically, as shown in FIG. 1, Figure 2 The display panel 1 includes a first substrate, a second substrate, and a liquid crystal layer 22 between the first substrate and the second substrate. The first substrate includes a substrate 211, a gate electrode layer 212, a gate insulating layer 213, an active layer 214, a source-drain electrode layer 215, an interlayer insulating layer 216, and a pixel electrode layer 217 arranged in sequence. The second substrate includes a base 231, a color filter layer 232, a black matrix (not shown), and a common electrode layer 233.

[0036] It can be understood that, Figure 2 The color filter layer 232 is arranged on the second substrate side in the display panel 1 shown in FIG. 1, but the embodiments of the present application are not limited thereto. The color filter layer 232 can be arranged on the first substrate side.

[0037] It can be understood that, Figure 2 The source-drain electrode layer 215 directly overlaps the active layer 214 in the source-drain electrode layer 215 in FIG. 1, but the embodiments of the present application are not limited thereto. An insulating layer can be arranged between the source-drain electrode layer 215 and the active layer 214, and the source-drain electrode layer 215 can be connected to the active layer 214 through a via of the insulating layer.

[0038] Specifically, as shown in FIG. 1, Figure 3 The display panel 1 includes a pixel circuit, which includes a main transistor T1, a sub-transistor T2, a sharing transistor T3, a scan line Scan, a data line Data, a first storage capacitor Cst1, and a second storage capacitor Cst2. The gate electrode of the main transistor T1 is electrically connected to the scan line Scan. The first electrode of the main transistor T1 is electrically connected to the data line Data. The second electrode of the main transistor T1 is electrically connected to the first storage capacitor Cst1. The gate electrode of the sub-transistor T2 is electrically connected to the scan line Scan. The first electrode of the sub-transistor T2 is electrically connected to the data line Data. The second electrode of the sub-transistor T2 is electrically connected to the second storage capacitor Cst2 and the first electrode of the sharing transistor T3. The second electrode of the sharing transistor T3 is electrically connected to a common wire Acom.

[0039] Specifically, the display panel 1 further comprises a liquid crystal capacitor Clc, a second electrode of the main transistor T1 is connected with the liquid crystal capacitor Clc, and a second electrode of the auxiliary transistor T2 is connected with the liquid crystal capacitor Clc. The liquid crystal capacitor connected with the second electrode of the main transistor T1 and the second electrode of the auxiliary transistor T2 can be different.

[0040] Specifically, it can be understood that the sub-pixel includes a main sub-pixel and an auxiliary sub-pixel, a pixel electrode of the main sub-pixel is connected with the main transistor, and a pixel electrode of the auxiliary sub-pixel is connected with the auxiliary transistor and the sharing transistor. By setting the sharing transistor T3, the voltage in the auxiliary sub-pixel can be changed, so that the signals in the main sub-pixel and the auxiliary sub-pixel are different, and the color cast is improved.

[0041] Specifically, one plate of the first storage capacitor can be a pixel electrode, and the other plate is a common wire. One plate of the second storage capacitor can be a pixel electrode, and the other plate is a common wire. One plate of the liquid crystal capacitor can be a pixel electrode, and the other plate is part of the common electrode layer. Figure 3 In the figure, it is marked as CFcom.

[0042] As shown in Figures 1 to 8 The display panel provided by the embodiment of the present application comprises a plurality of scanning lines Scan, a plurality of data lines Data, and a plurality of sub-pixel units 11 arranged in an array. Two scanning lines Scan are arranged between two adjacent rows of the sub-pixel units 11. Two adjacent sub-pixel units 11 in a row are connected with two adjacent scanning lines Scan, respectively. Every two adjacent sub-pixel units 11 in the same row are connected with the same data line Data. Two adjacent sub-pixel units 11 located on the same side of the data line Data are connected with the same data line Data. The sub-pixel unit 11 comprises a main sub-pixel 311 and an auxiliary sub-pixel 312. The main sub-pixel 311 is provided with a first pixel electrode 41 having four display domains 401. The auxiliary sub-pixel 312 is provided with a second pixel electrode 42 having four display domains 401. The display panel 1 further comprises a transistor region 32. The main sub-pixel 311 and the auxiliary sub-pixel 312 are arranged on the same side of the corresponding transistor region 32.

[0043] The transistor region 32 is provided with a main transistor T1 and an auxiliary transistor T2. One electrode of the main transistor T1 is connected with the first pixel electrode 41. One electrode of the auxiliary transistor T2 is connected with the second pixel electrode 42.

[0044] This application provides a display panel; the display panel reduces the number of flip-chip films required by connecting every two adjacent sub-pixel units 11 in the same row to the same data line Data, and connecting two adjacent sub-pixel units 11 on the same side of the data line Data; by setting the main sub-pixel 311 and the sub-pixel 312 on the same side of the corresponding transistor region 32, and setting a first pixel electrode 41 with four display domains in the main sub-pixel 311, and setting a second pixel electrode 42 with four display domains in the sub-pixel 312, so that each sub-pixel unit 11 has eight display domains, thereby improving the viewing angle; and by connecting one electrode of the main transistor T1 to the first pixel electrode 41, and one electrode of the sub-transistor T2 to the second pixel electrode 42, normal display of the sub-pixel units is achieved; thereby improving the viewing angle of the display panel.

[0045] In some embodiments, such as Figure 1 As shown, in the sub-pixel units 11 in the same row, the two scan lines Scan connected to two sub-pixel units 11 that are connected to the same data line Data are located on the upper and lower sides of the sub-pixel unit. By making the two scan lines Scan connected to two sub-pixel units 11 that are connected to the same data line Data located on the upper and lower sides of the sub-pixel unit 11, wiring intersections are avoided, wiring complexity is reduced, and the yield of the display panel is improved.

[0046] In some embodiments, such as Figures 1 to 8 As shown, the first pixel electrode 41 includes a first main electrode 411 disposed along the first direction X and a second main electrode 412 disposed along the second direction Y. The first main electrode 411 and the second main electrode 412 are intersected and divide the main sub-pixel 311 into four display domains 401. The second pixel electrode 42 includes a third main electrode 421 disposed along the first direction X and a fourth main electrode 422 disposed along the second direction Y. The third main electrode 421 and the fourth main electrode 422 are intersected and divide the sub-pixel 312 into four display domains 401.

[0047] In one of the sub-pixel units 11, an electrode of one of the main transistor T1 and the sub-transistor T2 passes through the area where the second main electrode 412 and the fourth main electrode 422 are located and connects to the corresponding pixel electrode; the angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees. By allowing an electrode of one of the main transistor T1 and the sub-transistor T2 to pass through the area where the second main electrode 412 and the fourth main electrode 422 are located and connect to the corresponding pixel electrode, normal display of the sub-pixel unit is achieved, thereby improving the viewing angle of the display panel.

[0048] Specifically, the pixel electrode layer 217 includes pixel electrodes, which include the first pixel electrode 41 disposed in the main sub-pixel 311 and the second pixel electrode 42 disposed in the auxiliary sub-pixel 312.

[0049] Specifically, it can be understood that the main sub-pixel 311 and the auxiliary sub-pixel 312 disposed on the same side of the corresponding transistor region 32 means that the main sub-pixel 311 and the auxiliary sub-pixel 312 of the same sub-pixel unit 11 are connected with the transistors in the same transistor region 32, and the transistor region 32 corresponding to the main sub-pixel 311 and the auxiliary sub-pixel 312 means the transistor region 32 where the transistors connected with the main sub-pixel 311 and the auxiliary sub-pixel 312 are located. Accordingly, the main sub-pixel 311 and the auxiliary sub-pixel 312 disposed on the same side of the corresponding transistor region 32 means that the main sub-pixel 311 and the auxiliary sub-pixel 312 are both disposed on the same side of the transistor region 32 where the transistors connected with the main sub-pixel 311 and the auxiliary sub-pixel 312 are located. For example, in Figure 4 , the main sub-pixel 311 and the auxiliary sub-pixel 312 in the first sub-pixel unit 11 are both located below the transistor region 32 where the transistors connected with the main sub-pixel 311 and the auxiliary sub-pixel 312 are located, and the main sub-pixel 311 and the auxiliary sub-pixel 312 in the second sub-pixel unit 11 are both located above the transistor region 32 where the transistors connected with the main sub-pixel 311 and the auxiliary sub-pixel 312 are located.

[0050] Specifically, one electrode of one of the main transistor T1 and the auxiliary transistor T2 is connected with the corresponding pixel electrode through the setting area of the second main electrode 412 and the fourth main electrode 422, which means that one electrode of the main transistor T1 is connected with the first pixel electrode 41 through the setting area of the second main electrode 412 and the fourth main electrode 422, or one electrode of the auxiliary transistor T2 is connected with the second pixel electrode 42 through the setting area of the second main electrode 412 and the fourth main electrode 422.

[0051] Specifically, Figure 4 In order to show the structure design of each film layer, the specific design of the first pixel electrode and the second pixel electrode in the pixel electrode layer 217 is not shown, and the specific design can be referred to Figure 8 .

[0052] In some embodiments, as shown in Figure 1 , the adjacent two sub-pixel units 11 in the same column are respectively connected with the adjacent two data lines Data. By making the adjacent two sub-pixel units 11 in the same column respectively connected with the adjacent two data lines Data, the polarity of the adjacent sub-pixel units is different, so that the dot inversion can be realized in the column direction, and the color cast is improved.

[0053] Specifically, as shown in Figure 1As shown in FIG. 1, the horizontal axis is time t, and the vertical axis is voltage V. As shown in FIG. 2, the display panel 1 has one display frame H. As shown in FIG. 3, the first data line D1 continuously outputs a signal of positive polarity, and the second data line D2 continuously outputs a signal of negative polarity. As shown in FIG. 4, the input signal of the sub-pixel unit 11 connected to the first data line D1 is of positive polarity, and the input signal of the sub-pixel unit 11 connected to the second data line D2 is of negative polarity. Thus, the signal of the sub-pixel unit in the same column is reversed, the signal of the sub-pixel unit in the same row is reversed, the display effect is improved, and power consumption is reduced.

[0054] In some embodiments, as shown in FIG. 1, in one display frame H of the display panel, the polarities of the input signals of the adjacent two data lines Data are opposite, the polarities of the input signals of the two sub-pixel units 11 located on the same side of the data line Data in the same row of sub-pixel units 11 are the same, the polarities of the input signals of the two sub-pixel units located on the two sides of the same data line are opposite, and the polarities of the input signals of the adjacent two sub-pixel units 11 in the same column are opposite. By making the polarities of the input signals of the adjacent two data lines Data opposite, the polarities of the input signals of the sub-pixel units in different columns in the same row are different, and the polarities of the input signals of the adjacent sub-pixel units in the same column are different. Thus, the display effect can be improved, and power consumption can be reduced. Figure 1 In some embodiments, as shown in FIG. 1, in one display frame H of the display panel, the polarities of the input signals of the adjacent two data lines Data are opposite, the polarities of the input signals of the two sub-pixel units 11 located on the same side of the data line Data in the same row of sub-pixel units 11 are the same, the polarities of the input signals of the two sub-pixel units located on the two sides of the same data line are opposite, and the polarities of the input signals of the adjacent two sub-pixel units 11 in the same column are opposite. By making the polarities of the input signals of the adjacent two data lines Data opposite, the polarities of the input signals of the sub-pixel units in different columns in the same row are different, and the polarities of the input signals of the adjacent sub-pixel units in the same column are different. Thus, the display effect can be improved, and power consumption can be reduced.

[0055] Figure 1 In some embodiments, as shown in FIG. 1, in one display frame H of the display panel, the polarities of the input signals of the adjacent two data lines Data are opposite, the polarities of the input signals of the two sub-pixel units 11 located on the same side of the data line Data in the same row of sub-pixel units 11 are the same, the polarities of the input signals of the two sub-pixel units located on the two sides of the same data line are opposite, and the polarities of the input signals of the adjacent two sub-pixel units 11 in the same column are opposite. By making the polarities of the input signals of the adjacent two data lines Data opposite, the polarities of the input signals of the sub-pixel units in different columns in the same row are different, and the polarities of the input signals of the adjacent sub-pixel units in the same column are different. Thus, the display effect can be improved, and power consumption can be reduced. Figure 9 Figure 9 In some embodiments, as shown in FIG. 1, in one display frame H of the display panel, the polarities of the input signals of the adjacent two data lines Data are opposite, the polarities of the input signals of the two sub-pixel units 11 located on the same side of the data line Data in the same row of sub-pixel units 11 are the same, the polarities of the input signals of the two sub-pixel units located on the two sides of the same data line are opposite, and the polarities of the input signals of the adjacent two sub-pixel units 11 in the same column are opposite. By making the polarities of the input signals of the adjacent two data lines Data opposite, the polarities of the input signals of the sub-pixel units in different columns in the same row are different, and the polarities of the input signals of the adjacent sub-pixel units in the same column are different. Thus, the display effect can be improved, and power consumption can be reduced. Figure 9 Figure 9 In some embodiments, as shown in FIG. 1, in one display frame H of the display panel, the polarities of the input signals of the adjacent two data lines Data are opposite, the polarities of the input signals of the two sub-pixel units 11 located on the same side of the data line Data in the same row of sub-pixel units 11 are the same, the polarities of the input signals of the two sub-pixel units located on the two sides of the same data line are opposite, and the polarities of the input signals of the adjacent two sub-pixel units 11 in the same column are opposite. By making the polarities of the input signals of the adjacent two data lines Data opposite, the polarities of the input signals of the sub-pixel units in different columns in the same row are different, and the polarities of the input signals of the adjacent sub-pixel units in the same column are different. Thus, the display effect can be improved, and power consumption can be reduced.

[0056] In some embodiments, as shown in FIG. 1, in one display frame H of the display panel, the polarities of the input signals of the adjacent two data lines Data are opposite, the polarities of the input signals of the two sub-pixel units 11 located on the same side of the data line Data in the same row of sub-pixel units 11 are the same, the polarities of the input signals of the two sub-pixel units located on the two sides of the same data line are opposite, and the polarities of the input signals of the adjacent two sub-pixel units 11 in the same column are opposite. By making the polarities of the input signals of the adjacent two data lines Data opposite, the polarities of the input signals of the sub-pixel units in different columns in the same row are different, and the polarities of the input signals of the adjacent sub-pixel units in the same column are different. Thus, the display effect can be improved, and power consumption can be reduced. Figure 1 In some embodiments, as shown in FIG. 1, in one display frame H of the display panel, the polarities of the input signals of the adjacent two data lines Data are opposite, the polarities of the input signals of the two sub-pixel units 11 located on the same side of the data line Data in the same row of sub-pixel units 11 are the same, the polarities of the input signals of the two sub-pixel units located on the two sides of the same data line are opposite, and the polarities of the input signals of the adjacent two sub-pixel units 11 in the same column are opposite. By making the polarities of the input signals of the adjacent two data lines Data opposite, the polarities of the input signals of the sub-pixel units in different columns in the same row are different, and the polarities of the input signals of the adjacent sub-pixel units in the same column are different. Thus, the display effect can be improved, and power consumption can be reduced.

[0057] Figure 1 ​​​​As shown, in the first row of sub-pixel units 11, the polarity of the input signals of the first sub-pixel unit 11 (i.e., the first type of sub-pixel 101) and the second sub-pixel unit 11 (i.e., the second type of sub-pixel 102) is positive, the polarity of the input signals of the third sub-pixel unit 11 (i.e., the third type of sub-pixel 103) and the fourth sub-pixel unit 11 (i.e., the first type of sub-pixel 101) is negative, and the polarity of the input signals of the fifth sub-pixel unit 11 (i.e., the second type of sub-pixel 102) and the sixth sub-pixel unit 11 (i.e., the third type of sub-pixel 103) is positive.

[0058] Specifically, such as Figure 1 As shown, in the first column of sub-pixel units 11, the polarity of the input signal of the first sub-pixel unit 11 is positive, the polarity of the input signal of the second sub-pixel unit 11 is negative, the polarity of the input signal of the third sub-pixel unit 11 is positive, and the polarity of the input signal of the fourth sub-pixel unit 11 is negative.

[0059] In some embodiments, such as Figures 4 to 8 As shown, two transistor regions 32 corresponding to two adjacent sub-pixel units 11 in the same row are disposed on both sides of the sub-pixel units 11 in the same row. In any sub-pixel unit 11, the main sub-pixel 311 in the sub-pixel unit 11 is disposed between the sub-sub-pixel 312 and the corresponding transistor region 32. One electrode of the sub-transistor T2 passes through the disposed area of ​​the second main electrode 412 and the fourth main electrode 422 and connects to the second pixel electrode 42. By disposing the main sub-pixel 311 between the sub-sub-pixel 312 and the corresponding transistor region 32, and by disposing the sub-transistor T2 through the disposed area of ​​the second main electrode 412 and the fourth main electrode 422 and connecting to the second pixel electrode 42, a lateral capacitance is formed between the electrode of the sub-transistor T2 and the scan line. This reduces the capacitance difference between the main sub-pixels in different sub-pixel units, thereby improving the display effect.

[0060] Specifically, it can be understood that the electrodes passing through the arrangement region of the second trunk electrode and the fourth trunk electrode will form a lateral capacitance with the scan lines, which will increase the capacitance between the pixel electrode and the scan lines. If the main sub-pixel of each sub-pixel unit is arranged in the same column, the electrodes of the main transistors connected to the main sub-pixels in some sub-pixel units need to pass through the arrangement region of the second trunk electrode and the fourth trunk electrode, that is, the electrodes of the main transistors connected to the main sub-pixels in some sub-pixel units will form a lateral capacitance with other scan lines, and the electrodes of the main transistors connected to the main sub-pixels in some sub-pixel units do not need to pass through the arrangement region of the second trunk electrode and the fourth trunk electrode, resulting in a large difference in parasitic capacitance in the main sub-pixels in different sub-pixel units, causing a large difference in brightness of the main sub-pixels in different sub-pixel units, and resulting in poor display effect in low gray scale display. The embodiment of the present application arranges the main sub-pixel 311 between the auxiliary sub-pixel 312 and the corresponding transistor region 32, so that one electrode of the auxiliary transistor T2 is connected to the second pixel electrode 42 by passing through the arrangement region of the second trunk electrode 412 and the fourth trunk electrode 422, so that the electrodes of each main transistor will not form parasitic capacitance with other scan lines, improving the uniformity of the parasitic capacitance in each main sub-pixel and improving the display effect.

[0061] Specifically, it can be understood that the second electrode of each transistor will form a parasitic capacitance with the scan line connected to this transistor. Here, the electrodes passing through the arrangement region of the second trunk electrode and the fourth trunk electrode will form a lateral capacitance with the scan lines, which means that the second electrode of this transistor will form a parasitic capacitance with other scan lines in addition to the scan line connected to this transistor, which is equivalent to forming two parasitic capacitances. For example, in the first sub-pixel unit, the second electrode of the auxiliary transistor T2 can form a parasitic capacitance with the scan line (i.e., the first scan line G1) connected to the auxiliary transistor T2, and the second electrode of the auxiliary transistor T2 will also form a lateral capacitance with the scan line (i.e., the second scan line G2) not connected to the auxiliary transistor T2, while the second electrode of the main transistor T1 is far away from the second scan line G2 not connected to the main transistor T1, and will not form an additional lateral capacitance. Such design exists in each sub-pixel unit, so that the parasitic capacitance between the second electrode of the main transistor connected to the main sub-pixel and the scan line (or the parasitic capacitance between the pixel electrode and the scan line) is similar or even the same, thereby improving the display effect. Figure 4

[0062] Specifically, it can be understood that in low gray scale display, the main sub-pixel has a greater impact on brightness, and therefore, improving the uniformity of the parasitic capacitance between the second electrode of the main transistor connected to the main sub-pixel and the scan line can improve the display effect.

[0063] ​Specifically, two transistor regions 32 corresponding to two adjacent sub-pixel units 11 in the same row can be arranged on both sides of the sub-pixel units 11 in the same row. In one sub-pixel unit 11, the main sub-pixel 311 in the sub-pixel unit 11 is arranged between the auxiliary sub-pixel 312 and the corresponding transistor region 32. One electrode of the auxiliary transistor T2 is connected with the second pixel electrode 42 through the arrangement region of the second stem electrode 412 and the fourth stem electrode 422. In another sub-pixel unit 11, the auxiliary sub-pixel 312 in the sub-pixel unit 11 is arranged between the main sub-pixel 311 and the corresponding transistor region 32. One electrode of the main transistor T1 is connected with the first pixel electrode 41 through the arrangement region of the second stem electrode 412 and the fourth stem electrode 422.

[0064] In some embodiments, as shown in Figures 2 to 4 , Figure 7 The transistor region 32 is also provided with a sharing transistor T3. The display panel 1 includes a substrate 211 and a source-drain layer 215 arranged on one side of the substrate 211. The source-drain layer 215 includes the data line Data, the first electrode T1S of the main transistor T1, the second electrode T1D of the main transistor T1, the first electrode T2S of the auxiliary transistor T2, the second electrode T2D of the auxiliary transistor T2, the first electrode T3S of the sharing transistor T3, the second electrode T3D of the sharing transistor T3, and a connection line SL.

[0065] The data line Data is connected with the first electrode T1S of the main transistor T1 and the first electrode T2S of the auxiliary transistor T2 through the connection line SL. The first electrode T3S of the sharing transistor T3 is connected with the second electrode T2D of the auxiliary transistor T2. The second electrode T1D of the main transistor T1 is connected with the first pixel electrode 41.

[0066] In some embodiments, as shown in Figure 4 , Figure 7As shown, in the two adjacent connection lines SL connected with the same data line Data and the two adjacent sub-pixel units 11, in the two adjacent connection lines SL, one connection line SL is arranged at one side of the sub-pixel unit 11 close to the data line Data, and the other connection line SL extends from the side of the sub-pixel unit 11 close to the data line Data to the side of the sub-pixel unit 11 away from the data line Data, and the length of the connection line SL connected with the sub-pixel unit 11 away from the data line Data is greater than the length of the connection line SL connected with the sub-pixel unit 11 close to the data line Data, and in the second direction Y, the connection line SL connected with the sub-pixel unit 11 away from the data line Data is located between the two adjacent scan lines Scan.

[0067] Specifically, as shown in Figure 4 , Figure 7 can be seen that, in the two connection lines SL connected with the first data line D1 and the two sub-pixel units 11, the connection line SL located at the upper side of the sub-pixel unit 11 only extends to the upper side of the sub-pixel unit 11 close to the first data line D1, and the connection line SL located at the lower side of the sub-pixel unit 11 extends from the lower side of the sub-pixel unit 11 close to the first data line D1 to the lower side of the sub-pixel unit 11 away from the first data line D1, so that the length of the connection line SL connected with the sub-pixel unit 11 away from the first data line D1 is greater than the length of the connection line SL connected with the sub-pixel unit 11 close to the first data line D1, and it can be seen that the connection line SL connected with the sub-pixel unit 11 away from the first data line D1 is located between the second scan line G2 and the third scan line G3.

[0068] Specifically, as shown in Figure 7 , it can be understood that the data line Data, the connection line SL, the first electrode T1S of the main transistor T1, and the first electrode T2S of the auxiliary transistor T2 are actually different parts of the same structure, and under the premise of not considering the voltage drop, each part of the structure transmits the same signal. Similarly, multiple parts in other structures also transmit the same signal.

[0069] Specifically, the second electrode of the auxiliary transistor T2 is connected with the second pixel electrode 42.

[0070] In some embodiments, as shown in Figure 2 , Figure 4 , Figure 6As shown, the display panel 1 further comprises an active layer 214, the active layer 214 comprises an active pattern T1A of a main transistor T1, an active pattern T2A of a sub-transistor T2, an active pattern T3A of a sharing transistor T3, a data pattern PL1, a connection pattern PL2, a first drain pattern PL3, a second drain pattern PL4, the active pattern T1A of the main transistor T1, the active pattern T2A of the sub-transistor T2 and the active pattern T3A of the sharing transistor T3 are connected, the data pattern PL1 is connected with the active pattern T1A of the main transistor T1 through the connection pattern PL2, the first drain pattern PL3 is connected with the active pattern T1A of the main transistor T1, and the second drain pattern PL4 is connected with the active pattern T2A of the sub-transistor T2.

[0071] The data pattern PL1, the connection pattern PL2, the first drain pattern PL3 and the second drain pattern PL4 are respectively arranged corresponding to the data line Data, the connection line SL, the second electrode T1D of the main transistor T1 and the second electrode T2D of the sub-transistor T2.

[0072] Specifically, as shown in Figure 4 , Figure 6 , Figure 7 It can be seen that the data pattern PL1, the connection pattern PL2, the first drain pattern PL3 and the second drain pattern PL4 are respectively arranged corresponding to the data line Data, the connection line SL, the second electrode T1D of the main transistor T1 and the second electrode T2D of the sub-transistor T2, and the active pattern T1A of the main transistor T1, the active pattern T2A of the sub-transistor T2 and the active pattern T3A of the sharing transistor T3 are respectively arranged corresponding to the first electrode T1S of the main transistor T1, the first electrode T2S of the sub-transistor T2, the first electrode T3S of the sharing transistor T3 and the second electrode T3D of the sharing transistor T3, so that when the active layer and the source-drain electrode layer are formed, the same mask plate can be used to form the active layer and the source-drain electrode layer, and the number of required mask plates is reduced.

[0073] In some embodiments, as shown in Figure 2 , Figure 4 , Figure 6 , Figure 7As shown, the projection of the data pattern PL1 on the substrate 211 overlaps with the projection of the data line Data on the substrate 211, the projection of the connection pattern PL2 on the substrate 211 overlaps with the projection of the connection line SL on the substrate 211, the projection of the first drain pattern PL3 on the substrate 211 overlaps with the projection of the second electrode T1D of the main transistor T1 on the substrate 211, and the projection of the second drain pattern PL4 on the substrate 211 overlaps with the projection of the second electrode T2D of the auxiliary transistor T2 on the substrate 211; so that when the active layer and the source-drain layer are formed, the active layer and the source-drain layer can be formed by using the same mask plate, thereby reducing the number of mask plates required.

[0074] Specifically, as shown in Figure 6 、 Figure 7 , in the active layer 214 and the source-drain layer 215, in addition to the active pattern of each transistor being an integral part, the first electrode and the second electrode of each transistor are separated, for other regions, the projection of the active layer 214 on the substrate can overlap with the projection of the source-drain layer 215 on the substrate, so that the active layer 214 and the source-drain layer 215 can be formed by using the same mask plate, and for each electrode of each transistor, the half-transmission process can be used to form.

[0075] In some embodiments, as shown in Figure 2 、 Figure 4 、 Figure 5 , the display panel 1 further includes a gate layer 212 disposed between the substrate 211 and the active layer 214, the gate layer 212 includes a scan line Scan, a common wire Acom, a gate T1G of the main transistor T1, a gate T2G of the auxiliary transistor T2, a gate T3G of the sharing transistor T3, and a light shielding pattern GL, the scan line Scan is connected with the gate T1G of the main transistor T1, the gate T2G of the auxiliary transistor T2, and the gate T3G of the sharing transistor T3, the gate T1G of the main transistor T1, the gate T2G of the auxiliary transistor T2, and the gate T3G of the sharing transistor T3 are respectively arranged corresponding to the active pattern T1A of the main transistor T1, the active pattern T2A of the auxiliary transistor T2, and the active pattern T3A of the sharing transistor T3, and the common wire Acom is arranged around the sub-pixel unit 11.

[0076] In this configuration, the second electrode T3D of the sharing transistor T3 is connected to the common trace Acom, and the light-shielding pattern GL corresponds to the second leak pattern PL4, while the light-shielding pattern GL is insulated from the common trace Acom. By connecting the second electrode T3D of the sharing transistor T3 to the common trace Acom, there is no need to set up a sharing trace. Furthermore, the light-shielding pattern GL corresponds to the second leak pattern PL4 and is insulated from the common trace Acom, thus blocking external light and preventing display abnormalities caused by light exposure to the active layer, thereby improving the display effect.

[0077] Specifically, such as Figure 4 As shown, it can be seen that since a connection line SL extends across one sub-pixel unit to another, it is difficult to set up a shared trace. Therefore, the second electrode of the shared transistor can be connected to the common trace.

[0078] Specifically, since the second drain pattern PL4 is set in the active layer and corresponds to the second electrode T2D of the sub-transistor T2, and the second drain pattern PL4 is connected to the active pattern of the transistor, when light shines on the active layer, the electron accumulation position in the active layer will be different in the positive and negative frames of the display panel, resulting in different capacitances of the positive and negative frames. This leads to different coupling of the pixel electrodes under the positive and negative frames, resulting in brightness differences. In this embodiment, a light-shielding pattern GL is set so that it corresponds to the second drain pattern PL4, and the light-shielding pattern GL is insulated from the common trace Acom, so that the second drain pattern PL4 is not exposed to light, avoiding the "watermark" abnormality, reducing parasitic capacitance, and improving the display effect.

[0079] Specifically, such as Figure 5 As shown, the scan line Scan, the gate T1G of the main transistor T1, the gate T2G of the secondary transistor T2, and the gate T3G of the sharing transistor T3 are actually multiple parts of the same structure. In other words, the parts of the scan line Scan that correspond to the active patterns T1A of the main transistor T1, T2A of the secondary transistor T2, and T3A of the sharing transistor T3 serve as the gate T1G of the main transistor T1, the gate T2G of the secondary transistor T2, and the gate T3G of the sharing transistor T3, respectively.

[0080] Specifically, such as Figure 5 As shown, the width of the gate T1G of the main transistor T1 is equal to the width of the gate T2G of the secondary transistor T2. The width of the gate T1G of the main transistor T1 can be greater than or equal to the width of the gate T3G of the sharing transistor T3. The width of the gate T3G of the sharing transistor T3 is greater than the width of the scan line.

[0081] Specifically, such as Figure 5As shown, the width of the portion of the common line Acom corresponding to the shared line can be greater than the width of the portion of the common line Acom located between the data line and the pixel electrode.

[0082] In some embodiments, as shown in Figure 5 、 Figure 6 As shown, the width L1 of the light shielding pattern GL is greater than the width L2 of the second drain pattern PL4. By making the width L1 of the light shielding pattern GL greater than the width L2 of the second drain pattern PL4, the light shielding effect of the light shielding pattern is improved, and display abnormalities caused by light irradiation to the second drain pattern PL4 are avoided.

[0083] In some embodiments, as shown in Figure 2 、 Figure 4 、 Figure 8 As shown, the display panel 1 further includes a pixel electrode layer 217, the pixel electrode layer 217 including the first pixel electrode 41 and the second pixel electrode 42, the first pixel electrode 41 further including a first branch electrode 431 and a first connecting electrode 413, the second pixel electrode 42 further including a second branch electrode 432 and a second connecting electrode 423, the orientations of the first branch electrodes 431 in the four display domains of the main sub-pixel unit 311 being different, the orientations of the second branch electrodes 432 in the four display domains of the auxiliary sub-pixel unit 312 being different, the first connecting electrode 413 connecting the first branch electrode 431 and the second electrode T1D of the main transistor T1, and the second connecting electrode 423 connecting the second branch electrode 432 and the second electrode T2D of the auxiliary transistor T2.

[0084] Specifically, as shown in Figure 8 As shown, it can be seen that the first trunk electrode 411 and the second trunk electrode 412 divide the first pixel electrode 41 into four regions, the orientations of the first branch electrodes 431 in the four regions being different, so that the angles of the slits are different, thereby forming four display domains; the third trunk electrode 421 and the fourth trunk electrode 422 divide the second pixel electrode 42 into four regions, the orientations of the second branch electrodes 432 in the four regions being different, so that the angles of the slits are different, thereby forming four display domains.

[0085] Specifically, it can be understood that Figure 8In order to illustrate the positions of the first stem electrode 411, the second stem electrode 412 and the first branch electrode 431, the third stem electrode 421, the fourth stem electrode 422 and the second branch electrode 432, a boundary line is shown between the first stem electrode 411, the second stem electrode 412 and the first branch electrode 431, but in fact, the first stem electrode 411, the second stem electrode 412 and the first branch electrode 431 are different parts of the same structure, and there is no boundary line; similarly, the third stem electrode 421, the fourth stem electrode 422 and the second branch electrode 432 have no boundary line in fact.

[0086] In some embodiments, as shown in FIG. 1, the plurality of sub-pixel units 11 include first sub-pixels 101, second sub-pixels 102 and third sub-pixels 103, the light-emitting colors of the first sub-pixels 101, the second sub-pixels 102 and the third sub-pixels 103 are different, the light-emitting colors of adjacent sub-pixel units 11 in the same row are different, and the light-emitting colors of adjacent sub-pixel units 11 in the same column are the same; thereby improving display uniformity. Figure 1

[0087] In some embodiments, as shown in FIG. 1, the area of the main sub-pixel 311 is smaller than the area of the auxiliary sub-pixel 312. Figures 4 to 8

[0088] Specifically, it can be understood that the above-mentioned embodiments have been described in detail from the aspects of film layer design, circuit design, film layer structure, etc. of the display panel, and it can be understood that the embodiments can be combined when there is no conflict between the embodiments, for example, the sub-pixel unit includes first sub-pixels, second sub-pixels and third sub-pixels, the light-emitting colors of the first sub-pixels, the second sub-pixels and the third sub-pixels are different, the light-emitting colors of adjacent sub-pixel units in the same row are different, the light-emitting colors of adjacent sub-pixel units in the same column are the same, the area of the main sub-pixel 311 is smaller than the area of the auxiliary sub-pixel 312.

[0089] Meanwhile, the embodiments of the present application provide a display device, which includes the display panel according to any one of the above-mentioned embodiments.

[0090] Specifically, the display device can further include a power supply, a time sequence control board and the like.

[0091] ​​In the description of the application, the terms "first", "second", "third" and the like are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implying the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0092] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0093] The embodiments, implementation manners and related technical features of the present application can be combined or replaced with each other without conflict.

[0094] The above is only the preferred embodiment of the present application, and does not limit the present application in any form. Any simple modification, equivalent change and modification made to the above embodiment in accordance with the technical essence of the present application without departing from the technical solution content of the present application still falls within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that, It includes multiple scan lines, multiple data lines, and multiple sub-pixel units arranged in an array. Two scan lines are provided between two adjacent rows of sub-pixel units. Two adjacent sub-pixel units in a row are respectively connected to the two adjacent scan lines. Every two adjacent sub-pixel units in the same row are connected to the same data line. Two adjacent sub-pixel units located on the same side of the data line are connected to the same data line. The sub-pixel unit includes a main sub-pixel and a sub-pixel. The main sub-pixel is provided with a first pixel electrode having four display domains, and the sub-pixel is provided with a second pixel electrode having four display domains. The display panel also includes a transistor area, and the main sub-pixel and the sub-pixel are disposed on the same side of the corresponding transistor area; The transistor region includes a main transistor and a sub-transistor. One electrode of the main transistor is connected to the first pixel electrode, and one electrode of the sub-transistor is connected to the second pixel electrode.

2. The display panel according to claim 1, characterized in that, In the same row of sub-pixel units, the two scan lines connected to two sub-pixel units that are connected to the same data line are located on the upper and lower sides of the sub-pixel unit.

3. The display panel according to claim 1, characterized in that, The first pixel electrode includes a first main electrode arranged along a first direction and a second main electrode arranged along a second direction. The first main electrode and the second main electrode are intersected and divide the main sub-pixel into four display domains. The second pixel electrode includes a third main electrode arranged along the first direction and a fourth main electrode arranged along the second direction. The third main electrode and the fourth main electrode are intersected and divide the sub-pixel into four display domains. In one of the sub-pixel units, an electrode of one of the main transistors and the sub-transistors passes through the area where the second main electrode and the fourth main electrode are disposed and is connected to the corresponding pixel electrode; the angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

4. The display panel according to claim 3, characterized in that, Two adjacent sub-pixel units located in the same column are respectively connected to two adjacent data lines.

5. The display panel according to claim 4, characterized in that, Within a display frame of the display panel, the polarities of the input signals of two adjacent data lines are opposite, and in the same row of sub-pixel units, the polarities of the input signals of two sub-pixel units located on the same side of the data lines are the same, the polarities of the input signals of two sub-pixel units located on opposite sides of the same data line are opposite, and the polarities of the input signals of two adjacent sub-pixel units located in the same column are opposite.

6. The display panel according to claim 4, characterized in that, Two transistor regions corresponding to two adjacent sub-pixel units in the same row are disposed on both sides of the sub-pixel units in the same row. In any sub-pixel unit, the main sub-pixel in the sub-pixel unit is disposed between the sub-sub-pixel and the corresponding transistor region. One electrode of the sub-transistor passes through the disposed area of ​​the second main electrode and the fourth main electrode and is connected to the second pixel electrode.

7. The display panel according to claim 6, characterized in that, The transistor region also includes a sharing transistor, and the display panel includes: Substrate; A source-drain layer is disposed on one side of the substrate. The source-drain layer includes the data line, a first electrode of the main transistor, a second electrode of the main transistor, a first electrode of the sub-transistor, a second electrode of the sub-transistor, a first electrode of the sharing transistor, a second electrode of the sharing transistor, and a connecting line. The data line is connected to the first electrode of the main transistor and the first electrode of the sub-transistor via the connecting line. The first electrode of the sharing transistor is connected to the second electrode of the sub-transistor, and the second electrode of the main transistor is connected to the first pixel electrode.

8. The display panel according to claim 7, characterized in that, In two adjacent connecting lines and two adjacent sub-pixel units that connect the same data line, one connecting line is located on the side of the sub-pixel unit close to the data line, and the other connecting line extends from the side of the sub-pixel unit close to the data line to the side of the sub-pixel unit away from the data line. The length of the connecting line connecting the sub-pixel unit away from the data line is greater than the length of the connecting line connecting the sub-pixel unit close to the data line. In a second direction, the connecting line connecting the sub-pixel unit away from the data line is located between two adjacent scan lines.

9. The display panel according to claim 7, characterized in that, The display panel further includes an active layer, which includes an active pattern of a main transistor, an active pattern of a secondary transistor, an active pattern of a sharing transistor, a data pattern, a connection pattern, a first drain pattern, and a second drain pattern. The active patterns of the main transistor, the secondary transistor, and the sharing transistor are connected. The data pattern is connected to the active pattern of the main transistor through the connection pattern. The first drain pattern is connected to the active pattern of the main transistor, and the second drain pattern is connected to the active pattern of the secondary transistor. The data pattern, the connection pattern, the first leak pattern, and the second leak pattern are respectively configured to correspond to the data line, the connection line, the second electrode of the main transistor, and the second electrode of the sub-transistor.

10. The display panel according to claim 9, characterized in that, The projections of the data pattern, the connection pattern, the first leak pattern, and the second leak pattern onto the substrate overlap with the projections of the data line, the connection line, the second electrode of the main transistor, and the second electrode of the sub-transistor onto the substrate, respectively.

11. The display panel according to claim 9, characterized in that, The display panel further includes a gate layer disposed between the substrate and the active layer. The gate layer includes scan lines, common traces, the gate of a main transistor, the gate of a sub-transistor, the gate of a sharing transistor, and a light-shielding pattern. The scan lines are connected to the gates of the main transistor, the sub-transistor, and the sharing transistor. The gates of the main transistor, the sub-transistor, and the sharing transistor are respectively configured to correspond to the active patterns of the main transistor, the sub-transistor, and the sharing transistor. The common traces are arranged around the sub-pixel units. The second electrode of the sharing transistor is connected to the common trace, the light-shielding pattern is correspondingly set to the second leakage pattern, and the light-shielding pattern is insulated from the common trace.

12. The display panel according to claim 11, characterized in that, The width of the light-blocking pattern is greater than the width of the second leak pattern.

13. The display panel according to claim 11, characterized in that, The display panel further includes a pixel electrode layer, which includes a first pixel electrode and a second pixel electrode. The first pixel electrode further includes a first branch electrode and a first connection electrode. The second pixel electrode further includes a second branch electrode and a second connection electrode. The first branch electrode in the four display domains of the main sub-pixel unit has a different orientation, and the second branch electrode in the four display domains of the sub-pixel unit has a different orientation. The first connection electrode connects the first branch electrode and the second electrode of the main transistor, and the second connection electrode connects the second branch electrode and the second electrode of the sub-transistor.

14. The display panel according to any one of claims 1 to 13, characterized in that, The plurality of sub-pixel units include a first type of sub-pixel, a second type of sub-pixel, and a third type of sub-pixel. The first type of sub-pixel, the second type of sub-pixel, and the third type of sub-pixel emit different colors. Adjacent sub-pixel units located in the same row emit different colors, while adjacent sub-pixel units located in the same column emit the same color.

15. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 14.

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