Hardware randomized boot clock

Abstract

The invention relates to a hardware randomized boot clock. In one embodiment, a hardware boot-up circuit includes: a random number generator circuit configured to generate a random value; a reference clock circuit configured to generate a reference clock signal, the reference clock signal comprising a series of fixed size intervals; a clock gate circuit configured to turn off at least one clock pulse in each interval to generate a randomized clock signal at a root node of the clock network; and a boot core circuit configured to access an internal memory storing a boot instruction using the randomized clock signal. The turned-off clock pulse is randomized by a random value from the random number generator. A randomized clock signal or additional randomized clock signal generated by a clock gate circuit may be used to clock a peripheral device and / or a processor of a digital electronic device including a hardware boot circuit. The random number generator may include a physical entropy source.

Description

Technical Field

[0001] The present invention generally relates to securely starting digital electronic devices, and in specific embodiments, to methods, apparatus, and systems for generating randomized startup clocks using hardware circuitry. Background Technology

[0002] Digital electronic systems and devices use a boot process to initialize various hardware, firmware, and / or software components. Multiple parties and modules may be involved in the boot process, especially in complex systems. For example, the hardware initiates the boot process (e.g., using read-only memory (ROM), such as non-volatile memory (NVM) storing boot instructions for execution by a hardware boot loader). Various firmware and software can then be initialized, up to and including one or more operating systems and applications running within the operating system environment.

[0003] To ensure proper operation, it is crucial that each component be authenticated at each step of the boot process. This sequential authentication forms a chain of trust that allows each component to be traced back to the root of trust. The hardware is the first step in the boot process and forms the root of trust (i.e., the underlying authentication that all subsequent components can trace back to). For example, the ROM may include an encryption key (e.g., an RSA key) that is checked at the start of the boot process to serve as the basis for the root of trust. At each stage of the boot process, security information (encryption keys, digital signatures, etc.) can be used to extend the chain of trust to higher-level components.

[0004] Malicious actors may attempt to access security information or unlock restricted functions of digital electronic systems during the startup process. Attackers may employ various active and passive modes of side-channel attacks at different levels of the system's physical or logical properties (e.g., chip level, device level, software level, etc.). For example, an attacker might use designed physical properties to manipulate or extract security information from the device. In some cases, these physical side-channel attacks can succeed even without design / implementation knowledge. Some possible methods include externally manipulating power, voltage, clock, etc.

[0005] Attackers may attempt to impose external stimuli on a system during specific operations of the startup process. However, without knowledge of the system, these specific operations must be identified using some form of analysis. One such analytical tool is power analysis, which analyzes the power signature of the system during startup to allow attackers to pinpoint precisely when the desired operation (e.g., authentication) is occurring. Differential power analysis (DPA) compares multiple trajectories to statistically determine the correlation between them and remove system noise. One possible DPA countermeasure is to make the power trajectories of the same operation less similar. Therefore, improved methods, devices, and systems for temporally obfuscating the power signature during startup may be needed. Summary of the Invention

[0006] According to one embodiment of the present invention, a hardware startup circuit includes a random number generator circuit, a reference clock circuit, a clock gate circuit, and a startup core circuit. The random number generator circuit is configured to generate random values. The reference clock circuit is configured to generate a reference clock signal comprising a series of intervals, each interval having N clock pulses. N is a natural number greater than 1. The clock gate circuit is operatively coupled to both the random number generator circuit and the reference clock circuit. The clock gate circuit is configured to turn off at least one clock pulse in each interval of the series of intervals to generate a randomized clock signal at the root node of the clock network. The at least one clock pulse turned off in each interval is randomized by a random value from the random number generator circuit. The startup core circuit is operatively coupled to the clock gate circuit and is configured to access an internal memory including a startup instruction using the randomized clock signal.

[0007] According to another embodiment of the present invention, a digital electronic device includes a random number generator circuit, a reference clock circuit, a clock gate circuit, a startup core circuit, at least one peripheral device, and at least one processor. The random number generator circuit is configured to generate random values. The reference clock circuit is configured to generate a reference clock signal comprising a series of intervals, each interval having N clock pulses. N is a natural number greater than 1. The clock gate circuit is operatively coupled to both the random number generator circuit and the reference clock circuit. The clock gate circuit is configured to turn off at least one clock pulse in each interval of the series of intervals to generate a randomized clock signal at the root node of the clock network. The at least one clock pulse turned off in each interval is randomized by a random value from the random number generator circuit. The startup core circuit is operatively coupled to the clock gate circuit and is configured to access an internal memory including a startup instruction using the randomized clock signal. At least one peripheral device and at least one processor are operatively coupled to the clock gate circuit. At least one peripheral device or at least one processor is clock-controlled using the randomized clock signal from the clock gate circuit.

[0008] According to another embodiment of the present invention, a method for securely starting a digital electronic device includes: generating a reference clock signal comprising a series of intervals, each interval having N clock pulses; and generating a randomized clock signal using the reference clock signal. For each interval in the series of intervals, the randomized clock signal is generated by: generating K random values ​​using a hardware random number generator circuit, each of the K random values ​​corresponding to a clock pulse of the interval; shutting off each clock pulse of the interval corresponding to one of the K random values ​​using a hardware clock gate circuit; and outputting the remaining clock pulses of the interval as the randomized clock signal. The method further includes executing a start command using a start core circuit controlled by the randomized clock signal. N is a natural number greater than 1, and K is a natural number less than or equal to N. Attached Figure Description

[0009] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 An example digital electronic device according to an embodiment of the present invention is shown, the example digital electronic device including a hardware startup circuit that uses clock gate circuits to generate a randomized startup clock and a startup core circuit controlled by the randomized startup clock.

[0011] Figure 2An example clock signal timing diagram according to an embodiment of the present invention is shown, which illustrates a reference clock signal and a corresponding random clock signal;

[0012] Figure 3 An example digital electronic device according to an embodiment of the present invention is shown, the example digital electronic device including a hardware startup circuit with a clock gate circuit having a random number generator, a clock gate and a finite state machine;

[0013] Figure 4 An example digital electronic device according to an embodiment of the present invention is shown, the example digital electronic device including a hardware startup circuit with clock gate circuitry having a random number generator, a plurality of clock gates and a finite state machine;

[0014] Figure 5 An example finite state machine according to an embodiment of the present invention is shown, which can be included in a clock gate circuit used to generate a randomized start clock;

[0015] Figure 6 Another example clock signal timing diagram according to an embodiment of the present invention is shown, which shows a reference clock signal and a corresponding random clock signal, wherein the interval size is 8 and the number of gated pulses per interval is 2;

[0016] Figure 7 Another example clock signal timing diagram according to an embodiment of the present invention is shown, which shows a reference clock signal and a corresponding random clock signal, wherein the interval size is 16 and the number of gate pulses per interval is 2;

[0017] Figure 8 Another example clock signal timing diagram according to an embodiment of the present invention is shown, which illustrates a reference clock signal and a corresponding random clock signal, wherein the interval size is 31 and the number of gated pulses per interval is 5; and

[0018] Figure 9 An example method for securely starting a digital electronic device using a randomized startup clock, according to an embodiment of the present invention, is shown.

[0019] Unless otherwise stated, corresponding numbers and symbols in different figures generally refer to corresponding parts. These figures are drawn to clearly illustrate relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of features drawn in the figures do not necessarily indicate the termination of the feature's extent. Detailed Implementation

[0020] The making and use of various embodiments will be discussed in detail below. However, it should be understood that the various embodiments described herein can be applied to various specific contexts. The specific embodiments discussed are only for illustrating specific ways of making and using various embodiments and should not be construed as limiting the scope. Unless otherwise stated, the expressions “about,” “approximately,” and “substantially” mean within 10% of a given value, preferably within 5% of a given value, or, such as in the case of substantially zero, mean less than 10% of a comparable amount, preferably less than 5% of a comparable amount.

[0021] System startup intrusion or manipulation is an attractive and effective method for malicious actors to gain system access and / or security information. During the startup process, additional system components are still resetting. Therefore, very distinctive power characteristics (and current characteristics) can be observed. The precise timing of the attack can be identified (e.g., manipulating the program counter). Due to system noise, identifying the desired power characteristics using only a small number of power traces can be very difficult. Therefore, Direct Power Acquisition (DPA) is often used to amplify small correlations between traces and remove system noise. However, if the power trace differences are large enough, DPA will fail because there is no correlation available for statistical analysis. As a result, temporal obfuscation (e.g., adding noise, changing timing, or altering the order of operations) can be an effective method to counter DPA attacks.

[0022] Temporal obfuscation of power characteristics during startup (i.e., masking secure startup power characteristics) can be achieved in various ways, such as by manipulating aspects of the clock signal used during the startup process. For example, clock signal unpredictability can be used to prevent malicious actors from knowing when specific events will occur and ultimately prevent attacks or tampering.

[0023] A traditional approach to time-power feature obfuscation (DPA) uses randomized clock network delays for different registers of the cryptographic engine, such as the S-box (replacement box) of the cryptographic module. Specifically, the clock network is modified within a combinational logic block by including delay circuitry between individual registers. Each delay circuitry may include a string of buffers or multiple static delay circuits with logic for randomly selecting different outputs. This enables DPA resistance by altering the power distribution (e.g., delaying the leading edge of the clock pulse, changing the timing of different registers, and altering the power distribution). However, managing individual delays for each register is very difficult. Furthermore, using delays for the clock pulses presents significant static timing analysis (STA) challenges, which can prevent the clock network from meeting the desired timing constraints and margins for a given circuit design.

[0024] Another traditional method for obfuscating time-power characteristics is to introduce clock division with random intervals. Specifically, the frequency of the clock signal is changed during random intervals to alter the power characteristics. However, this traditional technique suffers from unpredictable performance degradation due to the varying interval size. Furthermore, since division / switching is utilized, the intervals are typically large. A drawback of large intervals is that they limit the effectiveness of power signal obfuscation because the clock signal frequency remains constant over a longer period. Additionally, when clock division is used, the operation duration is scaled linearly. The ratio of time spent between operations remains constant, which allows attackers to filter out clock frequency changes.

[0025] Some traditional methods use pseudo-random number generators. Since the random numbers generated by pseudo-random number generators are not truly random, some of the reduced effectiveness of temporal power feature obfuscation is lost by using pseudo-random number generators.

[0026] According to the embodiments described herein, the present invention proposes introducing clock randomness at the root node of a clock network (e.g., in a hardware startup circuit used during the secure boot process of a digital electronic device). A reference clock signal is randomized using clock gating (i.e., removing clock pulses without changing the clock frequency, clock pulse width, or delaying subsequent clock pulses). The reference signal is logically divided into intervals, each interval having a fixed number of clock pulses. During each interval, a fixed number of pulses are gated. In some embodiments, more than one randomized clock signal is generated at the root node (i.e., with different interval sizes, gating pulses per interval, different randomizations, etc.).

[0027] The randomized clock signal can be generated using a random number generator circuit and clock gates. The random number generator circuit can be a real random number generator (e.g., a physical random number generator that includes a physical entropy source). The randomized clock signal can be used to provide a clock signal to a boot core circuit that is operatively coupled to the clock gates and configured to access internal memory containing boot instructions (e.g., as part of a secure boot process).

[0028] In contrast to traditional methods, clock randomness is introduced at the root node using clock gating. No modification to the clock network is required to create clock randomness. As a result, the circuit design of the embodiment system is simpler and more predictable compared to traditional methods that modify the clock network. Furthermore, pass-through clock gating allows for smaller intervals to be used (e.g., compared to traditional methods that utilize larger intervals with random durations).

[0029] Compared to conventional techniques, embodiments of the present invention can offer one or more advantages. For example, introducing gated clock pulses during each interval of the reference clock signal (e.g., at the root of a clock network for digital electronic devices) increases temporal noise, which advantageously alters the precise execution of each instruction / operation for each startup of the system (i.e., one or more digital electronic devices). This can help prevent pre-launch attacks by malicious actors, as the exact timing of the attack remains unknown.

[0030] Another potential advantage of some or all embodiments of the invention is that it provides the desired timing obfuscation of power characteristics with a deterministic performance reduction. That is, for each randomized clock signal used by the system, the interval size and the number of gated clock pulses per interval are predefined static values. Therefore, during each interval, the same number of clock pulses pass through the clock gate circuit, thereby advantageously triggering the same number of operations / instructions to be executed during each interval (a deterministic performance reduction, which has the advantage of being tailored to the specific requirements of a given application).

[0031] Another potential advantage of the implementation system and method is that the security system remains synchronized with the application modules. The implementation is part of the design and requires no additional overhead for the backend, STA, etc. Furthermore, the implementation system and method are transparent and seamless to the software / application system.

[0032] The embodiments provided below describe various hardware boot circuits, and in a specific embodiment, the hardware boot circuit includes a random number generator circuit and a clock gate circuit configured to generate a randomized clock signal at the root node of a clock network. This randomized clock signal is used by the boot core circuitry to access boot instructions from internal memory. These embodiments are described below. Figure 1 The example digital electronic device described is used to illustrate an example digital electronic device comprising: a hardware startup circuit that generates a randomized startup clock using clock gates, and a startup core circuit controlled by the randomized startup clock. An example clock signal timing diagram of the randomized clock signal is used. Figure 2 Described. Two other example digital electronic devices, including hardware startup circuitry, use... Figure 3 and Figure 4 Described. An example finite state machine that can be included in the hardware startup circuit of a digital electronic device. Figure 5 Described. Two other example signal timing diagrams are used. Figure 7 and Figure 8 Described, and Figure 9 This is used to describe an example method for securely starting a digital electronic device using a randomized startup clock.

[0033] Figure 1An example digital electronic device according to an embodiment of the present invention is shown. The example digital electronic device includes: a hardware startup circuit that generates a randomized startup clock using clock gate circuitry, and a startup core circuit that is clocked by the randomized startup clock.

[0034] refer to Figure 1 The digital electronic device 100 includes a hardware startup circuit that includes a clock gate circuit 102 operatively coupled to a startup core 104 and a controller 106. Although described as a device, it should be understood that the digital electronic device 100 can also be a digital electronic system, such as a computing system. For example, the digital electronic device 100 can be a microchip, a microcontroller, a system-on-a-chip (SoC), a personal computer, etc.

[0035] Controller 106 is configured to provide a reference clock signal 127 to clock gate circuit 102. For example, controller 106 may include a reference clock circuit 107 (as shown). The reference clock circuit 107 may also be included separately from controller 106 in digital electronic device 100. Controller 106 may also be configured to perform other functions, such as controlling the reset of various components of digital electronic device 100.

[0036] Clock gate 102 receives reference clock signal 127 and uses random number generator circuit 103 (RNG) to generate randomized startup clock 122. Startup core 104 uses randomized startup clock 122 as the clock during the startup process (e.g., accessing internal memory storing startup instructions and executing those instructions to perform the startup process of digital electronic device 100). Random number generator circuit 103 may be hardware circuitry configured to generate random values ​​(e.g., using physical values ​​susceptible to random fluctuations of digital electronic device 100). That is, in one embodiment, random number generator circuit 103 is a physical random number generator that includes a physical entropy source.

[0037] The random number generator circuit 103 can also be implemented using a pseudo-random number generator circuit. However, pseudo-random number generator implementations can receive a clock signal and are not truly random, both of which may be detrimental to providing the desired level of protection against malicious actors. In contrast, physical number generators use physical properties to generate truly random signals and do not require a clock signal.

[0038] Although the random number generator circuit 103 is shown as part of the clock gate circuit 102, the random number generator circuit 103 may also be logically or physically separate from the clock gate circuit 102. For example, in some implementations, the random number generator circuit 103 is also used for other randomization in the digital electronic device 100 and may be implemented as a separate module that is operatively connected to the module that can be considered as the clock gate circuit 102.

[0039] Clock gate 102 processes reference clock signal 127 into a series of intervals, each interval having N clock pulses (i.e., logically dividing reference clock signal 127 into intervals), where N is a natural number greater than 1 (i.e., {2, 3, ...}). These intervals are of fixed size; N does not change during randomization. For each interval, clock gate 102 is configured to randomly turn off (also referred to as gated shutdown or pass-through) at least one clock pulse in each interval (i.e., the turned-off clock pulse(s) are randomized by random values ​​from random number generator circuit 103). The remaining pulses form a randomized clock signal (randomized start clock 122). Randomized start clock 122 is formed at the root node of the clock network. That is, randomized start clock 122 is available for use by start core 104 as the clock at the root of the start process. Random clock pulses of reference clock signal 127 are gated off (pass-through) to generate randomized start clock 122 used by start core 104.

[0040] Digital electronic device 100 may also include various other types of circuitry, such as interconnects and peripherals 108 (e.g., networks for clock and data signaling transmission paths, etc.) and application systems 110 (including various processors, such as central processing units (CPUs), memory, etc.). Various components within any of these broad categories can be clocked by a reference clock signal 127 or a randomized clock. For example, an optional reference peripheral clock 128 and an optional reference system clock 129 may be included in an implementation where the startup core 104 is the only component clocked using a randomized clock signal. Alternatively, some or all of the interconnects and peripherals 108 and application systems 110 may be clocked using randomized clock signals (such as an optional randomized peripheral clock 123 and an optional randomized system clock 124). As shown, some or all of these randomized clock signals may branch off from a randomized startup clock 122, or (as will be discussed further below) any of these randomized clock signals may be generated as a separate signal by clock gate circuit 102.

[0041] In addition to the clock signaling discussed above, various circuit systems of the digital electronic device 100 can also be operatively coupled for control and communication. For example, the startup core 104 communicates with various components of the application system 110 via system operative coupling 134. Similarly, the startup core 104 can also communicate with components of the interconnect and peripheral devices 108 via peripheral operative coupling 138. In some embodiments, the startup core 104 can be operatively coupled to clock gate 102, enabling the startup core 104 to control aspects of clock gate 102 (shown as optional clock gate control 132).

[0042] Figure 2 An example clock signal timing diagram according to an embodiment of the present invention is shown, which illustrates a reference clock signal and a corresponding random clock signal. Figure 2 The random clock signal in the process can correspond to, for example, the randomized start clock described herein, such as... Figure 1 The randomized start clock in the [system / mechanism]. Elements with similar markers can be as described previously.

[0043] refer to Figure 2 Clock signal timing diagram 200 schematically illustrates a reference clock signal 227 and a corresponding random clock signal 222, which is generated using a number of clock pulses 246 equal to 8 per interval (N=8) and a number of gated pulses 247 equal to 1 per interval (K=1). Specifically, each interval 244 includes eight clock pulses 242 generated at a fixed clock frequency. For each interval 244, the random clock pulses are removed (by clock gates) based on random numbers obtained from a random number generator circuit, such that the removed pulses 243 are included in the random clock signal 222.

[0044] Specifically, the position of the clock pulse gated for a given interval does not depend on the previous pulse (it is randomly enabled and can be the same as or different from the previous pulse). For example, in the first interval, the first clock pulse is turned off (p0 = 0), while the third and sixth clock pulses in the second and third intervals are turned off, respectively. It should be noted that although the omitted pulses in back-to-back intervals will generally differ only due to the random nature of the random number generator, the same pulse may sometimes be omitted in back-to-back intervals. Of course, the clock gate circuit can also be configured to avoid such a situation if needed.

[0045] The number of clock pulses 246 per interval (i.e., repeating window) can be selected as any desired value. For example, for a given application, the number of clock pulses 246 per interval can be based on analysis and performance calculations to achieve the desired level of protection and performance. In various embodiments, the number of clock pulses 246 per interval is a power of 2 (e.g., 2^32). 3 =8,2 4 =16, 2 5 =32, etc. However, this is not a strict requirement (and choosing the number of clock pulses 246 per interval as an odd number, a prime number, or other unusual number in the context of a digital computing system can further protect against attacks).

[0046] Although in this particular example, the number of gated pulses 247 per interval is chosen to be 1, the number of gated pulses 247 per interval can be any natural number within the range of the number of clock pulses 246 per interval (but K ≠ N, since all pulses in each interval will be removed). Of course, practical limitations may exist in many applications, as increasing the number of gated pulses 247 per interval is directly related to a decrease in performance. Therefore, while the full range of possible values ​​has been described, the practical values ​​chosen for N and K can be constrained by the specific context of a given application (e.g., the K:N ratio can be kept relatively small, such as 1:8, 1:4, etc.).

[0047] In some cases, the number of clock pulses 246 per interval and the number of gate pulses 247 per interval can be selected to customize the desired randomness while keeping the performance impact constant. For example, N=8 and K=1 has the same (predictable and consistent) performance impact as N=16 and K=2, but the latter can provide a more random power distribution. Therefore, in some embodiments, K is at least 2, and typically higher.

[0048] Random number generator circuits (such as physical random number generator circuits) can be used to generate random numbers. For example, the output of a random number generator can be scaled (e.g., via a clock gate) to produce natural numbers spanning a range of interval sizes. In the example presented here, the signal output by the random number generator can be scaled to produce natural numbers spanning N = 8 possibilities (e.g., 0 to 7). When a physical random number generator is used, the output can be derived from a physical entropy source that is statistically present across a continuous range of possible values. Functions can be applied to the output of a physical number generator (e.g., via a clock circuit) to produce natural numbers with equal probability (e.g., truly random numbers without any determinism, in contrast to pseudo-random number generators which have a degree of determinism).

[0049] Figure 3An example digital electronic device according to an embodiment of the present invention is shown. The example digital electronic device includes a hardware startup circuit having a clock gate circuit having a random number generator, a clock gate, and a finite state machine. Figure 3 Digital electronic devices can be, for example, other digital electronic devices described herein (such as...) Figure 1 The specific implementation of a digital electronic device. Elements with similar tags can be as described above.

[0050] refer to Figure 3 The digital electronic device 300 includes a hardware startup circuit that includes a clock gate circuit 302 operatively coupled to a startup core 304 and a controller 306. It should be noted that, for the sake of brevity, a convention is used herein and hereinafter where elements following pattern [x02] (where “x” is a reference numeral) can be relevant implementations of clock gate circuits in various embodiments. For example, unless otherwise stated, clock gate circuit 302 can be similar to clock gate circuit 102. Similar conventions have been used for other elements, and this will be clear by using similar terminology in conjunction with the above numbering system.

[0051] Controller 306 is configured to provide a reference clock signal 327 to clock gate circuit 302 using reference clock circuit 307. As before, clock gate circuit 302 receives reference clock signal 327 and generates a randomized startup clock 322 using random number generator circuit 303. Startup core 304 uses the randomized startup clock 322 as the clock during the startup process. The randomized startup clock 322 is formed at the root node 325 of clock network 326 (i.e., the clock tree branching from the reference clock source). That is, the randomized startup clock 322 is available for startup core 304 to use as the clock at the root of the startup process. In some embodiments, all clock signals in digital electronic device 300 are randomized. For example, randomization can be targeted at the architecture / interconnection level (such as directly connecting the randomized startup clock 322 to the root of clock network 326 (and being the only connection to clock network 326)) to randomize all data delays in digital electronic device 300. In this case, wait flags and / or status flags can be used to ensure no data loss. In other embodiments, only some clock signals are randomized, while others are not.

[0052] Clock gate 302 includes non-volatile memory 301 (which can be any suitable implementation, such as read-only memory (ROM), or one-time programmable (OTP) memory, including fuse OTP memory, floating-gate OTP, antifuse OTP, etc.). For example, when non-volatile memory 301 is an OTP memory, clock gate 302 remains silicon-configurable (until the OTP memory is programmed). Other types of non-volatile memory can also be used. In other embodiments, non-volatile memory 301 is fully writable memory, although this may cause reduced system security in some cases. Non-volatile memory 301 stores values ​​for the number N of clock pulses per interval used to generate randomized start clock 322 and the number K of gate pulses per interval. Non-volatile memory 301 cannot be modified. However, in some cases, programmable memory can be used in place of non-volatile memory 301.

[0053] Finite state machine 350 is coupled to random number generator circuit 303 and clock gate 352. Finite state machine 350 is configured to generate a clock_enable signal, which clock gate 352 uses to determine which clock pulses to remove from reference clock signal 327 to generate randomized start clock 322. Finite state machine 350 uses random values ​​from random number generator circuit 303 along with interval counter 305 and gated pulse counter 309 to generate clock_enable signal.

[0054] Digital electronic device 300 may also include various other types of circuitry, such as interconnects and peripherals 308 and application systems 310. Various components within any of these major categories can be clocked by a reference clock signal 327 or a randomized clock. For example, an optional reference peripheral clock 328 and an optional reference system clock 329 may be included in an implementation where the startup core 304 is the only component clocked using a randomized clock signal. Alternatively, some or all of the interconnects and peripherals 308 and application systems 310 may be clocked using randomized clock signals, such as an optional randomized peripheral clock 323 and an optional randomized system clock 324. As shown, some or all of these randomized clock signals may branch off from a randomized startup clock 322, or (as will be discussed further below) any of these randomized clock signals may be generated as a separate signal by clock gate circuit 302.

[0055] In addition to the clock signaling discussed above, various circuit systems of the digital electronic device 300 can also be operatively coupled for control and communication. For example, the boot core 304 communicates with various components of the application system 310 via system operation coupling 334. Similarly, the boot core 304 can also communicate with components of the interconnect and peripheral devices 308 via peripheral operation coupling 338.

[0056] Figure 4 An example digital electronic device according to an embodiment of the present invention is shown. The example digital electronic device includes a hardware startup circuit having a clock gate circuit having a random number generator, a plurality of clock gates, and a finite state machine. Figure 4 The digital electronic device in this document can be, for example, other digital electronic devices described herein (such as...). Figure 1 The specific implementation of a digital electronic device. Elements with similar tags can be as described above.

[0057] refer to Figure 4 The digital electronic device 400 includes a hardware startup circuit that includes a clock gate circuit 402 operatively coupled to a startup core 404 and a controller 406. The controller 406 is configured to provide a reference clock signal 427 to the clock gate circuit 402 using a reference clock circuit 407. As before, the clock gate circuit 402 receives the reference clock signal 427 and generates a randomized startup clock 422 using a random number generator circuit 403. The startup core 404 uses the randomized startup clock 422 as the clock during the startup process. The randomized startup clock 422 is formed at the root node 425 of a clock network 426. That is, the randomized startup clock 422 is available for the startup core 404 to use as the clock at the root of the startup process. In some embodiments, all clock signals in the digital electronic device 400 are randomized. In other embodiments, only some clock signals are randomized, while others are not.

[0058] Clock gate circuit 402 includes non-volatile memory 401 (which can be any suitable implementation, such as OTP memory, including fuse OTP memory, floating gate OTP, antifuse OTP, etc.). In this specific implementation, clock gate circuit 402 includes multiple clock gates 452 (instead of the single clock gate already shown in the previous example). Non-volatile memory 401 stores values ​​for the number N of clock pulses per interval and the number K of gating pulses per interval for each clock gate. These values ​​are used to generate a randomized start clock 422 and other randomized clocks, such as an optional randomized peripheral clock 423 and an optional randomized system clock 424. The additional randomized clocks can have the same parameters (and different randomizations that sample random values ​​from random number generator circuit 403 at different times), or they can have different parameters (interval size and / or gating pulses per interval).

[0059] Finite state machine 450 is again coupled to random number generator circuit 403 and clock gate 452. Finite state machine 450 is configured to generate a clock_enable signal, which clock gate 452 uses to determine which clock pulses to remove from reference clock signal 427 to generate a randomized clock signal. Finite state machine 450 uses interval counter 405 and gated pulse counter 409 to generate the clock_enable signal.

[0060] Digital electronic device 400 may also include various other types of circuitry, such as interconnects and peripherals 408 and application systems 410. Various components within any of these categories can be clocked by a reference clock signal 427 or a randomized clock. For example, an optional reference peripheral clock 428 and an optional reference system clock 429 may be included in an implementation where the startup core 404 is the only component clocked using a randomized clock signal. Alternatively, some or all of the interconnects and peripherals 408 and application systems 410 may be clocked using randomized clock signals, such as an optional randomized peripheral clock 423 and an optional randomized system clock 424. As shown, some or all of these randomized clock signals may branch off from the randomized startup clock 422, or (as will be discussed further below) any of these randomized clock signals may be generated as a separate signal by clock gate circuit 402.

[0061] Multiple randomized clock signals can be used to select independent delays for various circuits / components within the digital electronic device 400. For example, peripheral device 408 and / or application system 410 may include various components such as accelerators, job descriptors, and processors (e.g., a central processing unit (CPU), graphics processing unit (GPU), general-purpose processing unit (APU), and dedicated processors including application-specific integrated circuits (ASICs) implemented using field-programmable gate arrays (FPGAs). Each or all components may be clock-controlled by randomized clock signals or reference clock signals. In one embodiment, independent randomized clock signals from clock gates are used to clock-control each of the accelerator, job descriptor, and CPU in the digital electronic device 400.

[0062] In addition to the clock signaling discussed above, various circuit systems of the digital electronic device 400 can also be operatively coupled for control and communication. For example, the boot core 404 communicates with various components of the application system 410 via system operation coupling 434. Similarly, the boot core 404 can also communicate with components of the interconnect and peripheral devices 408 via peripheral operation coupling 438.

[0063] Figure 5 An example finite state machine according to an embodiment of the present invention is shown, which can be included in a clock gate circuit used to generate a randomized start clock. Figure 5 Finite state machines can be included in, for example, clock gates as described herein, such as... Figure 1 Clock gate circuits. Elements with similar markings can be as described previously.

[0064] refer to Figure 5 The finite state machine 500 includes an initial state 501, in which the interval size N and the number of gated pulses K per interval are set (e.g., read from an OTP memory). In the randomized state 502, the finite state machine 500 obtains K random numbers in the range [1, N] and fills the pulse variable p with "0" or "1". i Then, finite state machine 500 enters pulse check state 503, where the index variable i changes with the state of finite state machine 500p. i It is checked and incremented. When p i When i = 0, finite state machine 500 enters pulse-gated state 504, where clock_enable is changed to "0" (e.g., causing the next clock pulse to be gated and removed from the clock signal). Afterward, finite state machine 500 returns to pulse-checking state 503. When i = N, since the interval has been completed, finite state machine 500 returns to randomized state 502.

[0065] Finite state machine 500 can be included in the clock gate circuitry of a hardware startup circuit. For example, finite state machine 500 can be operatively coupled to an NVM memory (such as, for example, an OTP memory) that stores parameters for clock pulses of a gated reference clock signal. Specifically, one or more interval size values ​​(N) and one or more gate pulse values ​​(K) per interval. Of course, the NVM memory can also store other information, which may or may not be related to the randomization of the clock signal. Finite state machine 500 can use counters to track the cycle of iterating the interval size and the number of gate pulses. For example, various counters can be coupled between the NVM memory and finite state machine 500.

[0066] Figure 6 Another example clock signal timing diagram according to an embodiment of the present invention is shown, which shows a reference clock signal and a corresponding random clock signal, wherein the interval size is 8 and the number of gated pulses per interval is 2. Figure 6 The random clock signal in the process can correspond to, for example, the randomized start clock described herein, such as... Figure 1 The randomized start clock. Elements with similar markers can be as described previously.

[0067] refer to Figure 6 The clock signal timing diagram 600 schematically illustrates a reference clock signal 627 and a corresponding random clock signal 622, which is generated using a number of clock pulses 646 equal to 8 per interval (N=8) and a number of gated pulses 647 equal to 2 per interval (K=2). Specifically, each interval 644 includes 8 clock pulses 642 generated at a fixed clock frequency. For each interval 644, two random clock pulses are removed (turned off by clock gates) based on random numbers obtained from a random number generator circuit, such that the turned-off pulse 643 is included in the random clock signal 622.

[0068] Figure 7 Another example clock signal timing diagram according to an embodiment of the present invention is shown, which shows a reference clock signal and a corresponding random clock signal, wherein the interval size is 16 and the number of gate pulses per interval is 2. Figure 7 The random clock signal in the process can correspond to, for example, the randomized start clock described herein, such as... Figure 1 The randomized start clock. Elements with similar markers can be as described previously.

[0069] refer to Figure 7The clock signal timing diagram 700 schematically illustrates a reference clock signal 727 and a corresponding random clock signal 722, which is generated using a number of clock pulses 746 equal to 16 (N = 16) per interval and a number of gated pulses equal to 2 (K = 2) per interval 747. Specifically, each interval 744 includes 16 clock pulses 742 generated at a fixed clock frequency. For each interval 744, two random clock pulses are removed (turned off by clock gates) based on random numbers obtained from a random number generator circuit, such that the turned-off pulses 743 are included in the random clock signal 722.

[0070] Figure 8 Another example clock signal timing diagram according to an embodiment of the present invention is shown, which shows a reference clock signal and a corresponding random clock signal, wherein the interval size is 31 and the number of gated pulses per interval is 5. Figure 8 The random clock signal in the process can correspond to, for example, the randomized start clock described herein, such as... Figure 1 The randomized start clock. Elements with similar markers can be as described previously.

[0071] refer to Figure 8 The clock signal timing diagram 800 schematically illustrates a reference clock signal 827 and a corresponding random clock signal 822, which is generated using a number of clock pulses 846 equal to 31 per interval (N = 31) and a number of gated pulses 847 equal to 5 per interval (K = 5). Specifically, each interval 844 includes 31 clock pulses 842 generated at a fixed clock frequency. For each interval 844, five random clock pulses are removed (by clock gates) based on random numbers obtained from a random number generator circuit, such that the removed pulses 843 are included in the random clock signal 822.

[0072] Figure 9 An example method for securely starting a digital electronic device using a randomized startup clock, according to an embodiment of the present invention, is illustrated. A digital electronic device incorporating the hardware startup circuitry described herein can be used to perform… Figure 9 The method. Figure 9 This method can also be combined with other methods as described in this article. For example, Figure 9 The method can be with Figures 1 to 8 Any combination of embodiments in the embodiments. Although Figure 9 The steps are arranged and numbered in a logical order, but this is not intended to limit the scope of the process. Figure 9 The arrangement and numbering of the steps in the process. Figure 9The method steps described herein can be performed in any suitable order, or can be performed concurrently with each other, as will be apparent to those skilled in the art.

[0073] refer to Figure 9 A method 900 for securely starting a digital electronic device includes step 901, which generates a reference clock signal comprising a series of intervals, each interval having N clock pulses, where N is a natural number greater than 1. In step 902, a randomized clock signal is generated using the reference clock signal. Specifically, step 902 is performed by executing steps 903, 904, and 905 for each interval in the series. The reference clock signal may be generated by a reference clock circuit configured to generate a series of pulses having defined frequencies, pulse widths, and voltages. Although the pulse frequency and pulse timing are not changed by step 902, in some cases, the parameters of the reference clock circuit may be variable (e.g., changing the reference clock for the entire system).

[0074] In step 903, K random values ​​(each corresponding to a clock pulse at an interval) are generated using a hardware random number generator circuit, where K is a natural number less than or equal to N. The hardware random number generator circuit can be a physical random number generator circuit that includes physical entropy suitable as the basis for generating truly random numbers.

[0075] In step 904, each clock pulse corresponding to one of the K random values ​​in the interval is turned off using a hardware clock gate. For example, the hardware clock gate can be operatively coupled to both a hardware random number generator circuit and a reference clock circuit. The hardware clock gate is configured to turn off at least one clock pulse in each interval of the series of intervals to generate a randomized clock signal at the root node of the clock network. The at least one clock pulse turned off in each interval is randomized by a random value from the hardware random number generator circuit.

[0076] In step 905, the remaining clock pulses of the interval are output as a randomized clock signal. In step 906, the startup instruction is executed using a startup core circuit controlled by the randomized clock signal. For example, the startup core circuit may be operatively coupled to a hardware clock gate and configured to access the internal memory containing the startup instruction using the randomized clock signal.

[0077] Additional steps may be included in some embodiments. For example, a hardware clock gate circuit may be configured to use values ​​stored in the NVM memory to generate the randomized clock signal in step 902. In various embodiments, method 900 includes the steps of storing an interval size value equal to N in the NVM memory of a digital electronic device, and storing a number equal to K of gating pulses for each interval value in the NVM memory. In one embodiment, the NVM memory is an OTP memory.

[0078] Furthermore, additional randomized clock signals can be generated. In one embodiment, some or all of the additional randomized clock signals have the same parameters as the first randomized clock signal (but different randomization). That is, N is equal to K. In one embodiment, some or all of the additional randomized clock signals have a different interval size than the first randomized clock signal. In one embodiment, some or all of the additional randomized clock signals have a different number of clock-controlled pulses per interval than the first randomized clock signal.

[0079] Exemplary embodiments of the invention are summarized herein. Other embodiments can also be understood from the entirety of this specification and the claims filed herein.

[0080] Example 1. A hardware startup circuit comprising: a random number generator circuit configured to generate random values; a reference clock circuit configured to generate a reference clock signal including a series of intervals, each interval having N clock pulses, where N is a natural number greater than 1; a clock gate circuit operatively coupled to both the random number generator circuit and the reference clock circuit, the clock gate circuit configured to turn off at least one clock pulse in each interval of the series of intervals to generate a randomized clock signal at the root node of a clock network, the at least one clock pulse turned off in each interval being randomized by the random value from the random number generator circuit; and a startup core circuit operatively coupled to the clock gate circuit and configured to access an internal memory including a startup instruction using the randomized clock signal.

[0081] Example 2. The hardware startup circuit according to Example 1, wherein the random number generator circuit is a physical random number generator including a physical entropy source.

[0082] Example 3. A hardware startup circuit according to one of Examples 1 and 2, wherein the clock gate circuit includes a finite state machine operatively coupled to a one-time programmable (OTP) memory that stores an interval size value equal to N and a number of gate pulses per interval value.

[0083] Example 4. The hardware startup circuit according to Example 3, wherein the clock gate circuit further includes an interval counter and a gated pulse counter, the interval counter and the gated pulse counter being operatively coupled between the finite state machine and the OTP memory.

[0084] Example 5. A hardware startup circuit according to any one of Examples 1 to 4, wherein the clock gate circuit includes a plurality of clock gates, each clock gate being configured to generate a different randomized clock signal.

[0085] Example 6. A hardware startup circuit according to any one of Examples 1 to 5, wherein the at least one clock pulse that is turned off in each interval is at least two clock pulses.

[0086] Example 7. A digital electronic device, comprising: a random number generator circuit configured to generate random values; a reference clock circuit configured to generate a reference clock signal including a series of intervals, each interval having N clock pulses, where N is a natural number greater than 1; and a clock gate circuit operably coupled to both the random number generator circuit and the reference clock circuit, the clock gate circuit being configured to turn off at least one clock pulse in each interval of the series of intervals to generate a randomized clock signal at the root node of a clock network, in each interval The at least one clock pulse that is turned off is randomized by the random value from the random number generator circuit; a startup core circuit that is operatively coupled to the clock gate circuit and configured to access an internal memory including a startup instruction using the randomized clock signal; at least one peripheral device that is operatively coupled to the clock gate circuit; and at least one processor that is operatively coupled to the clock gate circuit, wherein the at least one peripheral device or the at least one processor is clock-controlled using the randomized clock signal from the clock gate circuit.

[0087] Example 8. A digital electronic device according to Example 7, wherein the at least one peripheral device or the at least one processor is clock-controlled using the same randomized clock signal as the startup core circuit.

[0088] Example 9. A digital electronic device according to one of Examples 7 and 8, wherein the at least one peripheral device or the at least one processor is clock-controlled using a randomized clock signal that is different from the randomized clock signal used by the startup core circuit.

[0089] Example 10. The digital electronic device of claim 9, wherein the clock gate circuit comprises a plurality of clock gates, each clock gate being configured to generate a different randomized clock signal.

[0090] Example 11. A digital electronic device according to any one of claims 9 and 10, wherein the at least one peripheral device and the at least one processor include an accelerator, a job descriptor, and a central processing unit (CPU), and wherein an independent randomized clock signal from the clock gate is used to clock control each of the accelerator, the job descriptor, and the CPU.

[0091] Example 12. A digital electronic device according to any one of claims 7 to 11, wherein the randomized clock signal is propagated through at least a portion of the clock network such that a portion or all of the data delay in the data delay of the digital electronic device is randomized.

[0092] Example 13. A digital electronic device according to any one of Examples 7 to 12, wherein the clock gate circuit includes a finite state machine operatively coupled to a one-time programmable (OTP) memory of the digital electronic device, the OTP memory storing an interval size value equal to N and a number of gate pulses per interval value.

[0093] Example 14. A digital electronic device according to any one of Examples 7 to 13, wherein the random number generator circuit is a physical random number generator including a physical entropy source.

[0094] Example 15. A method for securely starting a digital electronic device, the method comprising: generating a reference clock signal comprising a series of intervals, each of the intervals having N clock pulses, where N is a natural number greater than 1; for each of the intervals, using the reference clock signal to generate a randomized clock signal by: generating K random values ​​using a hardware random number generator circuit, each of the K random values ​​corresponding to a clock pulse of the interval, where K is a natural number less than or equal to N; shutting off each clock pulse of the interval corresponding to one of the K random values ​​using a hardware clock gate circuit; and outputting the remaining clock pulses of the interval as the randomized clock signal; and executing a startup command using a startup core circuit controlled by the randomized clock signal.

[0095] Example 16. The method according to Example 15 further includes: storing an interval size value equal to N in a one-time programmable (OTP) memory of the digital electronic device; and storing a number equal to K of gating pulses for each interval value in the OTP memory.

[0096] Example 17. The method according to one of Examples 15 and 16, further comprising: for each of the series of intervals, using the reference clock signal to generate an additional randomized clock signal by: generating K random values ​​using the hardware random number generator circuit, each of the K random values ​​corresponding to a clock pulse of the interval; shutting off each clock pulse of the interval corresponding to one of the K random values ​​using the hardware clock gate circuit; and outputting the remaining clock pulses of the interval as the additional randomized clock signal; and providing the additional randomized clock signal to at least one peripheral device or at least one processor of the digital electronic device.

[0097] Example 18. The method according to any one of Examples 15 to 17, further comprising: for each of the series of intervals, using the reference clock signal to generate an additional randomized clock signal by: generating L random values ​​using the hardware random number generator circuit, each of the L random values ​​corresponding to a clock pulse of the interval, where L is a natural number less than or equal to N and not equal to K; shutting off each clock pulse of the interval corresponding to one of the L random values ​​using the hardware clock gate circuit; and outputting the remaining clock pulses of the interval as the additional randomized clock signal; and providing the additional randomized clock signal to at least one peripheral device or at least one processor of the digital electronic device.

[0098] Example 19. A method according to any one of Examples 15 to 18, further comprising: generating an additional randomized clock signal using the reference clock signal divided into a series of additional intervals, each of the series of additional intervals having M clock pulses, M being a natural number greater than 1 and not equal to N; for each of the series of additional intervals, the additional randomized clock signal being generated by: generating L random values ​​using the hardware random number generator circuit, each of the L random values ​​corresponding to a clock pulse of the additional interval, L being a natural number less than or equal to M and not equal to K; shutting off each clock pulse of the interval corresponding to one of the L random values ​​using the hardware clock gate circuit; and outputting the remaining clock pulses of the interval as the additional randomized clock signal; and providing the additional randomized clock signal to at least one peripheral device or at least one processor of the digital electronic device.

[0099] Example 20. The method according to one of Examples 15 to 19, wherein the hardware random number generator circuit is a physical random number generator that includes a physical entropy source.

[0100] While the invention has been described in conjunction with exemplary embodiments, this specification is not intended to be interpreted in a limiting sense. Various modifications and combinations of exemplary embodiments, as well as other embodiments of the invention, will become apparent to those skilled in the art upon reference to this specification. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A hardware startup circuit, comprising: A random number generator circuit, the random number generator circuit being configured to generate random values; A reference clock circuit is configured to generate a reference clock signal, the reference clock signal comprising a series of intervals, each of the series of intervals having N clock pulses, where N is a natural number greater than 1; A clock gate circuit, operably coupled to both the random number generator circuit and the reference clock circuit, is configured to turn off at least one clock pulse in each of the series of intervals to generate a randomized clock signal at the root node of the clock network, wherein the at least one clock pulse turned off in each interval is randomized by the random value from the random number generator circuit. as well as A startup core circuit is operatively coupled to the clock gate circuit and configured to access internal memory including startup instructions using the randomized clock signal.

2. The hardware startup circuit according to claim 1, wherein the random number generator circuit is a physical random number generator including a physical entropy source.

3. The hardware startup circuit of claim 1, wherein the clock gate circuit includes a finite state machine operatively coupled to a one-time programmable OTP memory, the OTP memory storing an interval size value equal to N and a number of gate pulses per interval value.

4. The hardware startup circuit according to claim 3, wherein the clock gate circuit further includes an interval counter and a gated pulse counter, the interval counter and the gated pulse counter being operatively coupled between the finite state machine and the OTP memory.

5. The hardware startup circuit according to claim 1, wherein the clock gate circuit includes a plurality of clock gates, each clock gate being configured to generate a different randomized clock signal.

6. The hardware startup circuit of claim 1, wherein the at least one clock pulse that is turned off in each interval is at least two clock pulses.

7. A digital electronic device, comprising: A random number generator circuit, the random number generator circuit being configured to generate random values; A reference clock circuit is configured to generate a reference clock signal, the reference clock signal comprising a series of intervals, each of the series of intervals having N clock pulses, where N is a natural number greater than 1; A clock gate circuit, operably coupled to both the random number generator circuit and the reference clock circuit, is configured to turn off at least one clock pulse in each of the series of intervals to generate a randomized clock signal at the root node of the clock network, wherein the at least one clock pulse turned off in each interval is randomized by the random value from the random number generator circuit. A startup core circuit is operatively coupled to the clock gate circuit and configured to access an internal memory including a startup instruction using the randomized clock signal. At least one peripheral device, said at least one peripheral device being operatively coupled to the clock gate circuit; as well as At least one processor, the at least one processor being operatively coupled to the clock gate circuit, wherein the at least one peripheral device or the at least one processor is clock-controlled using the randomized clock signal from the clock gate circuit.

8. The digital electronic device of claim 7, wherein the at least one peripheral device or the at least one processor is clock-controlled using the same randomized clock signal as the startup core circuit.

9. The digital electronic device of claim 7, wherein the at least one peripheral device or the at least one processor is clock-controlled using a randomized clock signal different from the randomized clock signal used by the startup core circuit.

10. The digital electronic device of claim 9, wherein the clock gate circuit comprises a plurality of clock gates, each clock gate being configured to generate a different randomized clock signal.

11. The digital electronic device of claim 9, wherein the at least one peripheral device and the at least one processor comprise an accelerometer, a job descriptor, and a central processing unit (CPU), and wherein an independent randomized clock signal from the clock gate is used to clock control each of the accelerometer, the job descriptor, and the CPU.

12. The digital electronic device of claim 7, wherein the randomized clock signal is propagated through at least a portion of the clock network, such that a portion or all of the data delay in the data delay of the digital electronic device is randomized.

13. The digital electronic device of claim 7, wherein the clock gate circuit comprises a finite state machine operatively coupled to a one-time programmable OTP memory of the digital electronic device, the OTP memory storing an interval size value equal to N and a number of gate pulses per interval value.

14. The digital electronic device of claim 7, wherein the random number generator circuit is a physical random number generator including a physical entropy source.

15. A method for securely starting a digital electronic device, the method comprising: A reference clock signal is generated, the reference clock signal comprising a series of intervals, each of the series of intervals having N clock pulses, where N is a natural number greater than 1; For each of the aforementioned intervals, a randomized clock signal is generated using the reference clock signal through the following steps: K random values ​​are generated using a hardware random number generator circuit. Each of the K random values ​​corresponds to one clock pulse at the specified interval, where K is a natural number less than or equal to N. Use hardware clock gates to shut off each clock pulse of the interval corresponding to one of the K random values, and The remaining clock pulses of the interval are output as the randomized clock signal; as well as The startup command is executed using a startup core circuit controlled by the randomized clock signal.

16. The method of claim 15, further comprising: The interval size value equal to N is stored in the one-time programmable OTP memory of the digital electronic device; as well as The number of gate pulses equal to K for each interval value is stored in the OTP memory.

17. The method of claim 15, wherein for each of the series of intervals, an additional randomized clock signal is generated using the reference clock signal by: The hardware random number generator circuit generates K random values, each of which corresponds to one clock pulse at the specified interval. The hardware clock gate circuit is used to shut off each clock pulse of the interval corresponding to one of the K random values, and The remaining clock pulses of the interval are output as the additional randomized clock signal; and The additional randomized clock signal is provided to at least one peripheral device or at least one processor of the digital electronic device.

18. The method of claim 15, further comprising: For each of the aforementioned intervals, an additional randomized clock signal is generated using the reference clock signal through the following steps: The hardware random number generator circuit generates L random values, each corresponding to one clock pulse at the specified interval, where L is a natural number less than or equal to N and not equal to K. The hardware clock gate circuit is used to shut off each clock pulse of the interval corresponding to one of the L random values, and The remaining clock pulses of the interval are output as the additional randomized clock signal; as well as The additional randomized clock signal is provided to at least one peripheral device or at least one processor of the digital electronic device.

19. The method of claim 15, further comprising: Additional randomized clock signals are generated using the reference clock signal, which is divided into a series of additional intervals, each of which has M clock pulses, where M is a natural number greater than 1 and not equal to N. For each of the additional intervals, the additional randomized clock signal is generated by the following: The hardware random number generator circuit generates L random values, each corresponding to one clock pulse of the additional interval, where L is a natural number less than or equal to M and not equal to K. The hardware clock gate circuit is used to shut off each clock pulse of the interval corresponding to one of the L random values, and The remaining clock pulses of the interval are output as the additional randomized clock signal; as well as The additional randomized clock signal is provided to at least one peripheral device or at least one processor of the digital electronic device.

20. The method of claim 15, wherein the hardware random number generator circuit is a physical random number generator including a physical entropy source.

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