Low-power-consumption high-precision timing method, module and chip

Abstract

The invention discloses a low-power-consumption high-precision timing method, module and chip. The method comprises the following steps: when a chip is dormant, a digital control module starts a low-power-consumption timer at a fixed phase and samples a current value of a high-precision timer; and then the high-precision timer is turned off, and counting is maintained only by the low-speed clock. During awakening, the low-power-consumption timer is stopped at the same phase, the high-speed clock is restarted, the high-precision timer is started, errors in the dormancy period are calculated through the high-low frequency proportional relation and compensated for at a time, and timing is continuous; the correction register presets starting delay of peripherals such as a crystal oscillator, and it is ensured that the switching time is accurate. Microsecond-level continuous timing can be realized under extremely low power consumption, and the method is suitable for scenes such as Internet of Things, wearable and industrial control.

Description

Technical Field

[0001] This invention relates to a low-power, high-precision timing method, as well as a corresponding high-precision timing module and a chip containing the high-precision timing module, belonging to the field of digital integrated circuit technology. Background Technology

[0002] In chip applications, high-precision timing functionality and low-power design are often a difficult contradiction to reconcile. High-precision timers typically rely on the CPU's high-speed clock as their clock source to meet stringent timing accuracy requirements; however, the continuous operation of a high-speed clock incurs significant dynamic power consumption overhead. Even more challenging is that when the system puts the CPU into sleep mode to reduce power consumption, the timer peripheral must continue running, and its counter must operate uninterruptedly to ensure the accuracy of the wake-up time. This requirement of "non-stop timer operation during sleep" directly conflicts with the overall system's goal of extremely low power consumption.

[0003] To alleviate this contradiction, existing technologies propose a compromise: during CPU sleep mode, the timer switches to a low-speed clock to continue counting, and the CPU is periodically woken up to recalibrate the deviation of the low-speed clock with a high-speed clock, and then the count value is corrected. Although this method can maintain accuracy to a certain extent, each CPU wake-up introduces additional power consumption, and the frequent wake-up-sleep switching itself also brings new power consumption burdens. Therefore, it does not truly solve the fundamental contradiction between "high accuracy" and "low power consumption".

[0004] Furthermore, regardless of whether a high-speed or low-speed crystal oscillator is used, the accuracy of the clock source itself always determines the upper limit of the timer's accuracy. Theoretically, if the crystal oscillator is absolutely accurate, the timing error can be ignored; however, real-world devices generally have frequency deviations of 20ppm to 500ppm, resulting in long-term cumulative errors that cannot be ignored. Therefore, even with the reliance on a crystal oscillator, it is difficult to maintain microsecond-level or even higher timing accuracy during sleep periods.

[0005] Against this backdrop, Chinese invention patent ZL 201610474382.0 proposes a method for clock synchronization between wireless network devices, attempting to correct clock deviations through external synchronization frames. The steps include: 1. A clock source device interconnects with at least one clock slave device; 2. The clock source device obtains a reference clock, and the clock slave device obtains an unsynchronized reference clock; 3. Both devices exchange clock information via clock synchronization frames; 4. The clock source device sends information containing the reference clock frequency and phase to the clock slave device, and the slave device's CPU calculates and corrects its own clock accordingly, thereby achieving clock synchronization between wireless network devices. However, this scheme still relies on periodic network synchronization frames and CPU computation, making it unsuitable for extremely low-power scenarios requiring long-term sleep and infrequent communication (such as button battery-powered IoT terminals); furthermore, network synchronization itself introduces additional power consumption and communication overhead, making it difficult to meet the stringent requirement of "99% sleep time."

[0006] In conclusion, how to maintain extremely low power consumption using a low-speed clock while eliminating crystal oscillator errors through a high-precision compensation mechanism under the premise of "long-term hibernation and minimal wake-up" remains a key issue that current technology urgently needs to overcome. Summary of the Invention

[0007] The primary technical problem to be solved by this invention is to provide a low-power, high-precision timing method.

[0008] Another technical problem to be solved by the present invention is to provide a low-power, high-precision timing module.

[0009] Another technical problem to be solved by the present invention is to provide a low-power, high-precision timing chip.

[0010] To achieve the above-mentioned technical objectives, the present invention adopts the following technical solution:

[0011] According to a first aspect of the present invention, a low-power, high-precision timing method is provided, comprising the following steps:

[0012] S1: The digital control module receives the sleep signal and starts a low-power timer at a fixed phase point;

[0013] S2: In the same phase when the low-power timer is started, sample the value of the current high-precision timer and save it to the register of the digital control module;

[0014] S3: Configure the low-power timer's compare register and set the wake-up condition so that the chip can be woken up when the low-power timer's count value reaches the set value;

[0015] S4: The digital control module shuts down the high-precision timer at this fixed phase.

[0016] S5: After receiving the wake-up signal, the digital control module stops the low-power timer counting at the fixed phase of the low-speed clock and records the current count value of the low-power timer into the register of the low-power timer.

[0017] S6: In the aforementioned fixed phase, turn on the high-speed clock and start the high-precision timer;

[0018] S7: Calculate the compensation value of the high-precision timer;

[0019] S8: Enable the interrupt function of the high-precision timer, complete the high-precision timer compensation, and restore the chip to its working state.

[0020] Preferably, in step S7, the compensation value of the high-precision timer is calculated using the following formula:

[0021] compensation=(high_freq*sleepcnt) / low_freq

[0022] Where, compensation is the compensation value, high_freq is the high-speed clock frequency, low_freq is the low-speed clock frequency, and sleepcnt is the current count value of the low-power timer.

[0023] Then, the total count of the compensated high-precision timer is calculated using the following formula:

[0024] total_cnt=samplecnt+compensation+current_cnt

[0025] Where total_cnt is the total count of the high-precision timer, samplecnt is the count value of the high-precision timer, and current_cnt is the current count value of the high-precision timer;

[0026] Finally, the calculated total count of the high-precision timer is written into the high-precision timer to overwrite the current count value of the high-precision timer.

[0027] Preferably, all operations from step S1 to step S4 are completed within one low-speed clock cycle.

[0028] Preferably, the digital control module controls the high-precision timer to sample its count value and start the high-precision timer at the same low-power timer counting phase.

[0029] Preferably, in step S6, the interrupt of the high-precision timer is temporarily disabled to prevent interruption during the compensation period.

[0030] Preferably, before writing, the high-precision timer interrupt is temporarily disabled; after compensation is completed in step S8, the high-precision timer interrupt is re-enabled.

[0031] Preferably, the low-power timer also includes a correction register; the value of the correction register is pre-filled by the user to inform the low-power timer of the current chip's high-speed crystal oscillator startup time in cycles;

[0032] The low-power timer wake-up time is the value of the low-power timer's compare register minus the value of the correction register;

[0033] After the wake-up signal is generated, the digital control module waits until the low-power timer count reaches the value of its comparison register before triggering the switch from the low-power timer to the high-precision timer.

[0034] Preferably, the value of the longest startup time required by each peripheral is configured in the correction register of the low-power timer.

[0035] According to a second aspect of the present invention, a low-power, high-precision timing module is provided, comprising a digital control module, a high-precision timer, a low-power timer, and a power supply, for implementing the aforementioned low-power, high-precision timing method.

[0036] According to a third aspect of the present invention, a low-power, high-precision timing chip is provided, including the aforementioned low-power, high-precision timing module.

[0037] Compared with existing technologies, this invention only operates the low-speed timer during chip sleep, while shutting down the high-speed timer and its clock, significantly reducing dynamic power consumption. At the same time, thanks to the phase synchronization sampling and dynamic compensation mechanism, the accumulated error during the sleep period is calibrated with a high-speed clock at the moment of wake-up, achieving seamless timing. By reserving a peripheral startup window in the correction register, the switch is made after the crystal oscillator and other modules have stabilized. The entire process does not require frequent CPU wake-ups or external synchronization, and can continuously provide high-precision timing under extremely low power conditions with long-term sleep and very few wake-ups, significantly extending battery life. It is widely applicable to various scenarios that require both ultra-low power consumption and high-precision timing. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the structure of the high-precision timing module provided in the first embodiment of the present invention;

[0039] Figure 2 This is a timing diagram of the count value (sleepcnt) of the low-power timer in the first embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram illustrating the process of entering a dormant state in the first embodiment of the present invention;

[0041] Figure 4 This is a schematic diagram of the wake-up process in the first embodiment of the present invention. Detailed Implementation

[0042] The technical content of the present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0043] The technical concept in this invention is as follows: When the chip is about to enter sleep mode, the digital control module first starts a low-power timer at a strictly fixed phase point and immediately samples and saves the current count value of the high-precision timer at the same phase. Then, it shuts down the high-precision timer and the high-speed clock, leaving only the low-speed clock to drive the low-power timer to continue counting, while the rest of the chip enters an ultra-low-power state. When it needs to be woken up, the digital control module stops the low-power timer at the same fixed phase and records its count value. Then, it restarts the high-speed clock and starts the high-precision timer. Based on the known ratio of the high and low frequency clocks, it calculates the deviation that should have accumulated during the sleep period, adds this deviation to the previously saved count value, and writes it to the high-precision timer all at once to ensure continuous and error-free counting. At the same time, the wake-up signal is brought forward and the actual switching action is delayed through the correction register, reserving startup stabilization time for peripherals such as the high-speed crystal oscillator. Ultimately, while ensuring microsecond-level accuracy, power consumption is minimized, achieving a balance between high-precision timing and ultra-low power consumption.

[0044] First Embodiment

[0045] like Figure 1 As shown, the first embodiment of the present invention provides a low-power, high-precision timing module, including a digital control module (DCM), a high-precision timer (also known as a high-speed timer), a low-power timer (also known as a low-speed timer), and a power supply. An external software control layer sends sleep or wake-up commands to the DCM. The DCM, as the core scheduling unit, can be implemented by a microcontroller. On one hand, it controls the low-power timer through state configuration, phase synchronizer, and sleep state activation signals, and receives its wake-up interrupt. On the other hand, it controls the high-precision timer through start / stop, interrupt masking, and compensation write signals, while simultaneously reading the current count value of the high-precision timer. The DCM also directly controls the power supply, turning off or restoring the clock and power supply of the high-precision timer. The low-power timer only counts continuously within the power-on domain and initiates a wake-up request to the DCM when it reaches a preset value; the high-precision timer relies on the DCM to resume precise timing from the compensation value after power-on, thus forming a complete closed loop of "phase synchronization sampling—sleep low-power counting—wake-up compensation recovery".

[0046] Specifically, the digital control module sends control signals to the high-precision timer to start or stop it, read its count value (samplecnt), writes a compensated count value to it, and configures interrupts for it. On the other hand, it also sends control signals to the low-power timer to start or stop it, reads its count value (sleepcnt), and sets a comparison value to wake up the high-precision timer.

[0047] The digital control module can also output external wake-up events (such as external interrupts) or high-precision timer interrupts to the outside (if needed). Typically, the wake-up event of a low-power timer is an internal signal, which is sent to the high-precision timer via the digital control module to wake up the high-precision timer, and can also be output to external circuits via the digital control module if needed.

[0048] The power supply connects to the digital control module, high-precision timer, and low-power timer. The digital control module can control the entire chip's sleep and wake-up processes, as well as the power state (e.g., shutting down the high-speed clock domain and maintaining the low-speed clock domain).

[0049] The high-precision timer and low-power timer are controlled by the digital control module to achieve the following: 1) At the preset low-power timer counting phase point, the digital control module triggers and samples the current count value of the high-precision timer; 2) When the chip wakes up from the low-power state, the digital control module first stops the low-power timer counting at the same phase point, then starts the high-precision timer and resumes continuous counting based on the latch value and compensation value, and the low-power timer stops and holds a zero value; 3) When the chip is about to enter the low-power state, the digital control module shuts down the high-precision timer at the same phase point, and at the same time starts the low-power timer to start counting, and the high-precision timer stops and is powered off.

[0050] Second Embodiment

[0051] Based on the low-power, high-precision timing module provided in the first embodiment, the second embodiment of the present invention provides a low-power, high-precision timing method, which includes at least the following steps:

[0052] S1: The digital control module receives the sleep signal and starts the low-power timer at a fixed phase point.

[0053] When the digital control module receives a sleep signal triggered by an external circuit or software (indicating that the chip has entered a sleep state, i.e., a low-power state), it sends a start signal to the low-power timer, causing the low-power timer to start counting at a fixed phase point (the counter starts from 0).

[0054] In this embodiment, the low-power timer uses a low-speed clock (e.g., 32768Hz, which can be provided by an internal oscillator or an external crystal oscillator) and only starts counting when the chip is in sleep mode, and stops and remains at 0 when the chip is woken up (i.e., it only counts during the chip's sleep period, and remains at 0 and does not count after the chip is woken up).

[0055] like Figures 2 to 4 As shown, the low-power timer uses an upward counting method. However, those skilled in the art will understand that the low-power timer can also use a downward counting method.

[0056] Fixed phase refers to a specific edge time of the low-speed clock (e.g., 32.768kHz) of a low-power timer, ensuring that the delay of the sampling time relative to the clock edge is constant, thus eliminating the impact of timing jitter on sampling accuracy. Fixed phase is a pre-configured specific phase; whether to use the rising edge or the falling edge is determined by the hardware design and cannot be changed once determined, otherwise it will introduce errors.

[0057] S2: In the same phase when the low-power timer is started, sample the current count value (samplecnt) of the high-precision timer and save it to the register of the digital control module.

[0058] In one embodiment of the invention, the high-precision timer uses a high-speed clock (e.g., 32MHz) and is a 32-bit up counter (the high-precision timer and the low-power timer are both up counters or both down counters), counting from 0 to 0xFFFFFFFF and then counting cyclically.

[0059] The digital control module (DCM) is equipped with multiple registers, allowing for the pre-configuration of multiple comparison values. When the comparison value equals the current high-precision timer's count value, an interrupt signal is generated for the high-precision timer and sent to the DCM, enabling timed sleep mode. Alternatively, through the software control layer, an interrupt signal can be sent to the DCM to stop the high-precision timer when the chip needs to sleep, achieving event-triggered sleep mode. When the high-precision timer's counter value equals the value in the comparison register (the pre-configured value), the high-precision timer generates an interrupt signal for the DCM, thus ending the chip's sleep state. `samplecnt` is stored in the DCM's register because this register has a non-power-loss domain; its value will not be lost even when the chip is in a low-power state.

[0060] S3: Configure the low-power timer's compare register and set the wake-up condition so that the chip can be woken up (ending the chip's sleep state) when the low-power timer's count value reaches the set value.

[0061] S4: The digital control module shuts down the high-precision timer at this fixed phase (i.e., the same phase in which the low-power timer is started).

[0062] After the high-precision timer is turned off, the control chip enters a low-power state. At this time, only the registers in the non-power-down domain (the area that is kept powered) and the low-speed, low-power timer are active to save power.

[0063] The digital control module controls the sampling of the high-precision timer's count value and starts the high-precision timer at the same low-power timer counting phase (i.e., the aforementioned fixed phase), thus ensuring that sampling and stopping operations are performed at the same phase of the low-speed clock each time, in order to reduce the impact of clock phase jitter.

[0064] It should be noted that all operations from steps S1 to S4 are completed within one low-speed clock cycle. At this point, the chip is ready to enter a low-power state, and the digital compensation control module takes over the subsequent entry and exit control.

[0065] The following is combined Figure 4 This section details the specific process of the wake-up operation.

[0066] When the low-power timer's count reaches the set value, or when the digital control module receives a wake-up signal from the interrupt chip's sleep state via software or external circuitry, the digital control module initiates the chip wake-up operation. That is, the wake-up signal can be a low-power timer compare-match event or other external events (such as a GPIO interrupt). Upon wake-up, the chip exits the low-power state.

[0067] S5: Upon receiving the wake-up signal, the digital control module stops the low-power timer counting at the aforementioned fixed phase of the low-speed clock (the same phase as when the low-power timer starts) and records the current count value (sleepcnt) of the low-power timer into the register.

[0068] S6: In the aforementioned fixed phase, turn on the high-speed clock and start the high-precision timer (counting from 0).

[0069] It should be noted that before compensation, the high-precision timer temporarily starts counting from 0, but the compensation value will then be used to correct the count value of the high-precision timer.

[0070] In step S6, the high-precision timer interrupt needs to be temporarily disabled to prevent interruptions from occurring during the compensation period.

[0071] S7: Calculate the compensation value of the high-precision timer.

[0072] First, calculate the value that the high-precision timer should count during sleep (i.e., the compensation value):

[0073] compensation=(high_freq*sleepcnt) / low_freq

[0074] Where compensation is the compensation value, sleepcnt is the current count value of the low-power timer, high_freq is the high-speed clock frequency (e.g., 32MHz), and low_freq is the low-speed clock frequency (e.g., 32768Hz).

[0075] Read the current count value current_cnt of the high-precision timer. At this point, because the high-precision timer has been counting from 0 since step S5, the current count value of the high-precision timer is not 0.

[0076] Then, the total count of the compensated high-precision timer is calculated using the following formula:

[0077] t otal_cnt=samplecnt+compensation+current_cnt;

[0078] Where total_cnt is the total count of the high-precision timer, samplecnt is the count value of the high-precision timer, and current_cnt is the current count value of the high-precision timer.

[0079] It should be noted that because the counter is 32-bit, the total count `total_cnt` needs to be modulo 2^32 (i.e., if it exceeds 0xFFFFFFFF, then the lower 32 bits are used). The value of `Current_cnt` should ideally be read just before `total_cnt` is written to the high-precision timer to minimize errors caused by software compensation; it's even possible to estimate the assembly instruction execution time from reading `current_cnt` to writing to the high-precision timer, expressed as `delay_cnt` in units of high-precision timer clock cycles. In this case, the above formula can be expressed as `total_cnt = samplecnt + compensation + current_cnt + delay_cnt`.

[0080] Finally, the calculated total count (total_cnt) of the high-precision timer is written to the high-precision timer to overwrite the current count value of the high-precision timer.

[0081] Because the high-precision timer's interrupt function is disabled in step S6, it is necessary to ensure that the high-precision timer's interrupt remains temporarily disabled before writing. Temporarily disabling the interrupt during the wake-up and recovery process avoids misjudgments of the count value due to timer interrupts during the compensation write process, as well as false interrupt events before compensation is completed.

[0082] It should be noted that the embodiments of the present invention use a fixed phase point, that is, the phase point sampled by the high-precision timer is the same as the phase point when the count value of the low-power timer changes. During sleep, the low-power timer starts counting from 0 after this phase occurs; during wake-up, the low-power timer activates the high-precision timer at this phase and the count value of the low-power timer is updated. This ensures that the low-power timer's operation is an integer multiple of the low-speed clock cycle. Because it is an integer multiple, the aforementioned compensation value calculation formula is accurate; otherwise, the compensation value would be: compensation = (high_freq * sleeppcnt) / low_freq + half_low_clk_cnt, where half_low_clk_cnt represents the number of high-speed clock cycles converted from half a low-speed clock cycle.

[0083] S8: Enable the interrupt function of the high-precision timer, complete the high-precision timer compensation, and restore the chip to its working state (high-precision timer starts, low-power timer stops).

[0084] Since the total count was written to the high-precision timer in the previous step, the compensation has been completed. The high-precision timer will then increment the total count by 1 on the next rising edge to resume timing.

[0085] After the compensation is completed, the high-precision timer interrupt is re-enabled, so that subsequent comparisons and matching can generate interrupts normally.

[0086] This invention addresses the challenge of timing interruptions during chip sleep by employing a collaborative mechanism involving a digital control module, a high-precision timer, and a low-power timer. At the same phase point before entering sleep mode, the high-precision timer is sampled and its current value is frozen. Subsequently, the system retains only the low-power timer driven by a low-speed clock for counting, while all other circuits are shut down. Upon arrival of the wake-up signal, the low-power timer stops at the same fixed phase, and the high-precision timer is immediately restarted. Then, using the two time values ​​obtained from phase synchronization sampling, a dynamic compensation algorithm calculates the count value to be compensated during sleep mode in one go, directly writing it into the high-precision timer for seamless counting continuity. Through this "phase synchronization sampling + dynamic compensation" mechanism, the chip can maintain extremely low power consumption during sleep mode and restore a continuous and high-precision time reference upon wake-up.

[0087] Actual testing shows that the technical solution provided by this invention controls the timing error of the sleep state within ±1μs, while providing high-precision, low-power timing support for the chip. The timing error is determined by two factors: the clock source and a method of real-time, continuous correction using an external synchronization signal. For example, if an external signal occurs every 10ms, and the high-speed timer uses a 32MHz crystal oscillator, then the high-precision timer count increments by 320000 for every 10ms. When the external signal occurs, the high-precision timer count is changed to the previous count plus 320000.

[0088] Furthermore, by sampling and recovering the high-precision timer at a fixed phase point on a low-speed clock, timing jitter is eliminated, ensuring that the time error during sleep is strictly limited to a controllable range, without requiring precise timing. This invention can operate without an internal oscillator circuit; the choice between using an external crystal oscillator or an internal oscillator circuit depends on the application requirements. This invention does not require absolute precision for the high / low-speed clock (allowing for errors up to ±500ppm), but rather requires that its error characteristics be known and stable. To this end, this invention achieves relative accuracy through compensation values ​​to compensate for relative errors, and, if necessary, ensures absolute accuracy through calibration strategies (such as GPS second pulse correction). Therefore, to guarantee accuracy requirements, this invention can continuously synchronize based on an external clock synchronization signal to ensure the accuracy of absolute time, not just the timing accuracy of the periodic timer.

[0089] When the chip enters a sleep state, this invention shuts down the high-speed clock, as well as the high-precision timers and CPU (Central Processing Unit) that rely on the high-speed clock. This directly cuts off the largest source of dynamic power consumption (dynamic power consumption is proportional to frequency). At this time, only the low-power timer operates under a low-speed clock, and its power consumption can be reduced to 1 / 1000 of the original (e.g., from the mA level to the μA level).

[0090] In sleep mode, except for the power supply to the low-power timer and holding register, the power supply to other circuits can be turned off, further reducing static leakage power consumption.

[0091] This invention balances the trade-off between power consumption and precision while ensuring continuous and uninterrupted operation of the 32-bit timer. This gives the chip performance advantages in low-power scenarios such as the Internet of Things (IoT) and wearable devices, while also meeting stringent timing requirements in high-precision scenarios such as industrial control. In particular, for IoT devices powered by button batteries, where sleep mode accounts for 99% of operating time, this invention can significantly reduce energy consumption and extend battery life and device endurance.

[0092] Third Embodiment

[0093] Considering that practical chip applications may require ultra-low power consumption, the third embodiment of this invention provides another low-power, high-precision timing method. The contents that are the same as those in the previous embodiments will not be repeated here; only the differences will be described.

[0094] When the chip is in sleep mode, all its digital peripherals, analog peripherals, crystal oscillator, and internal high-speed oscillator are powered off (except for those that cannot be powered off), so that the chip is in an ultra-low power state most of the time to save power consumption.

[0095] Taking a crystal oscillator as an example, it takes a certain amount of time to restart after the crystal oscillator is powered off, possibly ranging from several hundred microseconds to several milliseconds. Only after restarting is the high-frequency clock output by the crystal oscillator accurate, and only then can the high-precision timer supplied as the clock source maintain its accuracy. Therefore, before the crystal oscillator has completed its startup, the digital control module cannot execute the action of switching from a low-power timer to a high-precision timer; otherwise, a significant time error will occur.

[0096] In this embodiment, a correction register is added to the low-power timer. This correction register, as an internal component of the low-power timer, works in conjunction with other units to achieve precise timing control: the user needs to pre-calculate the longest startup time of peripherals such as high-speed crystal oscillators into the number of low-speed clock cycles and write it into the correction register of the low-power timer; this value directly determines the wake-up trigger point of the low-power timer—a wake-up signal is generated when the count value reaches the comparison register setting value minus the correction register value. At this time, the digital control module receives the signal but does not immediately perform the switching action, instead continuing to wait for the low-power timer to count to the complete comparison register setting value; this delay window reserved by the correction value provides a stable startup time for the high-speed crystal oscillator and other peripherals (such as analog circuits and RF modules), ensuring that the clock source is sufficiently stable when switching to the high-precision timer; finally, the digital control module completes the timer switching at a precise preset time point, enabling the high-precision timer to perform error compensation and continuous timing based on a reliable clock source, thereby eliminating timing deviations caused by peripheral startup delays at the hardware level and ensuring the unity of microsecond-level accuracy and ultra-low power consumption.

[0097] In one embodiment of the invention, the value of the correction register is pre-filled by the user to inform the low-power timer of the current high-speed crystal oscillator startup time in cycles (here, the cycle is the cycle of the low-speed clock source used by the low-power timer), that is, converting the high-speed crystal oscillator startup time into the number of cycles of the low-speed clock source. At this time, the low-power timer wake-up time is no longer the value of the low-power timer's compare register, but is advanced to the value of the low-power timer's compare register minus the value of the correction register. Therefore, after the wake-up signal is generated, the digital control module will not immediately execute the action of switching the low-power timer to the high-precision timer, but will continue to wait until the low-power timer count value reaches the value of its compare register before triggering execution. In other words, by advancing the wake-up signal and delaying the switching action, a fixed delay window, i.e., the crystal oscillator startup time window, is constructed, thus ensuring that the switching action time must be strictly aligned with the expected switching time.

[0098] Similarly, since different chips may have other peripherals, such as analog circuits, wireless radio frequency components, and internal oscillators, they all require a certain startup time after the wake-up signal is generated before they can operate stably. Therefore, the longest startup time required by each peripheral in the current sleep-wake scenario is configured in the correction register of the low-power timer to ensure that the chip can wake up on time, promptly, and normally.

[0099] If the wake-up signal is from another peripheral device (such as GPIO), the low-power timer will continue to count and correct the value of the register before initiating the action of switching from the low-power timer to the high-precision timer (at which point the high-precision timer will start working).

[0100] Fourth embodiment

[0101] The fourth embodiment of the present invention further provides a low-power, high-precision timing chip, including the aforementioned low-power, high-precision timing module. The chip internally houses a digital control module for uniformly receiving sleep or wake-up commands and coordinating the timing of each unit. The high-precision timer and the low-power timer are linked by a shared bus; the former provides system-level high-precision timing in normal operation, while the latter independently maintains minimum power consumption counting during sleep. Except for necessary registers, all other analog, digital, and RF modules of the chip can be completely powered off upon sleep command, thus achieving an integrated solution of "extremely low power consumption during sleep and instantaneous high-precision timing recovery upon wake-up" within the chip.

[0102] It should be noted that the above embodiments are merely illustrative examples. The technical solutions of the various embodiments can be combined, and the order of the steps can be changed, all of which are within the protection scope of this invention.

[0103] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0104] The low-power, high-precision timing method, module, and chip provided by this invention have been described in detail above. Any obvious modifications made by those skilled in the art without departing from the essence of this invention will constitute an infringement of the patent rights of this invention and will incur corresponding legal liability.

Claims

1. A low-power, high-precision timing method, characterized in that... Includes the following steps: S1: The digital control module receives the sleep signal and starts a low-power timer at a fixed phase point; S2: In the same phase when the low-power timer is started, sample the value of the current high-precision timer and save it to the register of the digital control module; S3: Configure the low-power timer's compare register and set the wake-up condition so that the chip can be woken up when the low-power timer's count value reaches the set value; S4: The digital control module shuts down the high-precision timer at this fixed phase. S5: After receiving the wake-up signal, the digital control module stops the low-power timer counting at the fixed phase of the low-speed clock and records the current count value of the low-power timer into the register of the low-power timer. S6: In the aforementioned fixed phase, turn on the high-speed clock and start the high-precision timer; S7: Calculate the compensation value of the high-precision timer; S8: Enable the interrupt function of the high-precision timer, complete the high-precision timer compensation, and restore the chip to its working state.

2. The low-power, high-precision timing method as described in claim 1, characterized in that... In step S7, the compensation value of the high-precision timer is calculated using the following formula: compensation=(high_freq*sleepcnt) / low_freq Where, compensation is the compensation value, high_freq is the high-speed clock frequency, low_freq is the low-speed clock frequency, and sleepcnt is the current count value of the low-power timer. Then, the total count of the compensated high-precision timer is calculated using the following formula: total_cnt=samplecnt+compensation+current_cnt Where total_cnt is the total count of the high-precision timer, samplecnt is the count value of the high-precision timer, and current_cnt is the current count value of the high-precision timer; Finally, the calculated total count of the high-precision timer is written into the high-precision timer to overwrite the current count value of the high-precision timer.

3. The low-power, high-precision timing method as described in claim 2, characterized in that: All operations from step S1 to step S4 are completed within one slow clock cycle.

4. The low-power, high-precision timing method as described in claim 3, characterized in that: The digital control module controls the high-precision timer to sample its count value and start it at the same low-power timer counting phase.

5. The low-power, high-precision timing method as described in claim 4, characterized in that: In step S6, the interrupt of the high-precision timer is temporarily disabled to prevent interruption during the compensation period.

6. The low-power, high-precision timing method as described in claim 5, characterized in that: Before writing, ensure that the high-precision timer interrupt remains temporarily disabled; after compensation is completed in step S8, re-enable the high-precision timer interrupt.

7. The low-power, high-precision timing method according to any one of claims 1 to 6, characterized in that: The low-power timer also includes a correction register; The value of the correction register is pre-filled by the user to inform the low-power timer of the current chip's high-speed crystal oscillator startup time in cycles; The low-power timer wake-up time is the value of the low-power timer's compare register minus the value of the correction register; After the wake-up signal is generated, the digital control module waits until the low-power timer count reaches the value of the compare register before triggering the switch from the low-power timer to the high-precision timer.

8. The low-power, high-precision timing method as described in claim 7, characterized in that: Configure the maximum startup time required by each peripheral device into the correction register of the low-power timer.

9. A low-power, high-precision timing module, characterized in that... The low-power, high-precision timing module includes a digital control module, a high-precision timer, a low-power timer, and a power supply, and is used to implement the low-power, high-precision timing method according to any one of claims 1 to 8.

10. A low-power, high-precision timing chip, characterized in that... This includes the low-power, high-precision timing module as described in claim 9.

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