Data distribution method, electronic equipment and medium

Abstract

The invention relates to the technical field of chips, in particular to a data distribution method, electronic equipment and a medium, and the method comprises the steps: S1, obtaining initialized data sent by a Pm, and storing the initialized data in a memory group Am corresponding to the Pm; s2, acquiring instruction data Um sent by the Pm, acquiring an instruction serial number corresponding to the Um, a target Qn identifier, an initialized data length and a memory identifier stored in the initialized data, adding the instruction data Um, the target Qn identifier, the initialized data length and the memory identifier into the Um, and sending the instruction data Um to a corresponding target Qn; s3, obtaining a memory identifier Bn corresponding to the current to-be-distributed instruction data corresponding to the Qn, and if a condition is met, executing a step S4; and S4, the Qn reads the initialization data from the Bn according to the initialization data length corresponding to the current to-be-distributed instruction data, and issues the instruction data and the corresponding initialization data to a downstream processing engine unit corresponding to the Qn. According to the invention, the data distribution efficiency can be improved on the basis of avoiding the consumption of a large amount of resources.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and more particularly to a data distribution method, electronic device, and medium. Background Technology

[0002] In a chip system, upstream instruction data and corresponding initialization data need to be sent to the downstream Processing Engine Unit (PEU). However, the size of the initialization data is variable, and some initialization data is quite large. Sending all initialization data along with the corresponding instruction data would consume a significant amount of chip area, resulting in wasted chip space. To avoid this waste, the initialization data can be cached in memory and then read out of memory one by one before being sent to the PEU. However, when encountering large amounts of initialization data, data distribution can easily become congested, leading to low efficiency. Storing initialization data in multiple memories can improve data distribution efficiency, but since the size of the initialization data is variable, reading it from memory using address addressing would consume a large amount of resources. Therefore, improving data distribution efficiency while avoiding excessive resource consumption is a pressing technical problem. Summary of the Invention

[0003] The purpose of this invention is to provide a data distribution method, electronic device, and medium that can improve the efficiency of data distribution without consuming a large amount of resources.

[0004] According to a first aspect of the present invention, a data distribution method is provided, comprising: Step S1: Obtain P m The initial data to be sent is stored in P. m Corresponding memory group A m In the middle, P m Let A be the m-th input channel, where m ranges from 1 to M, and M is the total number of input channels. m For P m The corresponding memory bank, each P m It includes at least two memories, with initialization data and instruction data corresponding one-to-one, and each initialization data is stored in one memory. Step S2, Obtain P m Sending command data U m , get U m The corresponding instruction number, target Q n Identify, initialize data length, initialize the memory identifier where the data is stored, and add it to U. m Then send to the corresponding target Q.n Q n This is the nth output processing module, where n ranges from 1 to N. m The corresponding instruction number is according to P m The order in which the sent instruction data is generated; Step S3, Obtain Q n The memory identifier B corresponding to the current instruction data to be dispatched n If the current other Q conditions are met n There is no corresponding memory identifier, which is also B. n And the corresponding instruction sequence number is in the instruction data preceding the current instruction data to be dispatched, and there are no other Qs. n Executing from B n If the conditions for the corresponding memory data reading operation are met, then step S4 is executed; Step S4, Q n Based on the initialization data length corresponding to the current instruction data to be distributed, from B n Read Q from the corresponding memory n The current pending instruction data corresponds to the initialization data, and the instruction data and the corresponding initialization data are sent to Q. n The corresponding downstream processing engine unit.

[0005] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in the first aspect of the present invention.

[0006] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions for performing the method described in the first aspect of the present invention.

[0007] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the data distribution method, electronic device, and medium provided by this invention achieve considerable technological advancement and practicality, and have broad industrial application value. It possesses at least the following beneficial effects: This invention provides a memory group for each input channel, storing the initialization data corresponding to each input channel in the memory group. It also provides multiple parallel output processing modules. The output processing modules distribute the initialization data from each register according to the instruction requirements, the storage order, and the length of the initialization data. This eliminates the need to read the initialization data from the memory through address addressing, thereby improving the efficiency of data distribution without consuming a lot of resources. Attached Figure Description

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description only represent some of the embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative effort based on these drawings.

[0009] Figure 1 The data distribution method flow chart provided by the embodiments of the present application is shown in the following. DETAILED DESCRIPTION

[0010] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments only represent some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative effort fall within the scope of the present application.

[0011] The embodiments of the present application provide a data distribution method, as shown in the following. Figure 1 The data distribution method comprises the following steps. Step S1, obtaining P m The initialization data sent by the upstream device is stored in P m The corresponding memory group A m , P m is the mth input channel, the value range of m is 1 to M, M is the total number of input channels, A m is the corresponding memory group of P m , each P m comprises at least two memories, and the initialization data and the instruction data are one-to-one corresponding, and each initialization data is stored in a memory.

[0012] P m is used for receiving the initialization data and the instruction data sent by the mth upstream device and sending to the input processing module, the initialization data and the instruction data are one-to-one corresponding, and the initialization data is sent earlier than the corresponding instruction data. In general, the initialization data and the instruction data in P m are sent alternately, for example, P m sends initialization data 1, instruction data 1, initialization data 2, instruction data 2, initialization data 3, instruction data 3... in turn. Each P m corresponds to an independent memory group A m , and each initialization data is stored in a memory in the corresponding memory group. The number of memories contained in each A m may be determined according to the chip area, the corresponding P mThe sending of data, and other factors determine that, as a preferred example, each A m includes two memories, which can avoid initialization data read conflict, and reduce the area of the chip. m The initialization data is stored in the register in A m in a polling manner, which can avoid initialization data read conflict and improve data distribution efficiency.

[0013] Step S2, get the instruction data U m sent by P m , get the instruction sequence number, target Q n identifier, initialization data length, and initialization data storage memory identifier corresponding to U m , and add them to U m and send to the corresponding target Q n , Q n is the nth output processing module, n is in the range of 1 to N, and the instruction sequence number corresponding to U m is generated according to the order of the instruction data sent by P m .

[0014] It should be noted that the instruction data can be sent through the instruction transmission channel. During the transmission process in the instruction transmission channel, the instruction sequence number, target Q n identifier, initialization data length, and initialization data storage memory identifier corresponding to the instruction data are obtained and added to the instruction data, which prepares for subsequent accurate and fast reading of the corresponding initialization data from the corresponding memory. N output processing modules run in parallel to improve data distribution efficiency. Each output processing module is connected to a downstream processing engine unit (PEU). Q n The number of Q m can be determined according to factors such as chip area, P m data sending conditions, and downstream devices required to be accessed by P n , as a preferred example, 2 Q n , that is, N=2, which can not only meet the requirement of avoiding initialization data read conflict and improving data distribution efficiency, but also reduce the area of the chip.

[0015] Step S3, get the memory identifier B n corresponding to the current to-be-distributed instruction data corresponding to Q n , if the current other Q n does not exist corresponding to the memory identifier B n and the instruction sequence number of the instruction data before the current to-be-distributed instruction data and there is no other Q n executing from B nIf the conditions for the corresponding memory data reading operation are met, then step S4 is executed.

[0016] It should be noted that Q n The corresponding currently pending instruction data refers to the instruction data that is currently waiting to be read from the corresponding memory to retrieve initialization data. However, since the same memory can only be accessed based on one Q at a time... n The data read operation is performed, and in this embodiment of the invention, for each memory, the data needs to be read according to the storage order of the initialization data and then according to the length of the initialization data. Therefore, when reading each Q... n Before initializing the corresponding data for the current instruction to be dispatched, a judgment needs to be made first. If the conditions of other Q values ​​are met... n There is no corresponding memory identifier, which is also B. n And the corresponding instruction sequence number is in the instruction data preceding the current instruction data to be dispatched, and there are no other Qs. n Executing from B n The initialization data read operation can only be executed when the corresponding conditions for memory data read operation are met; otherwise, it cannot be executed and must wait until the corresponding conditions are met before execution. During the waiting process, Q... n A new instruction data to be distributed can be determined for judgment.

[0017] Step S4, Q n Based on the initialization data length corresponding to the current instruction data to be distributed, from B n Read Q from the corresponding memory n The current pending instruction data corresponds to the initialization data, and the instruction data and the corresponding initialization data are sent to Q. n The corresponding downstream processing engine unit.

[0018] It should be noted that since step S3 has ensured that the reading order and the storage order of the initialization data in each memory are consistent, the corresponding initialization data can be read directly from the corresponding memory according to the length of the initialization data, without having to read the initialization data from the memory through address addressing, thus reducing resource consumption.

[0019] As one embodiment, in step S2, U is obtained. m The corresponding target Q n The identifiers include: Step C21, according to P m Priority, same P m The corresponding command data transmission order and Q n One or more factors in the load determine the target Q corresponding to each initialization data. n .

[0020] The output arbitration module is arranged in the instruction transmission channel, and the output arbitration module determines the target Q m according to one or more factors of the priority of the P m , the sending order of the corresponding instruction data, and the load of the Q n . n The order of transmission to the Q n is also determined. It should be noted that the existing arbitration methods are all within the protection scope of the present application, and will not be described here.

[0021] As an embodiment, the step S3 comprises: Step S31, obtaining the memory identifier B n corresponding to the current to-be-distributed instruction data corresponding to the Q n .

[0022] It should be noted that since the distribution instruction has been added with the corresponding memory identifier before reaching the Q n , the obtaining in step S31 can be directly performed.

[0023] Step S32, judging whether there is to-be-distributed instruction data with the memory identifier B n in all the Q n at present, if not, step S36 is executed, otherwise, step S33 is executed.

[0024] It should be noted that the Q n can access each other, and each Q n can know the current state of the other Q n .

[0025] Step S33, judging whether there is other Q n executing the operation of reading data from the memory corresponding to B n at present, if not, step S34 is executed, otherwise, step S35 is executed.

[0026] It should be noted that since the same memory can be read by only one Q n at the same time, when there is other Q n executing the operation of reading data from the memory corresponding to B n , the initialization data corresponding to the current to-be-distributed instruction data corresponding to the Q n cannot be read.

[0027] Step S34, judging whether there is the memory identifier B n and the instruction sequence number in the current to-be-distributed instruction data, if yes, step S35 is executed, otherwise, step S36 is executed.

[0028] It should be noted that, in order to avoid consuming a lot of resources by reading the initialization data based on the address of each initialization data, it is necessary to read the data from the memory in the same way as the storage order. In this way, the data can be accurately read from the corresponding memory based only on the length of the initialization data, avoiding data corruption.

[0029] Step S35, Reconfirm Q n The corresponding current instruction data to be dispatched is returned to the execution step S31.

[0030] It should be noted that when Q n If the corresponding current instruction data cannot be distributed, Q can be redefined. n The corresponding current instruction data to be distributed improves data distribution efficiency.

[0031] Step S36: Determine if other Q conditions are met. n There is no corresponding memory identifier, which is also B. n And the corresponding instruction sequence number is in the instruction data preceding the current instruction data to be dispatched, and there are no other Qs. n Executing from B n The conditions for the corresponding memory data reading operation are met, and step S4 is executed.

[0032] Instruction sequence numbers are used to identify the same P m The corresponding order of instruction data is determined by the one-to-one correspondence between initialization data and instruction data, which are sent alternately. Therefore, the instruction sequence number also indicates the order of initialization data. As one embodiment, each P... m A corresponding set of instruction sequence number data structures {R1 m R2 m}, R1 m For P m The first part of the instruction sequence number's data structure, R2 m For P m The second part of the instruction sequence number data structure, R1 m R² is one of the numbers in [0,2]. m Let Q be one of the numbers in [0, X], where X is all the numbers in Q. n The maximum amount of instruction data that can be cached, R1 m R2 m The initial values ​​are all 0; In step S2, U is obtained. m The corresponding instruction sequence numbers include: Step S21: Obtain the current P m The corresponding {R1 m R2m}; Step S22: If R2 m < X, then update R1 m = R1 m , R2 m = R2 m + 1; If R2 m = X, and R1 m ≠ 2, then update R1 m = R1 m + 1, R2 m = 1; If R2 m = X, and R1 m = 2, then update R1 m = 0, R2 m = 1; Determine the updated {R1 m , R2 m} as the instruction sequence number corresponding to U m The corresponding instruction sequence number.

[0033] It should be noted that through the above - mentioned required setting method, it can not only avoid infinite increase, but also avoid duplication between sequence numbers, and can clearly identify the order of instruction data corresponding to the same P m The order of instruction data corresponding to the same P

[0034] As an embodiment, step S34 includes: Step S341: If the first - part value of the sequence number corresponding to the current instruction data to be distributed corresponding to Q n is 0, then determine whether there exists corresponding memory identification also being B n and the first - part value of the corresponding instruction sequence number is 2, or there exists corresponding memory identification also being B n and the first - part value of the corresponding instruction sequence number is 0 and the second part is less than the second - part value of the sequence number corresponding to the current instruction data to be distributed corresponding to Q n If there exists, then determine that there exists corresponding memory identification also being B n and the corresponding instruction sequence number is within the current instruction data to be distributed, otherwise, execute step S342; Step S342: If the first - part value of the sequence number corresponding to the current instruction data to be distributed corresponding to Q n is 1, then determine whether there exists corresponding memory identification also being B n and the first - part value of the corresponding instruction sequence number is 0, or there exists corresponding memory identification also being B n and the first - part value of the corresponding instruction sequence number is 1 and the second part is less than the second - part value of the sequence number corresponding to the current instruction data to be distributed corresponding to Q nIf the instruction data corresponding to the second part value of the sequence number of the current to-be-distributed instruction data exists, it is determined that the memory identifier corresponding to the instruction data is also B n If the instruction sequence number corresponding to the instruction data is in the current to-be-distributed instruction data, the step S343 is executed, otherwise, the step S343 is executed. If Q n If the first part value of the sequence number of the current to-be-distributed instruction data is 2, it is determined whether the memory identifier corresponding to the instruction data is also B n If the first part value of the sequence number of the current to-be-distributed instruction data is 2, it is determined whether the memory identifier corresponding to the instruction data is also B n If the first part value of the sequence number of the current to-be-distributed instruction data is 2, it is determined whether the memory identifier corresponding to the instruction data is also B n If the instruction data corresponding to the second part value of the sequence number of the current to-be-distributed instruction data exists, it is determined that the memory identifier corresponding to the instruction data is also B n If the instruction sequence number corresponding to the instruction data is in the current to-be-distributed instruction data, the step S343 is executed, otherwise, the step S343 is executed. n If the instruction sequence number corresponding to the instruction data is in the current to-be-distributed instruction data.

[0035] As an embodiment, Q n is provided with g(n) cache units {C1 n ,C2 n ,...,C i n ,...,C g(n) n} and C i n is the i-th cache unit provided in Q n , i is in the range of 1 to g(n), g(n) is the number of cache units provided in Q n ; Q n receives the instruction data corresponding to the memory identifier, and stores the received instruction data and the corresponding memory identifier in the idle C i n ; Q n determines one of the non-idle C i n instruction data in Q n corresponding to the current to-be-distributed instruction data, and determines the memory identifier corresponding to the current to-be-distributed instruction data as B n By providing g(n) cache units, Q n can pre-process and cache the information corresponding to multiple instruction data, and speed up the data distribution efficiency. The value of g(n) can be determined comprehensively according to factors such as chip area, P m data transmission, etc. Preferably, the value of g(n) is all set to 2.

[0036] As an example, Q n The received instruction data and the corresponding memory identifier are stored in the idle C i n Then, in step S35, the Q n The non-idle C i n instruction data is determined as the Q n The memory identifier corresponding to the current instruction data to be distributed is determined as the B n .

[0037] It should be noted that some example embodiments are described as a process or method depicted as a flowchart. Although each step of the flowchart is described as occurring sequentially, many of the steps can be performed in parallel, concurrently or at the same time. In addition, the order of the steps can be re-arranged. The process can be terminated when its operations are completed, but can also have additional steps not included in the figure. The process can correspond to a method, function, routine, subroutine, or the like.

[0038] The embodiment of the present application also provides an electronic device, comprising: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executed by the at least one processor, and the instructions are arranged to execute the method provided by the embodiment of the present application.

[0039] The embodiment of the present application also provides a computer readable storage medium, which stores computer executable instructions, and the computer executable instructions are used for executing the method provided by the embodiment of the present application.

[0040] The embodiment of the present application sets a memory group for each input channel, stores the initialization data corresponding to each input channel in the memory group, and sets a plurality of output processing modules running in parallel. The output processing module distributes the initialization data from the corresponding initialization data in each register according to the storage order according to the instruction requirement, and does not need to read the initialization data in the memory through the address addressing mode, so that the efficiency of data distribution can be improved on the basis of avoiding consuming a large amount of resources.

[0041] The above merely describes preferred embodiments of the present application, and is not intended to limit the present application in any form. Although the present application has been disclosed with the preferred embodiments as above, it is not intended to limit the present application. Any person skilled in the art, without departing from the technical solution of the present application, can make some changes or modifications to the above disclosed technical content to obtain equivalent embodiments with equivalent changes. However, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, as long as it does not deviate from the technical solution of the present application, still belongs to the scope of the technical solution of the present application.

Claims

1. A data distribution method, characterized by, Comprising: Step S1, obtaining P m The transmitted initialization data is stored in P m Corresponding memory group A m , P m is the mth input channel, m is in the range of 1 to M, M is the total number of input channels, A m is P m Corresponding memory group, each P m Comprises at least two memories, and initialization data and instruction data are one-to-one corresponding, and each initialization data is stored in a memory; Step S2, obtaining P m transmitted instruction data U m , obtaining U m corresponding instruction sequence number, target Q n identification, initialization data length, storage identification of initialization data, and adding to U m and transmitting to the corresponding target Q n , Q n is the nth output processing module, n is in the range of 1 to N, U m corresponding instruction sequence number is generated according to the order of the instruction data transmitted by P m ; Step S3, obtaining Q n The memory identifier B corresponding to the current to-be-distributed instruction data n If the current other Q n There is no corresponding memory identifier B n And the instruction sequence number corresponding to the instruction data before the current to-be-distributed instruction data and there is no other Q n The operation of reading data from B n Corresponding memory, if the condition is met, step S4 is performed; Step S4, Q n According to the initialization data length corresponding to the current to-be-distributed instruction data from B n Read the corresponding initialization data of the current to-be-distributed instruction data in the memory Q n And issue the instruction data and the corresponding initialization data to the downstream processing engine unit Q n Corresponding.

2. The method of claim 1, wherein, In the step S2, the U m The corresponding target Q n Identification, comprising: Step C21, according to P m the priority of the same P m the sending order of the corresponding instruction data, and the load of Q n corresponding to each initialization data is determined by one or more factors of the target Q n .

3. The method of claim 1, wherein, The step S3 comprises: Step S31, obtaining Q n The memory identifier B corresponding to the current to-be-distributed instruction data n ; Step S32, judging whether there is memory identification of all Q n the to-be-distributed instruction data is B n Step S36 is executed, otherwise, step S33 is executed. Step S33, judging whether there is other Q n is being executed from B n corresponding memory read data operation, if not, step S34 is executed, otherwise, step S35 is executed; Step S34, judging whether there is a corresponding memory identifier B n and the corresponding instruction sequence number is in the current to be distributed instruction data. If there is, step S35 is executed, otherwise, step S36 is executed. Step S35, re-determine Q n If the current instruction data to be distributed corresponds, return to step S31 for execution. Step S36, determine that the current other Q n The corresponding memory identifier does not exist in B n And the corresponding instruction sequence number is the instruction data before the current to-be-distributed instruction data and there is no other Q n Executing from B n The operation of the corresponding memory reading data, execute step S4.

4. The method of claim 3, wherein, Each P m A corresponding set of instruction sequence number data structures {R1 m R2 m }, R1 m For P m The first part of the instruction sequence number's data structure, R2 m For P m The second part of the instruction sequence number data structure, R1 m R² is one of the numbers in [0,2]. m Let Q be one of the numbers in [0, X], where X is any number among all Q. n The maximum amount of instruction data that can be cached, R1 m R2 m The initial values ​​are all 0; In the step S2, the U m The corresponding instruction sequence number includes: Step S21, acquiring current P m corresponding {R1 m ,R2 m}; Step S22, if R2 m < X, then update R1 m = R1 m , R2 m = R2 m + 1; If R2 m = X, and R1 m ≠ 2, then update R1 m = R1 m + 1, R2 m = 1; If R2 m = X, and R1 m = 2, then update R1 m = 0, R2 m = 1; The updated {R1 m ,R2 m} is determined as the instruction sequence number corresponding to U m .

5. The method of claim 4, wherein, The step S34 comprises: Step S341, if Q n If the first part of the sequence number corresponding to the current to-be-distributed instruction data is 0, it is determined whether there is a memory identifier also being B n and the first part of the sequence number corresponding to the instruction is 2, or there is a memory identifier also being B n and the first part of the sequence number corresponding to the instruction is 0 and the second part is less than Q n If the second part of the sequence number corresponding to the current to-be-distributed instruction data is the instruction data, if there is, it is determined that there is a memory identifier also being B n and the sequence number corresponding to the instruction is in the current to-be-distributed instruction data, otherwise, step S342 is performed; Step S342, if Q n If the first part of the sequence number corresponding to the current to-be-distributed instruction data is 1, it is determined whether there is a memory identifier also being B n and the first part of the sequence number corresponding to the instruction is 0, or there is a memory identifier also being B n and the first part of the sequence number corresponding to the instruction is 1 and the second part is less than Q n If the second part of the sequence number corresponding to the current to-be-distributed instruction data is 1, it is determined whether there is a memory identifier also being B n and the sequence number corresponding to the instruction is in the current to-be-distributed instruction data, otherwise, step S343 is executed; Step S342, if Q n If the first part of the sequence number corresponding to the current to-be-distributed instruction data is 2, it is determined whether there is a memory identifier also being B n And the first part of the instruction sequence number is 1, or there is a memory identifier also being B n And the first part of the instruction sequence number is 2 and the second part is less than Q n If the instruction data of the second part of the sequence number corresponding to the current to-be-distributed instruction data exists, it is determined that there is a memory identifier also being B n And the corresponding instruction sequence number is in the current to-be-distributed instruction data, otherwise, it is determined that there is no memory identifier also being B n And the corresponding instruction sequence number is in the current to-be-distributed instruction data.

6. The method of claim 1, wherein, Each A m Each of the two memories comprises two memory banks.

7. The method of claim 1, wherein, N is 2.

8. An electronic device, comprising: Comprising: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executed by the at least one processor, the instructions configured to perform the method of any one of the preceding claims 1-7.

9. A computer-readable storage medium, characterized in that, Computer executable instructions stored in the memory, the computer executable instructions configured to perform the method of any one of the preceding claims 1-7.

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