Server, signal transmission method, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a server, a signal transmission method, electronic equipment and a storage medium, and relates to the technical field of servers, the system comprises a first chip, the first end of the first chip comprises a first chip selection pin, a first clock pin, a first master-in slave-out pin and a first master-out slave-in pin; the second chip comprises a second chip selection pin, a second clock pin, a second master-output-slave-input pin and a second master-input-slave-output pin, the first chip selection pin is electrically connected with the second chip selection pin, the first clock pin is electrically connected with the second clock pin, the first master-input-slave-output pin is electrically connected with the second master-output-slave-input pin, and the second chip selection pin is electrically connected with the second clock pin. The first master-output slave-input pin is electrically connected with the second master-input slave-output pin; and the UBB is electrically connected with the second end of the first chip. In this way, rapid communication connection between the second chip and the UBB is achieved, and then the out-of-band management function of the second chip on the components in the UBB can be conveniently achieved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of servers, and in particular to a server, a signal transmission method, an electronic device, and a storage medium. BACKGROUND

[0002] At present, a universal baseboard (UBB) usually adopts a universal serial bus (USB) protocol as one of the standards for its out-of-band management communication. However, due to the fact that some special-purpose chips are not designed to integrate a USB controller that can serve as a master, these chips cannot establish a fast communication connection with the UBB board, and thus cannot realize the monitoring and management functions of the components on the UBB board. SUMMARY

[0003] The present disclosure provides a server, a signal transmission method, an electronic device, and a storage medium to at least solve the above technical problems in the prior art.

[0004] In a first aspect, an embodiment of the present disclosure provides a server, which comprises: a first chip, a first end of the first chip comprising a first chip select pin, a first clock pin, a first master-in-slave-out pin, and a first master-out-slave-in pin; a second chip, the second chip comprising a second chip select pin, a second clock pin, a second master-out-slave-in pin, and a second master-in-slave-out pin, the first chip select pin being electrically connected to the second chip select pin, the first clock pin being electrically connected to the second clock pin, the first master-in-slave-out pin being electrically connected to the second master-out-slave-in pin, and the first master-out-slave-in pin being electrically connected to the second master-in-slave-out pin; a universal baseboard (UBB), the UBB being electrically connected to a second end of the first chip; the first end of the first chip and the second end of the first chip being different types of ports; the first chip receiving a first type signal transmitted by a first object through one end of the first chip, the first chip converting the first type signal into a second type signal, and transmitting the second type signal to a second object through another end of the first chip; wherein, in a case where the first object comprises the second chip and the second object comprises the UBB, the one end of the first chip is the first end, and the another end of the first chip is the second end; or, in a case where the first object comprises the UBB and the second object comprises the second chip, the one end of the first chip is the second end, and the another end of the first chip is the one end.

[0005] In a second aspect, an embodiment of the present disclosure provides a signal transmission method applied to a server, which comprises: obtaining a first type signal transmitted by a first object through one end of a first chip; convert the first type signal into a second type signal by the first chip; transmit the second type signal to a second object through the other end of the first chip; The server includes the first object and the second object; in a case where the first object includes the second chip and the second object includes the universal substrate UBB, the one end of the first chip is the first end, and the other end of the first chip is the second end; or in a case where the first object includes the UBB and the second object includes the second chip, the one end of the first chip is the second end, and the other end of the first chip is the one end. The first end of the first chip includes a first chip select pin, a first clock pin, a first master-in slave-out pin and a first master-out slave-in pin, the second chip includes a second chip select pin, a second clock pin, a second master-out slave-in pin and a second master-in slave-out pin, the first chip select pin is electrically connected with the second chip select pin, the first clock pin is electrically connected with the second clock pin, the first master-in slave-out pin is electrically connected with the second master-out slave-in pin, and the first master-out slave-in pin is electrically connected with the second master-in slave-out pin; the UBB is electrically connected with the second end of the first chip, and the first end of the first chip and the second end of the first chip are different types of ends.

[0006] In a third aspect, an electronic device is provided, including: at least one processor; and a memory communicatively connected with the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform any of the signal transmission methods.

[0007] In a fourth aspect, a non-transitory computer-readable storage medium storing computer instructions is provided, and the computer instructions are used to enable a computer to perform any of the signal transmission methods.

[0008] Based on the server provided by the embodiments of the present disclosure, the first chip, the second chip and the UBB are arranged in the server, wherein the first end of the first chip can include a first chip select pin, a first clock pin, a first master-in-slave-out pin and a first master-out-slave-in pin, the second chip can include a second chip select pin, a second clock pin, a second master-out-slave-in pin and a second master-in-slave-out pin, the first chip select pin is electrically connected with the second chip select pin, the first clock pin is electrically connected with the second clock pin, the first master-in-slave-out pin is electrically connected with the second master-out-slave-in pin, the first master-out-slave-in pin is electrically connected with the second master-in-slave-out pin, and the UBB is electrically connected with the second end of the first chip. In this way, the first chip can convert the first type signal supported by the first object into the second type signal supported by the second object, realize the communication connection between the first object and the second object, that is, realize the fast communication connection between the second chip and the UBB, avoid the situation that the chip cannot establish fast communication connection with the UBB due to that the chip is not integrated with the USB controller which can be used as the master device in the prior art, and then the out-of-band management function of the second chip to the components in the UBB can be conveniently realized.

[0009] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a structural schematic diagram of a server in a related technology provided by the embodiments of the present disclosure; Figure 2 is one of the structural schematic diagrams of a server provided by the embodiments of the present disclosure; Figure 3 is another of the structural schematic diagrams of a server provided by the embodiments of the present disclosure; Figure 4 is a third of the structural schematic diagrams of a server provided by the embodiments of the present disclosure; Figure 5 is a flowchart of a signal transmission method provided by the embodiments of the present disclosure; Figure 6 is a structural schematic diagram of an electronic device provided by the embodiments of the present disclosure. DETAILED DESCRIPTION

[0011] In order to make the objects, characteristics and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present disclosure.

[0012] In the following description, "some embodiments" are described, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0013] If the application file contains similar descriptions of "first / second", the following description is added. In the following description, the terms "first, second, third" are only used to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that "first, second, third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0014] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0015] Before the embodiments of the present disclosure are further described in detail, the terms and phrases involved in the embodiments of the present disclosure are explained, and the terms and phrases involved in the embodiments of the present disclosure are applicable to the following explanations.

[0016] As described in the background, the general-purpose substrate usually adopts the USB protocol as one of the standards for its out-of-band management communication, but due to the design of some special chips without integrating a USB controller that can be used as a host device, the special chips cannot establish a communication connection with the UBB.

[0017] Based on this, in order to solve the problem that some special chips cannot establish a communication connection with the UBB, as shown in Figure 1 The chip 11 can include an ‌Inter-Integrated Circuit (‌I2C) interface, and the Baseboard Management Controller (BMC) 121 in the UBB 12 can also include an I2C interface. In this way, the chip 11 can communicate with the BMC 121 in the UBB 12 through the I2C to realize the out-of-band management function of the UBB. It should be noted that based on the aboveFigure 1 As shown in the structure, the BMC 121 can be used as a slave, which first communicates with the Retimer, OAM, FRU, I2C EXP IO and the like in the UBB 12 through I2C, and then the chip 11 communicates with the BMC 121 in the UBB 12 through I2C to obtain the device information of the Retimer, OAM and the like in the UBB 12, such as temperature, vendor / device ID and the like. However, since I2C belongs to a fast communication mode, the communication speed is generally 100 kHz. Therefore, the chip 11 obtains the related information of the OAM and the Retimer card from the BMC 121 in the UBB 12 through I2C, and the upgrade of the UBB board BMC FW will be relatively slow, which causes the chip to be unable to establish a fast communication connection with the UBB board.

[0018] In view of the defect that the chip cannot establish a fast communication connection with the UBB board in the prior art, the embodiment of the present disclosure provides a server, a signal transmission method, an electronic device and a storage medium, which can solve the above problems. Specifically, the first chip, the second chip and the UBB can be arranged in the server, the first chip can include a first chip select pin, a first clock pin, a first master-in-slave-out pin and a first master-out-slave-in pin, the second chip can include a second chip select pin, a second clock pin, a second master-out-slave-in pin and a second master-in-slave-out pin, the first chip select pin is electrically connected with the second chip select pin, the first clock pin is electrically connected with the second clock pin, the first master-in-slave-out pin is electrically connected with the second master-out-slave-in pin, the first master-out-slave-in pin is electrically connected with the second master-in-slave-out pin, and the UBB is electrically connected with the second end of the first chip. In this way, the first chip can convert the first type signal supported by the first object into the second type signal supported by the second object, realize the communication connection between the first object and the second object, that is, realize the fast communication connection between the second chip and the UBB, avoid the situation that the chip cannot establish a fast communication connection with the UBB due to the fact that the chip does not integrate the USB controller which can be used as a master device in the prior art, and thus the out-of-band management function of the second chip to the components in the UBB can be conveniently realized.

[0019] The server provided by the embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] Figure 2 is one of the structural schematic diagrams of the server provided by the embodiment of the present disclosure.

[0021] As Figure 2 shown, the server provided by the embodiment of the present disclosure can include the following parts: The first chip 21, the first end of the first chip 21 comprises a first chip select pin SCS, a first clock pin SCK, a first master slave in pin SDI and a first master slave out pin SDO; The second chip 22, the second chip 22 comprises a second chip select pin CS, a second clock pin CLK, a second master slave in pin MOSI and a second master slave out pin MISO. Wherein, the first chip select pin SCS is electrically connected with the second chip select pin CS, the first clock pin SCK is electrically connected with the second clock pin CLK, the first master slave in pin SDI is electrically connected with the second master slave in pin MOSI, and the first master slave out pin SDO is electrically connected with the second master slave out pin MISO; The universal substrate UBB 23, the UBB 23 is electrically connected with the second end of the first chip 21; the first end of the first chip 21 and the second end of the first chip 21 are different types of ports.

[0022] Here, since the first end of the first chip 21 and the second end of the first chip 21 can be different types of ports, the first end of the first chip 21 and the second end of the first chip 21 can be used to transmit different types of signals, which are not limited here.

[0023] In addition, in some embodiments, the above-mentioned second chip 22 does not integrate a universal serial bus USB master controller.

[0024] Based on the structure of the above-mentioned server, the first chip 21 receives the first type signal transmitted by the first object through one end of the first chip 21, the first chip 21 converts the first type signal into the second type signal, and transmits the second type signal to the second object through the other end of the first chip 21.

[0025] In some embodiments, in the case that the first object comprises the second chip 22 and the second object comprises the UBB 23, the one end of the first chip 21 is the first end, and the other end of the first chip 21 is the second end; or, in the case that the first object comprises the UBB 23 and the second object comprises the second chip 22, the one end of the first chip 21 is the second end, and the other end of the first chip 21 is the first end, which is not limited here.

[0026] It also needs to be explained that the above-mentioned first type signal and the second type signal can be different types of signals, and the specific types of the first type signal and the second type signal can be determined according to the specific transmission object, which is not limited here.

[0027] It is conceivable that, in the process of the second chip 22 transmitting a signal to the UBB 23 through the first chip 21, the first chip 21 can receive a first type signal transmitted by the second chip 22 through the first end of the first chip 21, the first chip 21 can convert the first type signal into a second type signal, and can transmit the second type signal to the UBB 23 through the second end of the first chip 21.

[0028] Likewise, in the process of the UBB 23 transmitting a signal to the second chip 22 through the first chip 21, the first chip 21 can receive a first type signal transmitted by the UBB 23 through the second end of the first chip 21, the first chip 21 can convert the first type signal into a second type signal, and can transmit the second type signal to the second chip 22 through the second end of the first chip 21.

[0029] Based on the server provided by the embodiments of the present disclosure, the first chip, the second chip and the UBB can be arranged in the server, wherein the first end of the first chip can include a first chip select pin, a first clock pin, a first master-in-slave-out pin and a first master-out-slave-in pin, the second chip can include a second chip select pin, a second clock pin, a second master-out-slave-in pin and a second master-in-slave-out pin, and the first chip select pin is electrically connected with the second chip select pin, the first clock pin is electrically connected with the second clock pin, the first master-in-slave-out pin is electrically connected with the second master-out-slave-in pin, the first master-out-slave-in pin is electrically connected with the second master-in-slave-out pin, and the UBB is electrically connected with the second end of the first chip. In this way, the first chip can realize the communication connection between the first object and the second object by converting the first type signal supported by the first object into the second type signal supported by the second object, that is, realize the fast communication connection between the second chip and the UBB, avoid the situation that the chip cannot establish fast communication connection with the UBB due to the chip not integrating the USB controller which can be used as the master device in the prior art, and thus the out-of-band management function of the second chip to the components in the UBB can be conveniently realized.

[0030] Since the first type signal and the second type signal are different types of signals in the embodiments of the present disclosure, in order to describe the server provided by the embodiments of the present disclosure in more detail, in some embodiments, when the first object includes the second chip 22 and the second object includes the UBB 23, the first type signal can include a serial peripheral interface (SPI) signal, and the second type signal can include a universal serial bus (USB) signal. When the first object includes the UBB 23 and the second object includes the second chip 22, the first type signal can include a USB signal, and the second type signal can include an SPI signal.

[0031] For example, assuming that the second chip involved in the embodiments of the present disclosure is a ZX1000 chip, and the first chip is a CH374F chip, at this time, if the first object is a ZX1000 chip and the second object is a UBB, the first type signal transmitted between the first object and the first chip can be a serial peripheral interface (SPI) signal, and the second type signal transmitted between the first chip and the second object is a universal serial bus (USB) signal. If the first object is a UBB and the second object is a ZX1000 chip, the first type signal transmitted between the first object and the first chip can be a USB signal, and the second type signal transmitted between the first chip and the second object is an SPI signal.

[0032] In this embodiment, the SPI signal and the USB signal can be converted to each other during the communication between the second chip and the UBB, which improves the communication speed between the second chip and the UBB compared with the communication mode through the I2C in the prior art, and realizes the fast communication connection between the second chip and the UBB.

[0033] In order to better realize the fast communication connection between the second chip and the UBB and ensure the stability and integrity of the signal transmission between them, in some embodiments, as shown in Figure 3 The server can further include a plurality of first resistors 31.

[0034] Based on this, the first chip select pin SCS and the second chip select pin CS are electrically connected through the first resistor 31; the first clock pin SCK and the second clock pin CLK are electrically connected through the first resistor 31; the first master-in-slave-out pin SDI and the second master-out-slave-in pin MOSI are electrically connected through the first resistor 31, and the first master-out-slave-in pin SDO and the second master-in-slave-out pin MISO are electrically connected through the first resistor 31.

[0035] Each of the first resistors 31 can be a resistor with a resistance of 33 ohms, which is not limited here.

[0036] It is conceivable that, due to the first chip 21, the first end is provided with the first chip selection pin SCS, the first clock pin SCK, the first master-slave data input pin SDI and the first master-slave data output pin SDO, the second chip 22 is provided with the second chip selection pin CS, the second clock pin CLK, the second master-slave data output pin MOSI and the second master-slave data input pin MISO. In this way, the first chip selection pin SCS and the second chip selection pin CS are electrically connected through the first resistor 31, and the first resistor 31 is used for impedance matching of the line formed by the first chip selection pin SCS and the second chip selection pin CS; the first clock pin SCK and the second clock pin CLK are electrically connected through the first resistor 31, and the first resistor 31 is used for impedance matching of the line formed by the first clock pin SCK and the second clock pin CLK; the first master-slave data input pin SDI and the second master-slave data output pin MOSI are electrically connected through the first resistor 31, and the first resistor 31 is used for impedance matching of the line formed by the first master-slave data input pin SDI and the second master-slave data output pin MOSI, and the first master-slave data output pin SDO and the second master-slave data input pin MISO are electrically connected through the first resistor 31, and the first resistor 31 is used for impedance matching of the line formed by the first master-slave data output pin SDO and the second master-slave data input pin MISO.

[0037] In this way, impedance matching can be achieved by connecting one resistor in series between one pin in the first end of the first chip and one pin in the second chip, so as to ensure that the energy of the transmission signal can be maximally absorbed during the transmission of the transmission signal from the source end to the load end, avoid the reflection of the transmission signal, and further ensure the integrity and stability of the transmission signal during the transmission process.

[0038] In addition, in some embodiments, as shown in Figure 3 The server provided by the embodiments of the present disclosure can further include a power supply network P3V3_STBY and a plurality of second resistors 32.

[0039] In this way, the first chip selection pin SCS and the power supply network P3V3_STBY are electrically connected through the second resistor 32, and the second chip selection pin CS and the power supply network P3V3_STBY are electrically connected through the first resistor 31 and the second resistor 32; The first clock pin SCK and the power supply network P3V3_STBY are electrically connected through the second resistor 32, and the second clock pin CLK and the power supply network P3V3_STBY are electrically connected through the first resistor 31 and the second resistor 32; The first master-slave data input pin SDI and the power supply network P3V3_STBY are electrically connected through the second resistor 32, and the second master-slave data output pin MOSI and the power supply network P3V3_STBY are electrically connected through the first resistor 31 and the second resistor 32; The first main out slave in pin SDO is electrically connected with the power network P3V3_STBY through the second resistor 32, and the second main in slave out pin MISO is electrically connected with the power network P3V3_STBY through the first resistor 31 and the second resistor 32.

[0040] Here, the second resistor 32 can be a resistor with a resistance of 2.2k, which is not specifically limited here.

[0041] It is conceivable that, on the basis that the first chip 21 is provided with the first chip select pin SCS, the first clock pin SCK, the first main in slave out pin SDI and the first main out slave in pin SDO, and the second chip 22 is provided with the second chip select pin CS, the second clock pin CLK, the second main out slave in pin MOSI and the second main in slave out pin MISO, the first chip select pin SCS can be electrically connected with the power network P3V3_STBY through the second resistor 32, and the second chip select pin CS can be electrically connected with the power network P3V3_STBY through the first resistor 31 and the second resistor 32; then the first clock pin SCK can be electrically connected with the power network P3V3_STBY through the second resistor 32, and the second clock pin CLK can be electrically connected with the power network P3V3_STBY through the first resistor 31 and the second resistor 32; and the first main in slave out pin SDI can be electrically connected with the power network P3V3_STBY through the second resistor 32, and the second main out slave in pin MOSI can be electrically connected with the power network P3V3_STBY through the first resistor 31 and the second resistor 32; and the first main out slave in pin SDO can be electrically connected with the power network P3V3_STBY through the second resistor 32, and the second main in slave out pin MISO can be electrically connected with the power network P3V3_STBY through the first resistor 31 and the second resistor 32.

[0042] In this embodiment, by setting the second resistor on each line connected between the first end of the first chip and the second chip, the corresponding line can be pulled up to the power network, so that each line is in a determined and stable high level state in the idle state or initialization, thereby preventing the miscommunication caused by the uncertain pin state, and realizing the accurate and rapid communication between the second chip and the first chip.

[0043] In order to comprehensively and in detail describe the server provided by the embodiments of the present disclosure, in some embodiments, as shown in Figure 3 The server provided by the embodiments of the present disclosure can further include: The choke coil 33 has a first end electrically connected with the second end of the first chip 21, and a second end electrically connected with the UBB 23. The choke coil 33 is used to filter the common mode noise of the transmission signal between the first chip 21 and the UBB 23.

[0044] It is conceived that the choke 33 can be arranged in the server, and the first end of the choke 33 is electrically connected with the second end of the first chip 21, and the second end of the choke 33 is electrically connected with the UBB 23. In this way, the choke 33 can acquire the transmission signal between the first chip 21 and the UBB 23, and filter the common-mode noise in the transmission signal.

[0045] In this embodiment, the choke can be arranged in the server, and the first end of the choke is electrically connected with the second end of the first chip, and the second end of the choke can be electrically connected with the general substrate. In this way, the choke can be used to filter the common-mode noise of the transmission signal between the first chip and the general substrate, so as to effectively reduce the common-mode interference.

[0046] In addition, in some embodiments, as shown in Figure 3 The first chip 21 can further include an interrupt pin INT, and the second chip 22 can further include a general input / output pin GPIO. Here, the interrupt pin INT of the first chip 21 is electrically connected with the general input / output pin GPIO of the second chip 22.

[0047] Based on this, in the case that the first chip 21 detects an interrupt event, the interrupt request signal is transmitted from the interrupt pin INT of the first chip 21 to the general input / output pin GPIO of the second chip 22.

[0048] The interrupt event can be a related event that needs to pause the current task and turn to process a specific event in response to an external or internal signal.

[0049] In addition, since the low level is effective between the interrupt pin INT of the first chip 21 and the general input / output pin GPIO of the second chip 22 in the embodiments of the present disclosure, the interrupt request signal can include a low level signal, which is not limited here.

[0050] It is conceived that in the case that the first chip 21 detects an interrupt event, the interrupt request signal can be transmitted from the interrupt pin INT arranged in the first chip 21 to the general input / output pin GPIO arranged in the second chip 22, so as to request the second chip 22 to pause the current service and preferentially process the interrupt event.

[0051] In addition, it should be noted that, as shown in Figure 3 Since the server provided by the embodiments of the present disclosure can further include a third resistor 34 and a power supply network P3V3_STBY. Here, the third resistor 34 can be a resistor with a resistance of 33 ohm, which is not limited here.

[0052] In this way, the third resistor 34 can be connected in series between the power supply network P3V3_STBY and the interrupt pin INT of the first chip 21, and connected in series between the power supply network P3V3_STBY and the general input / output pin GPIO of the second chip 22.

[0053] It should be further noted that the interrupt pin INT of the first chip 21 can not be connected, but a read operation can be implemented by querying an interrupt flag register, which is slower.

[0054] In this embodiment, by providing the interrupt pin in the first chip, the general input / output pin in the second chip, and electrically connecting the interrupt pin and the general input / output pin, when the first chip detects an urgent interrupt event such as a device failure, a low-level signal can be transmitted through the interrupt pin of the first chip and the general input / output pin of the second chip, so that the interrupt event can be processed in time, and the idle waiting time of the interrupt event can be effectively reduced.

[0055] In order to accurately and in detail describe the server provided by the embodiments of the present disclosure, in some embodiments, as shown in Figure 3 The first chip 21 can further include a state indication pin ACT, and the state indication pin ACT of the first chip is electrically connected with the light emitting element 35.

[0056] Here, the state indication pin ACT of the first chip 21 can determine the working state of the first chip 21 through the state of the externally connected light emitting element 35. The light emitting element 35 can be a light emitting diode, which is not specifically limited here.

[0057] Based on this, when the first chip 21 controls the state indication pin ACT to output a first active signal, the light emitting element 35 is turned on and emits light.

[0058] The first active signal can be a low-level signal, which is not specifically limited here.

[0059] It can be conceived that when the first chip 21 controls the state indication pin ACT to output a low-level signal, the light emitting element 35 can be turned on and emit light, and at this time, the working state of the first chip 21 is a normal working state.

[0060] In addition, in some embodiments, when the first chip 21 controls the state indication pin ACT to output a second active signal, the light emitting element 35 is turned off and extinguished.

[0061] The second active signal can be a high-level signal, which is not specifically limited here.

[0062] It is conceivable that in the case that the first chip 21 controls the state indication pin ACT to output a high level signal, the light emitting element 35 can be turned off, at this time, the working state of the first chip 21 is an abnormal working state.

[0063] In this embodiment, by setting a light emitting element outside the state indication pin in the first chip, the working state of the first chip can be directly determined through the light emitting state or the off state of the light emitting element, which facilitates timely determination of the abnormality of the first chip.

[0064] In some embodiments, the first chip 21 can be integrated with a first hub, and the first hub can include a plurality of ports, which can collectively constitute the second end of the first chip 21. In this way, when the first chip 21 is used as a USB controller of the host device, a plurality of USB devices can be connected.

[0065] In this embodiment, by setting a hub in the first chip, the first chip can be connected to a plurality of devices, thereby significantly improving the device access capability of the first chip.

[0066] In order to completely and in detail describe the server provided by the embodiments of the present disclosure, in some embodiments, as shown in Figure 4 The UBB 23 can include: A second hub 41, a first end of the second hub 41 is electrically connected to the second end of the first chip 21; A baseboard management controller BMC 42, the BMC 42 is electrically connected to the second end of the second hub 41; Based on this, in the case that the first object includes the UBB 23 and the second object includes the second chip 22, the device information is obtained by the BMC 42, and the device information is transmitted to the first chip 21 through the second hub 41 by the BMC 42 in the form of the first type signal.

[0067] The device information can include UBB related information, such as sensor information including temperature information, which is not limited here.

[0068] It is conceivable that by setting the second hub 41 and the BMC 42 in the UBB 23, and by setting the first end of the second hub 41 to be electrically connected to the second end of the first chip 21 and the second end of the BMC 42 to be electrically connected to the second end of the second hub 41, in the process of transmitting data from the UBB 23 to the second chip 22, the device information can be obtained by the BMC 42, and the device information is transmitted to the first chip 21 by the BMC 42 in the form of the first type signal through the second hub 41.

[0069] In this embodiment, the second hub and the BMC can be arranged in the UBB, and the first end of the second hub is electrically connected with the second end of the first chip, and the first end of the BMC is connected with the first chip, so that the UBB can transmit the device information acquired by the BMC through the first chip, and the monitoring and management of the components on the UBB board by the second chip are facilitated.

[0070] It should be noted that in the embodiments of the present disclosure, the UBB can not only transmit the device information to the second chip through the first chip, but also transmit the fault monitoring information to the first device through the first chip. Based on this, in order to comprehensively and in detail describe the signal transmission method provided by the embodiments of the present disclosure, in one embodiment of the present disclosure, as shown in Figure 4 The UBB 23 involved in the embodiments of the present disclosure can further include: a multiplexer 43, a first end of the multiplexer 43 being electrically connected with a second end of the second hub 41; a conversion component 44, a first end of the conversion component 44 being electrically connected with a second end of the multiplexer 43; Based on this, in the case that the first object includes the UBB 23 and the second object includes the second chip 22, the fault monitoring information is acquired by the conversion component 44, and is transmitted to the first chip 21 in the form of the first type signal through the conversion component 44, the multiplexer 43 and the second hub 41.

[0071] It can be conceived that the multiplexer 43 and the conversion component 44 can be arranged in the UBB 23, and the first end of the multiplexer 43 is electrically connected with the second end of the second hub 41, and the conversion component 44 is electrically connected with the second end of the multiplexer 43. In this way, in the process of transmitting the signal from the UBB 23 to the second chip 22 through the first chip 21, the fault monitoring information can be acquired by the conversion component 44, and the fault monitoring information can be transmitted to the first chip 21 in the form of the first type signal through the conversion component 44, the multiplexer 43 and the second hub 41.

[0072] It should be noted that the above-mentioned fault monitoring information can be acquired by the conversion component 44 from the OAM component connected with the conversion component 44, which can be specifically seen from Figure 4 Each conversion component 44 is connected with an OAM component, which will not be described in detail here.

[0073] In this embodiment, the UBB provided by the embodiments of the present disclosure can include a multiplexer and a conversion component, and a first end of the multiplexer is electrically connected to a second end of the second hub, and a first end of the conversion component is electrically connected to a second end of the multiplexer. In this way, the second chip can realize fault monitoring of the UBB through the circuit constructed between the first chip, the second hub, the multiplexer, and the conversion component, facilitating timely management of the UBB by the second chip.

[0074] Based on any of the foregoing servers, the embodiments of the present disclosure further provide a signal transmission method, which can specifically be as shown in the following Figure 5 The execution subject of the method can be any of the foregoing servers, and the method can specifically include the following steps: S510, obtaining, by one end of a first chip, a first type signal transmitted by a first object.

[0075] S520, converting, by the first chip, the first type signal into a second type signal.

[0076] S530, transmitting, by another end of the first chip, the second type signal to a second object.

[0077] The server can include the first object, the second object, and the first chip.

[0078] In some embodiments, if the first object is a second chip and the second object includes a UBB, the one end of the first chip can be a first end, and correspondingly, the other end of the first chip can be a second end. If the first object includes a UBB and the second object includes a second chip, the one end of the first chip is a second end, and correspondingly, the other end of the first chip is a first end.

[0079] It should be noted that the first end of the first chip can include a first chip select pin, a first clock pin, a first master out slave in pin, and a first master in slave out pin, the second chip includes a second chip select pin, a second clock pin, a second master in slave out pin, and a second master out slave in pin, the first chip select pin is electrically connected to the second chip select pin, the first clock pin is electrically connected to the second clock pin, the first master out slave in pin is electrically connected to the second master in slave out pin, and the first master in slave out pin is electrically connected to the second master out slave in pin; the UBB is electrically connected to the second end of the first chip, and the first end of the first chip and the second end of the first chip are different types of ports.

[0080] In addition, the first type signal and the second type signal can be different types of signals. For example, assuming that the second chip is a ZX1000 chip and the first chip is a CH374F chip, if the first object includes the second chip and the second object includes a UBB, the first type signal can be an SPI signal, and the second type signal can be a USB signal. Correspondingly, if the first object includes a UBB and the second object includes the second chip, the first type signal can be a USB signal, and the second type signal can be an SPI signal.

[0081] Specifically, in the process of transmitting the signal from the second chip to the UBB through the first chip, the first chip can receive the first type signal transmitted by the second chip through the first end of the first chip, the first chip can convert the first type signal into the second type signal, and the first chip can transmit the second type signal to the UBB through the second end of the first chip.

[0082] Similarly, in the process of transmitting the signal from the UBB to the second chip through the first chip, the first chip can receive the first type signal transmitted by the UBB through the second end of the first chip, the first chip can convert the first type signal into the second type signal, and the first chip can transmit the second type signal to the second chip through the second end of the first chip.

[0083] Based on the signal transmission method provided by the embodiments of the present disclosure, whether in the process of transmitting the signal from the second chip to the UBB through the first chip or in the process of transmitting the signal from the UBB to the second chip through the first chip, the first chip can convert different types of signals, realize fast communication connection between the second chip and the UBB, and avoid the situation that the chip cannot establish fast communication connection with the UBB because the chip does not integrate a USB controller that can serve as a master device in the prior art, thereby conveniently realizing the out-of-band management function of the second chip on the components in the UBB.

[0084] In order to describe the signal transmission method provided by the embodiments of the present disclosure in detail, in an embodiment of the present disclosure, the signal transmission method provided by the embodiments of the present disclosure can further include the following steps: sending an address code and a command code from the second chip to the first chip; The address code can be used to indicate the starting address of the execution operation of the second chip, and the command code can be used to indicate the execution operation of the second chip. The execution operation of the second chip can include a read operation or a write operation.

[0085] It is conceivable that, in the process of the second chip transmitting signals to the UBB through the first chip, or in the process of the UBB transmitting signals to the second chip through the first chip, the address code and the command code need to be sent from the second chip to the first chip to indicate the execution operation of the second chip and the start address of the execution operation of the second chip, so as to realize the fast communication connection between the second chip and the UBB.

[0086] Based on this, if the execution operation of the second chip includes a write operation, the first object can include the second chip. The S410 can specifically include the following steps: transmit the to-be-written data from the second chip to the first chip; receive the to-be-written data transmitted by the second chip through the first chip, and store the to-be-written data to the first storage address.

[0087] The first type of signal can include the to-be-written data, and the first storage address can be determined based on the start address of the execution operation of the second chip.

[0088] Specifically, if the execution operation of the second chip includes a write operation, it indicates that the transmission direction at this time is that the second chip transmits data to the universal substrate through the first chip, and the first object is the second chip. Based on this, the to-be-written data can be transmitted from the second chip to the first chip, and the to-be-written data transmitted by the second chip can be received through the first chip, and the to-be-written data can be stored to the first storage address through the first chip.

[0089] Correspondingly, if the execution operation of the second chip is a read operation, the second object can include the second chip. The S430 can specifically include the following steps: read the to-be-read data from the second storage address through the first chip; transmit the to-be-read data from the first chip to the second chip.

[0090] The second type of signal can include the to-be-read data.

[0091] Specifically, if the execution operation of the second chip is a read operation, the transmission direction at this time is that the UBB transmits to the second chip through the first chip, that is, the second object can include the second chip. In this way, the universal server can read the to-be-read data from the second storage address through the first chip, and can transmit the to-be-read data from the first chip to the second chip.

[0092] In one example, the second chip can send a byte of address code in a preset manner for specifying a start address of a read / write operation of the second chip, the preset manner being associated with a signal type output by the second chip. If the transmission signal output by the second chip is an SPI signal, the preset manner can be an SPI output manner, which will not be described in detail herein. Then, the second chip can send a byte of command code for indicating an execution operation of the second chip. If the execution operation of the second chip is a read operation, the corresponding command code can be COH. If the first execution operation is a write operation, the corresponding command code can be 80H.

[0093] Based on this, if the execution operation of the second chip is a write operation, the second chip can send a byte of to-be-written data. The first chip can receive the to-be-written data and save it to a specified address (determined based on the start address of the read / write operation of the second chip), and the subsequent address can be automatically incremented by 1. When the second chip continues to send a plurality of bytes of to-be-written data, the first chip can process them in sequence until the second chip disables the chip selection, i.e., ends the current write operation.

[0094] If the execution operation of the second chip is a read operation, the first chip can read a byte of to-be-read data from a specified address and output the to-be-read data to the second chip, and then the address can be automatically incremented by 1. In this way, the second chip can receive and save the to-be-read data. Then, the first chip can continue to read to-be-read data from the next address and output it to the second chip until the second chip disables the chip selection, i.e., ends the current read operation.

[0095] In this embodiment, the second chip can send an address code and a command code to the first chip to indicate the execution operation of the second chip and the start address of the execution operation of the second chip. In this way, the communication connection between the second chip and the first chip can be effectively realized according to the execution operation of the second chip indicated by the command code and the start address of the execution operation of the second chip indicated by the address code, and the fast communication connection between the second chip and the UBB can be effectively realized.

[0096] In order to describe the signal transmission method provided by the embodiments of the present disclosure in detail, in one embodiment of the present disclosure, the signal transmission method provided by the embodiments of the present disclosure can specifically include the following steps: In the case where the first chip detects an interrupt event, an interrupt request signal is transmitted from the interrupt pin of the first chip to the general input / output pin of the second chip.

[0097] The interrupt event can be a related event that needs to pause the current task and switch to processing a specific event in response to an external or internal signal. In addition, the interrupt request signal can be a low-level signal for requesting the second chip to prioritize processing the interrupt event.

[0098] Thus, in the case that the first chip detects an interrupt event, the server can transmit an interrupt request signal to the general input / output pin of the second chip through the interrupt pin of the first chip, so as to request the second chip to suspend the current service and preferentially process the interrupt event.

[0099] In this embodiment, in the case that the first chip in the server detects an urgent interrupt event such as a device failure, a low-level signal can be transmitted through the interrupt pin of the first chip and the general input / output of the second chip, so as to timely process the interrupt event and effectively reduce the idle waiting time of the interrupt event.

[0100] In addition, in one embodiment of the present disclosure, the signal transmission method provided by the embodiment of the present disclosure can further include the following steps: In the case that the first chip controls the state indication pin to output a first active signal, the light-emitting element connected with the state indication pin is turned on and brightened.

[0101] The first active signal can be a low-level signal, which is not limited herein. In addition, the first chip can include the state indication pin.

[0102] Thus, in the case that the first chip controls the state indication pin to output a low-level signal, the light-emitting element can be turned on and brightened, and at this time, the working state of the first chip is a normal working state.

[0103] Based on this, the signal transmission method provided by the embodiment of the present disclosure can further include the following steps: In the case that the first chip controls the state indication pin to output a second active signal, the light-emitting element connected with the state indication pin is turned off and extinguished.

[0104] The second active signal can be a high-level signal, which is not limited herein.

[0105] Thus, in the case that the first chip controls the state indication pin to output a high-level signal, the light-emitting element can be turned off and extinguished, and at this time, the working state of the first chip is an abnormal working state.

[0106] In this embodiment, the working state of the first chip can be directly determined by the light-emitting state or the extinguishing state of the light-emitting element connected with the state indication pin in the first chip, so as to facilitate timely determination of the abnormality of the first chip.

[0107] In order to comprehensively and in detail describe the signal transmission method provided by the embodiment of the present disclosure, in one embodiment of the present disclosure, in the case that the first object includes a UBB and the second object includes a second chip, the UBB includes a second hub and a baseline management controller BMC.

[0108] Thus, before the first type signal transmitted by the first object is acquired by the first chip, the method further comprises: acquiring the device information by the BMC; transmitting the device information by the BMC to the first chip through the second hub in the form of the first type signal.

[0109] Thus, during the process that the UBB transmits data to the second chip, the device information can be acquired by the BMC, and the device information is transmitted by the BMC to the first chip through the second hub in the form of the first type signal.

[0110] In this embodiment, based on the communication line constituted by the first chip, the second hub and the UBB in the server, the UBB can transmit the device information acquired by the BMC through the first chip, so that the monitoring and management of the components on the UBB board by the second chip are facilitated.

[0111] In one embodiment of the present disclosure, when the first object comprises the UBB and the second object comprises the second chip, the UBB can comprise the second hub, the multiplexer and the conversion component.

[0112] Thus, before the first type signal transmitted by the first object is acquired by the first chip, the method further comprises: acquiring the fault monitoring information by the conversion component; transmitting the fault monitoring information by the conversion component to the first chip through the multiplexer and the second hub in the form of the first type signal.

[0113] Specifically, during the process that the UBB transmits signals to the second chip through the first chip, the fault monitoring information can be acquired by the conversion component, and the fault monitoring information is transmitted by the conversion component to the first chip through the multiplexer and the second hub in the form of the first type signal.

[0114] In this embodiment, the fault monitoring of the UBB by the second chip can be realized through the line constructed among the first chip, the second hub, the multiplexer and the conversion component, so that the timely management of the UBB by the second chip is facilitated.

[0115] The embodiment of the present application provides a computer program product or a computer program, which comprises computer instructions stored in a computer readable storage medium. A processor of a computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions, so that the computer device executes the signal transmission method.

[0116] The embodiment of the present application provides a computer readable storage medium storing executable instructions, wherein the executable instructions are stored, and when the executable instructions are executed by a processor, the processor executes the signal transmission method provided by the embodiment of the present application.

[0117] In some embodiments, the computer readable storage medium can be FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disc, or CD-ROM memory, and the like; or various devices including one or any combination of the above storage.

[0118] In some embodiments, the executable instructions can be in the form of programs, software, software modules, scripts or codes, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and can be deployed in any form, including being deployed as independent programs or as modules, components, subroutines or other units suitable for use in a computing environment.

[0119] As an example, the executable instructions can but not necessarily correspond to files in a file system, can be stored in part of a file storing other programs or data, for example, stored in one or more scripts in a Hyper Text Markup Language (HTML) document, stored in a single file dedicated to the program in question, or stored in multiple cooperative files (for example, files storing one or more modules, subroutines or code portions).

[0120] As an example, the executable instructions can be deployed to execute on one computing device, or on multiple computing devices located at one site, or on multiple computing devices distributed at multiple sites and interconnected through a communication network.

[0121] Figure 6 A structural schematic diagram of an electronic device provided by the embodiment of the present application is shown in the figure. Figure 6 As shown in the figure, the electronic device 60 includes a processor 601 and a memory 602 connected with the processor 601 in communication; the memory 602 stores instructions executable by the processor 601. The instructions are executed by the processor 601 to enable the processor 601 to execute: acquire a first type signal transmitted by a first object through one end of a first chip; convert the first type signal into a second type signal through the first chip; transmit the second type signal to a second object through the other end of the first chip; The server includes the first object and the second object; in the case that the first object includes a second chip and the second object includes a universal substrate (UBB), one end of the first chip is a first end and the other end of the first chip is a second end; or, in the case that the first object includes the UBB and the second object includes the second chip, one end of the first chip is the second end and the other end of the first chip is the first end. The first end of the first chip includes a first chip select pin, a first clock pin, a first master-in slave-out pin and a first master-out slave-in pin, the second chip includes a second chip select pin, a second clock pin, a second master-out slave-in pin and a second master-in slave-out pin, the first chip select pin is electrically connected with the second chip select pin, the first clock pin is electrically connected with the second clock pin, the first master-in slave-out pin is electrically connected with the second master-out slave-in pin, and the first master-out slave-in pin is electrically connected with the second master-in slave-out pin; the UBB is electrically connected with the second end of the first chip, and the first end of the first chip and the second end of the first chip are different types of ports.

[0122] The electronic device and the corresponding signal transmission method provided by the above embodiments belong to the same concept, and the specific implementation process is detailed in the method embodiments, which will not be repeated here.

[0123] In actual application, the electronic device 60 can further include at least one network interface 603. The various components in the electronic device 60 are coupled together by a bus system 604. It can be understood that the bus system 604 is used to realize the connection and communication between the components. In addition to including a data bus, the bus system 604 also includes a power bus, a control bus and a status signal bus. However, for the purpose of clear illustration, all kinds of buses are marked as the bus system 604 in the Figure 6 . The number of the processor 601 can be at least one, and the number of the memory 602 can be at least one. The network interface 603 is used for wired or wireless communication between the electronic device 60 and other devices.

[0124] The memory 602 in the embodiments of the present disclosure is used to store various types of data to support the operation of the electronic device 60.

[0125] The method disclosed by the embodiments of the present disclosure can be applied to the processor 601 or implemented by the processor 601. The processor 601 can be an integrated circuit chip having a signal processing capability. In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in the processor 601 or an instruction in the form of software. The processor 601 described above can be a general processor, a digital signal processor (DSP), or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, etc. The processor 601 can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the present disclosure. The general processor can be a microprocessor or any conventional processor, etc. In combination with the steps of the method disclosed in the embodiments of the present disclosure, the execution can be directly completed by a hardware decoding processor or a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, and the storage medium is located in the memory 602. The processor 601 reads the information in the memory 602 and combines the hardware to complete the steps of the above signal transmission method.

[0126] In some embodiments, the electronic device 60 can be implemented by one or more application specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors (Microprocessors), or other electronic elements, for executing the above method.

[0127] It should be understood that the steps can be reordered, added, or deleted using the various forms of flow shown above. For example, each step described in the present disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved, and the present disclosure is not limited herein.

[0128] In the above description, "some embodiments" are related to a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0129] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the disclosure is for the purpose of describing the embodiments of the disclosure only and is not intended to be limiting of the disclosure.

[0130] It should be understood that, in various embodiments of the disclosure, the magnitude of the serial number of each implementation process does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the disclosure.

[0131] In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the disclosure, the meaning of "a plurality of" is two or more, unless otherwise expressly and specifically limited.

[0132] The above is only a specific implementation of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the disclosure, which should be covered within the protection scope of the disclosure. Therefore, the protection scope of the disclosure should be subject to the protection scope of the claims.

Claims

1. A server, characterized by The server comprises: a first chip, a first end of the first chip comprising a first chip select pin, a first clock pin, a first master-in-slave-out pin and a first master-out-slave-in pin; a second chip, the second chip comprising a second chip select pin, a second clock pin, a second master-out-slave-in pin and a second master-in-slave-out pin, the first chip select pin being electrically connected with the second chip select pin, the first clock pin being electrically connected with the second clock pin, the first master-in-slave-out pin being electrically connected with the second master-out-slave-in pin, and the first master-out-slave-in pin being electrically connected with the second master-in-slave-out pin; a universal base board (UBB) electrically connected with a second end of the first chip; the first end of the first chip and the second end of the first chip being different types of ports; the first chip receiving a first type signal transmitted by a first object through one end of the first chip, the first chip converting the first type signal into a second type signal, and transmitting the second type signal to a second object through another end of the first chip; wherein, in the case that the first object comprises the second chip and the second object comprises the UBB, the one end of the first chip is the first end and the other end of the first chip is the second end; or, in the case that the first object comprises the UBB and the second object comprises the second chip, the one end of the first chip is the second end and the other end of the first chip is the one end.

2. The server of claim 1, wherein, The server further comprises a plurality of first resistors; the first chip select pin and the second chip select pin being electrically connected through the first resistors, the first clock pin and the second clock pin being electrically connected through the first resistors, the first master-in-slave-out pin and the second master-out-slave-in pin being electrically connected through the first resistors, and the first master-out-slave-in pin and the second master-in-slave-out pin being electrically connected through the first resistors.

3. The server of claim 2, wherein, The server further comprises a power supply network and a plurality of second resistors; the first chip select pin being electrically connected with the power supply network through the second resistors, the second chip select pin being electrically connected with the power supply network through the first resistors and the second resistors; the first clock pin being electrically connected with the power supply network through the second resistors, the second clock pin being electrically connected with the power supply network through the first resistors and the second resistors; the first master-in-slave-out pin being electrically connected with the power supply network through the second resistors, the second master-out-slave-in pin being electrically connected with the power supply network through the first resistors and the second resistors; the first master-out-slave-in pin being electrically connected with the power supply network through the second resistors, the second master-in-slave-out pin being electrically connected with the power supply network through the first resistors and the second resistors.

4. The server of claim 3, wherein, The server further comprises: a choke, a first end of the choke being electrically connected with a second end of the first chip, and a second end of the choke being electrically connected with the UBB; the choke being used for filtering common mode noise of transmission signals between the first chip and the UBB.

5. The server of any one of claims 1 to 4, characterized in that, The first chip further comprises an interrupt pin, and the second chip further comprises a general input / output pin, the interrupt pin of the first chip being electrically connected to the general input / output pin of the second chip. In the case that the first chip detects an interrupt event, the interrupt pin is controlled by the first chip to transmit an interrupt request signal to the general input / output pin of the second chip.

6. The server of any one of claims 1 to 4, wherein, The first chip further comprises a state indication pin, and the state indication pin of the first chip is electrically connected to a light-emitting element. In the case that the first chip controls the state indication pin to output a first active signal, the light-emitting element is turned on and brightened.

7. The server of claim 6, wherein, In the case that the first chip controls the state indication pin to output a second active signal, the light-emitting element is turned off and extinguished.

8. The server of any one of claims 1 to 4, wherein, The first chip internally integrates a first hub, and the first hub comprises a plurality of ports which collectively constitute a second end of the first chip.

9. The server of any one of claims 1 to 4, wherein, The UBB comprises: a second hub, a first end of the second hub being electrically connected to a second end of the first chip; a baseboard management controller (BMC), the BMC being electrically connected to a second end of the second hub; In the case that the first object comprises the UBB and the second object comprises the second chip, device information is acquired by the BMC and transmitted by the BMC to the first chip through the second hub in the form of a first type signal.

10. The server of claim 9, wherein, The UBB further comprises: a multiplexer, a first end of the multiplexer being electrically connected to a second end of the second hub; a conversion component, a first end of the conversion component being electrically connected to a second end of the multiplexer; The server is configured to: In the case that the first object comprises the UBB and the second object comprises the second chip, fault monitoring information is acquired by the conversion component and transmitted by the conversion component to the first chip through the multiplexer and the second hub in the form of a first type signal.

11. The server of any one of claims 1 to 4, wherein, The second chip does not integrate a universal serial bus (USB) master controller.

12. The server of any one of claims 1-4, wherein, In the case that the first object comprises the second chip and the second object comprises the UBB, the first type signal comprises a serial peripheral interface (SPI) signal, and the second type signal comprises a USB signal. In the case that the first object comprises the UBB and the second object comprises the second chip, the first type signal comprises the USB signal, and the second type signal comprises the SPI signal.

13. A signal transmission method, characterized by, The method is applied to a server, and the method comprises: acquiring, by one end of a first chip, a first type signal transmitted by a first object; converting, by the first chip, the first type signal into a second type signal; transmitting, by another end of the first chip, the second type signal to a second object; and transmitting, by the first chip, the second type signal to the second object. The server includes the first object and the second object; in the case that the first object includes a second chip and the second object includes a universal substrate (UBB), one end of the first chip is a first end and the other end of the first chip is a second end; or in the case that the first object includes the UBB and the second object includes the second chip, one end of the first chip is the second end and the other end of the first chip is the first end; The first end of the first chip includes a first chip select pin, a first clock pin, a first master-in-slave-out pin and a first master-out-slave-in pin, the second chip includes a second chip select pin, a second clock pin, a second master-out-slave-in pin and a second master-in-slave-out pin, the first chip select pin is electrically connected with the second chip select pin, the first clock pin is electrically connected with the second clock pin, the first master-in-slave-out pin is electrically connected with the second master-out-slave-in pin, and the first master-out-slave-in pin is electrically connected with the second master-in-slave-out pin; the UBB is electrically connected with the second end of the first chip, and the first end of the first chip and the second end of the first chip are different types of ports.

14. The method of claim 13, wherein, The method further includes: sending, by the second chip, an address code and a command code to the first chip, the address code being used to indicate a start address of an execution operation of the second chip, and the command code being used to indicate the execution operation of the second chip, the execution operation of the second chip including a read operation or a write operation; in the case that the execution operation of the second chip is the write operation, the first object includes the second chip; the first type signal transmitted by the first chip to obtain the first object includes: transmitting, by the second chip, to-be-written data to the first chip, the first type signal including the to-be-written data; receiving, by the first chip, the to-be-written data transmitted by the second chip, and storing the to-be-written data to a first storage address, the first storage address being determined based on the start address of the execution operation of the second chip; in the case that the execution operation of the second chip is the read operation, the second object includes the second chip; the second type signal transmitted by the first chip to the second object includes: reading, by the first chip, to-be-read data from a second storage address; transmitting, by the first chip, the to-be-read data to the second chip, the second type signal including the to-be-read data.

15. The method of claim 13, wherein, The method further includes: in the case that the first chip detects an interrupt event, transmitting, by the interrupt pin of the first chip, an interrupt request signal to a general input / output pin of the second chip.

16. The method of claim 13, wherein, The method further includes: in the case that the first chip controls a first active signal to be output from a state indication pin, a light-emitting element connected with the state indication pin is turned on and brightened, and the first chip includes the state indication pin.

17. The method of claim 13, wherein, The first object includes the UBB, and the second object includes the second chip; the UBB includes a second hub and a baseline management controller (BMC). Before the first type signal transmitted by the first object is acquired, the method further comprises: acquiring device information by the BMC; transmitting the device information by the BMC to the first chip in the form of the first type signal via the second hub.

18. The method of claim 13, wherein, The first object comprises the UBB, and the second object comprises the second chip; the UBB comprises a second hub, a multiplexer and a conversion component; Before the first type signal transmitted by the first object to the first chip is acquired, the method further comprises: acquiring fault monitoring information by the conversion component; transmitting the fault monitoring information by the conversion component to the first chip in the form of the first type signal via the multiplexer and the second hub.

19. An electronic device, comprising: comprise: at least one processor; and a memory connected to the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the signal transmission method of any one of claims 13 to 18.

20. A non-transitory computer-readable storage medium having stored thereon computer instructions, wherein, The computer instructions are used to enable the computer to perform the signal transmission method according to any one of claims 13 to 18.

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