Parallel arbitrary decimal interpolation module and method
Real-time data processing is achieved on the FPGA by using a parallel arbitrary fractional interpolation module, which solves the problems of real-time data processing and high hardware cost under weak hardware constraints and reduces hardware resource consumption.
Patent Information
- Application Number
- CN202510957019.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-11
- Publication Date
- 2025-11-21
AI Technical Summary
Existing technologies suffer from poor real-time data processing performance and high hardware costs under weak hardware constraints. In particular, interpolation methods in wireless communication systems require modifications to software algorithms or additional hardware resources.
A parallel arbitrary fractional interpolation module is adopted, including an interpolation point calculation submodule, an input data storage and update submodule, an input data selection submodule, and a cubic Lagrange interpolation submodule. The interpolation point calculation and data update are realized through FPGA registers, avoiding the use of FIFO or RAM cache, and the interpolation is performed using the cubic Lagrange interpolation submodule.
It enables real-time processing of input data under weak hardware constraints, reduces hardware costs, saves FPGA resources, and avoids increasing hardware costs.
Smart Images
Figure CN120994948A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of wireless communication technology, and specifically relates to a parallel arbitrary fractional interpolation module and interpolation method under weak hardware constraints. It can be used in wireless communication systems under weak hardware constraints where it is necessary to control hardware costs and improve the sampling rate of digital signals. Background Technology
[0002] A weakly constrained hardware environment refers to a situation where hardware resources are extremely limited under extreme environmental conditions, such as the lunar environment.
[0003] In wireless communication systems, interpolation is a practical technique for converting digital signals from low sampling rates to high sampling rates. Its core purpose is to adapt digital signals to systems with higher sampling rates without introducing distortion, so that they can meet the processing requirements of higher precision in the time and frequency domains.
[0004] Existing interpolation methods mainly employ fixed interpolation multiples, using analog-to-digital converters (ADCs) that can change the sampling clock frequency to perform upconversion of the sampling rate. This increases the cost of hardware. If the ADC does not support a certain frequency, the designed software interpolation algorithm also needs to be modified, further increasing costs. For example, patent application CN2021100855.3 discloses a variable symbol rate, arbitrary-path parallel input interpolation method. This method involves inputting control parameters from a host computer to determine the number P of parallel input paths, then reading the input data sequentially from RAM, calculating the error interval using a μ value generator, and then sequentially extracting P bits of data from the RAM data. The corresponding output value is then calculated based on the interval error. This method can achieve modulation with a large variation in sampling rate from low to high, even when the FPGA system's operating clock is not high. However, this invention requires pre-storing the input data in RAM, preventing real-time processing of the input data and limiting the FPGA's operating clock speed. Furthermore, using RAM to store data consumes more resources, increasing hardware costs. Summary of the Invention
[0005] The purpose of this invention is to address the shortcomings of the prior art by proposing a parallel arbitrary fractional interpolation method under weak hardware constraints, which solves the technical problems of poor real-time data processing and high hardware costs in the prior art.
[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:
[0007] A parallel arbitrary fractional interpolation module includes a first branch based on FPGA registers, consisting of an interpolation point calculation submodule; a second branch arranged in parallel with the first branch, consisting of an input data register and update submodule and a cascaded input data selection submodule; and a cubic Lagrange interpolation submodule connected to the outputs of the two branches. The output of the first branch is also connected to the input of the input data register and update submodule.
[0008] The interpolation point calculation submodule is used to calculate the location of the interpolation point at the current symbol rate;
[0009] The input data storage and update submodule is used to store the input parallel digital signal data and update each channel of data by using the interpolation point location output by the interpolation point calculation submodule.
[0010] The input data selection submodule is used to select the data required for the current interpolation from each updated data output by the input data register and update submodule;
[0011] The cubic Lagrange interpolation submodule is used to calculate the location of the interpolation point input to the submodule and select the data required for the current interpolation output of the input data selection submodule to perform cubic Lagrange interpolation on the digital signal.
[0012] A method for implementing the interpolation module according to claim 1 includes the following steps:
[0013] (1) Initialize parameters:
[0014] The current symbol rate is initialized to R. The digital signals to be interpolated are N parallel channels with a bit width of a, where N ≥ 2, and the nth digital signal is d. n ;
[0015] (2) The interpolation point calculation submodule calculates the location of the interpolation point at any decimal multiple of the current symbol rate:
[0016] Calculate the initial accumulation step size S for N channels using the current symbol rate R, and calculate the digital signal d for each channel using S. n The cumulative count value S n As d n The position of the interpolation point that is any decimal multiple;
[0017] (3) The second branch acquires the interpolation data for each digital signal to be interpolated:
[0018] The second branch passes through each digital signal to be interpolated, d. n and the position S of the interpolation point n Obtain the interpolation data A of this digital signal. n ;
[0019] (4) The cubic Lagrange interpolation submodule obtains the interpolation results of the digital signal:
[0020] The cubic Lagrange interpolation submodule uses the Lagrange interpolation coefficient matrix C and the interpolation data A of each digital signal. n Calculate the interpolation filter coefficient matrix Y n And through Y n and each digital signal d n The position of the interpolation point S n Calculate d n The interpolation result y n .
[0021] Compared with the prior art, the present invention has the following advantages:
[0022] (1) The present invention updates the registered data of each digital signal data through the second branch, and uses a portion of the updated registered data as the interpolation data of each digital signal to be interpolated. It does not require the use of FIFO or RAM to cache data, and can realize real-time processing of input digital signal data.
[0023] (2) Since the present invention only requires configuring the symbol rate, it can obtain any fractional multiple interpolation of the required sampling rate without replacing the digital-to-analog converter or changing the algorithm to add extra FPGA resources, thus saving resources and reducing hardware costs. Attached Figure Description
[0024] Figure 1 This is a schematic diagram of the interpolation module of the present invention.
[0025] Figure 2 This is a flowchart illustrating the implementation of the interpolation method of the present invention. Detailed Implementation
[0026] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.
[0027] Reference Figure 1 A parallel arbitrary fractional interpolation module includes a first branch based on an FPGA, consisting of an interpolation point calculation submodule; a second branch arranged in parallel with the first branch, consisting of an input data register and update submodule and an input data selection submodule cascaded therewith; and a cubic Lagrange interpolation submodule connected to the outputs of the two branches. The output of the first branch is also connected to the input of the input data register and update submodule.
[0028] The interpolation point calculation submodule is used to calculate the position of the interpolation point at the current symbol rate. This module calculates the initial accumulation step size based on the input symbol rate, and then calculates the interpolation position of any fractional multiple of the digital signal data for each channel based on the initial accumulation step size, thereby achieving the sampling rate required by the system. It does not require changing the adapted digital-to-analog converter or changing the algorithm structure, and does not require using more FPGA resources. The accumulation step size of the nth channel is n times the initial accumulation step size calculated from the current symbol rate. Since multiplication operations directly using the multiplication sign in the code written in the FPGA require a lot of lookup table resources and are prone to timing violations when the data is large, this example uses, but is not limited to, left shift to perform multiplication operations to save hardware resources.
[0029] The input data register and update submodule is used to register the input parallel digital signal data and update each channel of data by using the interpolation point calculated by the interpolation point calculation submodule. When the input data register and update submodule detects an overflow of the accumulated count value, it updates the registered input data. Because the interpolation data in this interpolation module is calculated in real time, it does not need to use FIFO or RAM for buffering. Therefore, this module uses, but is not limited to, a reg type shift register of a specified width in the FPGA to buffer and update the input data. When the accumulated value overflows, the new input data is placed in the low bit of the FPGA shift register, and the old data is shifted to the high bit, thereby completing the update of the registered data.
[0030] The input data selection submodule is used to select the data required for the current interpolation from each updated data output by the input data register and update submodule. Because the input data register uses a reg type shift register, a sliding window method is used to select the interpolation interval. When the integer part of the accumulated value is 0, the sliding window is in the initial position. Whenever the integer part of the accumulated count increases, the sliding window shifts to the right by a specified bit width. When the integer part of the accumulated value becomes the maximum value, the sliding window has just slid to the rightmost side of the reg type shift register.
[0031] The cubic Lagrange interpolation submodule is used to perform cubic Lagrange interpolation on digital signals based on the interpolation point location input to the submodule and the data required for the current interpolation output from the input data selection submodule. First, since the Lagrange interpolation coefficient matrix in the cubic Lagrange interpolation submodule is fixed, the calculation of the interpolation filter coefficients is implemented by left shift and signed number addition. Second, the cubic Lagrange interpolation submodule is implemented using a Farrow structure, which reduces the use of multipliers and saves hardware resources.
[0032] Reference Figure 2An implementation method for a parallel arbitrary decimal multiple interpolation module includes the following steps:
[0033] Step 1) Initialize parameters:
[0034] The current symbol rate is initialized to R. The digital signals to be interpolated are N parallel channels with a bit width of a, where N ≥ 2, and the nth digital signal is d. n In this embodiment, a = 16 and N = 8.
[0035] Step 2) The interpolation point calculation submodule calculates the location of the interpolation point at any decimal multiple of the current symbol rate:
[0036] Calculate the initial accumulation step size S for N channels using the current symbol rate R, and calculate the digital signal d for each channel using S. n The cumulative count value S n As d n The position of the interpolation point that is any decimal multiple;
[0037] The initial accumulation step size S for each channel, and the digital signal d for each channel n The cumulative count value S n The calculation formulas are as follows:
[0038]
[0039] S n =nS, n=1,2,...,8
[0040] Here, clk represents the operating clock frequency of the interpolation module.
[0041] The accumulated count values S1 to S8 are stored in, but are not limited to, 35-bit wide reg type registers, where the high 3 bits are the integer part of the accumulated count value and the low 32 bits are the fractional part of the accumulated count value.
[0042] Step 3) The second branch acquires the interpolation data for each digital signal to be interpolated:
[0043] (3a) Input data storage and update submodule for each data channel d n Register the data when the accumulated count value S for each channel is reached. n The integer part i n When 7 overflows to 0, for d n Registered data D n Perform an update to obtain the update register data D for each path. n ′;
[0044] For d n Registered data D n The steps to perform the update are as follows:
[0045] This module inputs 8 parallel data streams. This example uses, but is not limited to, a 256-bit wide reg type shift register to store the input data. The shift register is divided into two parts: a high 128-bit and a low 128-bit. The high 128 bits contain the previously stored 8 parallel input data streams, and the low 128 bits contain the newly entered 8 parallel input data streams.
[0046] (3b) The input data selection submodule uses the accumulated count value S for each channel. n The integer part i n Select the updated registered data D n Partial data A n And use it as the digital signal d to be interpolated for each channel. n Interpolated data;
[0047] Select the updated registered data D n Partial data A n The formula is:
[0048] A n =D n ′[(11-i n )×a-1:(7-i n )×a]
[0049] Among them, D n ′[(11-i n )×a-1:(7-i n [)×a] represents retrieving the updated registered data D n The (11-i)th n )×a-1 to the (7-i)th position n )×a-1 bits.
[0050] When the integer part of the accumulated count is 7, the lowest 64 bits of data are selected as the interpolation data. When the integer part of the accumulated count is 6, the sliding window is shifted to the left by one data bit width, and the 79th to 16th bits of data are selected as the interpolation data. And so on. When the integer part of the accumulated count is 0, the 175th to 112th bits are selected as the interpolation data.
[0051] Step 4) The cubic Lagrange interpolation submodule obtains the interpolation result of the digital signal:
[0052] The cubic Lagrange interpolation submodule uses the Lagrange interpolation coefficient matrix C and the interpolation data A of each digital signal. n Calculate the interpolation filter coefficient matrix Y n And through Y n and each digital signal d n The position of the interpolation point S n Calculate d nThe interpolation result y n ,in:
[0053]
[0054] y n =[1u n u n 2 u n 3 ]Y n
[0055] Where, x n (-1),x n (0),x n (1),x n (2) These represent the four numbers from left to right in the currently selected interpolation data of the nth data path. When the integer part of the accumulated value is 7, x(-1), x(0), x(1), and x(2) represent the lowest 64 bits of data, each occupying 16 bits of width. n The accumulated count value S output by the interpolation point calculation module n The high 12 bits of data are used. Matrix multiplication is implemented using, but not limited to, left shift and binary addition to save hardware resources. Multiplication, quadratic and cubic operations are all implemented using multipliers. The specific implementation structure uses, but is not limited to, the Farrow structure. Compared with the traditional structure, the Farrow structure can save multiplier resources.
[0056] The above description is merely two specific examples of the present invention and does not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and details without departing from the principles and structure of the present invention. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.
[0057] It should be noted that the step numbers in the specification and claims of this invention are only for the purpose of clearly describing the embodiments of this invention and facilitating understanding, and their order is not limited.
Claims
1. A parallel arbitrary decimal multiple interpolation module, characterized in that: It is implemented based on FPGA, including an FPGA-based interpolation point calculation submodule as the first branch, a second branch arranged in parallel with it consisting of an input data register and update submodule and a cascaded input data selection submodule, and a cubic Lagrange interpolation submodule connected to the outputs of the two branches. The output of the first branch is also connected to the input of the input data register and update submodule. Specifically: The interpolation point calculation submodule is used to calculate the location of any fractional interpolation point at the current symbol rate. The input data storage and update submodule is used to store the input parallel digital signal data and update each channel of data by using the interpolation point location output by the interpolation point calculation submodule. The input data selection submodule is used to select the data required for the current interpolation from each updated data output by the input data register and update submodule; The cubic Lagrange interpolation submodule is used to calculate the location of the interpolation point input to the submodule and select the data required for the current interpolation output of the input data selection submodule to perform cubic Lagrange interpolation on the digital signal.
2. A method for implementing the interpolation module according to claim 1, characterized in that: Includes the following steps: (1) Initialize parameters: The current symbol rate is initialized to R. The digital signals to be interpolated are N parallel channels with a bit width of a, where N ≥ 2, and the nth digital signal is d. n ; (2) The interpolation point calculation submodule calculates the location of the interpolation point at any decimal multiple of the current symbol rate: Calculate the initial accumulation step size S for N channels using the current symbol rate R, and calculate the digital signal d for each channel using S. n The cumulative count value S n As d n The position of the interpolation point that is any decimal multiple; (3) The second branch acquires the interpolation data for each digital signal to be interpolated: The second branch passes through each digital signal to be interpolated, d. n and the position S of the interpolation point n Obtain the interpolation data A of this digital signal. n ; (4) The cubic Lagrange interpolation submodule obtains the interpolation results of the digital signal: The cubic Lagrange interpolation submodule uses the Lagrange interpolation coefficient matrix C and the interpolation data A of each digital signal. n Calculate the interpolation filter coefficient matrix Y n And through Y n and each digital signal d n The position of the interpolation point S n Calculate d n The interpolation result y n .
3. The method according to claim 2, characterized in that, The initial accumulation step size S for each channel mentioned in step (2), and the digital signal d for each channel n The cumulative count value S n The calculation formulas are as follows: S n =nS Here, clk represents the operating clock frequency of the interpolation module.
4. The method according to claim 2, characterized in that, The second branch described in step (3) acquires the interpolation data for each digital signal to be interpolated. The implementation steps are as follows: (3a) Input data storage and update submodule for each data channel d n Register the data when the accumulated count value S for each channel is reached. n The integer part i n When N-1 overflows to 0, for d n Registered data D n Perform an update to obtain the update register data D for each path. n ′; (3b) The input data selection submodule uses the accumulated count value S for each channel. n The integer part i n Select the updated registered data D n Partial data A n And use it as the digital signal d to be interpolated for each channel. n Interpolated data.
5. The method according to claim 4, characterized in that, The update of the register data D for each path mentioned in step (3a) n The method to obtain ' is as follows: The input data register and update submodule allocates a 2aN shift register in the FPGA to handle each input data path d. n Registered as D n When the accumulated count value S n The integer part i n When N-1 overflows to 0, D will be... n Low-level aN bits of data, data per channel d n Set them to D respectively n The high aN bits and low aN bits of data are used to implement the processing of each data stream d. n Registered data D n Update.
6. The method according to claim 4, characterized in that, The step (3b) involves selecting the updated registered data D. n Partial data A n Specifically: A n =D n ′[(11-i n )×a-1:(7-i n )×a] Among them, D n ′[(11-i n )×a-1:(7-i n [)×a] represents retrieving the updated registered data D n The (11-i)th n )×a-1 to the (7-i)th position n )×a-1 bits.
7. The method according to claim 2, characterized in that, The expression for the Lagrange interpolation coefficient matrix C mentioned in step (4) is as follows:
8. The method according to claim 2, characterized in that, The interpolation filter coefficient matrix Y mentioned in step (4) n The calculation formula is: Where, x n (2) x n (1) x n (0), x n (-1) represent the nth interpolation data A. n The data from position a-1 to position 0, the data from position 2a-1 to position a, the data from position 3a-1 to position 2a, and the data from position 4a-1 to position 3a.
9. The method according to claim 2, characterized in that, The d mentioned in step (4) n The interpolation result y n The calculation formula is: y n =[1u n u n 2 u n 3 ]Y n Among them, u n The accumulated count value S of the nth data output by the interpolation point calculation module. n The high 12-bit width data.