PLC system based on AI acceleration unit and FPGA and operation method thereof

Abstract

The invention discloses a PLC system based on an AI acceleration unit and an FPGA and an operation method thereof, and the system comprises the AI acceleration unit which comprises an NPU and a CPU, the NPU is used for executing an AI reasoning task, and the CPU is used for operating a real-time operation system, scheduling the NPU task and carrying out safety monitoring; the bus processing unit is constructed based on an FPGA (Field Programmable Gate Array) and is in communication connection with the NPU and the CPU; and the bus processing unit verifies the start signature of the AI acceleration unit, and the CPU of the AI acceleration unit reverifies the bit stream integrity of the bus processing unit so as to realize a full-stack hardware-level trusted closed loop from start verification and data communication to control logic.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of industrial PLC, and particularly relates to a PLC system based on an AI acceleration unit and an FPGA and a running method thereof. BACKGROUND

[0002] With the continuous development of industrial automation, programmable logic controllers (PLC) play a crucial role in the field of industrial control. PLC can accurately control and monitor industrial production processes according to pre-set programs, ensuring efficient and stable operation of production.

[0003] However, traditional PLC systems gradually reveal some limitations when dealing with increasingly complex industrial tasks. For example, when facing a large amount of real-time data processing and complex control logic operations, its computing power is often insufficient, making it difficult to meet the demand for high precision and fast response in modern industry.

[0004] In order to improve the performance of PLC system, artificial intelligence (AI) technology is introduced into PLC system. AI acceleration unit can quickly analyze and process industrial data with its powerful computing power, realize more intelligent control strategy and optimization algorithm, and improve the efficiency and quality of industrial production. However, the application of AI acceleration unit also brings new problems, such as the security and reliability of its startup process need to be protected to prevent startup abnormalities caused by malicious attacks or hardware failures, which will affect the normal operation of the whole PLC system.

[0005] At the same time, field programmable gate array (FPGA) as a flexible hardware platform has been widely used in industrial control field. FPGA has the advantages of strong parallel processing ability, reconfigurability, etc., and can realize complex logic control and data processing tasks. Moreover, FPGA has certain advantages in hardware security, and its internal logic can be customized through programming to realize data encryption, authentication and other security functions.

[0006] At present, although there are some attempts to apply AI technology and FPGA technology to PLC systems, there are still some deficiencies in the safety and reliability of the system. For example, most of the existing solutions focus on single aspect security protection, lack of full-stack hardware-level trusted closed-loop mechanism from startup verification, data communication to control logic. In the startup process of the AI acceleration unit, the startup signature is often not effectively verified, and the legality and integrity of the startup cannot be ensured. At the same time, at the level of data communication and control logic, there is also a lack of verification mechanism for the integrity of the FPGA bit stream, making it difficult to ensure the safety and reliability of the system during the entire running process.

[0007] Therefore, how to organically combine the AI acceleration unit and the FPGA to build a PLC system with a full-stack hardware-level trusted closed loop has become a problem to be solved in the current industrial control field. SUMMARY

[0008] The purpose of the present application is to provide an AI acceleration unit and FPGA-based PLC system and its operation method, which verifies the AI acceleration unit startup signature by taking FPGA as a primary guardian unit, and the FPGA bit stream integrity is verified by the AI acceleration unit CPU to realize a double-chip mutual verification trusted startup mechanism and improve system security.

[0009] The present application provides an AI acceleration unit and FPGA-based PLC system, comprising: An AI acceleration unit comprising an NPU and a CPU, the NPU being used to execute AI inference tasks, and the CPU being used to run a real-time operating system and schedule NPU tasks and security monitoring; A bus processing unit based on FPGA and in communication connection with the NPU and the CPU; The bus processing unit verifies the AI acceleration unit startup signature, and the CPU of the AI acceleration unit verifies the bit stream integrity of the bus processing unit to realize a full-stack hardware-level trusted closed loop from startup verification, data communication to control logic.

[0010] Preferably, the bus processing unit verifies the AI acceleration unit startup signature, and the CPU of the AI acceleration unit verifies the bit stream integrity of the bus processing unit, comprising: The bus processing unit loads the first segment of boot code BootROM program, and sends the digital signature of the AI acceleration unit startup file through the signature verification channel between the bus processing unit and the AI acceleration unit; After receiving the digital signature, the AI acceleration unit enters a waiting state and loads the first segment of boot code Bootloader, verifies the digital signature sent by the bus processing unit, and after verification, the AI acceleration unit sends a custom security protocol to the bus processing unit; The bus processing unit verifies the security protocol, and then starts the firmware program of the bus processing unit, generates a temporary session key, and sends it to the AI acceleration unit again; After receiving the temporary session key, the AI acceleration unit verifies it, and then starts the application program.

[0011] Preferably, the bus processing unit verifies the security protocol based on a hash check.

[0012] Preferably, the PLC system further comprises a storage unit including a memory and a data storage, for storing programs and data during the operation of the PLC system, and the bus storage unit and the AI acceleration unit both load the first boot code from the storage unit.

[0013] Preferably, the PLC system further comprises a bus interface unit, a communication driving unit, and an external interface unit, the communication driving unit is used to convert the logical control signals of the AI acceleration unit and the bus processing unit into bus transmission signals, the bus interface unit is used to communicate with other expansion modules in the same rack of the PLC system, and the external interface unit provides rich peripheral interfaces.

[0014] Preferably, the PLC system further comprises a power management unit, which is used to convert an external power signal into a voltage required by each functional circuit unit in the PLC system.

[0015] Preferably, when the PLC system is working normally, the bus processing unit completes the functions of the bus ECN-B and ECN-E protocol stacks, the ECN-B master protocol stack completes the collection and control of local rack data, and the ECN-E completes the collection and control of extended rack data. The local rack ECN-B bus adopts a redundancy mechanism to increase the communication reliability of the local rack.

[0016] Based on the same concept, the application further provides a PLC system operation method based on an AI acceleration unit and an FPGA, comprising the following steps: The bus processing unit loads the first boot code BootROM program, and sends the digital signature of the AI acceleration unit start file through the signature channel between the bus processing unit and the AI acceleration unit; After receiving the digital signature, the AI acceleration unit enters a waiting state and loads the first boot code Bootloader, verifies the digital signature sent by the bus processing unit, and after verification, the AI acceleration unit sends a custom security protocol to the bus processing unit; The bus processing unit verifies the security protocol, and then starts the firmware program of the bus processing unit, generates a temporary session key, and sends it to the AI acceleration unit again; The AI acceleration unit receives the temporary session key, and after verification, the application is started.

[0017] Preferably, the bus processing unit verifies the security protocol based on a hash check, and in normal operation, the bus processing unit completes the functions of the autonomous bus ECN-B and ECN-E bus protocol stacks, the ECN-B master station protocol stack completes the collection and control of local rack data, and the ECN-E completes the collection and control of extended rack data. The local rack ECN-B bus adopts a redundancy mechanism to increase the communication reliability of the local rack.

[0018] Based on the same concept, the application also provides a readable storage medium, which stores a processing program, and the processing program is executed by a processor to realize the above-mentioned PLC system running method based on the AI acceleration unit and the FPGA.

[0019] Compared with the prior art, the application has the following advantages: In the technical solution of the application, the bus processing unit based on the FPGA is used as a first-level startup daemon unit to verify the digital signature of the AI acceleration unit (including NPU / CPU) startup file. After the AI acceleration unit is started, the CPU thereof verifies the integrity of the FPGA configuration bit stream, forming a double-chip cross-verification chain. The three-core heterogeneous function is divided: the NPU performs industrial AI inference tasks (such as visual defect detection and vibration analysis) that require computing power; the CPU runs a real-time operating system (RTOS) and a PLC runtime, and schedules NPU tasks and security monitoring; the bus processing unit based on the FPGA implements the industrial real-time bus protocol stack ECN-B and ECN-E designed by itself, and has a built-in hardware-level shared memory controller, which is directly connected to the NPU output and the PLC control loop. The edge computing PLC system realizes hardware-level trusted startup, real-time control, and autonomous bus communication. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 The hardware principle block diagram of the application is shown in the figure; Figure 2 The trusted startup flowchart of the application is shown in the figure; Figure 3 The double-chip mutual verification startup principle of the application is shown in the figure; Figure 4 The heterogeneous PLC system block diagram of the application is shown in the figure. DETAILED DESCRIPTION

[0021] Following, specific embodiments of the present application are described by specific examples, and other advantages and effects of the present application can be easily understood by those skilled in the art from the disclosure of the specification. The present application can also be implemented or applied by other different specific embodiments, and various modifications or changes can be made to the details in the specification based on different views and applications without departing from the spirit of the present application. It should be understood that the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and the like are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second", and the like can explicitly or implicitly include one or more features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0022] It should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integral connection; it can be mechanical connection, or electrical connection; it can be direct connection, or indirect connection through intermediate medium, or internal communication of two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0023] In addition, in the description of the present application, "proximal" and "distal" are terms commonly used in the medical field. Specifically, "proximal" is the end close to the operator, "proximal surface" is the end surface close to the operator, "distal" is the end away from the operator, and "distal surface" is the end surface away from the operator.

[0024] First embodiment Referring to Figure 1 , the present embodiment provides a PLC system based on AI acceleration unit and FPGA, comprising: AI acceleration unit, comprising NPU (Neural-network Processing Unit, neural network processor) and CPU, the NPU is used for executing AI inference task, and the CPU is used for running real-time operating system and scheduling NPU task and safety monitoring; Bus processing unit, constructed based on FPGA, in communication connection with the NPU and the CPU; The bus processing unit verifies the AI acceleration unit startup signature, and the CPU of the AI acceleration unit verifies the bus processing unit bit stream integrity to achieve startup verification, data communication to control logic, full stack hardware level trusted closed loop.

[0025] The bus processing unit based on FPGA is a primary startup daemon unit, verifying the digital signature of the AI acceleration unit (including NPU / CPU) startup file. After the AI acceleration unit is started, the FPGA configuration bit stream integrity is verified by the CPU of the AI acceleration unit, forming a double-chip cross-verification chain. Three-core heterogeneous function division: NPU executes industrial AI inference tasks (such as visual defect detection and vibration analysis) that require computing power; CPU runs real-time operating system (RTOS) and PLC runtime, scheduling NPU tasks and safety monitoring; the bus processing unit based on FPGA implements the self-designed industrial real-time bus protocol stack ECN-B and ECN-E, and has a built-in hardware-level shared memory controller, directly connecting NPU output and PLC control loop. The edge computing PLC system realizes hardware-level trusted startup, real-time control and autonomous bus communication.

[0026] The PLC system provided by the embodiment can take full advantage of the natural advantages of NPU in parallel computing and matrix operation, and significantly improve the speed and efficiency of AI reasoning. Compared with the traditional CPU-based computing method, NPU can process a large amount of data and complex computing models in a short time, meeting the application scenarios in the PLC system with high real-time requirements, such as complex logical judgment in industrial automation control, fault prediction and diagnosis, etc. The CPU runs a real-time operating system, which can ensure the real-time response capability of the system. The real-time operating system can reasonably schedule NPU tasks and safety monitoring tasks according to the priority and time requirement of the task, to ensure that critical tasks can be processed in time, and avoid system delay or failure caused by task conflict or unreasonable resource allocation. This cooperative working mode enables the entire PLC system to maintain high efficiency and stability when processing complex tasks, meeting the strict requirements of real-time in industrial field. The bus processing unit verifies the signature of the AI acceleration unit, and the CPU of the AI acceleration unit verifies the bit stream integrity of the bus processing unit, which constitutes a full-stack hardware-level trusted closed loop. This double verification mechanism can effectively prevent illegal or unauthorized code from being loaded and executed during system startup, ensuring the safety and legality of system startup. In the field of industrial control, safe and reliable startup of the system is crucial, and any unauthorized code or malicious attack may cause serious consequences, such as production accidents, equipment damage, etc. Through this strict startup verification mechanism, the risk of system security threats can be greatly reduced. The bus processing unit based on FPGA plays an important role in data communication. The programmability and flexibility of FPGA enable it to implement customized data encryption and verification algorithms, ensuring the safety and integrity of data during transmission. In industrial field, data transmission may be subject to various disturbances and attacks, such as electromagnetic interference, network attacks, etc. Through the data encryption and verification function of the bus processing unit, data tampering, theft or loss can be effectively prevented, ensuring the safe and reliable data communication between the PLC system and external devices. The full-stack hardware-level trusted closed loop not only ensures the safety of system startup and data communication, but also ensures the trusted execution of control logic. In the PLC system, the correct execution of control logic is directly related to the normal operation of industrial production. Through the hardware-level verification and trust mechanism, the control logic can be prevented from being maliciously modified or damaged, ensuring that the system runs according to the predetermined rules and logic, improving the reliability and stability of the system.

[0027] The logic control and reasoning of the PLC system are undertaken by the CPU (Atlas 200 main control unit), and the minimum system of the main control unit is completed to ensure the normal operation of the basic functions of Atlas. The bus processing function of the PLC is undertaken by the bus processing unit.

[0028] Referring to Figure 2 andFigure 3 Preferably, the bus handler unit verifies the AI acceleration unit boot signature, and the CPU of the AI acceleration unit verifies the bus handler unit bitstream integrity, including: The bus handler unit loads the first segment of the boot code BootROM program, and sends the digital signature of the AI acceleration unit boot file through the signature verification channel between the bus handler unit and the AI acceleration unit; After receiving the digital signature, the AI acceleration unit enters a waiting state and loads the first segment of the boot code Bootloader, verifies the digital signature sent by the bus handler unit, and after verification, the AI acceleration unit sends a custom security protocol to the bus handler unit; After the bus handler unit verifies the security protocol, the bus handler unit starts the firmware program of the bus handler unit, generates a temporary session key, and sends it to the AI acceleration unit again; After the AI acceleration unit receives the temporary session key and verifies it, it starts the application program.

[0029] The technical solution of the embodiment constructs a full-life-cycle hardware-level trust chain from startup to running through technical means such as bidirectional verification, dynamic key negotiation, hardware acceleration, and error recovery, and forms multiple advantages in security, real-time performance, reliability, and scalability, and is especially suitable for industrial control scenarios with high sensitivity and high real-time requirements, and has significant technical barriers and industrialization value. Through multiple interactive verifications (digital signature verification → custom security protocol verification → session key negotiation) of a bus processing unit (FPGA) and an AI acceleration unit (CPU+NPU), full-link dynamic authentication from a startup file to a communication link is realized. This “challenge-response” mechanism not only verifies the identity legitimacy of both parties, but also ensures the dynamic confidentiality of subsequent data communication by generating a temporary session key (such as based on the Diffie-Hellman algorithm), effectively resisting replay attacks and key leakage risks. A segmented boot code (BootROM → Bootloader → firmware program → application program) loading mode is adopted, combined with digital signature verification and security protocol review, to ensure the integrity and source credibility of each stage of code. For example, the FPGA directly verifies the signature of the AI acceleration unit through a signature verification channel, and the CPU reviews the integrity of the FPGA bit stream, forming a bidirectional chain trust, avoiding the system from being attacked by a single node. The AI acceleration unit sends a custom security protocol (such as a protocol based on AES encryption or RSA asymmetric encryption) after verifying the signature, and the FPGA needs to verify the protocol compliance before starting the firmware. This design allows the protocol content to be customized according to the requirements of the industrial scene (such as adding a timestamp, a random number, or a device feature identifier), enhancing the tamper resistance and anti-forgery capability of the protocol, while avoiding the vulnerabilities that may exist in relying on general-purpose protocols. The temporary session key generated by the FPGA is only used for communication encryption in the current startup period, and the key is transmitted to the AI acceleration unit through a secure channel. This design realizes the one-time key feature, reduces the risk of long-term key exposure, and combines the hardware encryption acceleration capability of the FPGA to greatly improve the efficiency of key negotiation and encrypted communication.

[0030] Preferably, the bus processing unit verifies the security protocol based on hash check.

[0031] The embodiment maps the security protocol content to a fixed-length hash value, ensuring that any minor modification (such as bit flipping or field tampering) of the protocol content will cause a significant change in the hash value. The bus processing unit (FPGA) can quickly detect protocol tampering or forgery by comparing the calculated hash value with the hash value sent by the AI acceleration unit, effectively resisting man-in-the-middle attacks, replay attacks, and other security threats.

[0032] Preferably, the PLC system further comprises a storage unit including a memory and a data storage, for storing programs and data during the operation of the PLC system, and the bus storage unit and the AI acceleration unit both load the first segment of boot code from the storage unit.

[0033] The memory (such as DRAM / SRAM) is used for temporarily storing the real-time operating system, the program code in operation, and the high-frequency data (such as the intermediate results of AI inference), and the low-latency access requirements of the CPU and the NPU are guaranteed by the high-speed read-write characteristics. The data storage (such as Flash / EEPROM) is used for persistent storage of the startup file, the firmware program, the security protocol template, and the historical data, to ensure that the configuration is not lost after the system restarts. The efficient cooperation of “transient data + persistent storage” is achieved through hardware isolation, avoiding the life problem (such as Flash wear) caused by frequent erasing and writing of the storage medium, while improving the system response speed. The first segment of boot code (BootROM / Bootloader) is uniformly stored in the storage unit, and the FPGA and the AI acceleration unit can both load the initial code from the same storage source. This design simplifies the system upgrade process, for example: when updating the firmware, only the boot code or the firmware file in the storage unit needs to be replaced, without the need to separately configure the loading path of the FPGA or the CPU; supporting over-the-air (OTA) upgrade, achieving batch device maintenance by remotely modifying the content of the storage unit, and reducing the industrial field operation and maintenance cost.

[0034] Preferably, the PLC system further comprises a bus interface unit, a communication driving unit, and an external interface unit, the communication driving unit is used for converting the logical control signals of the AI acceleration unit and the bus processing unit into bus transmission signals, the bus interface unit is used for bus communication with other expansion modules in the same rack of the PLC system, and the external interface unit provides rich peripheral interfaces.

[0035] Preferably, the PLC system further comprises a power management unit for converting an external power signal into a voltage required by each functional circuit unit in the PLC system.

[0036] In some embodiments, the program and data in the PLC running process are stored in the storage unit, including the memory and the data storage. The communication driving unit converts the logical control signals of the AI acceleration unit and the bus processing unit into bus transmission signals. The power management unit is connected with the external power supply, and converts the voltage required by each functional circuit unit through the power management unit. The bus interface unit is used for bus communication with other expansion modules in the same rack of the PLC system. The external interface unit provides rich peripheral interfaces. As a high-performance PLC, it provides two gigabit Ethernet interfaces for general gigabit Ethernet communication or other high-speed bus communication based on Ethernet, two USB interfaces and HDMI for human-computer interaction, connecting mouse, keyboard and display, and two general Ethernet interfaces for ECN-E bus for inter-rack communication of the PLC, and has redundancy function.

[0037] Preferably, when the PLC system is normally working, the bus processing unit completes the autonomous bus ECN-B and ECN-E bus protocol stack functions, the ECN-B master protocol stack completes the collection and control of local rack data, and the ECN-E completes the collection and control of extended rack data. The local rack ECN-B bus adopts a redundancy mechanism to increase the communication reliability of the local rack.

[0038] Second embodiment Based on the same concept, the application also provides a PLC system running method based on AI acceleration unit and FPGA, comprising the following steps: The bus processing unit loads the first boot code BootROM program, and sends the digital signature of the AI acceleration unit startup file through the signature channel between the bus processing unit and the AI acceleration unit; After receiving the digital signature, the AI acceleration unit enters a waiting state and loads the first boot code Bootloader, verifies the digital signature sent by the bus processing unit, and after verification, the AI acceleration unit sends a custom security protocol to the bus processing unit; After the bus processing unit verifies that the security protocol is passed, the firmware program of the bus processing unit is started, a temporary session key is generated, and the AI acceleration unit is sent again; After the AI acceleration unit receives the temporary session key and verifies it, the application program is started.

[0039] The PLC system of the application is divided into a trusted starting process and a normal running process. The trusted starting process occurs in the power-on stage of the system, that is, the external interface unit is powered by external power supply, the power management unit provides required voltage for all other functional circuit units, and each unit circuit is normally powered. The bus processing unit starts to start, and the FPGA loads the first boot code BootROM program from the Flash. After the bus processing unit loads the BootROM program, the bus processing unit and the AI acceleration unit are verified through the signature channel between the bus processing unit and the AI acceleration unit, and the digital signature of the AI acceleration unit starting file is sent. After the sending is successful, the AI acceleration unit enters a waiting state. The AI acceleration unit loads the first boot code Bootloader, verifies the digital signature sent by the bus processing unit, and after the verification is passed, the AI acceleration unit sends a custom security protocol to the bus processing unit. After the bus processing unit verifies the security protocol, the bus processing unit starts the firmware program of the bus processing unit, generates a temporary session key, and sends it to the AI acceleration unit again. After the AI acceleration unit receives the temporary session key and verifies it, the application program is started. The AI acceleration unit and the bus processing unit are started.

[0040] Preferably, the bus processing unit verifies the security protocol based on hash check. In normal operation, the bus processing unit completes the functions of the autonomous bus ECN-B and ECN-E bus protocol stack, the ECN-B master station protocol stack completes the collection and control of local rack data, and the ECN-E completes the collection and control of extended rack data. The local rack ECN-B bus adopts a redundancy mechanism to increase the communication reliability of the local rack.

[0041] After completing the trusted starting process, enter the normal operation process. Among them, after the AI acceleration unit starts normally, the open source operating system and the autonomous controllable runtime are run in the CPU core, interact with the storage unit to realize local data storage and data service functions. Interact with the communication driver unit to realize the protocol stack of external communication and complete motion control. Interact with the bus processing unit data to obtain local rack and extended rack communication data, complete data acquisition and control functions, and the CPU core efficiently completes storage, communication, scheduling, motion control and other high real-time requirement tasks to ensure the operation function of the PLC; the NPU core runs the flow processing module, inference module, analysis engine and other functions that require large computing power, so that the PLC not only completes the traditional logic task processing, but also has the function of AI acceleration. At the same time, the bus processing unit starts normally after starting, completes the functions of the autonomous bus ECN-B and ECN-E bus protocol stack, the ECN-B master station protocol stack completes the acquisition and control of local rack data, and the ECN-E completes the acquisition and control of extended rack data. The local rack ECN-B bus adopts a redundant mechanism to increase the communication reliability of the local rack. The extended rack ECN-E bus is an industrial bus based on Ethernet, which has the characteristics of long transmission distance and high reliability. The double ECN-E bus design can realize single ECN-E bus transmission and ECN-E ring network bus transmission. And through the memory bus interface, the AI acceleration unit and the bus data are interacted to synchronize and schedule the bus data and the logic control.

[0042] Based on the same concept, the application also provides a readable storage medium, wherein a processing program is stored on the readable storage medium, and the processing program is executed by a processor to realize the PLC system running method based on the AI acceleration unit and the FPGA.

[0043] The application constructs a three-layer autonomous controllable technology chain through the hardware-level collaborative design of the AI acceleration unit and the programmable logic device (FPGA). In the security layer, a double-chip mutual verification trusted starting mechanism is created - the FPGA verifies the AI acceleration unit starting signature as a first-level guardian unit, and the AI acceleration unit CPU verifies the FPGA bit stream integrity; in the function layer, a three-core heterogeneous division architecture is adopted: the AI acceleration unit NPU completes real-time industrial AI inference, its CPU runs an open source real-time operating system to implement hard task scheduling, and the FPGA realizes industrial bus protocol stack through self-written hardware logic; in the autonomy layer, the whole system adopts an open source kernel and a self-developed runtime and bus IP core, breaks through the foreign technology dependence of traditional PLCs in protocol authorization, computing power scheduling and security starting links, and realizes a full-stack hardware-level trusted closed loop from starting verification, data communication to control logic.

[0044] The embodiments of the present application are explained in detail above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments. Even if various changes are made to the present application, if the changes fall within the scope of the claims of the present application and equivalents thereof, they are still within the protective scope of the present application.

Claims

1. An AI acceleration unit and FPGA-based PLC system, characterized by, Comprise: AI acceleration unit, including NPU and CPU, the NPU is used to execute AI inference task, the CPU is used to run real-time operating system and dispatch NPU task and safety monitoring; Bus processing unit, based on FPGA construction, with the NPU and the CPU communication connection; The bus processing unit verifies the AI acceleration unit startup signature, and the CPU of the AI acceleration unit verifies the bitstream integrity of the bus processing unit, to realize the full-stack hardware level trusted closed loop of startup verification, data communication to control logic. 2.The AI acceleration unit and FPGA-based PLC system of claim 1, wherein, The bus processing unit verifies the AI acceleration unit startup signature, and the CPU of the AI acceleration unit verifies the bitstream integrity of the bus processing unit, to realize the full-stack hardware level trusted closed loop of startup verification, data communication to control logic. The bus processing unit loads the first segment boot code BootROM program, and sends the digital signature of the AI acceleration unit startup file through the signature channel between the bus processing unit and the AI acceleration unit; After receiving the digital signature, the AI acceleration unit enters a waiting state and loads the first segment boot code Bootloader, verifies the digital signature sent by the bus processing unit, and sends a custom security protocol to the bus processing unit after verification; After the bus processing unit verifies the security protocol, the firmware program of the bus processing unit is started, a temporary session key is generated, and the AI acceleration unit is sent again; The AI acceleration unit receives the temporary session key, and after verification, the application program is started. 3.The AI acceleration unit and FPGA-based PLC system of claim 1, wherein, The bus processing unit verifies the security protocol based on hash check. 4.The AI acceleration unit and FPGA-based PLC system of claim 1, wherein, Further comprising a storage unit, the storage unit includes memory and data storage, for storing the program and data in the running process of PLC system, the bus storage unit and the AI acceleration unit are loaded with the first segment boot code from the storage unit. 5.The AI acceleration unit and FPGA-based PLC system of claim 1, wherein, Further comprising a bus interface unit, a communication driving unit and an external interface unit, the communication driving unit is used to convert the logic control signal of the AI acceleration unit and the bus processing unit into bus transmission signal, the bus interface unit is used to communicate with other expansion modules in the same rack of PLC system, and the external interface unit provides rich peripheral interface. 6.The AI acceleration unit and FPGA-based PLC system of claim 1, wherein, The PLC system further comprises a power management unit for converting external power signal into voltage required by each functional circuit unit in the PLC system. 7.The AI acceleration unit and FPGA-based PLC system of claim 1, wherein, When the PLC system is working normally, the bus processing unit completes the functions of ECN-B and ECN-E bus protocol stacks, the ECN-B master station protocol stack completes the collection and control of local rack data, and the ECN-E completes the collection and control of extended rack data, and the local rack ECN-B bus adopts redundancy mechanism to increase the communication reliability of local rack.

8. An AI acceleration unit and FPGA-based PLC system operation method, characterized by, Comprise the following steps: The bus processing unit loads the first segment boot code BootROM program, and sends the digital signature of the AI acceleration unit startup file through the signature channel between the bus processing unit and the AI acceleration unit; After receiving the digital signature, the AI acceleration unit enters a waiting state and loads the first segment of the boot loader, verifies the digital signature sent by the bus processing unit, and after verification, the AI acceleration unit sends a custom security protocol to the bus processing unit; After the bus processing unit verifies the security protocol, it starts the firmware program of the bus processing unit, generates a temporary session key, and sends it to the AI acceleration unit again; After the AI acceleration unit receives the temporary session key and verifies it, it starts the application program. 9.The AI acceleration unit and FPGA-based PLC system operation method of claim 8, wherein, The bus processing unit verifies the security protocol based on hash check, and when working normally, the bus processing unit completes the functions of the ECN-B and ECN-E bus protocol stacks, the ECN-B master protocol stack completes the collection and control of local rack data, and the ECN-E completes the collection and control of extended rack data. The ECN-B bus of the local rack adopts a redundancy mechanism to increase the communication reliability of the local rack.

10. A readable storage medium, characterized by, The readable storage medium stores a processing program, and the processing program is executed by the processor to realize the running method of the PLC system based on the AI acceleration unit and the FPGA according to claim 8 or 9. The readable storage medium stores a processing program, and the processing program is executed by the processor to realize the running method of the PLC system based on the AI acceleration unit and the FPGA according to claim 8 or 9.

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