PUF (Physical Unclonable Function) anti-counterfeiting circuit and chip anti-counterfeiting method based on sub-threshold region current mirror mismatch
By using a PUF circuit based on subthreshold current mirror mismatch, the current difference is converted into a logic value by a capacitor and latched to generate a unique anti-counterfeiting code, which solves the problem of insufficient anti-counterfeiting capability caused by process error and achieves effective anti-counterfeiting of the chip.
Patent Information
- Application Number
- CN202511015058.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-23
- Publication Date
- 2025-11-21
AI Technical Summary
Existing PUF circuits based on subthreshold current mirrors are susceptible to mismatch due to process errors, resulting in insufficient anti-counterfeiting capabilities.
A PUF circuit based on subthreshold current mirror mismatch is adopted. The current difference is converted into a logic value by a capacitor, and the error result is latched by an RS latch to generate a unique anti-counterfeiting code.
By effectively utilizing process errors to generate unique PUF responses, a unique anti-counterfeiting code is created, protecting the legitimate interests of chip manufacturers and consumers.
Smart Images
Figure CN120995512A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of integrated circuit technology, in particular to a chip anti-counterfeiting circuit. BACKGROUND
[0002] Physical Unclonable Function (PUF) is a random number generation method based on physical response, which uses the randomness of physical systems to generate a unique random number sequence or unique identification. In the circuit, the PUF circuit is embedded, the random deviation generated in the manufacturing process of the integrated circuit is extracted and amplified by generating a specific circuit structure, to generate a random response corresponding to the circuit in the integrated circuit, so as to generate a unpredictable unique identification code for a specific integrated circuit entity, which has uniqueness and randomness.
[0003] Sub-threshold region refers to the working region of MOSFET when the gate voltage is lower than the threshold voltage, at which time the transistor is in a weak inversion state, and the drain current changes exponentially with the gate voltage. The sub-threshold region drain current is very small, and this working region is often used for low-power design. The current-voltage relationship is as formula 1, where μ is the carrier mobility, Cox is the gate oxide layer capacitance per unit area, W and L represent the channel width and length respectively, and n is the sub-threshold region slope factor.
[0004]
[0005] Using a current mirror working in the sub-threshold region, when the Vth value is affected by process error, a small deviation (ΔVth) will cause an exponential mismatch of the current:
[0006]
[0007] For example, if ΔVth = 10mV and n = 2, the mismatch rate is as high as
[0008] The RS latch is a basic digital circuit element used to store a binary data, which is composed of two cross feedback connected NAND gates or NOR gates, and has two input terminals (R and S) and two output terminals (Q and ). The RS latch composed of NAND gates has a circuit structure as shown in Figure 1 . Its truth table is shown in Table 1:
[0009]
[0010] Table 1 Truth table of RS latch composed of NAND gates SUMMARY
[0011] The technical problem solved by the present application is to provide a PUF anti-counterfeiting circuit based on sub-threshold region current mirror mismatch and an anti-counterfeiting method.
[0012] The technical solution adopted by the present application to solve the technical problem is a PUF anti-counterfeiting circuit based on sub-threshold region current mirror mismatch, characterized in that it comprises at least four parallel anti-counterfeiting units, each of which comprises a switch tube, a current mirror and an RS latch, the current mirror is composed of a first branch and a second branch, the first branch and the second branch are connected to a common point and controlled by the same control signal input end, the switch tube is arranged between the common point and a high-level end, and the first branch and the second branch are arranged in parallel between the common point and a ground level; the output end of the first branch is grounded through a capacitor and connected to the first input end of the RS latch through an inverter; and the output end of the second branch is grounded through a capacitor and connected to the second input end of the RS latch through an inverter.
[0013] Further, the first branch comprises a first MOS tube (M1) and a third MOS tube (M3) connected in series, and the series connection point of the two serves as the output end of the first branch; and the second branch comprises a second MOS tube (M2) and a fourth MOS tube (M4) connected in series, and the series connection point of the two serves as the output end of the second branch.
[0014] Further, the first MOS tube (M1) is a PMOS tube, the source thereof is connected to the common point, the drain thereof is connected to the output end of the first branch, and the gate thereof is connected to the control signal input end; and the third MOS tube (M3) is an NMOS tube, the drain thereof is connected to the drain of the first MOS tube (M1), and the source and the gate thereof are grounded.
[0015] The second MOS tube (M2) is a PMOS tube, the source thereof is connected to the common point, the drain thereof is connected to the output end of the second branch, and the gate thereof is connected to the control signal input end; and the fourth MOS tube (M4) is an NMOS tube, the drain thereof is connected to the drain of the second MOS tube (M2), and the source and the gate thereof are grounded.
[0016] Alternatively, the first MOS tube (M1) is a PMOS tube, the source thereof is connected to the common point, and the gate and the drain thereof are connected to the output end of the first branch; and the third MOS tube (M3) is an NMOS tube, the drain thereof is connected to the drain of the first MOS tube (M1), the source thereof is grounded, and the gate thereof is connected to the control signal input end.
[0017] The second MOS tube (M2) is a PMOS tube, the source thereof is connected to the common point, and the gate and the drain thereof are connected to the output end of the second branch; and the fourth MOS tube (M4) is an NMOS tube, the drain thereof is connected to the drain of the second MOS tube (M2), the source thereof is grounded, and the gate thereof is connected to the control signal input end.
[0018] The application also provides a PUF chip anti-counterfeiting method based on sub-threshold region current mirror mismatch, and the generation of each bit of anti-counterfeiting code comprises the following steps.
[0019] (1) the same sub-threshold control voltage is applied to the current mirror MOS tubes constituting two branches, so that the current mirror MOS tubes of the two branches work in the sub-threshold region;
[0020] (2) the output currents of the two branches respectively charge the corresponding capacitors;
[0021] (3) the states of the capacitors corresponding to the two branches are detected by using RS latches, and the RS latches output anti-counterfeiting codes.
[0022] The current mirror MOS tube refers to a MOS tube with a gate as a control signal input end, and is used to form a current mirror.
[0023] The application utilizes the characteristics that the current value of a MOS tube in the sub-threshold region is easily affected by the value Vth of the MOS tube, so that the current mirror composed of two PMOS tubes is easily affected by process errors to produce mismatch, converts the current value difference into a logic value by using a capacitor, and uses an RS latch to latch the error result, thereby amplifying the process error in chip production and manufacturing to produce a PUF response. The anti-counterfeiting code of the application can be used as a chip anti-counterfeiting ID, and effectively protects the legal interests of chip manufacturers and consumers. BRIEF DESCRIPTION OF DRAWINGS
[0024] Figure 1 The figure is a schematic diagram of an RS latch structure composed of AND and OR gates.
[0025] Figure 2 The figure is a circuit diagram of embodiment 1 (1-bit ID) of the application.
[0026] Figure 3 The figure is a circuit diagram of embodiment 1 (32-bit ID) of the application.
[0027] Figure 4 The figure is Figure 2 The figure is a schematic diagram of the first change condition of the voltage values of NET1 and NET2.
[0028] Figure 5 The figure is Figure 2 The figure is a schematic diagram of the second change condition of the voltage values of NET1 and NET2.
[0029] Figure 6 The figure is a PUF verification circuit diagram of 1-bit ID.
[0030] Figure 7 The figure is a schematic diagram of Monte Carlo simulation results of a PUF circuit for generating 1-bit ID.
[0031] Figure 8is the first Monte Carlo simulation result schematic diagram of a PUF circuit generating a 32-bit ID.
[0032] Figure 9 is the second Monte Carlo simulation result schematic diagram of a PUF circuit generating a 32-bit ID.
[0033] Figure 10 is the circuit diagram of the embodiment 2 (1-bit ID) of the present application. DETAILED DESCRIPTION
[0034] Embodiment 1
[0035] The anti-fake PUF circuit generating a 1-bit ID is shown in Figure 2 The PUF circuit generating a 32-bit ID is shown in Figure 3 In the figure, the PMOS transistor M0 is a switch transistor, responsible for switching the PUF circuit, and its gate is connected to the EN signal. When the voltage of the EN signal is 5V, the circuit does not work, and when the voltage is 0V, the circuit starts to work.
[0036] As shown in Figure 2 , two identical PMOS transistors M1 and M2 form a sub-threshold current mirror, and the gates of the two transistors are connected to a bias voltage of 4.3V. At this time, the two MOS transistors will work in the sub-threshold region (the voltage value of this bias voltage needs to be determined according to the electrical characteristics of the MOS transistors used to ensure that they work in the sub-threshold region). The gates of two identical NMOS transistors M3 and M4 are connected to ground and are in the cutoff region.
[0037] In the figure, NET1 and NET2 are connected to the same capacitance to ground. Two inverters are used to detect whether the values of NET1 and NET2 reach the logical flip threshold of the inverter. The output results of the inverters are input to the R and S ports of the RS latch on the right side, and finally the output value Q of the RS latch is output as a bit ID value.
[0038] The working principle of the present application is as follows:
[0039] (1) When the EN signal is 5V, the switch transistor M0 is off, and the circuit does not start to work. At this time, the voltage values of NET1 and NET2 are 0, and after passing through the inverter, the input end R voltage value is 5V, the input end S voltage value is 5V, and the output value Q is 0V.
[0040] (2) When the value of EN drops to 0V, the switch tube M0 is turned on, at this time, the two tubes M1 and M2 working in sub-threshold region will have weak current flowing through, the current of M1 will charge the capacitor C1, and the current of M2 will charge the capacitor C2. Due to the inevitable difference between M1 and M2 in the production process, the current flowing through the two tubes cannot be guaranteed to be completely consistent, and according to formula 2, if there is a difference in Vth value between the two tubes, the current will have a great difference. Therefore, the charging speed of the two capacitors C1 and C2 is not consistent, and due to the weak drain current of the sub-threshold current mirror MOS tube, the charging time is relatively long. Therefore, the time when the voltage values at NET1 and NET2 reach the logic threshold voltage will have a large difference.
[0041] (3) If the charging speed of C1 capacitor is faster, at this time, the voltage of NET1 will reach the threshold voltage faster. (In order to facilitate the description, the value that has not reached the threshold voltage is referred to as the logic value '0', and the value after reaching the threshold voltage is referred to as the logic value '1'), after three stages as shown in Figure 4 , the final output value Q is 1.
[0042] (4) If the charging speed of C2 capacitor is faster, at this time, the voltage of NET2 will reach the threshold voltage faster. After three stages as shown in Figure 5 , the final output value Q is 0.
[0043] Verification: see Figures 6 to 9 .
[0044] Design the PUF circuit for generating a one-bit ID as shown in Figure 6 , and perform 1000 Monte Carlo simulations on the circuit (Monte Carlo simulation is a method of evaluating the statistical distribution of circuit performance parameters by random sampling, which is commonly used to analyze the influence of component parameter tolerance, process fluctuation or environmental change on circuit performance).
[0045] The output value Q of the Monte Carlo simulation is shown in Figure 7 , and the number of times when the output value Q is the logic value '0' and the logic value '1' after 1000 Monte Carlo simulations is shown in Figure 7 , it can be seen that the output value Q has a logic value of '0' for 488 times and a logic value of '1' for 512 times. This represents that the output value Q exhibits strong randomness after introducing random errors, and can be regarded as a PUF response.
[0046] Arrange the PUF circuit for generating a one-bit ID as described above to generate a 32-bit ID, and also perform multiple Monte Carlo simulations. In multiple Monte Carlo simulations, take two experimental results at random, result 1 is shown in Figure 8 , and result 2 is shown in Figure 9As shown, each of the 32 outputs Q0 to Q31 is displayed, and the output value is shown in the right MC column. The output value of about 40nV voltage can be regarded as a logic value '0', and the 5V voltage can be regarded as a logic value '1'.
[0047] Therefore Figure 8 The value of Q0:31 is 1001_0101_0101_0001_0001_1000_0100_0111, which is a set of 32-bit ID obtained. In another Monte Carlo simulation, as shown in Figure 9 The value of Q0:31 is 1101_0001_1010_0111_0110_1010_1110_1010. The same circuit under the same test conditions introduces process errors and presents different output results, i.e. different ID values.
[0048] Embodiment 2
[0049] Referring to Figure 10 In this embodiment, the first MOS transistor M1 is a PMOS transistor, the source thereof is connected to the common point, and the gate and the drain thereof are connected to the output end of the first branch; the third MOS transistor M3 is an NMOS transistor, the drain thereof is connected to the drain of the first MOS transistor M1, the source thereof is connected to the ground, and the gate thereof is connected to the control signal input end;
[0050] The second MOS transistor M2 is a PMOS transistor, the source thereof is connected to the common point, and the gate and the drain thereof are connected to the output end of the second branch; the fourth MOS transistor M4 is an NMOS transistor, the drain thereof is connected to the drain of the second MOS transistor M2, the source thereof is connected to the ground, and the gate thereof is connected to the control signal input end.
[0051] When EN is 0V, NET1 and NET2 will be high VDD-VGS1 and VDD-VGS2, at this time Q1 is a logic value 0. When EN becomes 0V, C1 and C2 are discharged through M3 and M4, if C1 is discharged first, Q1 is still a logic value 0. If C2 is discharged first, Q1 becomes a logic value 1.
Claims
1. A PUF anti-counterfeiting circuit based on sub-threshold region current mirror mismatch, characterized in that, The anti-fake unit comprises a switch tube, a current mirror and an RS latch, the current mirror comprises a first branch and a second branch, the first branch and the second branch are connected to a common point and are controlled by a same control signal input end, the switch tube is arranged between the common point and a high level end, and the first branch and the second branch are arranged in parallel between the common point and a ground level; an output end of the first branch is grounded through a capacitor and is connected to a first input end of the RS latch through an inverter; and an output end of the second branch is grounded through a capacitor and is connected to a second input end of the RS latch through an inverter.
2. The subthreshold region current mirror mismatch based PUF anti-counterfeiting circuit of claim 1, wherein, The first branch comprises a first MOS tube (M1) and a third MOS tube (M3) connected in series, and a connection point of the two is an output end of the first branch; and the second branch comprises a second MOS tube (M2) and a fourth MOS tube (M4) connected in series, and a connection point of the two is an output end of the second branch.
3. The subthreshold region current mirror mismatch based PUF anti-counterfeiting circuit of claim 2, wherein, The first MOS tube (M1) is a PMOS tube, a source thereof is connected to the common point, a drain thereof is connected to the output end of the first branch, and a gate thereof is connected to the control signal input end; the third MOS tube (M3) is an NMOS tube, a drain thereof is connected to the drain of the first MOS tube (M1), and a source and a gate thereof are grounded. The second MOS tube (M2) is a PMOS tube, a source thereof is connected to the common point, a drain thereof is connected to the output end of the second branch, and a gate thereof is connected to the control signal input end; and the fourth MOS tube (M4) is an NMOS tube, a drain thereof is connected to the drain of the second MOS tube (M2), and a source and a gate thereof are grounded.
4. The subthreshold region current mirror mismatch based PUF anti-counterfeiting circuit of claim 2, wherein, The first MOS tube (M1) is a PMOS tube, a source thereof is connected to the common point, and a gate and a drain thereof are connected to the output end of the first branch; and the third MOS tube (M3) is an NMOS tube, a drain thereof is connected to the drain of the first MOS tube (M1), a source thereof is grounded, and a gate thereof is connected to the control signal input end. The second MOS tube (M2) is a PMOS tube, a source thereof is connected to the common point, a gate and a drain thereof are connected to the output end of the second branch; and the fourth MOS tube (M4) is an NMOS tube, a drain thereof is connected to the drain of the second MOS tube (M2), a source thereof is grounded, and a gate thereof is connected to the control signal input end.
5. A PUF chip anti-counterfeiting method based on sub-threshold region current mirror mismatch, characterized in that, The generation of each bit of the anti-fake code comprises the following steps: (1) the same subthreshold control voltage is applied to the current mirror MOS tubes of the two branches of the current mirror, so that the current mirror MOS tubes of the two branches work in the subthreshold region; (2) the output currents of the two branches charge corresponding capacitors respectively; (3) the RS latch detects the states of the capacitors corresponding to the two branches, and outputs the anti-fake code.