Display panel and display device

Abstract

The invention discloses a display panel and a display device, the display panel comprises a plurality of cascaded gate drive circuits and a plurality of pixel units arranged in an array, and each pixel unit comprises a pixel drive circuit and a light emitting device. The pixel driving circuit comprises a driving transistor, a second light-emitting control transistor and a reset transistor. The second light-emitting control transistor is controlled by a second light-emitting control signal, and the reset transistor is controlled by a third light-emitting control signal. The second light-emitting control signal is a light-emitting control signal output by the Nth-stage gate drive circuit, and the third light-emitting control signal is a light-emitting control signal output by the (N + X) th-stage gate drive circuit cascaded behind the Nth-stage gate drive circuit. According to the pixel driving circuit, the reset transistor and the second light-emitting control transistor can be turned on at the same time in a certain time period, and effective and accurate reset is achieved for the pixel driving circuit.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and a display device. Background Technology

[0002] With the development of display technology, self-emissive display panels have been widely used in various display devices such as smartphones, tablets, and televisions. A self-emissive display panel typically includes a light-emitting device and a pixel driving circuit. By writing data signals and control signals into the pixel driving circuit, the circuit can drive the light-emitting device to emit light according to the data and control signals, thus displaying an image on the panel. To ensure the display quality of each frame, the corresponding nodes in the pixel driving circuit can be reset before driving the light-emitting device to emit light. How to achieve an effective and precise reset of the pixel driving circuit is a technical problem that the industry is currently researching. Summary of the Invention

[0003] This application provides a display panel and display device that can effectively and accurately reset the pixel driving circuit, avoiding the influence of the potential of the previous frame on the display of the current frame.

[0004] This application provides a display panel, which includes a plurality of cascaded gate driving circuits and a plurality of pixel units arranged in an array. Each gate driving circuit is used to drive at least one pixel unit in a pixel row. Each pixel unit includes a pixel driving circuit and a light-emitting device. For the pixel unit driven by the Nth level gate driving circuit, the pixel driving circuit includes a driving transistor, a second light-emitting control transistor, and a reset transistor.

[0005] The driving transistor includes a first electrode connected to a first node, a second electrode connected to a second node, and a control electrode connected to a third node.

[0006] The second light-emitting control transistor includes a first electrode connected to the second node, a second electrode connected to the fourth node, and a control electrode that receives the second light-emitting control signal;

[0007] The reset transistor includes a first electrode that receives a reset signal, a second electrode that is connected to the fourth node, and a control electrode that receives a third light emission control signal.

[0008] Wherein, the second light emission control signal is the light emission control signal output by the Nth stage gate driving circuit; the third light emission control signal is the light emission control signal output by the (N+X)th stage gate driving circuit cascaded after the Nth stage gate driving circuit; where N and X are both positive integers.

[0009] This application also provides a display device, including the display panel described above.

[0010] In summary, the technical solution provided in this application embodiment involves a second light-emitting control transistor controlled by a second light-emitting control signal, and a reset transistor controlled by a third light-emitting control signal. The second and third light-emitting control signals are output from two cascaded gate driving circuits. Since the waveforms of the light-emitting control signals output from the two cascaded gate driving circuits are consistent but have a certain time delay, using the light-emitting control signals output from the two cascaded gate driving circuits to control the reset transistor and the second light-emitting control transistor respectively allows them to conduct simultaneously for a certain period without affecting their original functions. This enables the reset signal connected to the reset transistor to not only reset the fourth node but also the second and first nodes, releasing residual charges and resetting their potentials. This provides an effective and precise reset for the pixel driving circuit, preventing the potential of the previous frame from affecting the display of the current frame. In addition, the reset signal can flow through the driver transistor to enable the OBS function of the driver transistor, ensuring the performance of the driver transistor and thus ensuring the display effect of each frame. Especially for VRR application scenarios, it can provide a smoother visual experience. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of a pixel driving circuit;

[0012] Figure 2 This is a schematic diagram of the driving timing;

[0013] Figure 3 This is a schematic diagram of a display panel provided in an embodiment of this application;

[0014] Figure 4 This is a schematic diagram of a pixel driving circuit provided in an embodiment of this application;

[0015] Figure 5 This is a schematic diagram of a driving timing provided in an embodiment of this application. Detailed Implementation

[0016] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. The described technical solutions are for illustrative purposes only and should not be construed as limiting the scope of protection of this application.

[0017] Furthermore, in the embodiments of this application, "multiple" refers to two or more. The terms "first" and "second," etc., in the embodiments of this application are used to distinguish different technical features and do not indicate any order, quantity, or importance.

[0018] The various embodiments provided in this application are similar, and features in different embodiments can be combined with each other.

[0019] The order in which the following embodiments are described is not intended to limit the preferred order of the embodiments.

[0020] Please see Figure 1 , Figure 1 This is a schematic diagram of a pixel driving circuit. This pixel driving circuit can be connected to a light-emitting device to drive the device to emit light. Figure 1 As shown, the pixel driving circuit includes a driving transistor T1, a writing transistor T2, a transmission transistor T3, a reset transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, and a storage capacitor Cst.

[0021] The driving transistor T1 includes a first electrode connected to a first node A, a second electrode connected to a second node B, and a control electrode connected to a third node Q.

[0022] The write transistor T2 includes a first electrode connected to the data signal DATA, a second electrode connected to the second node B, and a control electrode connected to the second scan control signal SCAN2.

[0023] The transmission transistor T3 includes a first electrode connected to the first node A, a second electrode connected to the third node Q, and a control electrode connected to the first scan control signal SCAN1.

[0024] The reset transistor T4 includes a first electrode connected to the reset signal VI, a second electrode connected to the fourth node C, and a control electrode connected to the second light emission control signal EM2. Specifically, for the R pixel, the reset signal VI connected to the reset transistor T4 can be VI_R; for the G and B pixels, the reset signal VI connected to the reset transistor T4 can be VI_GB. VI_R and VI_GB can be different reset signals, thus the reset signal VI corresponding to the G and B pixels can be the same, while the reset signal VI corresponding to the R pixel can be different from the reset signals VI corresponding to the G and B pixels.

[0025] The first light-emitting control transistor T5 includes a first electrode connected to a high-potential signal VDD, a second electrode connected to a first node A, and a control electrode connected to a first light-emitting control signal EM1.

[0026] The second light-emitting control transistor T6 includes a first electrode connected to the second node B, a second electrode connected to the fourth node C, and a control electrode that receives the second light-emitting control signal EM2.

[0027] The storage capacitor Cst includes one end connected to the third node Q and the other end connected to the fourth node C.

[0028] The light-emitting device includes an anode connected to the fourth node C and a cathode connected to a low-potential signal VSS.

[0029] In some embodiments, the control electrode may be a gate, the first electrode may be one of the source or the drain, and the second electrode may be the other of the source or the drain.

[0030] It should be understood that Figure 1 In this example, the driving transistor T1, writing transistor T2, transmission transistor T3, and reset transistor T4 are all N-type thin film transistors (NTFTs), and the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both P-type thin film transistors (PTFTs). However, this does not constitute a limitation on the embodiments of this application. In practical applications, each transistor can be arbitrarily set to NTFT or PTFT in conjunction with the driving timing.

[0031] Please see Figure 2 , Figure 2 This is a schematic diagram of a driving timing. Figure 2 The driving timing shown can be used for driving. Figure 1 The corresponding components in the pixel driving circuit are shown. For example... Figure 2 As shown, a display frame of the display panel includes a reset phase, a data writing phase, and a light emission phase.

[0032] During the reset phase, the first light-emitting control signal EM1 is low, and the first light-emitting control transistor T5 is turned on; the second light-emitting control signal EM2 is high, the reset transistor T4 is turned on, and the second light-emitting control transistor T6 is turned off; the first scan control signal SCAN1 is high, and the transmission transistor T3 is turned on; the second scan control signal SCAN2 is low, and the write transistor T2 is turned off. Therefore, during the reset phase, both the transmission transistor T3 and the first light-emitting control transistor T5 are turned on, allowing the high-potential signal VDD to be written to the third node Q; the reset transistor T4 is turned on, allowing the reset signal VI to be written to the fourth node C to reset the anode of the light-emitting device.

[0033] During the data writing phase, the first light-emitting control signal EM1 is high, and the first light-emitting control transistor T5 is off; the second light-emitting control signal EM2 is high, the reset transistor T4 is on, and the second light-emitting control transistor T6 is off; the first scan control signal SCAN1 is high, and the transmission transistor T3 is on; the second scan control signal SCAN2 is high, and the write transistor T2 is on. Therefore, during the data writing phase, both the write transistor T2 and the transmission transistor T3 are on, the data signal DATA is written to the third node Q, and the gate voltage Vg of the driving transistor T1 is the sum of the threshold voltage Vth and the data signal DATA, thus compensating for the threshold voltage Vth of the driving transistor T1; the reset transistor T4 remains on, the reset signal VI is continuously written to the fourth node C, and the anode of the light-emitting device is continuously reset.

[0034] During the light-emitting phase, the first light-emitting control signal EM1 is low, and the first light-emitting control transistor T5 is turned on; the second light-emitting control signal EM2 is low, the reset transistor T4 is turned off, and the second light-emitting control transistor T6 is turned on; the first scan control signal SCAN1 is low, and the transmission transistor T3 is turned off; the second scan control signal SCAN2 is low, and the write transistor T2 is turned off. Therefore, during the light-emitting phase, both the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on. The driving transistor T1 is turned on because the third node Q is at a high potential. The current flowing through the driving transistor T1 can pass through the second node B and the fourth node C, thereby driving the light-emitting device to emit light.

[0035] In summary, Figure 1 In the pixel driving circuit shown, both the reset transistor T4 and the second light-emitting control transistor T6 are driven by the second light-emitting control signal EM2. Therefore, the reset transistor T4 and the second light-emitting control transistor T6 cannot be turned on simultaneously, and the reset signal VI cannot be written to the second node B and the first node A, thus preventing the reset of the second node B and the first node A. Furthermore, because the reset transistor T4 and the second light-emitting control transistor T6 cannot be turned on simultaneously, the reset signal VI cannot flow through the driving transistor T1, and the driving transistor T1 cannot perform the OBS (On Bias Stress) function.

[0036] Please see Figure 3 , Figure 3 This is a schematic diagram of a display panel provided in an embodiment of this application. Figure 3 As shown, the display panel includes multiple cascaded gate drive circuits 310 and multiple pixel units 320 arranged in an array.

[0037] Among them, such as Figure 3As shown, the display panel includes a display area AA and a non-display area NA adjacent to the display area AA, with the non-display area NA surrounding the display area AA. The display area AA is the region within the display panel used for display functions, and the multiple pixel units 320 arranged in the array described above can be disposed within the display area AA. The non-display area NA can be a border area of ​​the display panel, and functional components that assist the pixel units 320 in the display area AA in displaying functions can be disposed within it. The multiple gate driving circuits 310 described above can be disposed within the non-display area NA.

[0038] Each gate driving circuit 310 is used to drive pixel units 320 in at least one pixel row. In this embodiment, the gate driving circuit 310 can provide light emission control signals to the pixel units 320. For example, each gate driving circuit 310 can provide light emission control signals to pixel units 320 in one or two pixel rows.

[0039] For pixel units 320 driven by the Nth-stage gate driving circuit 310, driving these pixel units 320 to emit light requires multiple light emission control signals and multiple scan control signals. These multiple light emission control signals can be provided by different stages of the cascaded gate driving circuits 310, so that each pixel unit 320 can be driven by a different stage of the gate driving circuit 310. These multiple scan control signals can be provided by gate driving circuits of the same stage in the cascaded gate driving circuits 310.

[0040] For example, such as Figure 3 As shown, the display panel includes multiple cascaded first gate driving circuits 311, multiple cascaded second gate driving circuits 312, multiple cascaded third gate driving circuits 313, and multiple cascaded fourth gate driving circuits 314, as well as multiple pixel units 320 arranged in an array. For the pixel unit 320 driven by the Nth-level gate driving circuit 310, the light emission control signals required to drive the pixel unit 320 to emit light include a first light emission control signal EM1(N), a second light emission control signal EM2(N), and a third light emission control signal EM2(N+X). The scan control signals required to drive the pixel unit 320 to emit light include a first scan control signal SCAN1 and a second scan control signal SCAN2. The first light emission control signal EM1(N) can be provided by the first gate driving circuit 311, and the second light emission control signal EM2(N) and the third light emission control signal EM2(N+X) can be provided by two cascaded second gate driving circuits 312. The first scan control signal SCAN1 can be provided by the third gate drive circuit 313, and the second scan control signal SCAN2 can be provided by the fourth gate drive circuit 314.

[0041] It should be understood that Figure 3The arrangement of the display panel, gate driving circuit, and pixel units shown is merely an example and does not constitute a limitation of this application. In practical applications, other arrangements may be possible depending on the requirements. For example, the non-display area NA in the display panel may be located only on one side of the display area AA; or, multiple cascaded gate driving circuits 310 may be located only in the non-display area NA on one side of the display area AA, while other auxiliary pixel units 320 can be set in the non-display area AA on the other side of the display area AA as display functional components; or, each gate driving circuit 310 may be used to drive pixel units 320 in two or more pixel rows.

[0042] For details regarding the specific structure of the pixel unit 320, as well as other descriptions of the light emission control signals required to drive the pixel unit 320 to emit light, please refer to the following embodiments, which will not be elaborated here.

[0043] In the following embodiments, a pixel unit 320 driven by an Nth-level gate driving circuit is taken as an example. This pixel unit 320 includes a pixel driving circuit and a light-emitting device. The gate driving circuit described in the following embodiments can be... Figure 3 The second gate driving circuit 312 shown; the Nth stage gate driving circuit and the N+Xth stage gate driving circuit described in the following embodiments can be respectively Figure 3 The Nth stage second gate drive circuit 312 and the N+Xth stage second gate drive circuit 312 in the cascaded plurality of second gate drive circuits 312 shown. N and X are both positive integers.

[0044] Please see Figure 4 , Figure 4 This is a schematic diagram of a pixel driving circuit provided in an embodiment of this application. Figure 4 As shown, the pixel driving circuit includes: a driving transistor T1, a second light-emitting control transistor T6, and a reset transistor T4.

[0045] The driving transistor T1 includes a first electrode connected to a first node A, a second electrode connected to a second node B, and a control electrode connected to a third node Q.

[0046] The second light-emitting control transistor T6 includes a first electrode connected to the second node B, a second electrode connected to the fourth node C, and a control electrode connected to the second light-emitting control signal EM2(N).

[0047] The reset transistor T4 includes a first electrode connected to the reset signal VI, a second electrode connected to the fourth node C, and a control electrode connected to the third light emission control signal EM2(N+X).

[0048] This pixel driving circuit is used to drive the light-emitting device to emit light.

[0049] For a pixel unit driven by the Nth-level gate driving circuit, the second light emission control signal EM2(N) is the light emission control signal output by the Nth-level gate driving circuit; the third light emission control signal EM2(N+X) is the light emission control signal output by the (N+X)th-level gate driving circuit cascaded after the Nth-level gate driving circuit. N and X are both positive integers.

[0050] Since the waveforms of the light emission control signals output by the two cascaded gate drive circuits are consistent but have a certain time delay, by using the light emission control signals output by the two cascaded gate drive circuits to control the reset transistor T4 and the second light emission control transistor T6 respectively, it is possible to enable the reset transistor T4 and the second light emission control transistor T6 to conduct simultaneously for a certain period of time without affecting their original functions. Therefore, the reset signal VI connected to the reset transistor T4 can not only reset the fourth node C, but also the second node B and the first node A, so as to release the residual charge of the second node B and the first node A in time, reset the potential of the second node B and the first node A, and prevent the potential of the previous frame from affecting the display of the current frame. In addition, the reset signal VI can flow through the driver transistor T1 to realize the OBS function of the driver transistor T1, ensuring the performance of the driver transistor T1, thereby ensuring the display effect of each frame, especially for VRR (Variable Refresh Rate) applications, providing a smoother visual experience.

[0051] The specific value of X is not limited in this application embodiment, and can be flexibly set according to actual needs. The value of X can be obtained through experimentation or empirical values, etc., which needs to ensure that there is a certain time delay between the second light emission control signal EM2(N) and the third light emission control signal EM2(N+X), and also needs to avoid affecting other functions of the pixel driving circuit such as data writing, light emission, and reset. In some embodiments, X is a positive integer less than or equal to 3. Taking X as 1 as an example, the third light emission control signal EM2(N+1) is the light emission control signal output by the (N+1)th stage gate driving circuit cascaded after the Nth stage gate driving circuit; the control electrode of the second light emission control transistor T6 is connected to the second light emission control signal EM2(N), and the control electrode of the reset transistor T4 is connected to the third light emission control signal EM2(N+1).

[0052] In some embodiments, a display frame of the display panel includes a target phase; in the target phase, a reset transistor T4 is turned on according to the accessed third light emission control signal EM2(N+X), and a second light emission control transistor T6 is turned on according to the accessed second light emission control signal EM2(N), so that the reset signal VI accessed by the reset transistor T4 is transmitted to the fourth node C, the second node B and the first node A respectively, so as to reset the fourth node C, the second node B and the first node A.

[0053] Taking the reset transistor T4 as an NTFT and the second light-emitting control transistor T6 as a PTFT as an example, in the target stage, the second light-emitting control signal EM2(N) is low and the third light-emitting control signal EM2(N+1) is high. Then, both the second light-emitting control transistor T6 and the reset transistor T4 are turned on to realize the reset of the fourth node C, the second node B and the first node A, as well as the OBS function of the driving transistor T1.

[0054] In some embodiments, for the R pixel, the reset signal VI connected to the reset transistor T4 can be VI_R; for the G and B pixels, the reset signal VI connected to the reset transistor T4 can be VI_GB. VI_R and VI_GB can be different reset signals, so the reset signal VI corresponding to the G and B pixels can be the same, while the reset signal VI corresponding to the R pixel can be different from the reset signals VI corresponding to the G and B pixels.

[0055] In some embodiments, such as Figure 4 As shown, the pixel driving circuit also includes a first light-emitting control transistor T5.

[0056] The first light-emitting control transistor T5 includes a first electrode connected to a high-potential signal VDD, a second electrode connected to a first node A, and a control electrode connected to a first light-emitting control signal EM1(N).

[0057] The light-emitting device includes an anode connected to the fourth node C and a cathode connected to a low-potential signal VSS.

[0058] In this embodiment, a display frame of the display panel further includes a light-emitting stage. During the light-emitting stage, the first light-emitting control transistor T5 is turned on according to the received first light-emitting control signal EM1(N), and the second light-emitting control transistor T6 is turned on according to the received second light-emitting control signal EM2(N). The driving transistor T1 is turned on because the third node Q is at a high potential. The current flowing through the driving transistor T1 can pass through the second node B and the fourth node C, causing the light-emitting device to emit light. Taking a PTFT as an example, if both the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are PTFTs, during the light-emitting stage, both the first light-emitting control signal EM1(N) and the second light-emitting control signal EM2(N) are at a low level, then both the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, causing the light-emitting device to emit light. To avoid affecting the display of the current frame, the target stage can be located before the light-emitting stage.

[0059] In some embodiments, such as Figure 4 As shown, the pixel driving circuit also includes a transmission transistor T3 and a write transistor T2.

[0060] The transmission transistor T3 includes a first electrode connected to the first node A, a second electrode connected to the third node Q, and a control electrode connected to the first scan control signal SCAN1.

[0061] The write transistor T2 includes a first electrode connected to the data signal DATA, a second electrode connected to the second node B, and a control electrode connected to the second scan control signal SCAN2.

[0062] The first scan control signal SCAN1 and the second scan control signal SCAN2 are both scan control signals output by the Nth stage gate drive circuit.

[0063] In this design, write transistor T2 is used for data writing, and transmission transistor T3 is used to control the transmission path between the first node A and the third node Q. To achieve data writing, a display frame of the display panel also includes a data writing stage. During this stage, transmission transistor T3 is turned on according to the first scan control signal SCAN1, and write transistor T2 is turned on according to the second scan control signal SCAN2, so that the data signal DATA connected to write transistor T2 is written to the third node Q. Taking NTFTs as an example, during the data writing stage, if both the first scan control signal SCAN1 and the second scan control signal SCAN2 are high, then both write transistor T2 and transmission transistor T3 are turned on, so that the data signal DATA connected to write transistor T2 is written to the third node Q. Since OBS is performed on drive transistor T1 during the target stage, the channel charge distribution and other characteristics of drive transistor T1 may change. To avoid the inability of drive transistor T1 to accurately adjust its conduction level and affect the accuracy of data storage, the target stage can be located after the data writing stage.

[0064] In this embodiment, a display frame of the display panel further includes a reset phase. During the reset phase, the first light-emitting control transistor T5 is turned on according to the received first light-emitting control signal EM1(N), and the transmission transistor T3 is turned on according to the received first scan control signal SCAN1, so that the high-potential signal VDD received by the first light-emitting control transistor T5 is written to the third node Q; during the reset phase, the reset transistor T4 is turned on according to the received third light-emitting control signal EM2(N+X), so that the reset signal VI received by the reset transistor T4 is transmitted to the fourth node C to reset the fourth node C. Taking the first light-emitting control transistor T5 as a PTFT and both the transmission transistor T3 and the reset transistor T4 as NTFTs as an example, during the reset phase, the first light-emitting control signal EM1(N) is low and both the first scan control signal SCAN1 and the third light-emitting control signal EM2(N+X) are high. Then, the first light-emitting control transistor T5 and the transmission transistor T3 are turned on so that the high-potential signal VDD received by the first light-emitting control transistor T5 is written to the third node Q, and the reset transistor T4 is turned on so that the reset signal VI received by the reset transistor T4 is written to the fourth node C. The data writing phase occurs after the reset phase.

[0065] In some embodiments, such as Figure 4 As shown, the pixel driving circuit also includes a storage capacitor Cst; the storage capacitor Cst includes one end connected to the third node Q and the other end connected to the fourth node C; wherein, the storage capacitor Cst is used to control a stable voltage difference between the third node Q and the fourth node C.

[0066] In some embodiments, the driving transistor T1 is an oxide transistor.

[0067] In some embodiments, the second light-emitting control transistor T6 and the reset transistor T4 are thin-film transistors of different types.

[0068] It should be understood that the control electrode described in the above embodiments can be a gate, the first electrode can be one of the source or drain, and the second electrode can be the other of the source or drain. Furthermore, Figure 4 Taking the driving transistor T1, writing transistor T2, transmission transistor T3, and reset transistor T4 as examples, and the first light-emitting control transistor T5 and the second light-emitting control transistor T6 as examples, this does not constitute a limitation on the embodiments of this application. In practical applications, each transistor can be arbitrarily set to NTFT or PTFT in conjunction with the driving timing.

[0069] In summary, in the technical solution provided by the embodiments of this application, the second light-emitting control transistor T6 is controlled by the second light-emitting control signal EM2(N), and the reset transistor T4 is controlled by the third light-emitting control signal EM2(N+X). The second light-emitting control signal EM2(N) and the third light-emitting control signal EM2(N+X) are light-emitting control signals output by two cascaded gate driving circuits respectively. Since the waveforms of the light emission control signals output by the two cascaded gate drive circuits are consistent but have a certain time delay, by using the light emission control signals output by the two cascaded gate drive circuits to control the reset transistor T4 and the second light emission control transistor T6 respectively, it is possible to enable the reset transistor T4 and the second light emission control transistor T6 to conduct simultaneously for a certain period of time without affecting their original functions. Therefore, the reset signal connected to the reset transistor T4 can not only reset the fourth node C, but also the second node B and the first node A, so as to release the residual charge of the second node B and the first node A in time and reset the potential of the second node B and the first node A. This achieves effective and precise reset of the pixel drive circuit, preventing the potential of the previous frame from affecting the display of the current frame. Furthermore, the reset signal VI can flow through the drive transistor T1 to realize the OBS function of the drive transistor T1, ensuring the performance of the drive transistor T1 and thus ensuring the display effect of each frame, especially for VRR applications, providing a smoother visual experience.

[0070] In this embodiment, the first light-emitting control transistor T5 is connected to the first light-emitting control signal EM1(N) and the first node A; the second light-emitting control transistor T6 is connected to the second light-emitting control signal EM2(N) and the second node B and the fourth node C; the transmission transistor T3 is connected to the first scan control signal SCAN1 and the first node A and the third node Q; the reset transistor T4 is connected to the third light-emitting control signal EM2(N+1) and the reset signal VI and the fourth node C; and the write transistor T2 is connected to the second scan control signal SCAN2 and the data signal DATA and the second node B. This design allows for efficient signal transmission to key nodes in the pixel driving circuit and optimizes transistor layout while reducing wiring redundancy. Figure 4 As shown, the embodiments of this application rationally arrange the transistors, and this highly integrated circuit structure helps to reduce the size of the pixel driving circuit; and, as Figure 3 As shown, the embodiments of this application reduce the complexity of wiring and optimize the wiring space, allowing the pixel driving circuit to be arranged more compactly. Through the transistor layout and wiring design of the embodiments of this application, the integration of the circuit can be improved, which not only ensures the display effect of the screen (such as providing a smoother visual experience for VRR application scenarios), but also helps to achieve narrow bezels.

[0071] Please see Figure 5 , Figure 5 This is a schematic diagram of a driving timing. Figure 5 The driving timing shown can be used for driving. Figure 4 The corresponding components in the pixel driving circuit shown. Figure 4 Taking the example where the driving transistor T1, writing transistor T2, transmission transistor T3, and reset transistor T4 are all NTFTs, and the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both PTFTs. Figure 5 As shown, a display frame of the display panel includes a reset phase, a data writing phase, a target phase, and a light emission phase.

[0072] During the reset phase, the first light-emitting control signal EM1(N) is low, and the first light-emitting control transistor T5 is turned on; the second light-emitting control signal EM2(N) is high, and the second light-emitting control transistor T6 is turned off; the third light-emitting control signal EM2(N+X) is high, and the reset transistor T4 is turned on; the first scan control signal SCAN1 is high, and the transmission transistor T3 is turned on; the second scan control signal SCAN2 is low, and the write transistor T2 is turned off. Therefore, during the reset phase, both the transmission transistor T3 and the first light-emitting control transistor T5 are turned on, allowing the high-potential signal VDD to be written to the third node Q; the reset transistor T4 is turned on, allowing the reset signal VI to be written to the fourth node C, thus resetting the anode of the light-emitting device.

[0073] During the data writing phase, the first light-emitting control signal EM1(N) is high, and the first light-emitting control transistor T5 is turned off; the second light-emitting control signal EM2(N) is high, and the second light-emitting control transistor T6 is turned off; the third light-emitting control signal EM2(N+X) is high, and the reset transistor T4 is turned on; the first scan control signal SCAN1 is high, and the transmission transistor T3 is turned on; the second scan control signal SCAN2 is high, and the write transistor T2 is turned on. Therefore, during the data writing phase, both the write transistor T2 and the transmission transistor T3 are turned on, the data signal DATA is written to the third node Q, and the gate voltage Vg of the driving transistor T1 is the sum of the threshold voltage Vth and the data signal DATA, thus compensating for the threshold voltage Vth of the driving transistor T1; the reset transistor T4 remains on, the reset signal VI is continuously written to the fourth node C, and the anode of the light-emitting device is continuously reset.

[0074] During the target phase, the first light-emitting control signal EM1(N) is high, and the first light-emitting control transistor T5 is off; the second light-emitting control signal EM2(N) is low, and the second light-emitting control transistor T6 is on; the third light-emitting control signal EM2(N+X) is high, and the reset transistor T4 is on; the first scan control signal SCAN1 is low, and the transmission transistor T3 is off; the second scan control signal SCAN2 is low, and the write transistor T2 is off. Therefore, during the target phase, both the second light-emitting control transistor T6 and the reset transistor T4 are on, and the reset signal VI can be sequentially written to the fourth node C, the second node B, and the first node A, promptly releasing the residual charge of the first node A and the second node B, resetting the potential of the second node B and the first node A, and preventing the potential of the previous frame from affecting the display of the current frame; in addition, the reset signal VI can flow through the driving transistor T1 to realize the OBS function of the driving transistor T1.

[0075] During the light-emitting phase, the first light-emitting control signal EM1(N) is low, and the first light-emitting control transistor T5 is turned on; the second light-emitting control signal EM2(N) is low, and the second light-emitting control transistor T6 is turned on; the third light-emitting control signal EM2(N+X) is low, and the reset transistor T4 is turned off; the first scan control signal SCAN1 is low, and the transmission transistor T3 is turned off; the second scan control signal SCAN2 is low, and the write transistor T2 is turned off. Therefore, during the light-emitting phase, both the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the driving transistor T1 is turned on because the third node Q is at a high potential. The current flowing through the driving transistor T1 can pass through the second node B and the fourth node C, thereby driving the light-emitting device to emit light.

[0076] This application embodiment also provides a display device, which includes the display panel described in the above embodiments, for example, including the aforementioned... Figure 3 The display panel shown is described above. For a detailed explanation of the structure and beneficial effects of the display panel in the display device, please refer to the above embodiments; further details will not be repeated here.

[0077] The embodiments of this application do not limit the specific type of display device. For example, the display device can be implemented as any of the following: OLED (Organic Light Emitting Diode) display, Micro LED (Micro Light Emitting Diode) display, Mini LED (Miniature Light Emitting Diode) display, AMOLED (Active Matrix Organic Light Emitting Diode) display, etc.

[0078] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0079] The above provides a detailed description of a display panel and display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized in that, The display panel includes a plurality of cascaded gate driving circuits and a plurality of pixel units arranged in an array. Each gate driving circuit is used to drive at least one pixel unit in a pixel row. Each pixel unit includes a pixel driving circuit and a light-emitting device. For the pixel unit driven by the Nth level gate driving circuit, the pixel driving circuit includes a driving transistor (T1), a second light-emitting control transistor (T6), and a reset transistor (T4). The driving transistor (T1) includes a first electrode connected to a first node (A), a second electrode connected to a second node (B), and a control electrode connected to a third node (Q); The second light-emitting control transistor (T6) includes a first electrode connected to the second node (B), a second electrode connected to the fourth node (C), and a control electrode that receives the second light-emitting control signal (EM2(N)). The reset transistor (T4) includes a first electrode connected to a reset signal (VI), a second electrode connected to the fourth node (C), and a control electrode connected to a third light emission control signal (EM2(N+X)). Wherein, the second light emission control signal (EM2(N)) is the light emission control signal output by the Nth stage gate driving circuit; the third light emission control signal (EM2(N+X)) is the light emission control signal output by the N+Xth stage gate driving circuit cascaded after the Nth stage gate driving circuit; N and X are both positive integers.

2. The display panel according to claim 1, characterized in that, X is 1, and the third light emission control signal (EM2(N+X)) is the light emission control signal output by the (N+1)th stage gate driving circuit cascaded after the Nth stage gate driving circuit.

3. The display panel according to claim 1, characterized in that, One display frame of the display panel includes a target phase; In the target stage, the reset transistor (T4) is turned on according to the received third light emission control signal (EM2(N+X)), and the second light emission control transistor (T6) is turned on according to the received second light emission control signal (EM2(N)), so that the reset signal (VI) received by the reset transistor (T4) is transmitted to the fourth node (C), the second node (B) and the first node (A) respectively, so as to reset the fourth node (C), the second node (B) and the first node (A).

4. The display panel according to claim 3, characterized in that, The pixel driving circuit further includes a first light-emitting control transistor (T5); wherein, The first light-emitting control transistor (T5) includes a first electrode connected to a high-potential signal (VDD), a second electrode connected to the first node (A), and a control electrode connected to a first light-emitting control signal (EM1(N)). The light-emitting device includes an anode connected to the fourth node (C) and a cathode connected to a low-potential signal (VSS).

5. The display panel according to claim 4, characterized in that, One of the display frames of the display panel further includes a light-emitting phase; During the light-emitting stage, the first light-emitting control transistor (T5) is turned on according to the first light-emitting control signal (EM1(N)) and the second light-emitting control transistor (T6) is turned on according to the second light-emitting control signal (EM2(N)) to make the light-emitting device emit light; The target stage is located before the light emission stage.

6. The display panel according to claim 4, characterized in that, The pixel driving circuit also includes a transmission transistor (T3) and a write transistor (T2); The transmission transistor (T3) includes a first electrode connected to the first node (A), a second electrode connected to the third node (Q), and a control electrode connected to the first scan control signal (SCAN1); The write transistor (T2) includes a first electrode that receives a data signal (DATA), a second electrode that is connected to the second node (B), and a control electrode that receives a second scan control signal (SCAN2).

7. The display panel according to claim 6, characterized in that, The first scan control signal (SCAN1) and the second scan control signal (SCAN2) are both scan control signals output by the gate drive circuit of the Nth stage.

8. The display panel according to claim 6, characterized in that, One of the display frames of the display panel further includes a data writing phase; During the data writing phase, the transmission transistor (T3) is turned on according to the first scan control signal (SCAN1) and the writing transistor (T2) is turned on according to the second scan control signal (SCAN2) so that the data signal (DATA) connected to the writing transistor (T2) is written to the third node (Q). The target stage is located after the data writing stage.

9. The display panel according to claim 8, characterized in that, One of the display frames of the display panel further includes a reset phase; During the reset phase, the first light-emitting control transistor (T5) is turned on according to the first light-emitting control signal (EM1(N)) and the transmission transistor (T3) is turned on according to the first scan control signal (SCAN1) so that the high potential signal (VDD) connected to the first light-emitting control transistor (T5) is written to the third node (Q). During the reset phase, the reset transistor (T4) is turned on according to the third light emission control signal (EM2(N+X)) so that the reset signal (VI) connected to the reset transistor (T4) is transmitted to the fourth node (C) to reset the fourth node (C); The data writing phase occurs after the reset phase.

10. The display panel according to claim 1, characterized in that, The pixel driving circuit also includes a storage capacitor (Cst); The storage capacitor (Cst) includes one end connected to the third node (Q) and the other end connected to the fourth node (C); The storage capacitor (Cst) is used to control a stable voltage difference between the third node (Q) and the fourth node (C).

11. The display panel according to claim 1, characterized in that, The driving transistor (T1) is an oxide transistor.

12. The display panel according to claim 1, characterized in that, The second light-emitting control transistor (T6) and the reset transistor (T4) are thin-film transistors of different types.

13. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1 to 12.

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