Display panel and display device

Abstract

The invention discloses a display panel and a display device, a first scanning line and a second scanning line of the same scanning unit are arranged on two opposite sides of a pixel row along a column direction, and in the same scanning unit, the first scanning line is electrically connected with a part of sub-pixels of the corresponding pixel row, and the second scanning line is electrically connected with a part of sub-pixels of the corresponding pixel row. The second scanning line is electrically connected with the other part of sub-pixels of the corresponding pixel row, and the ending time of the effective pulse of the first scanning signal transmitted by the first scanning line is ahead of the starting time of the effective pulse of the second scanning signal transmitted by the second scanning line, so that the effective pulse of the second scanning signal is generated by utilizing the jump of the second scanning signal from the ineffective level to the effective level. The influence on the pixel voltage of the sub-pixel electrically connected with the first scanning line due to the fact that the second scanning signal jumps from the effective level to the ineffective level and is coupled through the stray capacitor is reduced, and the problem that the head shaking lines appear when the display panel carries out picture display is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] Compared with a 1Gate 1Data (1G1D) driving architecture, a dual gate pixel structure (DLS) can reduce the number of chip on film (COF) used by a display panel. However, in the DLS architecture, the voltage of a pixel electrode can be affected by the level variation of a scanning signal transmitted by a scanning line, thereby causing a feedthrough effect and leading to a display problem of a wobble line in the display panel. SUMMARY

[0003] The present application provides a display panel and a display device for improving the display problem of a wobble line in a display panel.

[0004] To achieve the above object, the present application provides a display panel, comprising a plurality of sub-pixels, a plurality of data lines and a plurality of scanning units. The plurality of sub-pixels are arranged along a row direction and a column direction to form a plurality of pixel rows arranged along the column direction and a plurality of pixel columns arranged along the row direction. The plurality of data lines are electrically connected with the plurality of sub-pixels, and each data line is configured to transmit a data signal to a corresponding plurality of sub-pixels. Each scanning unit comprises a first scanning line and a second scanning line, and the first scanning line and the second scanning line of the same scanning unit are located on opposite sides of a pixel row along the column direction. In the same scanning unit, the first scanning line is electrically connected with part of the sub-pixels of the corresponding pixel row, and the second scanning line is electrically connected with another part of the sub-pixels of the corresponding pixel row. Wherein, in the same scanning unit, the end time of the effective pulse of the first scanning signal transmitted by the first scanning line is ahead of the start time of the effective pulse of the second scanning signal transmitted by the second scanning line.

[0005] The present application also provides a display device comprising any of the above display panels.

[0006] The above technical solution arranges the first and second scan lines of the same scanning unit on opposite sides of a pixel row along the column direction. In the same scanning unit, the first scan line is electrically connected to a portion of the sub-pixels of the corresponding pixel row, and the second scan line is electrically connected to another portion of the sub-pixels of the corresponding pixel row. The end time of the effective pulse of the first scan signal transmitted by the first scan line precedes the start time of the effective pulse of the second scan signal transmitted by the second scan line. This utilizes the transition of the second scan signal from an invalid level to an effective level to compensate for the impact on the pixel voltage of the sub-pixels electrically connected to the first scan line when the first scan signal transitions from an effective level to an invalid level. Consequently, when the second scan signal transitions from an effective level to an invalid level, the impact of the fluctuation of the second scan signal on the pixel voltage of the sub-pixels electrically connected to the first scan line through parasitic capacitive coupling is reduced, thus improving the problem of head-shaking patterns on the display panel. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0008] Figures 1A-1B This is a schematic diagram of the display panel structure according to an embodiment of this application;

[0009] Figure 2 This is a schematic diagram of the sub-pixel structure according to an embodiment of this application;

[0010] Figure 3 for Figures 1A-1B The timing diagram of the scan signals corresponding to the display panel is shown.

[0011] Figures 4A-4B This is a schematic diagram of the structure of a 4-row pixel row as a comparative example of this application;

[0012] Figures 4C-4D This is a schematic diagram of the structure of a 4-row pixel row according to an embodiment of this application;

[0013] Figure 5A for Figures 4A-4B The timing diagram of the scan signal corresponding to the pixel row shown;

[0014] Figure 5B for Figures 4C-4D The timing diagram of the scan signal corresponding to the pixel row shown;

[0015] Figure 6 This is a schematic diagram showing the connection between the gate drive circuit and the clock line in an embodiment of this application;

[0016] Figure 7 A clock timing diagram of a plurality of clock signals of an embodiment of the present application;

[0017] Figure 8 Another structural schematic diagram of a display panel of an embodiment of the present application;

[0018] The implementation, functional features and advantages of the embodiments of the present application will be further described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of the present application.

[0020] In addition, the descriptions such as “first”, “second” and the like in the embodiments of the present application are only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by “first”, “second” can explicitly or implicitly include at least one of the features. In addition, the technical solutions of the various embodiments can be combined with each other, but it must be based on the fact that the technical solutions can be realized by those of ordinary skill in the art. When the combination of technical solutions appears to be contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, and is not within the scope of protection claimed by the present application.

[0021] As Figures 1A-1B A structural schematic diagram of a display panel of an embodiment of the present application. The present application provides a display panel, which includes a plurality of sub-pixels Spx, a plurality of data lines DL and a plurality of scanning units SU.

[0022] Optionally, the display panel includes a liquid crystal display panel. The display panel includes an array substrate, a color film substrate and liquid crystal located between the array substrate and the color film substrate.

[0023] The plurality of sub-pixels Spx are arranged along a row direction x and a column direction y, so as to form a plurality of pixel rows Spr arranged along the column direction y and a plurality of pixel columns Spc arranged along the row direction x.

[0024] Optionally, the plurality of sub-pixels Spx include first sub-pixels Spx1, second sub-pixels Spx2 and third sub-pixels Spx3 having different light-emitting colors.

[0025] It should be noted that the row direction x and the column direction y can be set according to actual needs. That is, the row direction x in the present application can be regarded as the column direction in some embodiments, and the column direction y in the present application can be regarded as the row direction x in some embodiments.

[0026] As Figure 2 is a structural schematic diagram of a sub-pixel in an embodiment of the present application. Each sub-pixel Spx includes a first transistor T1, a liquid crystal capacitor Clc, a storage capacitor Cst, a pixel electrode PE, a common electrode CE, and a liquid crystal (not shown in the figure) arranged between the common electrode CE and the pixel electrode PE.

[0027] The control end of the first transistor T1 is electrically connected with a corresponding scan line, the input end of the first transistor T1 is electrically connected with a corresponding data line DL, and the output end of the first transistor T1 is electrically connected with a corresponding pixel electrode PE.

[0028] The liquid crystal capacitor Clc is formed by the pixel electrode PE, the common electrode CE, and the liquid crystal.

[0029] Optionally, the pixel electrode PE is arranged on the array substrate side, and the common electrode CE is arranged on the color filter substrate side.

[0030] Optionally, the two electrodes of the storage capacitor Cst can be formed by the pixel electrode PE and the common bus line CE1, or can be formed by the pixel electrode PE and the scan line SL.

[0031] Please continue to refer to Figures 1A-1B and Figure 2 A plurality of data lines DL are electrically connected with a plurality of sub-pixels Spx, and each data line DL is configured to transmit a data signal to a corresponding plurality of sub-pixels Spx.

[0032] Each scan unit SU includes a first scan line SLA and a second scan line SLB, and the first scan line SLA and the second scan line SLB of the same scan unit SU are located on opposite sides of a pixel row Spr along the column direction y; in the same scan unit SU, the first scan line SLA is electrically connected with part of the sub-pixels Spx of the corresponding pixel row Spr, and the second scan line SLB is electrically connected with another part of the sub-pixels Spx of the corresponding pixel row Spr.

[0033] As Figure 3 is Figures 1A-1BThe diagram shows the timing of the scanning signals corresponding to the display panel. In the same scanning unit SU, the end time tA of the effective pulse of the first scanning signal ScanA transmitted by the first scanning line SLA precedes the start time tB of the effective pulse of the second scanning signal ScanB transmitted by the second scanning line SLB. Thus, the transition of the second scanning signal ScanB from an invalid level to an effective level can compensate for the impact on the pixel voltage of the sub-pixel Spx electrically connected to the first scanning line SLA when the first scanning signal ScanA transitions from an effective level to an invalid level. Consequently, when the second scanning signal ScanB transitions from an effective level to an invalid level, the impact of the fluctuation of the second scanning signal ScanB on the pixel voltage of the sub-pixel Spx electrically connected to the first scanning line SLA through parasitic capacitive coupling is reduced, thus improving the display panel's "head-shaking" display problem.

[0034] To facilitate understanding of this application, in conjunction with Figures 4A-4D , Figures 5A-5B and Figure 2 Let's take an N-type transistor as an example for comparison. Among them, Figures 4A-4B This is a schematic diagram of the structure of a 4-row pixel row as a comparative example of this application; Figures 4C-4D This is a schematic diagram of the structure of a 4-row pixel row according to an embodiment of this application; Figure 5A for Figures 4A-4B The timing diagram of the scan signal corresponding to the pixel row shown; Figure 5B for Figures 4C-4D The timing diagram of the scan signal corresponding to the pixel row shown. Figures 5A-5B In this context, Vspx represents the voltage corresponding to the pixel electrode of the sub-pixel.

[0035] correspond Figures 4A-4BIn the display panel shown, multiple sub-pixels Spx of the first pixel row Spr (1) are electrically connected to the first gate line GL1 and the second gate line GL2; multiple sub-pixels Spx of the second pixel row Spr (2) are electrically connected to the third gate line GL3 and the fourth gate line GL4; multiple sub-pixels Spx of the third pixel row Spr (3) are electrically connected to the fifth gate line GL5 and the sixth gate line GL6; multiple sub-pixels Spx of the fourth pixel row Spr (4) are electrically connected to the seventh gate line GL7 and the eighth gate line GL8, and so on, resulting in the electrical connection configuration of multiple gate lines and multiple sub-pixels Spx of multiple pixel rows Spr. The gate control signals transmitted by the multiple gate lines have effective pulses with sequentially delayed phases. For example, the end time of the effective pulse of the first gate control signal Gs1 transmitted by the first gate line GL1 is delayed by the start time of the effective pulse of the second gate control signal Gs2 transmitted by the second gate line GL2, and the end time of the effective pulse of the second gate control signal Gs2 transmitted by the second gate line GL2 is delayed by the start time of the effective pulse of the third gate control signal Gs3 transmitted by the third gate line GL3, and so on, to obtain the timing of the fourth gate control signal Gs4 transmitted by the fourth gate line GL4, the fifth gate control signal Gs5 transmitted by the fifth gate line GL5, the sixth gate control signal Gs6 transmitted by the sixth gate line GL6, the seventh gate control signal Gs7 transmitted by the seventh gate line GL7, and the eighth gate control signal Gs8 transmitted by the eighth gate line GL8 as follows: Figure 5A As shown.

[0036] like Figure 2 and Figure 5A As shown, when the first gate control signal Gs1 transmitted through the first gate line GL1 is high, the first transistor T1 of the sub-pixel Spx electrically connected to the first gate line GL1 is turned on, allowing the data signal transmitted through the data line DL to be transmitted to the corresponding pixel electrode PE. This causes the voltage of the pixel electrode PE of the sub-pixel Spx electrically connected to the first gate line GL1 to be equal to the data voltage of the received data signal. Subsequently, the first gate control signal Gs1 transitions from high to low, causing the voltage of the pixel electrode PE of the sub-pixel Spx electrically connected to the first gate line GL1 to change due to the influence of the first parasitic capacitance Cgs1 between the pixel electrode PE and the first gate line GL1. This results in a first feedthrough effect in the sub-pixel Spx electrically connected to the first gate line GL1, causing the voltage corresponding to the pixel electrode PE of the sub-pixel Spx electrically connected to the first gate line GL1 to be lower than the data voltage.

[0037] Afterwards, the second gate control signal Gs2 jumps from high level to low level, so that the voltage of the pixel electrode PE of the sub-pixel Spx electrically connected with the first gate line GL1 changes under the influence of the second parasitic capacitance Cgs2 between the pixel electrode PE and the second gate line GL2, the sub-pixel Spx electrically connected with the first gate line GL1 generates a second feed-through effect, so that the voltage corresponding to the pixel electrode PE of the sub-pixel Spx electrically connected with the first gate line GL1 is lowered again. And when the second gate control signal Gs2 jumps from high level to low level, the voltage of the pixel electrode PE of the sub-pixel Spx electrically connected with the second gate line GL2 changes under the influence of the first parasitic capacitance Cgs1 between the pixel electrode PE and the second gate line GL2, the sub-pixel Spx electrically connected with the second gate line GL2 generates a first feed-through effect, so that the voltage corresponding to the pixel electrode PE of the sub-pixel Spx electrically connected with the second gate line GL2 is lower than the data voltage.

[0038] Therefore, under the influence of the jump of the first gate line GL1 and the second gate line GL2 from high level to low level, the sub-pixel Spx electrically connected with the first gate line GL1 generates twice feed-through effect, and the sub-pixel Spx electrically connected with the second gate line GL2 generates once feed-through effect. Similarly, for other pixel rows Spr, the sub-pixel Spx electrically connected with the odd gate line generates twice feed-through effect, and the sub-pixel Spx electrically connected with the even gate line generates once feed-through effect, thereby causing the charging rate difference between the plurality of sub-pixels Spx of the display panel, causing the shaking line display problem.

[0039] In the present application, the plurality of sub-pixels Spx of the first pixel row Spr(1) are electrically connected to the first scan line SL1 and the second scan line SL2, the plurality of sub-pixels Spx of the second pixel row Spr(2) are electrically connected to the third scan line SL3 and the fourth scan line SL4, the plurality of sub-pixels Spx of the third pixel row Spr(3) are electrically connected to the fifth scan line SL5 and the sixth scan line SL6, the plurality of sub-pixels Spx of the fourth pixel row Spr(4) are electrically connected to the seventh scan line SL7 and the eighth scan line SL8, and so on, to obtain the electrical connection of the plurality of scan lines and the plurality of sub-pixels Spx of the plurality of pixel rows Spr. The first scan line SL1, the third scan line SL3, the fifth scan line SL5 and the seventh scan line SL7 correspond to the first scan line SLA, the second scan line SL2, the fourth scan line SL4, the sixth scan line SL6 and the eighth scan line SL8, respectively. In each scan unit SU, the end time of the effective pulse of the first scan signal ScanA transmitted by the first scan line SLA is earlier than the start time of the effective pulse of the second scan signal ScanB transmitted by the second scan line SLB, and the scan signals Scan1-Scan8 transmitted by the first scan line SL1 to the eighth scan line SL8 are obtained, as shown in FIG. 8. The first scan signal ScanA corresponding to the first pixel row Spr(1) is the first-level scan signal Scan1, and the second scan signal ScanB corresponding to the first pixel row Spr(1) is the fifth-level scan signal Scan5. The first scan signal ScanA and the second scan signal ScanB corresponding to the plurality of pixel rows Spr are obtained in the same manner. Figure 5B

[0040] Thus, in the present application, when the first scan signal ScanA transmitted by the first scan line SLA has a high level, the first transistor T1 of the sub-pixel Spx electrically connected to the first scan line SLA is turned on, so that the data signal transmitted by the data line DL can be transmitted to the corresponding pixel electrode PE, thereby making the voltage of the pixel electrode PE of the sub-pixel Spx electrically connected to the first scan line SLA correspond to the data voltage of the received data signal.

[0041] Then, the first scan signal ScanA jumps from high level to low level, so that the voltage of the pixel electrode PE of the sub-pixel Spx electrically connected to the first scan line SLA is changed due to the influence of the first parasitic capacitance Cgs1 between the pixel electrode PE and the first scan line SLA, the first feedthrough effect occurs in the sub-pixel Spx electrically connected to the first scan line SLA, thereby making the voltage corresponding to the pixel electrode PE of the sub-pixel Spx electrically connected to the first scan line SLA lower than the data voltage. ​

[0042] After that, the second scan signal ScanB jumps from low level to high level, so that the voltage of the pixel electrode PE of the sub-pixel Spx electrically connected with the first scan line SLA changes under the influence of the second parasitic capacitance Cgs2 between the pixel electrode PE and the second scan line SLB, and the voltage corresponding to the pixel electrode PE of the sub-pixel Spx electrically connected with the first scan line SLA will rise under the influence of the second scan signal ScanB jumping from low level to high level. The second scan signal ScanB jumps from low level to high level, so that the first transistor T1 of the sub-pixel Spx electrically connected with the second scan line SLB is turned on to transmit the data signal transmitted by the corresponding data line DL to the corresponding pixel electrode PE, so that the voltage of the pixel electrode PE of the sub-pixel Spx electrically connected with the second scan line SLB corresponds to equal to the data voltage possessed by the received data signal.

[0043] After that, the second scan signal ScanB jumps from high level to low level, so that the voltage of the pixel electrode PE of the sub-pixel Spx electrically connected with the first scan line SLA changes under the influence of the second parasitic capacitance Cgs2 between the pixel electrode PE and the second scan line SLB, and the voltage corresponding to the pixel electrode PE of the sub-pixel Spx electrically connected with the first scan line SLA will decrease under the influence of the second scan signal ScanB jumping from high level to low level. And, when the second scan signal ScanB jumps from high level to low level, the voltage of the pixel electrode PE of the sub-pixel Spx electrically connected with the second scan line SLB changes under the influence of the first parasitic capacitance Cgs1 between the pixel electrode PE and the second scan line SLB, the first feedthrough effect occurs in the sub-pixel Spx electrically connected with the second scan line SLB, so that the voltage corresponding to the pixel electrode PE of the sub-pixel Spx electrically connected with the second scan line SLB will be lower than the data voltage.

[0044] Therefore, after the first scan signal ScanA jumps from the high level to the low level, the second scan signal ScanB is controlled to jump from the low level to the high level. The jump of the second scan signal ScanB from the low level to the high level can raise the voltage corresponding to the pixel electrode PE of the sub-pixel Spx electrically connected to the first scan line SLA, thereby compensating for the voltage drop of the pixel electrode PE of the sub-pixel Spx electrically connected to the first scan line SLA caused by the jump of the first scan signal ScanA from the high level to the low level. Then, when the second scan signal ScanB jumps from the effective level to the ineffective level, the voltage corresponding to the pixel electrode PE of the sub-pixel Spx electrically connected to the first scan line SLA can drop from a higher voltage starting point. As a result, the voltage corresponding to the pixel electrode PE of the sub-pixel Spx electrically connected to the first scan line SLA has a smaller voltage variation range caused by the jumps of the first scan signal ScanA and the second scan signal ScanB from the high level to the low level. The influence of the variation of the second scan signal ScanB on the voltage of the pixel electrode of the sub-pixel Spx electrically connected to the first scan line SLA caused by parasitic capacitance coupling is reduced. The influence of the secondary feed-through effect corresponding to the sub-pixel Spx electrically connected to the first scan line SLA is improved. The charging rate difference between the plurality of sub-pixels Spx of the display panel is improved, and the shaking stripe display problem is improved.

[0045] Figure 6 FIG. 1 is a schematic diagram of the connection of the gate drive circuit and the clock line according to an embodiment of the present application. Figure 7 FIG. 2 is a clock timing diagram of a plurality of clock signals according to an embodiment of the present application. The display panel can further include Z clock lines CL and a gate drive circuit GDC.

[0046] The Z clock lines CL are configured to transmit Z clock signals having a phase difference in sequence. Wherein, Z > 1.

[0047] The gate drive circuit GDC is electrically connected between the Z clock lines CL and the plurality of scan units SU. The gate drive circuit GDC includes a plurality of cascaded shift registers GA. The plurality of shift registers GA are configured to generate effective pulses of a plurality of scan signals according to the Z clock signals, and output the plurality of scan signals from the output end Gout of the shift register to the plurality of first scan lines SLA and the plurality of second scan lines SLB.

[0048] Optionally, the ZK+Tth shift register GA(ZK+T) is electrically connected to the Tth clock line CL. The ZK+Tth shift register GA(ZK+T) is configured to generate effective pulses of a corresponding scan signal according to the clock signal transmitted by the Tth clock line CL. Wherein, K ≥ 0, 1 ≤ T ≤ Z.

[0049] As Figures 6-7For example, when Z=8, the Z clock lines include a first clock line CL1 to an eighth clock line CL8, the first clock line CL1 transmits a first clock signal CK1, the second clock line CL2 transmits a second clock signal CK2, the third clock line CL3 transmits a third clock signal CK3, the fourth clock line CL4 transmits a fourth clock signal CK4, the fifth clock line CL5 transmits a fifth clock signal CK5, the sixth clock line CL6 transmits a sixth clock signal CK6, the seventh clock line CL7 transmits a seventh clock signal CK7, and the eighth clock line CL8 transmits an eighth clock signal CK8. The first clock signal CK1 to the eighth clock signal CK8 have phase differences in sequence. The 8K+1 stage shift register GA(8K+1) is electrically connected to the first clock line CL1, the 8K+2 stage shift register GA(8K+2) is electrically connected to the second clock line CL2, the 8K+3 stage shift register GA(8K+3) is electrically connected to the third clock line CL3, the 8K+4 stage shift register GA(8K+4) is electrically connected to the fourth clock line CL4, the 8K+5 stage shift register GA(8K+5) is electrically connected to the fifth clock line CL5, the 8K+6 stage shift register GA(8K+6) is electrically connected to the sixth clock line CL6, the 8K+7 stage shift register GA(8K+7) is electrically connected to the seventh clock line CL7, and the 8K+8 stage shift register GA(8K+8) is electrically connected to the eighth clock line CL8.

[0050] It should be noted that the plurality of scanning signals output by the plurality of shift registers GA can have corresponding effective pulses in sequence. The shift register GA can include a combination of a transistor and a capacitor. The specific implementation of the gate drive circuit GDC can be obtained by referring to the design in the related art, and will not be described here.

[0051] Optionally, in the same scanning unit SU, the shift register GA electrically connected to the first scanning line SLA corresponds to receiving an xth clock signal, and the shift register GA electrically connected to the second scanning line SLB corresponds to receiving a yth clock signal; 1≤x≤Z / 2, y=x+Z / 2, and y≤Z. In this way, without changing the cascade design of the gate drive circuit GDC, the end time of the effective pulse of the first scanning signal ScanA corresponding to the same scanning unit SU can be made to be ahead of the start time of the effective pulse of the second scanning signal ScanB, which is beneficial to reduce the preparation difficulty of the display panel.

[0052] As Figures 6-7For example, when Z=8, the 8 clock lines CL include a first clock line CL1 to an eighth clock line CL8, the first clock line CL1 to the eighth clock line CL8 transmit clock signals with sequentially lagging phases, and the clock signals transmitted by the first clock line CL1 to the eighth clock line CL8 have a plurality of effective pulses. When x=1, y=5; that is, in the same scan unit SU, when the shift register GA electrically connected to the first scan line SLA corresponds to receive the first clock signal CK1 transmitted by the first clock line CL1, the shift register GA electrically connected to the second scan line SLB corresponds to receive the fifth clock signal CK5 transmitted by the fifth clock line CL5. When x=2, y=6; that is, in the same scan unit SU, when the shift register GA electrically connected to the first scan line SLA corresponds to receive the second clock signal CK2 transmitted by the second clock line CL2, the shift register GA electrically connected to the second scan line SLB corresponds to receive the sixth clock signal CK6 transmitted by the sixth clock line CL6. When x=3, y=7; that is, in the same scan unit SU, when the shift register GA electrically connected to the first scan line SLA corresponds to receive the third clock signal CK3 transmitted by the third clock line CL3, the shift register GA electrically connected to the second scan line SLB corresponds to receive the seventh clock signal CK7 transmitted by the seventh clock line CL7. When x=4, y=8; that is, in the same scan unit SU, when the shift register GA electrically connected to the first scan line SLA corresponds to receive the fourth clock signal CK4 transmitted by the fourth clock line CL4, the shift register GA electrically connected to the second scan line SLB corresponds to receive the eighth clock signal CK8 transmitted by the eighth clock line CL8.

[0053] For example, when Z=16, the 16 clock lines CL include a first clock line CL1 to a sixteenth clock line CL, the first clock line CL1 to the sixteenth clock line CL transmit clock signals with phase lag in turn, and the clock signals transmitted by the first clock line CL1 to the sixteenth clock line CL have a plurality of effective pulses. When x=1, y=9; that is, in the same scan unit SU, when the shift register GA electrically connected to the first scan line SLA corresponds to receive the first clock signal transmitted by the first clock line CL1, the shift register GA electrically connected to the second scan line SLB corresponds to receive the ninth clock signal transmitted by the ninth clock line CL. When x=2, y=10; that is, in the same scan unit SU, when the shift register GA electrically connected to the first scan line SLA corresponds to receive the second clock signal transmitted by the second clock line CL2, the shift register GA electrically connected to the second scan line SLB corresponds to receive the tenth clock signal transmitted by the tenth clock line CL. When x=3, y=11; that is, in the same scan unit SU, when the shift register GA electrically connected to the first scan line SLA corresponds to receive the third clock signal transmitted by the third clock line CL3, the shift register GA electrically connected to the second scan line SLB corresponds to receive the eleventh clock signal transmitted by the eleventh clock line CL. When x=4, y=12; that is, in the same scan unit SU, when the shift register GA electrically connected to the first scan line SLA corresponds to receive the fourth clock signal transmitted by the fourth clock line CL4, the shift register GA electrically connected to the second scan line SLB corresponds to receive the twelfth clock signal transmitted by the twelfth clock line CL. When x=5, y=13; that is, in the same scan unit SU, when the shift register GA electrically connected to the first scan line SLA corresponds to receive the fifth clock signal transmitted by the fifth clock line CL5, the shift register GA electrically connected to the second scan line SLB corresponds to receive the thirteenth clock signal transmitted by the thirteenth clock line CL. When x=6, y=14; that is, in the same scan unit SU, when the shift register GA electrically connected to the first scan line SLA corresponds to receive the sixth clock signal transmitted by the sixth clock line CL6, the shift register GA electrically connected to the second scan line SLB corresponds to receive the fourteenth clock signal transmitted by the fourteenth clock line CL. When x=7, y=15; that is, in the same scan unit SU, when the shift register GA electrically connected to the first scan line SLA corresponds to receive the seventh clock signal transmitted by the seventh clock line CL7, the shift register GA electrically connected to the second scan line SLB corresponds to receive the fifteenth clock signal transmitted by the fifteenth clock line CL. When x=8, y=16; that is, in the same scan unit SU, when the shift register GA electrically connected to the first scan line SLA corresponds to receive the eighth clock signal transmitted by the eighth clock line CL8, the shift register GA electrically connected to the second scan line SLB corresponds to receive the sixteenth clock signal transmitted by the sixteenth clock line CL.

[0054] Please continue to refer to Figures 1A-1B The plurality of sub-pixels Spx located at the MK+Nth pixel row Spr(MK+N) are electrically connected with the ZK+Nth shift register GA(ZK+N) through a corresponding first scan line SLA, and the plurality of sub-pixels Spx located at the MK+Nth pixel row Spr(MK+N) are electrically connected with the ZK+N+Z / 2th shift register GA(ZK+N+Z / 2) through a corresponding second scan line SLB. Wherein, MK+N≥1, ZK+N≥1, ZK+N+Z / 2>1; M=Z / 2; K≥0, and K is a positive integer; 1≤N≤Z / 2, so that the first scan signal ScanA and the second scan signal ScanB corresponding to the plurality of pixel rows Spr all meet the requirement of improving the secondary feedthrough.

[0055] For example, with Z=8, the plurality of sub-pixels Spx of the 4K+1th pixel row Spr(4K+1) are electrically connected with the 8K+1th shift register GA(8K+1) through a corresponding first scan line SLA, and are electrically connected with the 8K+5th shift register GA(8K+5) through a corresponding second scan line SLB. The plurality of sub-pixels Spx of the 4K+2th pixel row Spr(4K+2) are electrically connected with the 8K+2th shift register GA(8K+2) through a corresponding first scan line SLA, and are electrically connected with the 8K+6th shift register GA(8K+6) through a corresponding second scan line SLB. The plurality of sub-pixels Spx of the 4K+3th pixel row Spr(4K+3) are electrically connected with the 8K+3th shift register GA(8K+3) through a corresponding first scan line SLA, and are electrically connected with the 8K+7th shift register GA(8K+7) through a corresponding second scan line SLB. The plurality of sub-pixels Spx of the 4K+4th pixel row Spr(4K+4) are electrically connected with the 8K+4th shift register GA(8K+4) through a corresponding first scan line SLA, and are electrically connected with the 8K+8th shift register GA(8K+8) through a corresponding second scan line SLB.

[0056] When K=0, the plurality of sub-pixels Spx of the first pixel row Spr(1) are electrically connected to the first stage shift register GA(1) through the corresponding first scan line SLA and electrically connected to the fifth stage shift register GA(5) through the corresponding second scan line SLB, the first scan signal ScanA corresponding to the plurality of sub-pixels Spx of the first pixel row Spr(1) is the first stage scan signal Scan(1) output by the first stage shift register GA(1), and the second scan signal ScanB corresponding to the plurality of sub-pixels Spx of the first pixel row Spr(1) is the fifth stage scan signal Scan(5) output by the fifth stage shift register GA(5). The plurality of sub-pixels Spx of the second pixel row Spr(2) are electrically connected to the second stage shift register GA(2) through the corresponding first scan line SLA and electrically connected to the sixth stage shift register GA(6) through the corresponding second scan line SLB, the first scan signal ScanA corresponding to the plurality of sub-pixels Spx of the second pixel row Spr(2) is the second stage scan signal Scan(2) output by the second stage shift register GA(2), and the second scan signal ScanB corresponding to the plurality of sub-pixels Spx of the second pixel row Spr(2) is the sixth stage scan signal Scan(6) output by the sixth stage shift register GA(6). The plurality of sub-pixels Spx of the third pixel row Spr(3) are electrically connected to the third stage shift register GA(3) through the corresponding first scan line SLA and electrically connected to the seventh stage shift register GA(7) through the corresponding second scan line SLB, the first scan signal ScanA corresponding to the plurality of sub-pixels Spx of the third pixel row Spr(3) is the third stage scan signal Scan(3) output by the third stage shift register GA(3), and the second scan signal ScanB corresponding to the plurality of sub-pixels Spx of the third pixel row Spr(3) is the seventh stage scan signal Scan(7) output by the seventh stage shift register GA(7). The plurality of sub-pixels Spx of the fourth pixel row Spr(4) are electrically connected to the fourth stage shift register GA(4) through the corresponding first scan line SLA and electrically connected to the eighth stage shift register GA(8) through the corresponding second scan line SLB, the first scan signal ScanA corresponding to the plurality of sub-pixels Spx of the fourth pixel row Spr(4) is the fourth stage scan signal Scan4 output by the fourth stage shift register GA(4), and the second scan signal ScanB corresponding to the plurality of sub-pixels Spx of the fourth pixel row Spr(4) is the eighth stage scan signal (8) output by the eighth stage shift register GA(8), that is, the design of Figures 4C-4D and Figure 5B is obtained. By analogy, the first scan signal ScanA and the second scan signal ScanB corresponding to the plurality of sub-pixel rows Spr are obtained.

[0057] Similarly, the first scan signal ScanA and the second scan signal ScanB corresponding to the plurality of sub-pixels Spx in the fifth pixel row Spr(5) and the plurality of pixel rows Spr after the fifth pixel row Spr(5) can also be obtained when K = 1, 2, 3, or other positive integers.

[0058] For example, when Z = 16, the sub-pixels Spx of the 8K+1th pixel row Spr(8K+1) are electrically connected to the 16K+1th shift register GA(16K+1) through the corresponding first scan line SLA and to the 16K+9th shift register GA(16K+9) through the corresponding second scan line SLB. The sub-pixels Spx of the 8K+2th pixel row Spr(8K+2) are electrically connected to the 16K+2th shift register GA(16K+2) through the corresponding first scan line SLA and to the 16K+10th shift register GA(16K+10) through the corresponding second scan line SLB. The sub-pixels Spx of the 8K+3th pixel row Spr(8K+3) are electrically connected to the 16K+3th shift register GA(16K+3) through the corresponding first scan line SLA and to the 16K+11th shift register GA(16K+11) through the corresponding second scan line SLB. The sub-pixels Spx of the 8K+4th pixel row Spr(8K+4) are electrically connected to the 16K+4th shift register GA(16K+4) through the corresponding first scan line SLA and to the 16K+12th shift register GA(16K+12) through the corresponding second scan line SLB. The sub-pixels Spx of the 8K+5th pixel row Spr(8K+5) are electrically connected to the 16K+5th shift register GA(16K+5) through the corresponding first scan line SLA and to the 16K+13th shift register GA(16K+13) through the corresponding second scan line SLB. The sub-pixels Spx of the 8K+6th pixel row Spr(8K+6) are electrically connected to the 16K+6th shift register GA(16K+6) through the corresponding first scan line SLA and to the 16K+14th shift register GA(16K+14) through the corresponding second scan line SLB. The sub-pixels Spx of the 8K+7th pixel row Spr(8K+7) are electrically connected to the 16K+7th shift register GA(16K+7) through the corresponding first scan line SLA and to the 16K+15th shift register GA(16K+15) through the corresponding second scan line SLB. The sub-pixels Spx of the 8K+8th pixel row Spr(8K+8) are electrically connected to the 16K+8th shift register GA(16K+8) through the corresponding first scan line SLA and to the 16K+16th shift register GA(16K+16) through the corresponding second scan line SLB.

[0059] When K=0, the plurality of sub-pixels Spx of the first pixel row Spr(1) are electrically connected to the first shift register GA(1) through the corresponding first scan line SLA and electrically connected to the ninth shift register GA(9) through the corresponding second scan line SLB, the first scan signal ScanA corresponding to the plurality of sub-pixels Spx of the first pixel row Spr(1) is the first level scan signal Scan(1) output by the first shift register GA(1), and the second scan signal ScanB corresponding to the plurality of sub-pixels Spx of the first pixel row Spr(1) is the ninth level scan signal Scan(9) output by the ninth shift register GA(9). The plurality of sub-pixels Spx of the second pixel row Spr(2) are electrically connected to the second shift register GA(2) through the corresponding first scan line SLA and electrically connected to the tenth shift register GA(10) through the corresponding second scan line SLB, the first scan signal ScanA corresponding to the plurality of sub-pixels Spx of the second pixel row Spr(2) is the second level scan signal Scan(2) output by the second shift register GA(2), and the second scan signal ScanB corresponding to the plurality of sub-pixels Spx of the second pixel row Spr(2) is the tenth level scan signal Scan(10) output by the tenth shift register GA(10). The plurality of sub-pixels Spx of the third pixel row Spr(3) are electrically connected to the third shift register GA(3) through the corresponding first scan line SLA and electrically connected to the eleventh shift register GA(11) through the corresponding second scan line SLB, the first scan signal ScanA corresponding to the plurality of sub-pixels Spx of the third pixel row Spr(3) is the third level scan signal Scan(3) output by the third shift register GA(3), and the second scan signal ScanB corresponding to the plurality of sub-pixels Spx of the third pixel row Spr(3) is the eleventh level scan signal Scan(11) output by the eleventh shift register GA(11). The plurality of sub-pixels Spx of the fourth pixel row Spr(4) are electrically connected to the fourth shift register GA(4) through the corresponding first scan line SLA and electrically connected to the twelfth shift register GA(12) through the corresponding second scan line SLB, the first scan signal ScanA corresponding to the plurality of sub-pixels Spx of the fourth pixel row Spr(4) is the fourth level scan signal Scan(4) output by the fourth shift register GA(4), and the second scan signal ScanB corresponding to the plurality of sub-pixels Spx of the fourth pixel row Spr(4) is the twelfth level scan signal Scan(12) output by the twelfth shift register GA(12).The plurality of sub-pixels Spx of the 5th pixel row Spr(5) are electrically connected with the 5th shift register GA(5) through the corresponding first scan line SLA and are electrically connected with the 13th shift register GA(13) through the corresponding second scan line SLB. The corresponding first scan signal ScanA of the plurality of sub-pixels Spx of the 5th pixel row Spr(5) is the 5th level scan signal Scan(5) output by the 5th shift register GA(5). The corresponding second scan signal ScanB of the plurality of sub-pixels Spx of the 5th pixel row Spr(5) is the 13th level scan signal Scan(13) output by the 13th shift register GA(13). The plurality of sub-pixels Spx of the 6th pixel row Spr(6) are electrically connected with the 6th shift register GA(6) through the corresponding first scan line SLA and are electrically connected with the 14th shift register GA(14) through the corresponding second scan line SLB. The corresponding first scan signal ScanA of the plurality of sub-pixels Spx of the 6th pixel row Spr(6) is the 6th level scan signal Scan(6) output by the 6th shift register GA(6). The corresponding second scan signal ScanB of the plurality of sub-pixels Spx of the 6th pixel row Spr(6) is the 14th level scan signal Scan(14) output by the 14th shift register GA(14). The plurality of sub-pixels Spx of the 7th pixel row Spr(7) are electrically connected with the 7th shift register GA(7) through the corresponding first scan line SLA and are electrically connected with the 15th shift register GA(15) through the corresponding second scan line SLB. The corresponding first scan signal ScanA of the plurality of sub-pixels Spx of the 7th pixel row Spr(7) is the 7th level scan signal Scan(7) output by the 7th shift register GA(7). The corresponding second scan signal ScanB of the plurality of sub-pixels Spx of the 7th pixel row Spr(7) is the 15th level scan signal Scan(15) output by the 15th shift register GA(15). The plurality of sub-pixels Spx of the 8th pixel row Spr(8) are electrically connected with the 8th shift register GA(8) through the corresponding first scan line SLA and are electrically connected with the 16th shift register GA(16) through the corresponding second scan line SLB. The corresponding first scan signal ScanA of the plurality of sub-pixels Spx of the 8th pixel row Spr(8) is the 8th level scan signal Scan(8) output by the 8th shift register GA(8). The corresponding second scan signal ScanB of the plurality of sub-pixels Spx of the 8th pixel row Spr(8) is the 16th level scan signal Scan(16) output by the 16th shift register GA(16).

[0060] Similarly, the first scanning signal ScanA and the second scanning signal ScanB corresponding to the plurality of sub-pixels Spx in the 9th pixel row Spr(9) and the pixel rows Spr after the 9th pixel row Spr(9) can also be obtained when K = 1, 2, 3 or other positive integers.

[0061] In order to reduce the number of driving chips for generating data signals for the display panel on the basis of improving the shaking line display problem, the plurality of sub-pixels Spx can share the data signals transmitted by the same data line DL.

[0062] Please continue to refer to Figure 1A and Figure 4C Two pixel columns Spc are arranged between the adjacent two data lines DL. The plurality of sub-pixels Spx arranged in each pixel row Spr are alternately electrically connected to the first scanning line SLA and the second scanning line SLB of the corresponding scanning unit SU. The two sub-pixels Spx of the same pixel row Spr in the two pixel columns Spc between the adjacent two data lines DL are electrically connected to the same data line DL, and the plurality of sub-pixels Spx in the same pixel column Spc are alternately electrically connected to the adjacent two data lines DL.

[0063] For example, the first data line DL1 to the fourth data line DL4, the plurality of sub-pixels Spx in the first pixel column Spc(1) and the second pixel column Spc(2) are located between the first data line DL1 and the second data line DL2, the plurality of sub-pixels Spx in the third pixel column Spc(3) and the fourth pixel column Spc(4) are located between the second data line DL2 and the third data line DL3, the plurality of sub-pixels Spx in the fifth pixel column Spc(5) and the sixth pixel column Spc(6) are located between the third data line DL3 and the fourth data line DL4, and the position distribution between the plurality of data lines DL and the plurality of sub-pixels Spx in the plurality of pixel columns Spc is obtained in turn.

[0064] The first sub-pixel and the second sub-pixel in the odd pixel row are electrically connected to one of the first data line DL1 and the second data line DL2, and the first sub-pixel and the second sub-pixel in the even pixel row are electrically connected to the other of the first data line DL1 and the second data line DL2. The third sub-pixel and the fourth sub-pixel in the odd pixel row are electrically connected to one of the second data line DL2 and the third data line DL3, and the third sub-pixel and the fourth sub-pixel in the even pixel row are electrically connected to the other of the second data line DL2 and the third data line DL3, and the matching relationship between the plurality of data lines DL and the plurality of sub-pixels Spx in the plurality of pixel rows Spr is obtained in turn.

[0065] In some embodiments, the first and second sub-pixels in the first pixel row Spr(1) and the third pixel row Spr(3) are electrically connected to the first data line DL1, the third and fourth sub-pixels in the first pixel row Spr(1) and the third pixel row Spr(3) and the first and second sub-pixels in the second pixel row Spr(2) are electrically connected to the second data line DL2, the fifth and sixth sub-pixels in the first pixel row Spr(1) and the third pixel row Spr(3) and the third and fourth sub-pixels in the second pixel row Spr(2) are electrically connected to the third data line DL3, and the fifth and sixth sub-pixels in the third pixel row Spr(3) are electrically connected to the fourth data line DL4, as shown in FIGS. 1A and 1B. Figure 1A and Figure 4C The matching relationship between the plurality of data lines DL and the plurality of sub-pixels Spx of the plurality of pixel rows Spr can be obtained in sequence by analogy.

[0066] Optionally, in the same pixel row Spr, the sub-pixel Spx at an odd position is electrically connected to one of the first and second scan lines SLA and SLB of the corresponding scanning unit SU, and the sub-pixel Spx at an even position is electrically connected to the other of the first and second scan lines SLA and SLB of the corresponding scanning unit SU.

[0067] As shown in some embodiments, the plurality of sub-pixels Spx of the first pixel row Spr(1) correspond to the first scanning unit SU of the plurality of scanning units SU, the first, third, and fifth sub-pixels of the first pixel row Spr(1) are electrically connected to the first scan line SLA of the first scanning unit SU, and the second, fourth, and sixth sub-pixels of the first pixel row Spr(1) are electrically connected to the second scan line SLB of the first scanning unit SU.

[0068] For example, as shown in some embodiments, the first, third, and sixth sub-pixels of the first pixel row Spr(1) are electrically connected to the first scan line SLA of the first scanning unit SU, and the second, fourth, and fifth sub-pixels of the first pixel row Spr(1) are electrically connected to the second scan line SLB of the first scanning unit SU. Figure 1A and Figure 4C

[0069] ​Optionally, in the odd pixel row, the sub-pixel Spx at the odd position is electrically connected with the first scan line SLA of the corresponding scan unit SU, and the sub-pixel Spx at the even position is electrically connected with the second scan line SLB of the corresponding scan unit SU. In the even pixel row, the sub-pixel Spx at the odd position is electrically connected with the second scan line SLB of the corresponding scan unit SU, and the sub-pixel Spx at the even position is electrically connected with the first scan line SLA of the corresponding scan unit SU, so that the wiring design in the display panel tends to be symmetrical, thereby making the display effect of the display panel tend to be uniform.

[0070] To further improve the display quality of the display panel, in the same frame, the polarities of the pixel voltages received by the plurality of sub-pixels Spx in the ith pixel row Spr(i) are opposite to the polarities of the pixel voltages received by the plurality of sub-pixels Spx in the (i+1)th pixel row Spr(i+1), the polarities of the pixel voltages received by the plurality of sub-pixels Spx in the rth pixel column Spc(r) are the same as the polarities of the pixel voltages received by the plurality of sub-pixels Spx in the (r+1)th pixel column Spc(r+1), and the polarities of the pixel voltages received by the plurality of sub-pixels Spx in the rth pixel column Spc(r) are opposite to the polarities of the pixel voltages received by the plurality of sub-pixels Spx in the (r+2)th pixel column Spc(r+2). Wherein, the polarities of the pixel voltages received by the same sub-pixel Spx in two adjacent frames are opposite; i≥1, r≥1 and r is an odd number. In this way, the display problem of the display panel caused by the long-term reception of the pixel voltage with the same polarity by the sub-pixel Spx can be improved, and the display quality of the display panel can be improved.

[0071] Please continue to refer to Figure 1A and Figure 4CCorresponding to the Wth frame of the display panel, the pixel voltage received by the first and second sub-pixels in the first pixel row Spr(1) is positive polarity voltage, the pixel voltage received by the third and fourth sub-pixels in the first pixel row Spr(1) is negative polarity voltage, and so on, to obtain the polarity of the pixel voltage received by the plurality of sub-pixels Spx in the first pixel row Spr(1). The polarity of the pixel voltage received by the plurality of sub-pixels Spx in the second pixel row Spr(2) is opposite to that received by the first pixel row Spr(1). Therefore, the pixel voltage received by the first and second sub-pixels in the second pixel row Spr(2) is negative polarity voltage, the pixel voltage received by the third and fourth sub-pixels in the second pixel row Spr(2) is positive polarity voltage, and so on, to obtain the polarity of the pixel voltage received by the plurality of sub-pixels Spx in the second pixel row Spr(2). Corresponding to the (W+1)th frame of the display panel, the pixel voltage received by the first and second sub-pixels in the first pixel row Spr(1) is negative polarity voltage, the pixel voltage received by the third and fourth sub-pixels in the first pixel row Spr(1) is positive polarity voltage, and so on, to obtain the polarity of the pixel voltage received by the plurality of sub-pixels Spx in the first pixel row Spr(1). The pixel voltage received by the first and second sub-pixels in the second pixel row Spr(2) is positive polarity voltage, the pixel voltage received by the third and fourth sub-pixels in the second pixel row Spr(2) is negative polarity voltage, and so on, to obtain the polarity of the pixel voltage received by the plurality of sub-pixels Spx in the second pixel row Spr(2). Wherein, W≥1.

[0072] Please continue to see Figure 1B and Figure 4D Each data line DL is provided with a pixel column Spc on each side along the row direction x, and two pixel columns Spc are provided between adjacent two data lines DL. Wherein, the plurality of sub-pixels Spx arranged in each pixel row Spr are alternately electrically connected to the first and second scan lines SLA and SLB of the corresponding scan unit SU, and each data line DL is electrically connected to the plurality of sub-pixels Spx of the adjacent two pixel columns Spc, so that the plurality of sub-pixels Spx can share the data signal transmitted by the same data line DL, thereby reducing the number of driving chips for generating data signals used by the display panel, and saving the cost of the display panel.

[0073] As an example of the first data line DL1 to the fourth data line DL4, the first data line DL1 is located between the first pixel column SPC(1) and the second pixel column SPC(2), the second data line DL2 is located between the third pixel column SPC(3) and the fourth pixel column SPC(4), the third data line DL3 is located between the fifth pixel column SPC(5) and the sixth pixel column SPC(6), and the fourth data line DL4 is located between the seventh pixel column SPC(7) and the eighth pixel column SPC(8). Similarly, the position distribution relationship of the plurality of data lines DL and the plurality of sub-pixels Spx in the plurality of pixel columns SPC can be obtained.

[0074] Optionally, to further improve the display quality of the display panel, in the same frame, the polarities of the pixel voltages received by the plurality of sub-pixels Spx electrically connected to the same data line DL are the same, and the polarities of the pixel voltages transmitted by the adjacent two data lines DL are opposite. The polarities of the pixel voltages received by the same sub-pixel Spx in the adjacent two frames are opposite. In this way, the display quality of the display panel can be improved by avoiding the sub-pixel Spx from receiving the pixel voltage of the same polarity for a long time.

[0075] As an example of the first data line DL1 to the fourth data line DL4, the first data line DL1 is located between the first pixel column SPC(1) and the second pixel column SPC(2), the second data line DL2 is located between the third pixel column SPC(3) and the fourth pixel column SPC(4), the third data line DL3 is located between the fifth pixel column SPC(5) and the sixth pixel column SPC(6), and the fourth data line DL4 is located between the seventh pixel column SPC(7) and the eighth pixel column SPC(8). Similarly, the position distribution relationship of the plurality of data lines DL and the plurality of sub-pixels Spx in the plurality of pixel columns SPC can be obtained. Figure 1B Figure 4D For the Wth frame of the display panel, the pixel voltages received by the plurality of sub-pixels Spx in the pixel column SPC electrically connected to the data line located at the odd position are positive polarity voltages, and the pixel voltages received by the plurality of sub-pixels Spx in the pixel column SPC electrically connected to the data line located at the even position are negative polarity voltages. For the W+1th frame of the display panel, the pixel voltages received by the plurality of sub-pixels Spx in the pixel column SPC electrically connected to the data line located at the odd position are negative polarity voltages, and the pixel voltages received by the plurality of sub-pixels Spx in the pixel column SPC electrically connected to the data line located at the even position are positive polarity voltages. Wherein, W≥1.

[0076] Optionally, to realize multi-color display of the display panel, the light-emitting colors of the plurality of sub-pixels Spx located in the same pixel column SPC can be the same or different, and the light-emitting colors of the plurality of sub-pixels Spx in the adjacent two pixel columns SPC are different. As an example of the first data line DL1 to the fourth data line DL4, Figures 1A-1B Figures 4C-4D ​​In the 3F+1 pixel column Spc(3F+1), multiple sub-pixels Spx can all be the first sub-pixel Spx1; in the 3F+2 pixel column Spc(3F+2), multiple sub-pixels Spx can all be the second sub-pixel Spx2; and in the 3F+3 pixel column Spc(3F+3), multiple sub-pixels Spx can all be the third sub-pixel Spx3. The first sub-pixel Spx1 can emit light in one of three colors: red, green, or blue; the second sub-pixel Spx2 can emit light in one of three colors: red, green, or blue; and the third sub-pixel Spx3 can emit light in one of three colors: red, green, or blue. The first sub-pixel Spx1, the second sub-pixel Spx2, and the third sub-pixel Spx3 have different emitted light colors.

[0077] It should be understood that this application is only illustrative using the example of a display panel comprising sub-pixels Spx with three emitting colors, but this is not intended to limit the application. In some embodiments, the display panel may include sub-pixels Spx with one or more emitting colors, which will not be elaborated here.

[0078] It should be noted that, compared to Figure 1A The design shown in this application Figure 1B The design of the display panel shown also allows for the following: during the period when multiple sub-pixels Spx electrically connected to the corresponding first scan line SLA in the i-th pixel row Spr(i) receive the corresponding pixel voltage, multiple sub-pixels Spx electrically connected to the corresponding first scan line SLA in the (i+1)-th pixel row Spr(i+1) also receive the corresponding pixel voltage. Similarly, during the period when multiple sub-pixels Spx electrically connected to the corresponding second scan line SLB in the i-th pixel row Spr(i) receive the corresponding pixel voltage, multiple sub-pixels Spx electrically connected to the corresponding second scan line SLB in the (i+1)-th pixel row Spr(i+1) also receive the corresponding pixel voltage. This enables a frequency multiplication design for the display panel, increasing its display frequency.

[0079] like Figure 8 This is another structural schematic diagram of the display panel according to an embodiment of this application. In the display panel, the 4p+1th and 4p+2th sub-pixels located in the same pixel row Spr are electrically connected to one of the first scan line SLA and the second scan line SLB in the corresponding scanning unit SU. The 4p+3th and 4p+4th sub-pixels in the same pixel row Spr are electrically connected to the other of the first scan line SLA and the second scan line SLB in the corresponding scanning unit SU. Multiple data lines DL and multiple pixel columns Spc are arranged alternately along the row direction x. Multiple sub-pixels Spx of the same pixel column Spc are electrically connected to the same data line DL. Wherein, p≥0, and p is a positive integer.

[0080] As an example of p = 0, the first and second sub-pixels in the first pixel row Spr(1) are electrically connected to one of the first and second scan lines SLA and SLB in the corresponding scan unit SU, and the third and fourth sub-pixels are electrically connected to the other of the first and second scan lines SLA and SLB in the corresponding scan unit SU. Similarly, for p = 1, 2, 3, or other positive integers, the remaining sub-pixels Spx in the first pixel row Spr(1) can be electrically connected to the first and second scan lines SLA and SLB in the corresponding scan unit SU in the same manner.

[0081] Since the sub-pixels Spx in the same pixel row Spr are electrically connected to the first and second scan lines SLA and SLB in the same scan unit SU, and the end time of the active pulse of the first scan signal ScanA transmitted by the first scan line SLA is earlier than the start time of the active pulse of the second scan signal ScanB transmitted by the second scan line SLB. Thus, Figure 8 In the design of the display panel shown, the jump of the second scan signal ScanB from the inactive level to the active level can be used to compensate for the effect of the jump of the first scan signal ScanA from the active level to the inactive level on the pixel voltage of the sub-pixel Spx electrically connected to the first scan line SLA, and then reduce the effect of the change of the second scan signal ScanB on the pixel voltage of the sub-pixel Spx electrically connected to the first scan line SLA through parasitic capacitance coupling when the second scan signal ScanB jumps from the active level to the inactive level, thereby improving the wobble display problem of the display panel.

[0082] Optionally, to further reduce the driving chip for generating the data signal used in the display panel on the basis of improving the wobble display problem, the display panel can further include a plurality of pixel column units SpcU arranged along the row direction x, as shown. Figure 8

[0083] ​Each of the pixel column units SpcU includes q pixel columns Spc. In the same pixel column unit SpcU, the data line DL electrically connected to the plurality of sub-pixels Spx of the hth pixel column Spc(h) is electrically connected to the data line DL electrically connected to the plurality of sub-pixels Spx of the h+q / 2th pixel column Spc(h+q / 2), the light-emitting color of the plurality of sub-pixels Spx of the hth pixel column Spc(h) is the same as the light-emitting color of the plurality of sub-pixels Spx of the h+q / 2th pixel column Spc(h+q / 2), q is an even number, and 1≤h≤q / 2. In this way, the plurality of sub-pixels Spx of the hth pixel column Spc(h) and the plurality of sub-pixels Spx of the h+q / 2th pixel column Spc(h+q / 2) can share the data signal transmitted by the same data line DL, thereby reducing the number of data signals applied to the display panel, and thus reducing the power consumption and cost of the display panel.

[0084] As an example of q = 12, in the same pixel column unit SpcU, the data lines DL electrically connected to the plurality of sub-pixels Spx of the first pixel column Spc(1) are electrically connected to the data lines DL electrically connected to the plurality of sub-pixels Spx of the seventh pixel column Spc(7), and the light emitting colors of the plurality of sub-pixels Spx of the first pixel column Spc(1) are the same as the light emitting colors of the plurality of sub-pixels Spx of the seventh pixel column Spc(7); the data lines DL electrically connected to the plurality of sub-pixels Spx of the second pixel column Spc(2) are electrically connected to the data lines DL electrically connected to the plurality of sub-pixels Spx of the eighth pixel column Spc(8), and the light emitting colors of the plurality of sub-pixels Spx of the second pixel column Spc(2) are the same as the light emitting colors of the plurality of sub-pixels Spx of the eighth pixel column Spc(8); the data lines DL electrically connected to the plurality of sub-pixels Spx of the third pixel column Spc(3) are electrically connected to the data lines DL electrically connected to the plurality of sub-pixels Spx of the ninth pixel column Spc(9), and the light emitting colors of the plurality of sub-pixels Spx of the third pixel column Spc(3) are the same as the light emitting colors of the plurality of sub-pixels Spx of the ninth pixel column Spc(9); the data lines DL electrically connected to the plurality of sub-pixels Spx of the fourth pixel column Spc(4) are electrically connected to the data lines DL electrically connected to the plurality of sub-pixels Spx of the tenth pixel column Spc(10), and the light emitting colors of the plurality of sub-pixels Spx of the fourth pixel column Spc(4) are the same as the light emitting colors of the plurality of sub-pixels Spx of the tenth pixel column Spc(10); the data lines DL electrically connected to the plurality of sub-pixels Spx of the fifth pixel column Spc(5) are electrically connected to the data lines DL electrically connected to the plurality of sub-pixels Spx of the eleventh pixel column Spc(11), and the light emitting colors of the plurality of sub-pixels Spx of the fifth pixel column Spc(5) are the same as the light emitting colors of the plurality of sub-pixels Spx of the eleventh pixel column Spc(11); and the data lines DL electrically connected to the plurality of sub-pixels Spx of the sixth pixel column Spc(6) are electrically connected to the data lines DL electrically connected to the plurality of sub-pixels Spx of the twelfth pixel column Spc(12), and the light emitting colors of the plurality of sub-pixels Spx of the sixth pixel column Spc(6) are the same as the light emitting colors of the plurality of sub-pixels Spx of the twelfth pixel column Spc(12).

[0085] In some embodiments, in the same pixel column unit SpcU, the light emitting color of the plurality of sub-pixels Spx in the hth pixel column Spc(h) is different from the light emitting color of the plurality of sub-pixels Spx in the (h+1)th pixel column Spc(h+1), and is different from the light emitting color of the plurality of sub-pixels Spx in the (h+2)th pixel column Spc(h+2), and the light emitting color of the plurality of sub-pixels Spx in the (h+1)th pixel column Spc(h+1) is different from the light emitting color of the plurality of sub-pixels Spx in the (h+2)th pixel column Spc(h+2), so that the same pixel column unit SpcU includes sub-pixels Spx of multiple light emitting colors, so as to realize full-color display of the display panel.

[0086] As will be appreciated Figure 8 , the light emitting color of the plurality of sub-pixels Spx in the 1st pixel column Spc(1) is red, the light emitting color of the plurality of sub-pixels Spx in the 2nd pixel column Spc(2) is green, and the light emitting color of the plurality of sub-pixels Spx in the 3rd pixel column Spc(3) is blue.

[0087] In some embodiments, in the same pixel column unit SpcU, the light emitting color of the plurality of sub-pixels Spx in the hth pixel column Spc(h) is the same as the light emitting color of the plurality of sub-pixels Spx in the (h+3)th pixel column Spc(h+3). As will be appreciated Figure 8 , the light emitting color of the plurality of sub-pixels Spx in the 1st pixel column Spc(1) and the 4th pixel column Spc(4) is the same, the light emitting color of the plurality of sub-pixels Spx in the 2nd pixel column Spc(2) and the 5th pixel column Spc(5) is the same, and the light emitting color of the plurality of sub-pixels Spx in the 3rd pixel column Spc(3) and the 6th pixel column Spc(6) is the same.

[0088] Optionally, in the same frame, the polarity of the pixel voltage received by the plurality of sub-pixels Spx located in the jth pixel column Spc(j) is opposite to the polarity of the pixel voltage received by the plurality of sub-pixels Spx located in the (j+1)th pixel column Spc(j+1). Wherein, the polarity of the pixel voltage received by the same sub-pixel Spx in adjacent two frames is opposite, j≥1 and j is an odd number. In this way, on the basis of improving the display problem of the wobble line, the sub-pixel Spx can be prevented from receiving the pixel voltage of the same polarity for a long time, which is beneficial to improving the display quality of the display panel.

[0089] As will be appreciated Figure 8Corresponding to the W-th frame of the display panel, the pixel voltage received by the plurality of sub-pixels Spx located in the odd pixel column is a negative polarity voltage, and the pixel voltage received by the plurality of sub-pixels Spx located in the even pixel column is a positive polarity voltage. Corresponding to the W+1-th frame of the display panel, the pixel voltage received by the plurality of sub-pixels Spx located in the odd pixel column is a positive polarity voltage, and the pixel voltage received by the plurality of sub-pixels Spx located in the even pixel column is a negative polarity voltage. Wherein, W≥1.

[0090] The application also provides a display device comprising any of the display panels described above.

[0091] Optionally, the display device can further comprise a source driving chip and a timing controller. The source driving chip is configured to generate a plurality of data signals for transmission to the plurality of data lines DL. The timing controller is configured to generate a plurality of clock signals for output to the plurality of clock lines.

[0092] Optionally, the display device can further comprise a sensor, a pixel driving circuit, etc.

[0093] Optionally, the display device can be a mobile phone, a computer, a virtual reality display, an augmented reality display, or the like. The display device can be a device for realizing display function applied in the fields of education, entertainment, transportation, medical treatment, national defense, etc.

[0094] The above description is only optional embodiments of the application, and does not limit the patent scope of the application. Any equivalent structural transformation, direct / indirect application in other related technical fields based on the inventive concept of the application, and the contents of the specification and drawings are included in the patent protection scope of the application.

Claims

1. A display panel, characterized in that, include: Multiple sub-pixels are arranged along a row direction and a column direction to form multiple pixel rows arranged along the column direction and multiple pixel columns arranged along the row direction. Multiple data lines are electrically connected to multiple sub-pixels, and each data line is configured to transmit a data signal to the corresponding multiple sub-pixels; as well as Multiple scanning units are provided, each of which includes a first scan line and a second scan line. The first scan line and the second scan line of the same scanning unit are located on opposite sides of a pixel row along the column direction. In the same scanning unit, the first scan line is electrically connected to a portion of the sub-pixels of the corresponding pixel row, and the second scan line is electrically connected to another portion of the sub-pixels of the corresponding pixel row. In the same scanning unit, the end time of the effective pulse of the first scanning signal transmitted by the first scanning line precedes the start time of the effective pulse of the second scanning signal transmitted by the second scanning line.

2. The display panel according to claim 1, characterized in that, Also includes: Z clock lines are configured to transmit Z clock signals with phase differences in sequence; A gate drive circuit, electrically connected between the Z clock lines and the plurality of scan units, includes a plurality of cascaded shift registers, the plurality of shift registers being configured to generate valid pulses of the plurality of scan signals according to the Z clock signals, and output the plurality of scan signals to the plurality of first scan lines and the plurality of second scan lines; In the same scanning unit, the shift register electrically connected to the first scan line receives the x-th clock signal, and the shift register electrically connected to the second scan line receives the y-th clock signal; 1≤x≤Z / 2, y=x+Z / 2, and y≤Z, Z>1.

3. The display panel according to claim 2, characterized in that, The multiple sub-pixels of the MK+Nth pixel row are electrically connected to the shift register of the ZK+Nth level through the corresponding first scan line, and the multiple sub-pixels of the MK+Nth pixel row are electrically connected to the shift register of the ZK+N+Z / 2th level through the corresponding second scan line. Where MK+N≥1, ZK+N≥1, ZK+N+Z / 2>1; M=Z / 2; K≥0, and K is a positive integer; 1≤N≤Z / 2.

4. The display panel according to claim 3, characterized in that, Z＝8； Among them, the multiple sub-pixels of the 4K+1th pixel row are electrically connected to the shift register of the 8K+1th level through the corresponding first scan line, and are electrically connected to the shift register of the 8K+5th level through the corresponding second scan line; The multiple sub-pixels of the 4K+2th pixel row are electrically connected to the shift register of the 8K+2th level through the corresponding first scan line, and are electrically connected to the shift register of the 8K+6th level through the corresponding second scan line; The multiple sub-pixels of the 4K+3rd pixel row are electrically connected to the shift register of the 8K+3rd level through the corresponding first scan line, and are electrically connected to the shift register of the 8K+7th level through the corresponding second scan line; The plurality of sub-pixels of the 4K+4th pixel row are electrically connected to the shift register of the 8K+4th level via the corresponding first scan line, and are electrically connected to the shift register of the 8K+8th level via the corresponding second scan line.

5. The display panel according to claim 3, characterized in that, Z＝16； Among them, the multiple sub-pixels of the 8K+1th pixel row are electrically connected to the shift register of the 16K+1th level through the corresponding first scan line, and are electrically connected to the shift register of the 16K+9th level through the corresponding second scan line; The multiple sub-pixels of the 8K+2th pixel row are electrically connected to the shift register of the 16K+2th level through the corresponding first scan line, and are electrically connected to the shift register of the 16K+10th level through the corresponding second scan line. The multiple sub-pixels of the 8K+3rd pixel row are electrically connected to the shift register of the 16K+3rd level through the corresponding first scan line, and are electrically connected to the shift register of the 16K+11th level through the corresponding second scan line. The multiple sub-pixels of the 8K+4th pixel row are electrically connected to the shift register of the 16K+4th level through the corresponding first scan line, and are electrically connected to the shift register of the 16K+12th level through the corresponding second scan line. The multiple sub-pixels of the 8K+5th pixel row are electrically connected to the shift register of the 16K+5th level through the corresponding first scan line, and are electrically connected to the shift register of the 16K+13th level through the corresponding second scan line. The multiple sub-pixels of the 8K+6th pixel row are electrically connected to the shift register of the 16K+6th level through the corresponding first scan line, and are electrically connected to the shift register of the 16K+14th level through the corresponding second scan line. The multiple sub-pixels of the 8K+7th pixel row are electrically connected to the shift register of the 16K+7th level through the corresponding first scan line, and are electrically connected to the shift register of the 16K+15th level through the corresponding second scan line. The plurality of sub-pixels of the 8K+8th pixel row are electrically connected to the shift register of the 16K+8th level via the corresponding first scan line, and are electrically connected to the shift register of the 16K+16th level via the corresponding second scan line.

6. The display panel according to claim 1, characterized in that, Two pixel columns are provided between two adjacent data lines; In each pixel row, a plurality of sub-pixels are alternately electrically connected to the first scan line and the second scan line of the corresponding scanning unit; in two pixel columns located between two adjacent data lines, two sub-pixels in the same pixel row are electrically connected to the same data line, and a plurality of sub-pixels in the same pixel column are alternately electrically connected to two adjacent data lines.

7. The display panel according to claim 6, characterized in that, In the same frame, the polarity of the pixel voltage received by multiple sub-pixels located in the i-th pixel row is opposite to the polarity of the pixel voltage received by multiple sub-pixels located in the (i+1)-th pixel row, and the polarity of the pixel voltage received by multiple sub-pixels located in the r-th pixel column is the same as the polarity of the pixel voltage received by multiple sub-pixels located in the (r+1)-th pixel column, while the polarity of the pixel voltage received by multiple sub-pixels located in the r-th pixel column is opposite to the polarity of the pixel voltage received by multiple sub-pixels located in the (r+2)-th pixel column. Wherein, the polarities of the pixel voltages received in two adjacent frames corresponding to the same sub-pixel are opposite, i≥1, r≥1 and r is an odd number.

8. The display panel according to claim 1, characterized in that, Each data line has a pixel column on each of its opposite sides along the row direction, and two pixel columns are provided between two adjacent data lines. In each pixel row, a plurality of sub-pixels are alternately electrically connected to the first scan line and the second scan line of the corresponding scanning unit, and each data line is electrically connected to a plurality of sub-pixels in two adjacent pixel columns.

9. The display panel according to claim 8, characterized in that, In the same frame, the pixel voltages received by multiple sub-pixels electrically connected to the same data line have the same polarity, while the pixel voltages transmitted by two adjacent data lines have opposite polarities; the pixel voltages received by the same sub-pixel in two adjacent frames have opposite polarities.

10. The display panel according to claim 1, characterized in that, The 4p+1th and 4p+2nd sub-pixels of the same pixel row are electrically connected to one of the first and second scan lines in the corresponding scanning unit, and the 4p+3rd and 4p+4th sub-pixels of the same pixel row are electrically connected to the other of the first and second scan lines in the corresponding scanning unit. Multiple data lines and multiple pixel columns are arranged alternately along the row direction, and multiple sub-pixels of the same pixel column are electrically connected to the same data line; Where p≥0, and p is a positive integer.

11. The display panel according to claim 10, characterized in that, The display panel includes a plurality of pixel column units arranged along the row direction, and each pixel column unit includes q pixel columns; In the same pixel column unit, the data lines electrically connected to the multiple sub-pixels of the h-th pixel column are electrically connected to the data lines electrically connected to the multiple sub-pixels of the h+q / 2-th pixel column. The emission color of the multiple sub-pixels of the h-th pixel column is the same as the emission color of the multiple sub-pixels of the h+q / 2-th pixel column, where q is an even number and 1≤h≤q / 2.

12. The display panel according to claim 10, characterized in that, In the same frame, the polarity of the pixel voltage received by a plurality of sub-pixels located in the j-th pixel column is opposite to the polarity of the pixel voltage received by a plurality of sub-pixels located in the (j+1)-th pixel column; Wherein, the polarities of the pixel voltages received in two adjacent frames corresponding to the same sub-pixel are opposite, j≥1 and j is an odd number.

13. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 12.

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