Memory device, operating method thereof, memory system, and storage medium

Abstract

The embodiment of the invention provides a memory device, an operation method thereof, a memory system and a storage medium. The memory device includes: a memory cell array; a plurality of bit lines, each of which is coupled to the memory cell array; the peripheral circuit is coupled with each bit line, and is configured to execute N times of voltage boosting operation in a charging stage, so that the voltage on at least one bit line in the plurality of bit lines is boosted from an initial voltage to a target voltage; wherein N is a positive integer smaller than a preset threshold value, and / or the time interval between two adjacent voltage boosting operations is smaller than or equal to a first preset duration.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory device and its operation method, memory system and storage medium. Background Technology

[0002] Semiconductor memory devices can be mainly divided into volatile memory devices and non-volatile memory devices. Non-volatile memory devices retain stored data even when power is off, and are therefore commonly used as storage media in portable and / or electronic products. Common non-volatile memory devices include 3D NAND flash memory, phase-change random access memory (PCRAM), resistive random access memory (RRAM), and ferroelectric random access memory (FRAM).

[0003] With the advancement of semiconductor technology, 3D NAND flash memory has gradually become the mainstream storage device, increasing storage density through stacked multi-layer storage cells. To meet the ever-increasing storage demands, the number of storage cell layers in 3D NAND flash memory is constantly increasing, which also increases the requirements for controlling the storage device (e.g., programming, reading, or erasing). Summary of the Invention

[0004] This disclosure provides a memory device, its operation method, memory system, and storage medium.

[0005] In a first aspect, embodiments of this disclosure provide a memory device, comprising: a memory cell array; a plurality of bit lines, each bit line being coupled to the memory cell array; and peripheral circuitry coupled to each bit line and configured to: perform N voltage boosting operations during a charging phase, such that the voltage on at least one of the plurality of bit lines rises from an initial voltage to a target voltage; wherein N is a positive integer less than a preset threshold, and / or the time interval between two adjacent voltage boosting operations is less than or equal to a first preset duration.

[0006] In some optional embodiments, N is greater than or equal to 2; the peripheral circuit is configured to: apply an Mth voltage pulse to at least one of the plurality of bit lines at the first moment of performing the Mth voltage boost operation during the charging phase; the voltage on the at least one bit line reaches the voltage of the Mth voltage pulse at the second moment of the Mth voltage boost operation; apply an (M+1)th voltage pulse to at least one of the plurality of bit lines at the first moment of the (M+1)th voltage boost operation during the charging phase; the time interval between the second moment of the Mth voltage boost operation and the first moment of the (M+1)th voltage boost operation is less than or equal to the first preset duration; wherein the voltage of the Mth voltage pulse is less than the voltage of the (M+1)th voltage pulse; and M+1 is greater than 1 and less than or equal to N.

[0007] In some optional embodiments, the memory device further includes a plurality of word lines, each word line being coupled to the memory cell array and the peripheral circuitry; the peripheral circuitry is configured to perform the N voltage boosting operations on a selected bit line among the plurality of bit lines before a third time point when the voltage on a selected word line among the plurality of word lines reaches the verification voltage during a programming verification operation; wherein the voltage on the selected bit line reaches the target voltage at a second time point of the Nth voltage boosting operation, and the time interval between the third time point and the second time point of the Nth voltage boosting operation is greater than or equal to a second preset duration.

[0008] In some optional embodiments, the memory device further includes a plurality of word lines, each word line being coupled to the memory cell array and the peripheral circuitry; the peripheral circuitry is configured to perform the N voltage boosting operations on the non-selected bit lines during a programming operation, prior to a fourth time when the voltage on a selected word line among the plurality of word lines reaches the programming voltage; wherein the voltage on the non-selected bit lines reaches the target voltage at a second time during the Nth voltage boosting operation, and the time interval between the fourth time and the second time during the Nth voltage boosting operation is greater than or equal to a second preset duration.

[0009] In some optional embodiments, the memory device further includes multiple word lines; the peripheral circuitry is configured to perform the N voltage boosting operations on the multiple bit lines before a fifth time when the voltage on a selected word line among the multiple word lines reaches the read voltage during a read operation; wherein the voltage on the multiple bit lines reaches the target voltage at a second time during the Nth voltage boosting operation, and the time interval between the fifth time and the second time during the Nth voltage boosting operation is greater than or equal to a second preset duration.

[0010] In some optional embodiments, the memory device further includes a plurality of word lines, each word line being coupled to the memory cell array and the peripheral circuitry; the peripheral circuitry is configured to perform the Nth voltage boosting operation on the plurality of bit lines before a sixth moment when the voltage on a selected word line among the plurality of word lines reaches the erase verification voltage during an erase operation; wherein the voltage on the plurality of bit lines reaches the target voltage at a second moment of the Nth voltage boosting operation, and the time interval between the sixth moment and the second moment of the Nth voltage boosting operation is greater than or equal to a second preset duration.

[0011] In some optional embodiments, the first preset duration is less than the second preset duration.

[0012] In some optional embodiments, the preset threshold value ranges from 2 to 7.

[0013] In some optional embodiments, the storage cell array includes storage cells with a storage bit length of P bits; wherein P is an integer greater than or equal to 2 and less than or equal to 4.

[0014] In a second aspect, embodiments of this disclosure provide a memory system comprising: one or more memory devices as described in any of the first aspects; and a memory controller coupled to the memory devices and configured to control the memory devices.

[0015] Thirdly, embodiments of this disclosure provide an operation method for a memory device, the method comprising: performing N voltage boosting operations during a charging phase, such that the voltage on at least one of a plurality of bit lines of the memory device rises from an initial voltage to a target voltage; wherein N is a positive integer less than a preset threshold, and / or the time interval between two adjacent voltage boosting operations is less than or equal to a first preset duration.

[0016] In some optional embodiments, performing N voltage boost operations during the charging phase includes: at a first moment during the first voltage boost operation of the charging phase, applying an Mth voltage pulse to at least one of the plurality of bit lines; the voltage on the at least one bit line reaching the voltage of the Mth voltage pulse at a second moment during the second voltage boost operation of the Mth voltage boost operation; at a first moment during the (M+1)th voltage boost operation of the charging phase, applying an (M+1)th voltage pulse to at least one of the plurality of bit lines; the time interval between the second moment during the second voltage boost operation of the Mth voltage boost operation and the first moment during the (M+1)th voltage boost operation is less than or equal to the first preset duration; wherein the voltage of the Mth voltage pulse is less than the voltage of the (M+1)th voltage pulse; and M+1 is greater than 1 and less than or equal to N.

[0017] In some optional embodiments, the method includes: performing the N voltage boosting operations on selected bit lines among the plurality of bit lines before a third time when the voltage on a selected word line among the plurality of word lines of the memory device reaches a verification voltage during a programming verification operation; wherein the voltage on the selected bit line reaches the target voltage at a second time during the Nth voltage boosting operation, and the time interval between the third time and the second time during the Nth voltage boosting operation is greater than or equal to a second preset duration.

[0018] In some optional embodiments, the method includes: performing the N voltage boosting operations on non-selected bit lines among the plurality of bit lines before a fourth time when the voltage on a selected word line among the plurality of word lines of the memory device reaches the programming voltage during a programming operation; wherein the voltage on the non-selected bit lines reaches the target voltage at a second time during the Nth voltage boosting operation, and the time interval between the fourth time and the second time during the Nth voltage boosting operation is greater than or equal to a second preset duration.

[0019] In some optional embodiments, the method includes: performing the N voltage boosting operations on the plurality of bit lines before a fifth time when the voltage on a selected word line among the plurality of word lines of the memory device reaches the read voltage during a read operation; wherein the voltage on the plurality of bit lines reaches the target voltage at a second time during the Nth voltage boosting operation, and the time interval between the fifth time and the second time during the Nth voltage boosting operation is greater than or equal to a second preset duration.

[0020] In some optional embodiments, the method includes: performing the N voltage boosting operations on the plurality of bit lines before a sixth moment when the voltage on selected word lines of the plurality of word lines of the memory device reaches the erase verification voltage during an erase operation; wherein the voltage on the plurality of bit lines reaches the target voltage at a second moment of the Nth voltage boosting operation, and the time interval between the sixth moment and the second moment of the Nth voltage boosting operation is greater than or equal to a second preset duration.

[0021] In some optional embodiments, the first preset duration is less than the second preset duration.

[0022] In some optional embodiments, the preset threshold value ranges from 2 to 7.

[0023] In some optional embodiments, the storage cell array includes storage cells with a storage bit length of P bits; wherein P is an integer greater than or equal to 2 and less than or equal to 4.

[0024] Fourthly, embodiments of this disclosure provide a storage medium storing executable instructions, which, when executed, can implement the steps of any of the operation methods described in the third aspect.

[0025] In the various embodiments of this disclosure, by reducing the number of voltage boost operations and / or reducing the time interval between two adjacent voltage boost operations, the charging speed of at least one of the multiple bit lines can be accelerated, enabling it to reach the target voltage more quickly. This shortens the total time of the programming, reading, or erasing process, while reducing power consumption and improving the performance of the memory device. Attached Figure Description

[0026] Figure 1 A schematic diagram of an exemplary system with a memory system provided in the embodiments of this disclosure;

[0027] Figure 2A A schematic diagram of an exemplary memory card with a memory system provided for embodiments of this disclosure;

[0028] Figure 2B A schematic diagram of an exemplary solid-state drive with a memory system provided for embodiments of this disclosure;

[0029] Figure 3 A schematic diagram of an exemplary memory device including peripheral circuitry provided for embodiments of this disclosure;

[0030] Figure 4 A schematic diagram of an exemplary memory device including a memory cell array and peripheral circuitry, provided for embodiments of this disclosure;

[0031] Figure 5 A voltage curve for charging at least one of a plurality of bit lines provided in an embodiment of this disclosure;

[0032] Figure 6 A second voltage curve for charging at least one of a plurality of bit lines, provided as an embodiment of this disclosure;

[0033] Figure 7 Three voltage curves for charging at least one of a plurality of bit lines provided in embodiments of this disclosure;

[0034] Figure 8 A voltage curve for charging at least one of a plurality of bit lines provided in an embodiment of this disclosure;

[0035] Figure 9 A block diagram of a storage medium provided in an embodiment of this disclosure. Detailed Implementation

[0036] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0037] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0038] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0039] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0040] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0042] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0043] The memory systems in the embodiments of this disclosure include, but are not limited to, memory systems with three-dimensional NAND type memory. For ease of understanding, the memory systems provided in this disclosure will be described using a memory system including three-dimensional NAND type memory as an example.

[0044] Figure 1 This is a schematic diagram of an exemplary system with a memory system provided for embodiments of this disclosure. In embodiments of this disclosure, system 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 1As shown, system 100 may include a host 108 and a memory system 102, which may include one or more memory devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory device 104.

[0045] In some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as in Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or in other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0046] In some implementations, the memory controller 106 is designed to operate in a high duty cycle environment in a solid state disk (SSD) or an embedded multimedia card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0047] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes relating to data read from or written to the memory device 104.

[0048] The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with external devices (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0049] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products.

[0050] In such Figure 2A In one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108.

[0051] In such Figure 2B In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0052] Figure 3 A circuit diagram of an exemplary memory device 300 including peripheral circuitry, provided for embodiments of this disclosure. The memory device 300 may be... Figure 1 An example of memory device 104 is provided. Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 is illustrated as a three-dimensional NAND-type memory cell array, wherein the memory cells 306 are NAND-type memory cells, provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0053] In some implementations, each storage cell 306 is a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range. In some implementations, each storage cell 306 is a multi-level cell capable of storing more than one bit of data in four or more storage states, such as a multi-level cell (MLC) storing two bits per cell, a triple-level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0054] like Figure 3As shown, each memory string 308 may include a lower selection transistor (BSG) 310 (also known as a source-side selection transistor) at its source end and an upper selection transistor (TSG) 312 (also known as a drain-side selection transistor) at its drain end. BSG 310 and TSG 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of memory strings 308 within the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 within the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0055] like Figure 3 As shown, memory strings 308 can be organized into multiple memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some implementations, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 314 of the selected memory block 304 and the unselected memory blocks 304 on the same plane as the selected memory block 304. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0056] refer to Figure 3 Each memory cell 306 in the multiple memory cells is coupled to the corresponding word line 318, and each memory string 308 is coupled to the corresponding bit line 316 through the corresponding selection transistor (such as the selection transistor (TSG) 312 above).

[0057] In some embodiments, peripheral circuitry 302 can be coupled to memory cell array 301 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. Peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. Peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 4 Some exemplary peripheral circuitry is shown, including a page buffer / sensor amplifier 401, a column decoder / bit line driver 402, a row decoder / word line driver 403, a voltage generator 404, control logic 405, a register 406, an interface 407, and a data bus 408. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 4 Additional peripheral circuitry not shown.

[0058] Page buffer / sensor amplifier 401 can be configured to read data from memory cell array 301 and program (write) data to memory cell array 301 according to control signals from control logic 405. In one example, page buffer / sensor amplifier 401 can store programming data to be programmed into memory cell array 301 (write data). In another example, page buffer / sensor amplifier 401 can perform a programming verification operation to ensure that data has been correctly programmed into memory cells coupled to selected word lines. In yet another example, page buffer / sensor amplifier 401 can also sense low-power signals from bit lines representing data bits stored in memory cells and amplify small voltage swings to recognizable logic levels during read operations. Column decoder / bit line driver 402 can be configured to be controlled by control logic 405 and select one or more memory strings by applying bit line voltages generated from voltage generator 404.

[0059] The row decoder / word line driver 403 can be configured to be controlled by control logic 405 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 403 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 404. In some embodiments, the row decoder / word line driver 403 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, the row decoder / word line driver 403 is configured to perform programming operations on memory cells coupled to one or more selected word lines. Voltage generator 404 can be configured to be controlled by control logic 405 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, channel boost voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0060] Control logic 405 can be coupled to each of the other parts of the peripheral circuitry described above and is configured to control the operation of each of the other parts of the peripheral circuitry. Register 406 can be coupled to control logic 405 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 407 can be coupled to control logic 405 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 405, as well as to buffer status information received from control logic 405 and relay it to the host. Interface 407 can also be coupled to column decoder / bitline driver 402 via data bus 408 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0061] As consumers demand higher performance and reliability from electronic products, the market is placing greater demands on the programming / reading / erasing speed of 3D NAND flash memory. In some embodiments, the programming, reading, or erasing processes of 3D NAND flash memory all involve a charging phase, which involves raising the voltage on at least one of the multiple bit lines from an initial voltage to a target voltage. If this charging phase lasts too long, it will increase the total time of the programming, reading, or erasing process, thus reducing the performance of the memory device.

[0062] The present disclosure proposes the following implementation method.

[0063] In a first aspect, embodiments of this disclosure provide a memory device, in conjunction with reference to... Figure 3 and Figure 4The memory device 300 includes: a memory cell array 301; a plurality of bit lines 316, each bit line 316 coupled to the memory cell array 301; and peripheral circuitry 302, coupled to each bit line 316, and configured to: perform N voltage boosting operations during the charging phase, such that the voltage on at least one of the plurality of bit lines 316 rises from an initial voltage to a target voltage; wherein N is a positive integer less than a preset threshold, and / or the time interval between two adjacent voltage boosting operations is less than or equal to a first preset duration.

[0064] By reducing the number of voltage boost operations and / or reducing the time interval between two adjacent voltage boost operations, the charging speed of at least one of the multiple bit lines can be accelerated, enabling it to reach the target voltage more quickly. This, in turn, shortens the total time of the programming, reading, or erasing process, while reducing power consumption and improving the performance of the memory device.

[0065] It should be noted that the setting of N is related to the voltage difference between the initial voltage and the target voltage, as well as the voltage change of at least one of the multiple bit lines in each voltage boosting operation.

[0066] In some embodiments, the preset threshold value ranges from 2 to 7. More specifically, the preset threshold value can be 2, 3, 4, 5, 6, or 7.

[0067] In some embodiments, N is greater than or equal to 2; the peripheral circuit is configured to: apply the Mth voltage pulse to at least one of the multiple bit lines at a first moment during the Mth voltage boost operation in the charging phase; the voltage on the at least one bit line reaches the voltage of the Mth voltage pulse at a second moment during the Mth voltage boost operation; apply the (M+1)th voltage pulse to at least one of the multiple bit lines at a first moment during the (M+1)th voltage boost operation in the charging phase; the time interval between the second moment during the Mth voltage boost operation and the first moment during the (M+1)th voltage boost operation is less than or equal to a first preset duration; wherein the voltage of the Mth voltage pulse is less than the voltage of the (M+1)th voltage pulse; M+1 is greater than 1 and less than or equal to N.

[0068] In some implementations, reference Figure 5 N is greater than or equal to 2; the peripheral circuit is configured to: apply the Mth voltage pulse to at least one of the multiple bit lines at the first moment t1 of the Mth voltage boost operation during the charging phase; the voltage on at least one bit line reaches the voltage V of the Mth voltage pulse at the second moment t2 of the Mth voltage boost operation. MDuring the (M+1)th voltage boost operation in the charging phase, at the first time t3, the (M+1)th voltage pulse is applied to at least one of the multiple bit lines; the time interval Δt1 between the second time t2 in the Mth voltage boost operation and the first time t3 in the (M+1)th voltage boost operation is less than or equal to a first preset duration; wherein, the voltage V of the Mth voltage pulse... M The voltage V less than the (M+1)th voltage pulse M+1 M+1 is greater than 1 and less than or equal to N.

[0069] In some implementations, such as Figure 5 As shown, the voltage on at least one of the multiple bit lines reaches the voltage V of the (M+1)th voltage pulse at the second time t4 during the (M+1)th voltage boost operation in the charging phase. M+1 .

[0070] In some implementations, at the first moment t1 during the Mth voltage boost operation in the charging phase, the voltage on at least one of the multiple bit lines is V. bl When M equals 1, V bl This is the initial voltage. When M+1 equals N, the voltage V of the (M+1)th voltage pulse... M+1 That is, the target voltage.

[0071] In some embodiments, reference Figure 6 The second time t2 in the Mth voltage boost operation is the same as the first time t3 in the (M+1)th voltage boost operation, that is, the time interval between the second time t2 in the Mth voltage boost operation and the first time t3 in the (M+1)th voltage boost operation is equal to 0.

[0072] By further reducing the time interval between two adjacent voltage boosting operations to 0, the setup time of the voltage on at least one of the multiple bit lines from the initial voltage to the target voltage can be further shortened, thereby improving the speed of the programming, reading, or erasing process.

[0073] In some embodiments, for three-dimensional NAND flash memory, incremental step pulse programming (ISPP) is typically used for programming, which involves sequentially programming the memory cell with multiple progressively increasing pulse programming voltages. Each programming process may include a programming operation and a subsequent programming verification operation.

[0074] In some implementations, the above-mentioned charging phase can be for... Figure 3 and Figure 4When the memory cell array 301 shown is programmed, before the voltage on the selected word line reaches the programming voltage Vpgm, the selected word line coupled to the memory cell to be programmed is floated or discharged, and the non-selected word line coupled to the programming inhibit memory cell is charged to the programming inhibit voltage to inhibit programming. This stage can enhance the coupling potential of the channel and reduce programming interference. The programming inhibit voltage can be, for example, the power supply voltage VDD.

[0075] like Figure 3 As shown, the memory device 300 also includes multiple word lines 318, each word line 318 being coupled to the memory cell array 301 and the peripheral circuitry 302; the peripheral circuitry 302 is configured to perform N voltage boosting operations on the non-selected bit lines 316 before the voltage on the selected word line among the multiple word lines 318 reaches the programming voltage Vpgm at a fourth time during a programming operation; wherein the voltage on the non-selected bit lines reaches the target voltage at a second time during the Nth voltage boosting operation, and the time interval between the fourth time and the second time during the Nth voltage boosting operation is greater than or equal to a second preset duration.

[0076] In some embodiments, reference Figure 3 and Figure 5 Taking M+1 equal to N as an example, the peripheral circuit 302 is configured such that during the programming operation, the voltage on the selected word line among the multiple word lines 318 reaches the programming voltage Vpgm at the fourth moment. Figure 5 Before time t5, N voltage boosting operations are performed on the non-selected positioning lines among the multiple bit lines 316; wherein, the voltage on the non-selected positioning lines reaches the target voltage at the second time t4 of the Nth voltage boosting operation, and at the fourth time ( Figure 5 The time interval Δt2 between the time shown (t5) and the second time (t4) of the Nth voltage boost operation is greater than or equal to the second preset duration.

[0077] In some implementations, the initial voltage can be ground voltage VSS, such as 0V, and the target voltage can be power supply voltage VDD, such as 2V.

[0078] It is understandable that the voltage on the non-selective positioning line reaches the target voltage at the second moment t4 of the Nth voltage boost operation. Figure 5 The V shown M+1 After a time interval Δt2, at the fourth time ( Figure 5 At the time shown (t5), the voltage on the selected word line among the multiple word lines 318 reaches the programming voltage Vpgm. This ensures that the voltage on the non-selected word lines has stabilized at the target voltage, such as the power supply voltage VDD, at the start of the programming operation, which helps reduce programming interference.

[0079] By reducing the number of voltage boost operations and / or reducing the time interval between two adjacent voltage boost operations, the charging speed of the non-selective positioning line can be accelerated, enabling it to reach the target voltage more quickly. This shortens the preparation time before starting the programming operation, thereby reducing the total programming time and improving the performance of the memory device.

[0080] In some embodiments, the charging phase described above can be the process of programming. Figure 3 and Figure 4 During the at least one programming verification operation performed after each of the multiple programming operations performed by the memory cell array 301 shown, the selected bit lines among the multiple bit lines are charged from the initial voltage to the target voltage.

[0081] For example, during the programming verification operation phase, the voltage on the selected word line is charged from 0V to 0.5-0.7V before the voltage on the selected word line reaches the verification voltage.

[0082] In some embodiments, reference Figure 3 and Figure 5 Taking M+1 equal to N as an example, the memory device 300 also includes multiple word lines 318, each word line 318 being coupled to the memory cell array 301 and the peripheral circuit 302. The peripheral circuit 302 is configured to perform N voltage boosting operations on selected word lines among the multiple word lines 316 before the voltage on the selected word line among the multiple word lines 318 reaches the verification voltage Vverify at a third time during the programming verification operation. The voltage on the selected word line reaches the target voltage at the second time of the Nth voltage boosting operation, and the time interval between the third time and the second time of the Nth voltage boosting operation is greater than or equal to a second preset duration.

[0083] In some implementations, the initial voltage can be 0V, and the target voltage can be 0.5V to 0.7V. More specifically, the target voltage can be 0.5V, 0.6V, or 0.7V.

[0084] The voltage on the selected positioning line reaches the target voltage at the second moment t4 of the Nth voltage boost operation. Figure 5 The V shown M+1 After a time interval Δt2, at the third time ( Figure 5 At the time shown (t5), the voltage on the selected word line among the multiple word lines 318 reaches the verification voltage Vverify. This ensures that the voltage on the selected word line has stabilized at the target voltage when the programming verification operation begins, which helps improve the accuracy of the programming verification operation.

[0085] By reducing the number of voltage boost operations and / or the time interval between two adjacent voltage boost operations, the charging speed of the selected line can be accelerated, allowing it to reach the target voltage more quickly, thereby shortening the programming verification operation time. Since each programming process includes multiple programming verification operations, the total duration of each programming process can be significantly reduced, improving the performance of the memory device.

[0086] In some embodiments, reference Figure 3 and Figure 6 With M equal to 1, N equal to 2, and the target voltage V M+1 Taking the example of the voltage V of the first voltage pulse... M That is, V1, the voltage V of the second voltage pulse. M+1 That is, V2. The peripheral circuit 302 is configured to perform two voltage boost operations on the selected word line among the multiple word lines 316 before the third moment when the voltage on the selected word line among the multiple word lines 318 reaches the verification voltage Vverify during the programming verification operation; wherein, the initial voltage on the selected word line is V... bl For example, 0V, the voltage on the selected positioning line reaches the voltage V1 of the first voltage pulse at the second moment t2 of the first voltage boost operation. V1 can be, for example, 0.3V. Simultaneously with the voltage on the selected positioning line reaching V1 ( Figure 6 At the times shown (t2 / t3), the second voltage pulse is applied to the selected positioning line. The voltage on the selected positioning line reaches the target voltage, i.e., the voltage V2 of the second voltage pulse, at the second time t4 of the second voltage boost operation. V2 can be, for example, 0.6V. At the third time ( Figure 6 The time interval Δt2 between the time shown (t5) and the second time (t4) of the second voltage boost operation is greater than or equal to the second preset duration.

[0087] In some embodiments, reference Figure 3 and Figure 7 The peripheral circuit 302 is configured to: during the programming verification operation, before the third moment Q5 of the verification voltage Vverify on the selected word line among the multiple word lines 318, perform three voltage boost operations to raise the voltage on the selected word line from the initial voltage V0 to the target voltage V3 during the charging phase; wherein the time interval between two adjacent voltage boost operations is equal to 0.

[0088] In the first time (Q1) of the first voltage boost operation, the first voltage pulse is applied to the selected positioning line; the voltage on the selected positioning line reaches the voltage V1 of the first voltage pulse at the second time (Q2) of the first voltage boost operation; in the first time (Q3) of the second voltage boost operation during the charging phase, the second voltage pulse is applied to the selected positioning line; the voltage on the selected positioning line reaches the voltage V2 of the second voltage pulse at the second time (Q4) of the second voltage boost operation; in the first time (Q3) of the third voltage boost operation during the charging phase... Figure 7 At the time shown (Q4), the third voltage pulse is applied to the selected positioning line, and the voltage on the selected positioning line reaches the voltage V3 of the third voltage pulse at the second time (Q6) of the third voltage boost operation; for example, V0 can be 0V, V1 can be 0.2V, V2 can be 0.4V, and V3 can be 0.6V.

[0089] In some embodiments, reference Figure 3 and Figure 8 The peripheral circuit 302 is configured to: during the programming verification operation, before the third moment Q5 of the verification voltage Vverify on the selected word line among the multiple word lines 318, perform three voltage boosting operations to raise the voltage on the selected word line from the initial voltage V0 to the target voltage V3 during the charging phase; wherein the time interval between adjacent first voltage boosting operations and second voltage boosting operations is greater than 0, and the time interval between adjacent second voltage boosting operations and third voltage boosting operations is equal to 0.

[0090] In the first voltage boost operation, at the first moment Q1, the first voltage pulse is applied to the selected positioning line; the voltage on the selected positioning line reaches the voltage V1 of the first voltage pulse at the second moment Q2 of the first voltage boost operation. After a time interval Δt1, at the first moment Q3 of the second voltage boost operation, the second voltage pulse is applied to the selected positioning line; the voltage on the selected positioning line reaches the voltage V2 of the second voltage pulse at the second moment Q4 of the second voltage boost operation; in the first moment of the third voltage boost operation during the charging phase... Figure 8 At time Q4, the third voltage pulse is applied to the selected positioning line, and the voltage on the selected positioning line reaches the voltage V3 of the third voltage pulse at the second time Q6 of the third voltage boost operation; exemplarily, V0 can be 0V, V1 can be 0.4V, V2 can be 0.5V, and V3 can be 0.6V.

[0091] Since the first voltage boost operation raises the voltage on the selected positioning line from 0V to 0.4V, the voltage change on the positioning line is greater than that in the second and third voltage boost operations. Therefore, a time interval Δt1 is set after the first voltage boost operation to stabilize the voltage on the selected positioning line.

[0092] Understandably, in practice, during the process of charging the voltage generated by at least one of multiple bit lines from the initial voltage to the target voltage, the time interval between any two adjacent voltage boosting operations can be set according to requirements. For example, the number of voltage boosting operations can be set according to the difference between the initial voltage and the target voltage. Furthermore, the time interval between adjacent voltage boosting operations can be determined according to the voltage change that needs to be achieved in each voltage boosting operation.

[0093] In some embodiments, during the read operation of a three-dimensional NAND flash memory, a pass voltage Vpass is applied to a non-selected word line. Vpass can be, for example, 4V or 5V. A read voltage Vread is applied to the selected word line. Vread can be, for example, 0V. Multiple bit lines need to be charged to a target voltage, which can be 2V. Exemplarily, this charging phase can be a phase during the read operation where, before the voltage on the selected word line reaches the read voltage Vread at the fifth moment, the voltage on multiple bit lines is charged from 0V to 2V.

[0094] In some embodiments, the memory device further includes multiple word lines; the peripheral circuitry is configured to perform N voltage boosting operations on the multiple bit lines before the voltage on a selected word line among the multiple word lines reaches the read voltage at a fifth time during a read operation; wherein the voltage on the multiple bit lines reaches the target voltage at a second time during the Nth voltage boosting operation, and the time interval between the fifth time and the second time during the Nth voltage boosting operation is greater than or equal to a second preset duration.

[0095] In some embodiments, reference Figure 3 and Figure 5 Taking M+1 equal to N as an example, the peripheral circuit 302 is configured such that during programming operations, the voltage on the selected word line among the multiple word lines 318 reaches the fifth moment of the read voltage Vread. Figure 5 Before time t5, N voltage boosting operations are performed on multiple bit lines 316; wherein, the voltage on multiple bit lines 316 reaches the target voltage at the second time t4 of the Nth voltage boosting operation, and at the fifth time ( Figure 5 The time interval Δt2 between the time shown (t5) and the second time (t4) of the Nth voltage boost operation is greater than or equal to the second preset duration.

[0096] In some implementations, the initial voltage can be ground voltage VSS, such as 0V, and the target voltage can be power supply voltage VDD, such as 2V.

[0097] It is understandable that multiple bit lines reach the target voltage at the second time t4 of the Nth voltage boost operation. Figure 5 The V shown M+1 After a time interval Δt2, at the fifth moment ( Figure 5 At the time shown (t5), the voltage on the selected word line among the multiple word lines 318 reaches the read voltage Vread. This ensures that the voltage on the multiple bit lines has stabilized at the target voltage when the read operation begins, which helps reduce read interference.

[0098] By reducing the number of voltage boost operations and / or reducing the time interval between two adjacent voltage boost operations, the charging speed of multiple bit lines can be accelerated, enabling them to reach the target voltage more quickly, thereby shortening the total reading time and improving the performance of the memory device.

[0099] In some embodiments, for three-dimensional NAND flash memory, incremental step pulse erase (ISPE) is typically used for erasure. That is, the starting pulse and the step size (ISPE step) are fixed, the voltage of the erase pulse gradually increases by one step, and an erase verify operation is performed after each erase pulse.

[0100] like Figure 3 As shown, in the erase verification operation of the three-dimensional NAND flash memory, an erase verification voltage, such as 0V, or other voltages, is applied to each word line in the memory block 304. Multiple bit lines 316 coupled to each memory string 308 in the memory block 304 are pre-charged, for example, by charging the multiple bit lines 316 coupled to each memory string 308 in the memory block 304 to 1V.

[0101] For example, the charging phase described above can be a phase in which the multiple bit lines 316 coupled to each memory string 308 in the memory block 304 are pre-charged before the sixth moment when the voltage on the selected word line among the multiple word lines reaches the erase verification voltage during the erase verification operation performed after each erase pulse in the erase process.

[0102] In some embodiments, the memory device further includes a plurality of word lines, each word line being coupled to a memory cell array and peripheral circuitry; the peripheral circuitry is configured to perform N voltage boosting operations on the plurality of bit lines before the voltage on a selected word line among the plurality of word lines reaches the sixth time of the erase verification voltage during an erase operation; wherein the voltage on the plurality of bit lines reaches the target voltage at the second time of the Nth voltage boosting operation, and the time interval between the sixth time and the second time of the Nth voltage boosting operation is greater than or equal to a second preset duration.

[0103] In some embodiments, reference Figure 3 and Figure 5 Taking M+1 equal to N as an example, the peripheral circuit 302 is configured such that during the erase operation, the voltage on the selected word line among the multiple word lines 318 reaches the sixth moment of the erase verification voltage. Figure 5 Before time t5, N voltage boosting operations are performed on multiple bit lines 316; wherein, the voltage on multiple bit lines 316 reaches the target voltage at the second time t4 of the Nth voltage boosting operation, and at the sixth time ( Figure 5 The time interval Δt2 between the time shown (t5) and the second time (t4) of the Nth voltage boost operation is greater than or equal to the second preset duration.

[0104] In some implementations, the initial voltage can be ground voltage VSS, for example, 0V, and the target voltage can be 1V.

[0105] It is understandable that multiple bit lines reach the target voltage at the second time t4 of the Nth voltage boost operation. Figure 5 The V shown M+1 After a time interval Δt2, at the sixth time ( Figure 5 At the time shown (t5), the voltage on the selected word line among the multiple word lines 318 reaches the erase verification voltage. This ensures that the voltage on the multiple bit lines has stabilized at the target voltage when the erase verification operation begins, which helps improve the accuracy of the erase verification operation.

[0106] By reducing the number of voltage boost operations and / or reducing the time interval between two adjacent voltage boost operations, the charging speed of multiple bit lines can be accelerated, enabling them to reach the target voltage more quickly, thereby shortening the total time of the erase process and improving the performance of the memory device.

[0107] In some embodiments, the first preset duration is shorter than the second preset duration. This ensures that the interval between multiple rise operations during the charging phase is short for at least one bit line across multiple bit lines, which helps reduce the overall operation time and overall energy consumption. Simultaneously, it ensures that at least one bit line across multiple bit lines stabilizes for a sufficient period after reaching the target voltage before performing other operations (e.g., programming, programming verification, reading, or erasure verification), avoiding reduced accuracy of related operations due to bit line voltage instability.

[0108] In some embodiments, the memory cell array includes memory cells with a storage bit width of P bits; wherein P is an integer greater than or equal to 2 and less than or equal to 4. For multi-bit memory cells, the operation process is more complex and frequent, involving multiple bit line charging processes, further amplifying the impact of bit line charging time. By optimizing the bit line charging process in different operations (e.g., programming operations, programming verification operations, reading operations, or erasure verification operations), the setup time of at least one bit line from the initial voltage to the target voltage can be shortened, effectively improving the performance of the memory device.

[0109] For example, the storage cells in the storage cell array can be MLC, TLC or QLC.

[0110] Secondly, based on a concept similar to that of memory devices, this disclosure also provides a memory system comprising: one or more memory devices as described in any of the foregoing embodiments; and a memory controller coupled to the memory devices and configured to control the memory devices. For the specific composition and functional implementation of the memory system, please refer to the preceding description. Figures 1 to 4 For the sake of brevity, the description will not be repeated here.

[0111] Thirdly, embodiments of this disclosure provide an operating method for a memory device, the method comprising: performing N voltage boosting operations during a charging phase, such that the voltage on at least one of a plurality of bit lines of the memory device rises from an initial voltage to a target voltage; wherein N is a positive integer less than a preset threshold, and / or the time interval between two adjacent voltage boosting operations is less than or equal to a first preset duration.

[0112] In some embodiments, performing N voltage boost operations during the charging phase includes: at a first moment during the first time of performing the Mth voltage boost operation during the charging phase, applying the Mth voltage pulse to at least one of the multiple bit lines; the voltage on the at least one bit line reaching the voltage of the Mth voltage pulse at a second moment during the Mth voltage boost operation; at a first moment during the (M+1)th voltage boost operation during the charging phase, applying the (M+1)th voltage pulse to at least one of the multiple bit lines; the time interval between the second moment during the Mth voltage boost operation and the first moment during the (M+1)th voltage boost operation is less than or equal to a first preset duration; wherein the voltage of the Mth voltage pulse is less than the voltage of the (M+1)th voltage pulse; and M+1 is greater than 1 and less than or equal to N.

[0113] In some implementations, reference Figure 5 N is greater than or equal to 2; N voltage boost operations are performed during the charging phase, including: at the first time t1 of the Mth voltage boost operation during the charging phase, the Mth voltage pulse is applied to at least one of the multiple bit lines; the voltage on at least one bit line reaches the voltage V of the Mth voltage pulse at the second time t2 of the Mth voltage boost operation. M During the (M+1)th voltage boost operation in the charging phase, at the first time t3, the (M+1)th voltage pulse is applied to at least one of the multiple bit lines; the time interval Δt1 between the second time t2 in the Mth voltage boost operation and the first time t3 in the (M+1)th voltage boost operation is less than or equal to a first preset duration; wherein, the voltage V of the Mth voltage pulse... M The voltage V less than the (M+1)th voltage pulse M+1 M+1 is greater than 1 and less than or equal to N.

[0114] In some embodiments, reference Figure 6 The second time t2 in the Mth voltage boost operation is the same as the first time t3 in the (M+1)th voltage boost operation, that is, the time interval between the second time t2 in the Mth voltage boost operation and the first time t3 in the (M+1)th voltage boost operation is equal to 0.

[0115] By further reducing the time interval between two adjacent voltage boosting operations to 0, the setup time of the voltage on at least one of the multiple bit lines from the initial voltage to the target voltage can be further shortened, thereby improving the speed of the programming, reading, or erasing process.

[0116] In some embodiments, the method includes: performing N voltage boosting operations on selected bit lines among a plurality of bit lines before a third time when the voltage on a selected word line among a plurality of word lines of the memory device reaches a verification voltage during a programming verification operation; wherein the voltage on the selected bit line reaches a target voltage at a second time during the Nth voltage boosting operation, and the time interval between the third time and the second time during the Nth voltage boosting operation is greater than or equal to a second preset duration.

[0117] In some embodiments, the charging phase described above can be the process of programming. Figure 3 and Figure 4 During the at least one programming verification operation performed after each of the multiple programming operations performed by the memory cell array 301 shown, the selected bit lines among the multiple bit lines are charged from the initial voltage to the target voltage.

[0118] In some embodiments, reference Figure 3 and Figure 6 With M equal to 1, N equal to 2, and the target voltage V M+1 Taking the example of the voltage V of the first voltage pulse... M That is, V1, the voltage V of the second voltage pulse. M+1 That is, V2. The operation method of the memory device includes: before the voltage on the selected word line among the multiple word lines 318 reaches the verification voltage Vverify at the third time point, performing two voltage boost operations on the selected bit line among the multiple bit lines 316; wherein, the initial voltage on the selected bit line is V... bl For example, 0V, the voltage on the selected positioning line reaches the voltage V1 of the first voltage pulse at the second moment t2 of the first voltage boost operation. V1 can be, for example, 0.3V. Simultaneously with the voltage on the selected positioning line reaching V1 ( Figure 6 At the times shown (t2 / t3), the second voltage pulse is applied to the selected positioning line. The voltage on the selected positioning line reaches the target voltage, i.e., the voltage V2 of the second voltage pulse, at the second time t4 of the second voltage boost operation. V2 can be, for example, 0.6V. At the third time ( Figure 6 The time interval Δt2 between the time shown (t5) and the second time (t4) of the second voltage boost operation is greater than or equal to the second preset duration.

[0119] The above charging stages can be used for... Figure 3 and Figure 4 When the memory cell array 301 shown is programmed, before the voltage on the selected word line reaches the programming voltage Vpgm, the selected word line coupled to the memory cell to be programmed is floated or discharged, and the non-selected word line coupled to the programming-prohibited memory cell is charged to the programming-prohibited voltage to prohibit programming.

[0120] In some embodiments, the method includes: performing N voltage boosting operations on non-selected bit lines among a plurality of bit lines during a programming operation, before a fourth time when the voltage on a selected word line among a plurality of word lines of the memory device reaches the programming voltage; wherein the voltage on the non-selected bit lines reaches the target voltage at a second time during the Nth voltage boosting operation, and the time interval between the fourth time and the second time during the Nth voltage boosting operation is greater than or equal to a second preset duration.

[0121] In some embodiments, reference Figure 3 and Figure 5 Taking M+1 equal to N as an example, the operation method of the memory device includes: during the programming operation, the voltage on the selected word line among the multiple word lines 318 reaches the programming voltage Vpgm at the fourth moment ( Figure 5 Before time t5, N voltage boosting operations are performed on the non-selected positioning lines among the multiple bit lines 316; wherein, the voltage on the non-selected positioning lines reaches the target voltage at the second time t4 of the Nth voltage boosting operation, and at the fourth time ( Figure 5 The time interval Δt2 between the time shown (t5) and the second time (t4) of the Nth voltage boost operation is greater than or equal to the second preset duration.

[0122] In some embodiments, the charging phase described above may be a phase in which the voltage on multiple bit lines is charged from 0V to 2V before the fifth moment when the voltage on the selected word line reaches the read voltage Vread during the reading process.

[0123] In some embodiments, the method includes: performing N voltage boosting operations on multiple bit lines before a fifth time when the voltage on a selected word line among multiple word lines of the memory device reaches the read voltage during a read operation; wherein the voltage on the multiple bit lines reaches the target voltage at a second time during the Nth voltage boosting operation, and the time interval between the fifth time and the second time during the Nth voltage boosting operation is greater than or equal to a second preset duration.

[0124] In some embodiments, reference Figure 3 and Figure 5 Taking M+1 equal to N as an example, the operation method of the memory device includes: during the programming operation, the voltage on the selected word line among the multiple word lines 318 reaches the fifth moment of the read voltage Vread. Figure 5 Before time t5, N voltage boosting operations are performed on multiple bit lines 316; wherein, the voltage on multiple bit lines 316 reaches the target voltage at the second time t4 of the Nth voltage boosting operation, and at the fifth time ( Figure 5 The time interval Δt2 between the time shown (t5) and the second time (t4) of the Nth voltage boost operation is greater than or equal to the second preset duration.

[0125] In some embodiments, the charging phase described above may be a phase in which multiple bit lines 316 coupled to each memory string 308 in the memory block 304 are pre-charged before the sixth moment when the voltage on a selected word line among the multiple word lines reaches the erase verification voltage during the erase verification operation performed after each erase pulse in the erase process.

[0126] In some embodiments, the method of operating the memory device includes: performing N voltage boosting operations on the multiple bit lines before a sixth time when the voltage on a selected word line among the multiple word lines of the memory device reaches the erase verification voltage during an erase operation; wherein the voltage on the multiple bit lines reaches the target voltage at a second time during the Nth voltage boosting operation, and the time interval between the sixth time and the second time during the Nth voltage boosting operation is greater than or equal to a second preset duration.

[0127] In some embodiments, reference Figure 3 and Figure 5 Taking M+1 equal to N as an example, the operation method of the memory device includes: during the erase operation, the voltage on the selected word line among the multiple word lines 318 reaches the sixth moment of the erase verification voltage ( Figure 5 Before time t5, N voltage boosting operations are performed on multiple bit lines 316; wherein, the voltage on multiple bit lines 316 reaches the target voltage at the second time t4 of the Nth voltage boosting operation, and at the sixth time ( Figure 5 The time interval Δt2 between the time shown (t5) and the second time (t4) of the Nth voltage boost operation is greater than or equal to the second preset duration.

[0128] In some embodiments, the first preset duration is shorter than the second preset duration. This ensures that the interval between multiple rise operations during the charging phase is short for at least one bit line across multiple bit lines, which helps reduce the overall operation time and overall energy consumption. Simultaneously, it ensures that at least one bit line across multiple bit lines stabilizes for a sufficient period after reaching the target voltage before performing other operations (e.g., programming, programming verification, reading, or erasure verification), avoiding reduced accuracy of related operations due to bit line voltage instability.

[0129] In some embodiments, the preset threshold value ranges from 2 to 7. More specifically, the preset threshold value can be 2, 3, 4, 5, 6, or 7.

[0130] In some embodiments, the storage cell array includes storage cells with a storage bit length of P bits; wherein P is an integer greater than or equal to 2 and less than or equal to 4.

[0131] For example, the storage cells in the storage cell array can be MLC, TLC or QLC.

[0132] Fourthly, such as Figure 9 As shown, this embodiment of the present disclosure provides a storage medium 900, which stores executable instructions 910. When the executable instructions 910 are executed, the steps of any of the operation methods described in the third aspect can be implemented.

[0133] In some specific embodiments, the storage medium may be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.; or it may be a device that includes one or any combination of the above-mentioned memory devices.

[0134] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0135] As an example, executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborative files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0136] As an example, executable instructions can be deployed to execute on a single electronic device, or on multiple electronic devices located in one location, or on multiple electronic devices distributed across multiple locations and interconnected via a communication network.

[0137] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments of this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0138] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0139] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0140] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory device, characterized in that, include: Storage cell array; Multiple bit lines, each of which is coupled to the memory cell array; as well as The peripheral circuitry, coupled to each of the bit lines, is configured as follows: During the charging phase, N voltage boost operations are performed, causing the voltage on at least one of the multiple bit lines to rise from the initial voltage to the target voltage. Wherein, N is a positive integer less than a preset threshold, and / or, the time interval between two adjacent voltage boosting operations is less than or equal to a first preset duration.

2. The memory device according to claim 1, characterized in that, N is greater than or equal to 2; the peripheral circuit is configured as follows: At the first moment of performing the Mth voltage boost operation during the charging phase, the Mth voltage pulse is applied to at least one of the multiple bit lines; the voltage on the at least one bit line reaches the voltage of the Mth voltage pulse at the second moment of the Mth voltage boost operation. In the first moment of the (M+1)th voltage boost operation during the charging phase, the (M+1)th voltage pulse is applied to at least one of the multiple bit lines; the time interval between the second moment of the Mth voltage boost operation and the first moment of the (M+1)th voltage boost operation is less than or equal to the first preset duration. Wherein, the voltage of the Mth voltage pulse is less than the voltage of the (M+1)th voltage pulse; M+1 is greater than 1 and less than or equal to N.

3. The memory device according to claim 1, characterized in that, The memory device further includes multiple word lines, each word line being coupled to the memory cell array and the peripheral circuitry; the peripheral circuitry is configured as follows: During the programming verification operation, before the voltage on the selected word line among the multiple word lines reaches the verification voltage at the third moment, the N voltage boosting operations are performed on the selected bit line among the multiple bit lines; wherein the voltage on the selected bit line reaches the target voltage at the second moment of the Nth voltage boosting operation, and the time interval between the third moment and the second moment of the Nth voltage boosting operation is greater than or equal to a second preset duration.

4. The memory device according to claim 1, characterized in that, The memory device further includes multiple word lines, each word line being coupled to the memory cell array and the peripheral circuitry; the peripheral circuitry is configured as follows: During the programming operation, before the voltage on the selected word line among the multiple word lines reaches the programming voltage at the fourth moment, the N voltage boosting operations are performed on the non-selected bit lines among the multiple bit lines; wherein the voltage on the non-selected bit lines reaches the target voltage at the second moment of the Nth voltage boosting operation, and the time interval between the fourth moment and the second moment of the Nth voltage boosting operation is greater than or equal to a second preset duration.

5. The memory device according to claim 1, characterized in that, The memory device further includes multiple word lines; the peripheral circuitry is configured as follows: During the read operation, before the voltage on the selected word line among the multiple word lines reaches the read voltage at the fifth moment, the N voltage boosting operations are performed on the multiple bit lines; wherein the voltage on the multiple bit lines reaches the target voltage at the second moment of the Nth voltage boosting operation, and the time interval between the fifth moment and the second moment of the Nth voltage boosting operation is greater than or equal to a second preset duration.

6. The memory device according to claim 1, characterized in that, The memory device further includes multiple word lines, each word line being coupled to the memory cell array and the peripheral circuitry; the peripheral circuitry is configured as follows: During the erase operation, before the voltage on the selected word line among the multiple word lines reaches the erase verification voltage at the sixth moment, the Nth voltage boost operation is performed on the multiple bit lines; wherein the voltage on the multiple bit lines reaches the target voltage at the second moment of the Nth voltage boost operation, and the time interval between the sixth moment and the second moment of the Nth voltage boost operation is greater than or equal to a second preset duration.

7. The memory device according to any one of claims 3 to 6, characterized in that, The first preset duration is less than the second preset duration.

8. The memory device according to claim 1, characterized in that, The preset threshold value ranges from 2 to 7.

9. The memory device according to claim 1, characterized in that, The storage cell array includes storage cells with a storage bit length of P bits; wherein P is an integer greater than or equal to 2 and less than or equal to 4.

10. A memory system, characterized in that, The memory system includes: one or more memory devices as described in any one of claims 1 to 9; and A memory controller coupled to the memory device and configured to control the memory device.

11. A method of operating a memory device, characterized in that, The method includes: During the charging phase, N voltage boosting operations are performed, causing the voltage on at least one of the multiple bit lines of the memory device to rise from the initial voltage to the target voltage. Wherein, N is a positive integer less than a preset threshold, and / or, the time interval between two adjacent voltage boosting operations is less than or equal to a first preset duration.

12. The operating method according to claim 11, characterized in that, The process of performing N voltage boost operations during the charging phase includes: At the first moment of performing the Mth voltage boost operation during the charging phase, the Mth voltage pulse is applied to at least one of the multiple bit lines; the voltage on the at least one bit line reaches the voltage of the Mth voltage pulse at the second moment of the Mth voltage boost operation. In the first moment of the (M+1)th voltage boost operation during the charging phase, the (M+1)th voltage pulse is applied to at least one of the multiple bit lines; the time interval between the second moment of the Mth voltage boost operation and the first moment of the (M+1)th voltage boost operation is less than or equal to the first preset duration. Wherein, the voltage of the Mth voltage pulse is less than the voltage of the (M+1)th voltage pulse; M+1 is greater than 1 and less than or equal to N.

13. The operating method according to claim 11, characterized in that, The method includes: During programming operations, before the voltage on a selected word line among the multiple word lines of the memory device reaches the verification voltage at a third time, the N voltage boosting operations are performed on the selected bit line among the multiple bit lines; wherein the voltage on the selected bit line reaches the target voltage at a second time of the Nth voltage boosting operation, and the time interval between the third time and the second time of the Nth voltage boosting operation is greater than or equal to a second preset duration.

14. The operating method according to claim 11, characterized in that, The method includes: During programming operations, before the voltage on a selected word line among the multiple word lines of the memory device reaches the programming voltage at a fourth time, the N voltage boosting operations are performed on the non-selected bit lines among the multiple bit lines; wherein the voltage on the non-selected bit lines reaches the target voltage at a second time of the Nth voltage boosting operation, and the time interval between the fourth time and the second time of the Nth voltage boosting operation is greater than or equal to a second preset duration.

15. The operating method according to claim 11, characterized in that, The method includes: During a read operation, before the voltage on a selected word line among the multiple word lines of the memory device reaches the read voltage at a fifth time, the N voltage boosting operations are performed on the multiple bit lines; wherein the voltage on the multiple bit lines reaches the target voltage at a second time of the Nth voltage boosting operation, and the time interval between the fifth time and the second time of the Nth voltage boosting operation is greater than or equal to a second preset duration.

16. The operating method according to claim 11, characterized in that, The method includes: During the erase operation, before the voltage on a selected word line among the multiple word lines of the memory device reaches the erase verification voltage at the sixth moment, the N voltage boosting operations are performed on the multiple bit lines; wherein the voltage on the multiple bit lines reaches the target voltage at the second moment of the Nth voltage boosting operation, and the time interval between the sixth moment and the second moment of the Nth voltage boosting operation is greater than or equal to a second preset duration.

17. The operating method according to any one of claims 13 to 16, characterized in that, The first preset duration is less than the second preset duration.

18. The operating method according to claim 11, characterized in that, The preset threshold value ranges from 2 to 7.

19. The operating method according to claim 11, characterized in that, The storage cell array includes storage cells with a storage bit length of P bits; wherein P is an integer greater than or equal to 2 and less than or equal to 4.

20. A storage medium, characterized in that, The storage medium stores executable instructions, which, when executed, can implement the steps of the operation method according to any one of claims 11 to 19.

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