EFLASH data prefetching circuit

Abstract

The invention provides an EFLASH data prefetching circuit. The EFLASH data prefetching circuit comprises a basic state and initial state module, an error processing branch module, a maintaining module, a normal response sending module, a judging module and a data receiving module. According to the method, when an ahb read request is received, firstly, a thread signal of an ahb bus is pulled down, the ahb bus waits, then flash data are read according to an address sequence, multiple address data are continuously read at a time and stored in a data buffer area, then the thread signal of the ahb bus is pulled up, the bus is released, and therefore the next read request of the ahb bus is obtained. According to the method and the device, the data can be directly read out from the data buffer area if the read request hits the data buffer area, and the data can be directly taken away if the read request hits the data buffer area, so that the aims of reading without bubbles and improving the reading efficiency are fulfilled.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics and integrated circuit technology, and particularly relates to an EFLASH data prefetch circuit. Background Technology

[0002] In chip design, it is common for the CPU to read data from flash memory via the AHB bus. However, the clock speed of the AHB bus is usually very fast, while the clock speed of the flash memory is relatively slow. When an AHB read request arrives, the flash memory starts reading data, and the AHB needs to wait until the flash memory has read the data before it can send the next request. This creates timing bubbles and reduces the efficiency of reading data. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention provides an EFLASH data prefetch circuit, which avoids timing bubbles when the CPU reads the flash memory via the AHB bus, thereby improving read efficiency.

[0004] An EFLASH data prefetching circuit includes a basic state and initial state module, an error handling branch module, a maintenance module, a normal response transmission module, a judgment module, and a received data module. The basic state and initial state module is connected to the error handling branch module via wires; the error handling branch module is connected to the maintenance module via wires; the maintenance module is connected to the normal response transmission module via wires; the normal response transmission module is connected to the judgment module via wires; and the judgment module is connected to the received data module via wires.

[0005] Compared with the prior art, the beneficial effects of the present invention are as follows: In this invention, upon receiving a read request from the AHB bus, the Hready signal of the AHB bus is first pulled low to allow the AHB bus to wait. Then, the flash data is read sequentially according to address, with multiple address data read out continuously at one time and stored in the data buffer. Next, the Hready signal of the AHB bus is pulled high to release the bus. In this way, the next read request will directly read data from the data buffer. If the read request hits the data buffer, the data can be retrieved directly. This achieves bubble-free reading and improves reading efficiency. Attached Figure Description

[0006] Figure 1 This is a flowchart of the process of the present invention.

[0007] In the picture: 1. Basic state and initial state module; 2. Error handling branch module; 3. Maintenance module; 4. Send normal response module; 5. Judgment module; 6. Received data module. Detailed Implementation

[0008] The present invention will now be described in detail with reference to the accompanying drawings, as shown below. Figure 1 As shown, an EFLASH data prefetching circuit includes a basic state and initial state module 1, an error handling branch module 2, a maintenance module 3, a normal response transmission module 4, a judgment module 5, and a received data module 6. The basic state and initial state module 1 is connected to the error handling branch module 2 via wires; the error handling branch module 2 is connected to the maintenance module 3 via wires; the maintenance module 3 is connected to the normal response transmission module 4 via wires; the normal response transmission module 4 is connected to the judgment module 5 via wires; and the judgment module 5 is connected to the received data module 6 via wires.

[0009] In this embodiment, specifically, the basic state and initial state module 1 is electrically connected to the maintenance module 3.

[0010] In this implementation scheme, specifically, the basic state and initial state module 1 is also electrically connected to the normal response sending module 4.

[0011] In this implementation scheme, specifically, the basic state and initial state module 1 is electrically connected to the judgment module 5. Working principle

[0012] In this invention, conditions such as request type (correct / incorrect), data buffer hit status, and Flash access status are switched between AHBS_IDLE (idle) → AHBS_REQ (request initiated) → AHBS_WAIT (waiting for Flash data) → AHBS_RSP (response sent) and error handling branches (AHBS_ERR_FST / AHBS_ERR_SND) to achieve orderly processing of AHB bus transactions, ensuring data interaction and error feedback between slave devices and bus master devices. The initial state is AHBS_IDLE. After receiving a correct AHB request in this state, it enters the AHBS_REQ state. After entering the AHBS_REQ state, if the flash memory is not currently active, it enters the AHBS-WAIT state and begins reading data from the flash memory. Upon receiving data from the flash memory, it enters the AHBS_RSP state. After entering the AHBS_RSP state, the bus is released, and the bus continues to send read requests. When a read request hits the buffer, the data can be read directly. If read requests are continuously sent, data can be read continuously, thus achieving bubble-free data reading and improving data reading efficiency.

[0013] Any technical solution that achieves the above-mentioned technical effects by utilizing the technical solutions described in this invention, or by designing similar technical solutions by those skilled in the art under the inspiration of the technical solutions described in this invention, falls within the protection scope of this invention.

Claims

1. An EFLASH data prefetch circuit, characterized in that, The EFLASH data prefetching circuit includes a basic state and initial state module (1), an error handling branch module (2), a maintenance module (3), a normal response sending module (4), a judgment module (5), and a data receiving module (6). The basic state and initial state module (1) is connected to the error handling branch module (2) via a wire; the error handling branch module (2) is connected to the maintenance module (3) via a wire; and the maintenance module (3) is connected to the normal response sending module (4) via a wire.

2. The EFLASH data prefetch circuit as described in claim 1, characterized in that, The above-mentioned normal response sending module (4) and wire connection judgment module (5).

3. The EFLASH data prefetch circuit as described in claim 1, characterized in that, The judgment module (5) is connected to the received data module (6) via a wire.

4. The EFLASH data prefetch circuit as described in claim 1, characterized in that, The basic state and initial state module (1) is electrically connected to the maintenance module (3).

5. The EFLASH data prefetch circuit as described in claim 1, characterized in that, The basic state and initial state module (1) is also electrically connected to the normal response module (4).

6. The EFLASH data prefetch circuit as described in claim 1, characterized in that, The basic state and initial state module (1) and the electrical connection judgment module (5) are described.

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