Memory device and operating method thereof

Abstract

The invention discloses a memory device and an operating method thereof. The operation method for retrying to read the data in the memory device comprises the following steps of: applying a first reading voltage to the memory device, and calculating a first absolute difference value between the number of first bit values and the number of second bit values, which are obtained corresponding to the first reading voltage, when a reading error occurs; applying a second read voltage to the memory device, and calculating a second absolute difference between the number of the first bit values and the number of the second bit values obtained corresponding to the second read voltage when a read error occurs; and comparing the second absolute difference value with the first absolute difference value, and determining the next retry reading voltage according to the relationship between the second absolute difference value and the first absolute difference value until the read data is decoded through an error correction code (ECC).

Description

TECHNICAL FIELD

[0001] The present disclosure is directed to semiconductor devices, such as for retrying reading data in a memory semiconductor device. BACKGROUND

[0002] Semiconductor devices, such as NAND flash devices, have physical characteristics that cause the bit values of stored data to shift on a threshold voltage distribution when data is saved, so data read using a normal read voltage can not pass error correction code (ECC) decoding. Constantly retrying reading data using different read voltages to attempt to pass ECC decoding causes reduced reading efficiency and reading delay. SUMMARY

[0003] The present disclosure describes methods, devices, systems, and techniques for reducing the number of retry read operations in a non-volatile memory device, such as a NAND flash device.

[0004] A first aspect of the present disclosure features a method of operation for retrying reading data in a memory device, the method of operation comprising: applying a first read voltage to the memory device, calculating a first absolute difference between a number of first bit values and a number of second bit values resulting from the first read voltage; applying a second read voltage to the memory device, the second read voltage having a first voltage difference from the first read voltage in a first direction, calculating a second absolute difference between the number of first bit values and the number of second bit values resulting from the second read voltage; and comparing the second absolute difference with the first absolute difference. When the second absolute difference is less than the first absolute difference, sequentially increasing the first voltage difference from the second read voltage in the first direction to obtain at least one retry read voltage, and applying the at least one retry read voltage to the memory device for reading until data read by one of the at least one retry read voltage passes error correction code (ECC) decoding. When the second absolute difference is greater than the first absolute difference, sequentially decreasing the first voltage difference from the first read voltage in a second direction opposite to the first direction to obtain at least one retry read voltage, and applying the at least one retry read voltage to the memory device for reading until data read by one of the at least one retry read voltage passes ECC decoding.

[0005] In some implementations, at least two absolute difference values between the number of first bit values and the number of second bit values obtained at a plurality of retry read voltages are calculated during the sequential increase of the first voltage difference to the second read voltage in the first direction to obtain at least one retry read voltage. When the at least two absolute difference values increase, the sequential decrease of a second voltage difference in the second direction to a previous retry read voltage is performed until data read at one of the at least one retry read voltage is decoded by the error correction code. The second voltage difference is less than the first voltage difference.

[0006] In some implementations, at least two absolute difference values between the number of first bit values and the number of second bit values obtained at a plurality of retry read voltages are calculated during the sequential decrease of the first voltage difference to the first read voltage in the second direction to obtain at least one retry read voltage. When the at least two absolute difference values increase, the sequential increase of a second voltage difference in the first direction to a previous retry read voltage is performed until data read at one of the at least one retry read voltage is decoded by the error correction code. The second voltage difference is less than the first voltage difference.

[0007] In some implementations, the second voltage difference is one-half or one-quarter of the first voltage difference.

[0008] In some implementations, a plurality of absolute difference value slopes between a plurality of absolute difference values between the number of first bit values and the number of second bit values obtained at a plurality of retry read voltages are calculated during the sequential increase of the first voltage difference to the second read voltage in the first direction to obtain at least one retry read voltage. When the plurality of absolute difference value slopes of the plurality of absolute difference values corresponding decrease, a read to the memory device is performed in the first direction to a previous retry read voltage with a sequential increase of a third voltage difference. When the plurality of absolute difference value slopes of the plurality of absolute difference values corresponding increase, a read to the memory device is performed in the first direction to a previous retry read voltage with a sequential increase of a fourth voltage difference. The third voltage difference is greater than the first voltage difference and the fourth voltage difference is less than the first voltage difference.

[0009] In some implementations, a plurality of absolute difference value slopes between a plurality of absolute difference values between the number of first bit values and the number of second bit values obtained at a plurality of retry read voltages are calculated during the sequential decrease of the first voltage difference to the first read voltage in the second direction to obtain at least one retry read voltage. When the plurality of absolute difference value slopes of the plurality of absolute difference values corresponding decrease, a read to the memory device is performed in the second direction to a previous retry read voltage with a sequential decrease of a third voltage difference. When the plurality of absolute difference value slopes of the plurality of absolute difference values corresponding increase, a read to the memory device is performed in the second direction to a previous retry read voltage with a sequential decrease of a fourth voltage difference. The third voltage difference is greater than the first voltage difference and the fourth voltage is less than the third voltage.

[0010] In some embodiments, the absolute voltage difference between the first voltage difference and the third voltage difference or the fourth voltage difference corresponds to a change in the plurality of absolute difference slopes.

[0011] A second aspect of the present disclosure features a method of operating for retrying reading data from a memory device, comprising: performing a read operation on the memory device, the read operation comprising the steps of: applying a first hard-decoded read voltage to the memory device, calculating a first absolute difference value corresponding to a number of first bit values and a number of second bit values obtained from the first hard-decoded read voltage; applying a second hard-decoded read voltage to the memory device, the second hard-decoded read voltage having a first voltage difference from the first hard-decoded read voltage in a first direction, calculating a second absolute difference value corresponding to the number of first bit values and the number of second bit values obtained from the second hard-decoded read voltage; and comparing the second absolute difference value with the first absolute difference value. When the second absolute difference value is less than the first absolute difference value, sequentially increasing the first voltage difference in the first direction from the second hard-decoded read voltage in a predetermined order to obtain at least one hard-decoded read voltage, and performing a read operation on the memory device using the at least one hard-decoded read voltage. When the second absolute difference value is greater than the first absolute difference value, sequentially decreasing the first voltage difference in a second direction opposite to the first direction from the first hard-decoded read voltage in the predetermined order to obtain at least one hard-decoded read voltage, and performing a read operation on the memory device using the at least one hard-decoded read voltage. When a predetermined order of the read operation is reached and the read data is still unable to be decoded by an error correction code, performing a soft decode operation on the memory device, the soft decode operation comprising the steps of: using a hard-decoded read voltage corresponding to a smallest absolute difference value of the number of first bit values and the number of second bit values among the at least one hard-decoded read voltage as a first soft-decoded read voltage; generating a second soft-decoded read voltage and a third soft-decoded read voltage based on the first soft-decoded read voltage; calculating log-likelihood ratios (LLRs) using the first soft-decoded read voltage, the second soft-decoded read voltage, and the third soft-decoded read voltage and performing a soft decode; and repeating the soft decode operation until the read data is decoded by the error correction code.

[0012] In some embodiments, during the sequentially increasing the first voltage difference in the first direction from the second hard-decoded read voltage in the predetermined order to obtain at least one hard-decoded read voltage, at least two absolute difference values of the number of first bit values and the number of second bit values obtained from the at least one hard-decoded read voltage are calculated. When the at least two absolute difference values increase, a read operation is performed on the memory device in the second direction sequentially decreasing a second voltage difference from a previous hard-decoded read voltage. The second voltage difference is smaller than the first voltage difference.

[0013] In some embodiments, at least two absolute difference values between the number of first bit values and the number of second bit values obtained at the at least one hard-decision read voltage are calculated during the sequentially reducing the first voltage difference in the preset order to obtain the at least one hard-decision read voltage from the first hard-decision read voltage in the second direction. When the at least two absolute difference values increase, the memory device is read in the first direction sequentially increasing a second voltage difference to a previous hard-decision read voltage. The second voltage difference is smaller than the first voltage difference.

[0014] In some embodiments, the second voltage difference is one-half or one-fourth of the first voltage difference.

[0015] In some embodiments, a corresponding plurality of absolute difference value slopes between a plurality of absolute difference values between the number of first bit values and the number of second bit values obtained at the plurality of hard-decision read voltages are calculated during the sequentially increasing the first voltage difference in the preset order to obtain the at least one hard-decision read voltage from the second hard-decision read voltage in the first direction. When the plurality of difference slopes of the corresponding plurality of absolute difference values decrease, the memory device is read in the first direction sequentially increasing a third voltage difference to a previous hard-decision read voltage. When the plurality of difference slopes of the corresponding plurality of absolute difference values increase, the memory device is read in the first direction sequentially increasing a fourth voltage difference to a previous hard-decision read voltage. The third voltage difference is greater than the first voltage difference, and the fourth voltage is smaller than the third voltage.

[0016] In some embodiments, a corresponding plurality of absolute difference value slopes between a plurality of absolute difference values between the number of first bit values and the number of second bit values obtained at the plurality of hard-decision read voltages are calculated during the sequentially reducing the first voltage difference in the preset order to obtain the at least one hard-decision from the first hard-decision read voltage in the second direction. When the plurality of difference slopes of the corresponding plurality of absolute difference values decrease, the memory device is read in the second direction sequentially decreasing a third voltage difference to a previous hard-decision read voltage. When the plurality of difference slopes of the corresponding plurality of absolute difference values increase, the memory device is read in the second direction sequentially decreasing a fourth voltage difference to a previous hard-decision read voltage. The third voltage difference is greater than the first voltage difference, and the fourth voltage is smaller than the third voltage.

[0017] In some embodiments, an absolute voltage difference between the first voltage difference and the third voltage difference or the fourth voltage difference corresponds to a change in the plurality of absolute difference value slopes.

[0018] A third aspect of the present disclosure features a memory device, comprising: a memory array; and a controller coupled to the memory array. The controller comprises: a processor; an error correction code (ECC) module coupled to the processor; and a read failure module coupled to the processor and the ECC module. The controller performs a read operation on a read of the memory array, and executes the following procedures: applying, by the controller, a first hard-decoding read voltage to the memory array to read data, and when the read data fails to pass an ECC decoding by the ECC module, the read failure module calculates and records a first absolute difference between a number of first bit values and a number of second bit values resulting from the first hard-decoding read voltage; applying, by the controller, a second hard-decoding read voltage to the memory array to read data, the second hard-decoding read voltage having a first voltage difference from the first hard-decoding read voltage in a first direction, and when the read data fails to pass the ECC decoding by the ECC module, the read failure module calculates and records a second absolute difference between the number of first bit values and the number of second bit values resulting from the second hard-decoding read voltage; and the processor compares the second absolute difference with the first absolute difference. When the second absolute difference is less than the first absolute difference, the controller sequentially increases the first voltage difference from the second hard-decoding read voltage in the first direction in a predetermined order to sequentially generate at least one hard-decoding read voltage to perform a read operation on the memory array until the read data passes the ECC decoding by the ECC module. When the second absolute difference is greater than the first absolute difference, the controller sequentially decreases the first voltage difference from the first hard-decoding read voltage in a second direction opposite to the first direction in the predetermined order to sequentially generate at least one hard-decoding read voltage to perform a read operation on the memory array until the read data passes the ECC decoding by the ECC module.

[0019] In some embodiments, when the read data still fails to pass the ECC decoding by the ECC module after reaching a predetermined order of the read operation, the controller performs a soft-decoding operation on the read of the memory array, and executes the following procedures: the processor uses a hard-decoding read voltage corresponding to a smallest absolute difference between the number of first bit values and the number of second bit values among the at least one hard-decoding read voltage recorded by the read failure module as a first soft-decoding read voltage; the processor generates a second soft-decoding read voltage and a third soft-decoding read voltage based on the first soft-decoding read voltage; the ECC module calculates log-likelihood ratios (LLRs) using the first, second, and third soft-decoding read voltages and performs a soft-decoding; and the controller repeats the soft-decoding operation until the read data passes the ECC decoding by the ECC module.

[0020] In some embodiments, during the reading of the memory array by the controller sequentially in the first direction with the second hard-decoded read voltage with the first voltage difference in a preset order, the read failure module calculates at least two absolute difference values between the number of first bit values and the number of second bit values obtained at least one hard-decoded read voltage. When the at least two absolute difference values increase, the controller sequentially reads the memory array in the second direction with the previous hard-decoded read voltage with the second voltage difference. The second voltage difference is smaller than the first voltage difference.

[0021] In some embodiments, during the reading of the memory array by the controller sequentially in the second direction with the first hard-decoded read voltage with the first voltage difference in a preset order, the read failure module calculates at least two absolute difference values between the number of first bit values and the number of second bit values obtained at least one hard-decoded read voltage. When the at least two absolute difference values increase, the controller sequentially reads the memory array in the first direction with the previous hard-decoded read voltage with the second voltage difference. The second voltage difference is smaller than the first voltage difference.

[0022] In some embodiments, during the reading of the memory array by the controller sequentially in the first direction with the second hard-decoded read voltage with the first voltage difference in a preset order, the read failure module calculates a plurality of absolute difference values between the number of first bit values and the number of second bit values obtained at a plurality of hard-decoded read voltages. When a plurality of absolute difference slopes between the plurality of absolute difference values decreases, the controller sequentially reads the memory array in the first direction with the previous hard-decoded read voltage with a third voltage difference. When the plurality of absolute difference slopes between the plurality of absolute difference values increases, the controller sequentially reads the memory array in the first direction with the previous hard-decoded read voltage with a fourth voltage difference. The third voltage difference is greater than the first voltage difference, the fourth voltage is smaller than the first voltage difference, and an absolute voltage difference between the first voltage difference and the third voltage difference or the fourth voltage difference corresponds to a change of the plurality of absolute difference slopes.

[0023] In some embodiments, during the reading of the memory array by the controller in the second direction with the first hard-decoded read voltage sequentially reduced by the first voltage difference in the preset order, the read failure module calculates a plurality of absolute difference values slopes between a plurality of absolute difference values between the number of first bit values and the number of second bit values obtained among the plurality of hard-decoded read voltages. When the plurality of absolute difference values slopes between the plurality of absolute difference values decreases, the controller reads the memory device in the second direction with the previous hard-decoded read voltage sequentially reduced by a third voltage difference. When the plurality of absolute difference values slopes between the plurality of absolute difference values increases, the controller reads the memory array in the second direction with the previous hard-decoded read voltage sequentially reduced by a fourth voltage difference. The third voltage difference is greater than the first voltage difference, the fourth voltage difference is less than the first voltage difference, and an absolute voltage difference between the first voltage difference and the third voltage difference or the fourth voltage difference corresponds to a change in the plurality of absolute difference values slopes.

[0024] Embodiments of the described techniques include methods, systems, circuits, computer program products, and computer-readable media. In one example, a method can include the actions described above. In another example, a computer program product is adapted to be implemented in a non-transitory machine-readable medium that stores instructions executable by one or more processors. The instructions are to cause the one or more processors to perform the actions described above. A computer-readable medium stores instructions. The instructions are to cause one or more processors to perform the actions described above when executed by the one or more processors.

[0025] For a better understanding of the above-described and other aspects and embodiments of the present disclosure, reference is made to the following detailed description and to the accompanying drawings that form a part of this disclosure. Other features, aspects, and advantages will become apparent from the description, the drawings, and the claims. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 A schematic diagram illustrating an example of a system in accordance with one or more embodiments of the present disclosure.

[0027] Figure 2 A schematic diagram illustrating encoding and decoding of an example ECC module in accordance with one or more embodiments of the present disclosure.

[0028] Figure 3 A schematic diagram illustrating a deviation of a threshold voltage distribution of user data and a retry read in accordance with one or more embodiments of the present disclosure.

[0029] Figure 4A flowchart illustrating a hard-decoding procedure for ECC according to one or more embodiments of the application is shown.

[0030] Figure 5 A diagram illustrating a threshold voltage distribution of user data according to one or more embodiments of the application is shown.

[0031] Figure 6 A diagram illustrating a bit value number difference distribution of user data according to one or more embodiments of the application is shown.

[0032] Figure 7 A flowchart illustrating a soft-decoding procedure for ECC according to one or more embodiments of the application is shown.

[0033] Figure 8 A diagram illustrating a threshold voltage distribution of user data for a soft-decoding procedure according to one or more embodiments of the application is shown. Figure 7

[0034] Figure 9 A flowchart illustrating a hard-decoding procedure for ECC with read failure error handling according to one or more embodiments of the application is shown.

[0035] Figure 10 A diagram illustrating a threshold voltage distribution of user data for a hard-decoding procedure according to one or more embodiments of the application is shown. Figure 9

[0036] A flowchart illustrating a retry read voltage setting procedure for ECC with read failure error handling according to one or more embodiments of the application is shown. Figure 11A Figure 11B A diagram illustrating a threshold voltage distribution of user data for a retry voltage setting procedure according to one or more embodiments of the application is shown.

[0037] Figure 12 Figure 13 A flowchart illustrating a soft-decoding procedure for ECC with read failure error handling according to one or more embodiments of the application is shown. Figure 11A Figure 11B A diagram illustrating a threshold voltage distribution of user data for a soft-decoding procedure according to one or more embodiments of the application is shown.

[0038] Figure 14

[0039] Figure 15 A diagram illustrating a threshold voltage distribution of user data for a soft-decoding procedure according to one or more embodiments of the application is shown. Figure 14 Like reference numbers or names in the various drawings indicate like elements. It is also to be understood that the various illustrative embodiments shown in the figures are only examples and that other embodiments can be used.

[0040] Legend for the Figures:

[0041]

[0042] ​​​​​​100: system

[0043] 110: host

[0044] 120: memory device

[0045] 121: NAND flash memory

[0046] 131: NAND flash memory controller

[0047] 132: SRAM

[0048] 133: processor

[0049] 134, 200: ECC module

[0050] 135: read failure module

[0051] 136: host interface

[0052] 137: NAND flash memory interface

[0053] 200a, 241: encode

[0054] 200b, 240: decode

[0055] 242: randomizer

[0056] 300, 500, 800, 1000, 1200, 1300, 1500: threshold voltage distribution

[0057] 300a, 300b, 300c, 502, 802, 1000a, 1000b, 1000c, 1000d, 1202,

[0058] 1302, 1500a: threshold voltage distribution graph

[0059] 400, 700, 900, 1100, 1400: program

[0060] 501, 602, 1201, 1301, 1500b: data table

[0061] 600: bit number difference distribution

[0062] 601: bit number difference distribution graph

[0063] 801, 1501: predefined retry read data table

[0064] S401~S406, S701~S711, S901~S914, S1101~S1113,

[0065] S1401~S1417: step DETAILED DESCRIPTION

[0066] Embodiments of the present disclosure provide techniques for non-volatile memory devices, such as NAND flash devices, to retry read data. These techniques ensure that the number of retry read operations in the memory device is reduced. Instead, these techniques enable the memory device to reduce the number of retry read operations by determining the direction of the lower or lowest number of error bits, so that the read data can successfully pass ECC decoding, increasing the chance of data error bits being corrected, achieving higher read operation performance.

[0067] For example, the absolute difference between the number of first bit values and the number of second bit values obtained from comparing the number of read errors is compared, and the next read voltage is determined based on the relationship between the two, so that the read data passes ECC decoding, rather than repeatedly reading using a predetermined retry read voltage, to reduce the number of retry read operations and increase the chance of read data successfully passing ECC decoding.

[0068] These techniques can be applied to different types of semiconductor devices, such as non-volatile memory devices, such as NAND flash. This technique can also be applied to different memory types, such as single-level cell (SLC) devices, multi-level cell (MLC) devices such as 2-level cell devices, triple-level cell (TLC) devices, quad-level cell (QLC) devices, or penta-level cell (PLC) devices. Additionally and alternatively, the techniques can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid-state drives (SSD), embedded systems, or others. For the purpose of illustration, in the present disclosure, memory devices are described as an example of semiconductor devices.

[0069] Figure 1A schematic diagram illustrating an example of a system 100 in accordance with one or more embodiments of the present disclosure is shown. The system 100 includes a host 110 and a memory device 120. The memory device 120 includes a NAND flash controller 131 and a NAND flash 121. The NAND flash controller 131 includes a host interface 136, an SRAM 132, a processor 133, an ECC module 134, a read failure module 135, and a NAND flash interface 137. In some implementations, the NAND flash 121 can include a plurality of memory blocks coupled to the NAND flash controller 131. The NAND flash 121 can be a two-dimensional memory having two-dimensional (2D) memory blocks. The NAND flash 121 can also be a three-dimensional memory having three-dimensional (3D) memory blocks. The NAND flash 121 can be a semiconductor device and formed on a semiconductor substrate (e.g., a silicon wafer).

[0070] The host 110 can include at least one processor and at least one memory coupled to the at least one processor and storing program instructions for execution by the at least one processor to implement one or more corresponding operations.

[0071] In some implementations, the memory device 120 is a storage device. For example, the memory device 120 can be an embedded Multi-Media Card (eMMC), a Secure Digital (SD) card, a Solid State Drive (SSD), or some other suitable memory. In some implementations, the memory device 120 is a client device coupled to the host 110 through the host interface 136.

[0072] The NAND flash controller 131 is a general-purpose microprocessor or a special-purpose microcontroller. In some implementations, the NAND flash controller 131 is a memory controller for the memory device 120. In the following paragraphs in accordance with various implementations, the NAND flash controller 131 is described as a memory controller in a number of techniques. However, the techniques described in the following paragraphs are also applicable in implementations in which the NAND flash controller 131 is other types of controllers different from memory controllers.

[0073] The processor 133 is configured to execute instructions and process data. The instructions include firmware instructions and / or other program instructions stored in secondary storage as firmware code and / or other program code. The data includes program data or other suitable data corresponding to the firmware and / or other programs executed by the processor. In some implementations, the processor 133 is a general-purpose microprocessor or a special-purpose microcontroller.

[0074] The processor 133 accesses instructions and data from the SRAM 132. For example, in some implementations, when the memory device 120 is an eMMC, an SD card, or a smart watch, the SRAM 132 can serve as the internal memory of these devices.

[0075] In some implementations, SRAM 132 is a cache memory included in NAND flash controller 131, as shown. SRAM 132 stores instructions corresponding to instructions executed by processor 133 and / or data required by processor 133 at runtime. NAND flash controller 131 transfers instruction codes and / or data from NAND flash 121 to SRAM 132 through NAND flash interface 137. Figure 1

[0076] In some embodiments, NAND flash 121 is a non-volatile memory or some other suitable non-volatile storage device used to store instructions and / or data for long periods of time. NAND flash 121 can include one or more memory chips. Corresponding to NAND flash 121 and NAND flash controller 131, memory device 120 is a flash memory device, such as a flash memory card. For example, in some embodiments, when memory device 120 is an eMMC or an SD card, NAND flash 121 serves as its memory. In some cases, memory device 120 can not include a device controller, and NAND flash 121 can communicate directly with host 110.

[0077] NAND flash 121 can have an array of memory cells that can include a plurality of memory cells. The memory cells can be coupled in series to a string of word lines, and to a row of bit lines. Each memory cell can include at least one memory transistor to serve as a storage element to store data. The memory transistor can include a silicon-oxide-nitride-oxide-silicon (SONOS) transistor, a floating gate transistor, a nitride read only memory (NROM) transistor, or any suitable non-volatile memory metal-oxide semiconductor (MOS) device that can store charge.

[0078] Memory device 120 can include NAND flash interface 137 and host interface 136 as data input / output circuitry, and can have a plurality of pins for coupling to external devices. These pins can include SI / SIOO for serial data input / serial data input and output, SO / SIOI for serial data output / serial data input and output, SIO2 for serial data input or output, SIO3 for serial data input or output, RESET# for hardware reset pin active low, CS# for chip select, and R / B# pin for indicating the ready or busy status of memory device 100. Data input / output circuitry 150 can also include one or more other pins, such as WP# for write protect active low and / or Hold# for holding input signals.

[0079] ​In some embodiments, at a write operation, the memory device 120 receives a write command (or write instruction) through the NAND flash controller 131, for example, according to the ONFI protocol, the SPI protocol, or the QPI protocol. The write instruction can be transmitted using SDR or DDR. In some embodiments, at a write operation, after the NAND flash controller 131 receives user data from the host 110 through the host interface 136, the processor 133 enables the ECC module 134 to randomize the number of bit values (e.g., bit values of 1 and bit values of 0) of the user data and generate ECC parity. The user data processed as described above is then stored to the NAND flash 121 through the NAND flash interface 137. Further description of the ECC module 134 is described below with reference to Figure 2 .

[0080] Figure 2 A schematic diagram of encoding 200a and decoding 200b of an example ECC module 200 according to one or more embodiments of the present disclosure is shown. The ECC module 200 is similar to the ECC module 134 of Figure 1 . The ECC module 200 is used to perform the function of error correction code (ECC), including decoding 240, encoding 241, and a randomizer 242. The randomizer 242 is used to randomize the number of bit values of the user data, that is, to make the number of bit values of 0 and 1 in the user data as equal as possible (e.g., the number of 0s is slightly equal to the number of Is). As shown in the encoding 200a, after the user data is encoded by the ECC module 200 using LDPC (Low-Density Parity-Check code) or BCH (Bose-Chaudhuri-Hocquenghem), the randomized user data and ECC parity are generated and stored in a memory (e.g., stored in the NAND flash 121 of Figure 1 ). The ECC parity is used as a basis when the stored user data is decoded using ECC. As shown in the decoding 200b, at the ECC decoding, the ECC module 200 decodes using LDPC or BCH based on the read user data and the ECC parity (e.g., read from the NAND flash 121 of Figure 1 ), where when there are error bits in the read data, the ECC module 200 can correct the error bits based on the read user data and the ECC parity to obtain the original user data. As described above, the ECC module 200 can protect the user data by encoding and decoding the user data using ECC.

[0081] Referring back to Figure 1 In some embodiments, at the time of a read operation, the memory device 120 receives a read command (or read instruction) through the NAND flash controller 131, for example, according to the SPI protocol or the QPI protocol. The read instruction can be transmitted using SDR or DDR. In some embodiments, after the processor 133 of the NAND flash controller 131 receives the command (e.g., the read command or the read instruction) through the host interface 136, the NAND flash controller 131 reads user data from the NAND flash memory 121 through the NAND flash interface 137 and transfers the user data to the ECC module 134 for ECC decoding (e.g., decoding 200b in Figure 2 However, due to the characteristics of the NAND flash memory, after the user data is stored, the threshold voltage distribution in the NAND flash memory can deviate, such that the user data read from the NAND flash memory 121 cannot pass the ECC decoding of the ECC module 134, and thus the read fails. In the case of read failure, the processor 133 can control the use of a predefined different read voltage to repeatedly retry reading the user data in the NAND flash memory 121 until the data read from the NAND flash memory 121 can pass the ECC decoding of the ECC module 134. The deviation of the threshold voltage distribution and the retry read will be described with reference to Figure 3

[0082] Figure 3 A deviation diagram of the threshold voltage distribution 300 of the user data according to one or more embodiments of the present application is shown. As described above, since the user data is encoded by the ECC before storage, the number distribution of the bit values of the user data is randomized, and thus, as shown in the threshold voltage distribution diagram 300a, the read voltage V Read is located at the point where the number of cells of the bit value 1 and the number of cells of the bit value 0 are approximately equal, that is, in the valley of the graph. After the data is stored for a period of time, due to the characteristics of the NAND flash memory, the threshold voltage distribution of the user data can deviate, as shown in the threshold voltage distribution diagram 300b, for example, the threshold voltage range of the bit value 0 changes. Thus, the original read voltage V Read is no longer located at the point where the number of cells of the bit value 1 and the number of cells of the bit value 0 are approximately equal, that is, in the valley of the graph, and at this time, the user data read by the read voltage V Read may not be able to pass the ECC decoding to correct the error bits, and thus the data read fails.

[0083] As described above, in the case of read failure, the processor (e.g., the processor 133) can control the use of a predefined different read voltage to repeatedly retry reading the user data in the NAND flash memory 121 until the data read from the NAND flash memory 121 can pass the ECC decoding of the ECC module 134. The deviation of the threshold voltage distribution and the retry read will be described with reference to Figure 1 ​The processor 133 can control the repeated reading of NAND flash memory (such as...) using predefined different read voltages. Figure 1 The user data in the NAND flash memory (121) is retried to find the lowest or minimum error bit count (EBC), as shown in the threshold voltage distribution diagram 300c. In the example of threshold voltage distribution diagram 300c, at the read voltage V Read After a read failure, different predefined retry read voltages V were used for retry. RR1 V RR2 V RR3 V RR4 V RR5 V RR6 Perform a read. After retrying the read, the retry read voltage V can be determined. RR3 The number of cells where the number of cells with bit value 1 and the number of cells with bit value 0 are approximately equal (the difference between the number of cells with bit value 1 and bit value 0 is close to 0, indicating a lower EBC), which is located in the trough of the graph, is where the retry reading voltage V is indicated. RR3 The retrieved user data can be decoded via ECC, indicating a successful read. This retry read method can also be viewed as multiple hard decoding processes, followed by... Figure 4 illustrate.

[0084] Figure 4 A flowchart illustrating a hard decoding program 400 for ECC according to one or more embodiments of the present invention is shown. Figure 4 As shown, after the hard decoding begins in step S401, the hard decoding read operation is transmitted to the NAND flash memory in step S402, for example, in Figure 1 The processor 133 transmits the hard-decoded read operation to the NAND flash memory 121. Then, in step S403, the ECC module acquires the read data, for example... Figure 1 The ECC module 134 in the middle obtains read data from the NAND flash memory 121. After receiving the read data, in step S404, the ECC module (such as...) Figure 1 The ECC module 134) performs hard decoding, and in step S405 the ECC module returns the result, for example, in Figure 1 The ECC module 134 feeds back the hardware decoding result to the processor 133. If the feedback result is successful, it means that the read user data has passed ECC decoding and can be read successfully; if the feedback result is unsuccessful, it means that the read user data cannot pass ECC decoding, that is, the read fails. In this case, the reading voltage can be changed (e.g., using different retry reading voltages) to perform hardware decoding again, and the above multiple hardware decoding processes can be repeated (e.g., in...). Figure 3the predefined different retry read voltages V RR1 , V RR2 , V RR3 , V RR4 , V RR5 , V RR6 are used to perform the read until a voltage that can successfully read the user data is found.

[0085] To further illustrate the retry read voltages of hard decoding, the following will be described with reference to Figure 5 and Figure 6 . Figure 5 and Figure 6 are respectively a schematic diagram of threshold voltage distribution 500 and bit value quantity difference distribution 600 of user data according to one or more embodiments of the present application. In Figure 5 , according to data table 501 and threshold voltage distribution diagram 502, the cell quantities of bit values 1 (1#) and 0 (0#) and the quantity difference ((1#)-(0#)) obtained by using the predefined different retry read voltages V RR1 , V RR2 , V RR3 , V RR4 , V RR5 , V RR6 , V RR7 , V RR8 to perform the read can be known. Similar to the example in Figure 3 , in the threshold voltage distribution diagram 502, due to the threshold voltage distribution deviation, the original read voltage V Read is no longer located at the position where the cell quantities of bit values 1 (1#) and 0 (0#) are roughly equal (at this time, the quantity difference is +1850). However, after multiple hard decoding processes using different retry read voltages (such as V RR1 , V RR2 , V RR3 , V RR4 , V RR5 , V RR6 , V RR7 , V RR8 ), the retry read voltage V RR3 is located at the position where the cell quantities of bit values 1 (1#) and 0 (0#) are roughly equal (the quantity difference is +13, close to 0, which is a lower EBC), that is, in the valley of the graph, and thus the retry read voltage V RR3 can be used as a new read voltage to successfully read the user data.

[0086] Similarly, as shown in Figure 6 , compared with data table 602 (which is the same as Figure 5data table 501) and the bit value quantity difference distribution graph 601, the original read voltage V Read The cell quantity difference corresponding to the bit values 1 (#) and 0 (#) is +1850, which is not located in the valley of the bit value quantity difference distribution graph 601. The retry read voltage V RR3 The cell quantity difference corresponding to the bit values 1 (#) and 0 (#) is the minimum (+13) among all voltages and close to 0 (lower EBC), that is, in the valley of the graph, so the retry read voltage V RR3 As the read voltage can be used to successfully read user data.

[0087] As described in the above multiple examples, the controller (e.g. Figure 1 NAND flash controller 131) of the memory device can control the ECC module (e.g. Figure 1 ECC module 134 or Figure 2 ECC module 200) to repeatedly perform multiple hard decoding processes (as shown in Figure 3 to Figure 6 ) until a read voltage that can allow user data to successfully pass ECC decoding is found (e.g. Figure 3 , Figure 5 and Figure 6 retry read voltage V RR3 ) in the above examples. Such a hard decoding technique can require a very large number of retries (or retry orders) to successfully read (get a lower EBC and pass ECC decoding), or can still fail to read (fail to pass ECC decoding) after multiple retries. In some embodiments, the ECC module (e.g. Figure 1 ECC module 134 or Figure 2 ECC module 200) further provides a soft decoding (Soft Decode) technique. Soft decoding can be used as an alternative ECC decoding method when multiple hard decoding processes are performed on the retry read in the preset order, and still fail to read (fail to pass ECC decoding).

[0088] Next, refer to Figure 7 and Figure 8 , Figure 7 a flowchart of a soft decoding procedure 700 for ECC according to one or more embodiments of the present application is shown, and Figure 8 a schematic diagram of the soft decoding procedure 700 of Figure 7 on the threshold voltage distribution 800 of user data is shown. As shown in Figure 7 , after the soft decoding starts at step S701, a hard decoding read operation is first transmitted to the NAND flash at step S702, for example, the processor 133 of Figure 1 transmits a hard decoding read operation to the NAND flash 121 or Figure 4Step S402. Next, in step S703, the ECC module acquires the read data, for example... Figure 1 The ECC module 134 in the middle obtains read data from the NAND flash memory 121 or Figure 4 Step S403. When the ECC module still cannot decode the read data, for example... Figure 8 After the predefined retry read data in the predefined order (order 0 to n-1) shown in the data table 801, in step S704, the processor (such as...) Figure 1 The processor 133) can control the ECC module (such as... Figure 1 The ECC module 134) selects the SD card based on the predefined retry data table 801. 11 (In sequence n) read operations to NAND flash memory (e.g.) Figure 1 The NAND flash memory 121 in the memory is read, and in step S705, the ECC module obtains the read data. Similarly, in step S706, the processor (such as...) Figure 1 The processor 133) can control the ECC module (such as... Figure 1 The ECC module 134) selects the SD card based on the predefined retry data table 801. 12 (Similarly, in sequence n) read operations are performed to NAND flash memory (e.g.) Figure 1 The NAND flash memory 121 in the memory is read, and in step S707, the ECC module obtains the read data. Figure 8 As shown in the predefined retry read data table 801 and threshold voltage distribution diagram 802, the retry read parameters HD are predefined based on the order n. n SD11 n and SD12 n (This can also be referred to as HD) n +SD11 n +SD12 n However, this does not mean adding these three values ​​together. LDPC in the ECC module (such as...) Figure 2 (As shown) can be further modified for HD n +SD11 n +SD12 n The corresponding bit value distribution is calculated, and a soft data model of the log-likelihood ratio (LLR) is established. In other words, the ECC module calculates the distribution based on the predefined HD. n +SD11 n +SD12 n By executing HD n +SD11 n +SD12 nThe obtained results are used to calculate the LLR (step S708), and the NAND flash memory is retried using software decoding (step S709). Since software decoding calculates the LLR based on the threshold voltage distribution map, it has a higher probability of passing ECC decoding than hard decoding. Next, in step S710, the ECC module reports the result of the software decoding. If the feedback result is successful, it means that the read user data has passed ECC decoding and can be read successfully; if the feedback result is unsuccessful, it means that the read user data cannot pass ECC decoding, that is, the read fails. In this case, software decoding can be performed according to the order in the predefined retry read data table 801 (e.g., n+1, n+2…n+x), and the above process is repeated (e.g., retry using HD in order n+1). n+1 +SD11 n+1 +SD12 n+1 The LLR is calculated for reading, until user data can be successfully read (via ECC decoding). Based on the example above, software decoding requires at least three reads (HD). n +SD11 n +SD12 n ).

[0089] Based on the hard and soft decoding techniques for retrying reads of NAND flash memory proposed in the above examples and embodiments, this invention proposes a hard and soft decoding technique with read failure error handling, which can also be applied to NAND flash memory to reduce the number (or order) of read retries and increase the speed of retrying ECC decoding. Read failure error handling can be achieved through a read failure module in the memory controller (e.g., Figure 1 The NAND flash memory controller 131 of the memory device 120 has a read failure module 135 according to the ECC module (e.g., Figure 1 The ECC module 134) uses read (failure) feedback to set a new retry read voltage, instead of using a predefined retry read voltage (e.g., at...). Figure 3 or Figure 5 The retry read voltage V RR1 V RR2 V RR3 V RR4 V RR5 V RR6 V RR7 V RR8 According to several embodiments of the present invention, which include hard decoding and soft decoding techniques for handling read failures, [the technology will be used in conjunction with these techniques]. Figure 9 to Figure 15 The following is a detailed explanation.

[0090] Figure 9 A flowchart illustrating a hard decoding program 900 for ECC with read failure error handling according to one or more embodiments of the present invention is shown.Figure 9 Steps S901 to S904 are similar to Figure 4 Steps S401 to S404 are omitted here. Figure 4 The hard decoding program 400 is different from that of the 400. Figure 9 In step S905 of the hard decoding program 900, the read voltage V is determined. Read If the read user data can be successfully decoded by ECC, the user data is output to the host (step S906); if the ECC decoding fails, the read failure error is handled (steps S907 to S913).

[0091] Simultaneously refer to Figure 10 , Figure 10 Implementation of the drawing Figure 9 The hard decoding program is illustrated in the threshold voltage distribution 1000 of the user data. When the read failure error handling begins, in step S907, the read failure module (e.g., Figure 1 The read failure module 135 calculates the read voltage V. Read The absolute difference in the number of corresponding 0 / 1 bit values ​​(|(1#)-(0#)|), such as Figure 10 The |(1#)-(0#)|V shown Read Next, the processor (e.g.) Figure 1 The processor 133) transmits the retry read voltage V. RRi Operation to NAND flash memory (step S908). Retry read voltage V. RRi By reading the voltage V Read Increase the predefined voltage difference (V) RRi -V Read This can be used as a reference. To configure, retry reading voltage V. RRi In the examples of threshold voltage distribution diagrams 1000a and 1000c, the retry read voltage V is set. RR1 Relative to the reading voltage V Read On the X-axis (representing the threshold voltage V) th The right side of ) is the retry reading voltage V. RR1 Greater than the reading voltage V Read In such a situation, the voltage difference The first direction corresponding to the X-axis (X-axis to the right) is positive. Conversely, retry reading the voltage V. RRi In the examples of threshold voltage distribution diagrams 1000b and 1000d, the retry read voltage V is set. RR1 Relative to the reading voltage V Read On the X-axis (representing the threshold voltage V) thThe left side of ) is the retry reading voltage V RR1 Less than the reading voltage V Read In such a situation, the voltage difference The first direction corresponding to the X-axis (X-axis to the right) is negative. That is, based on the retry reading voltage V... RR1 ( Figure 9 The retry read voltage V RRi For reference Figure 10 The first retry reading voltage V RR1 (relative to the reading voltage V) Read The voltage difference between the two at the position set on the X-axis. The corresponding first direction (to the right of the X-axis) can be either positive or negative (e.g., in...). Figure 10 The threshold voltage distribution is shown in four cases, from threshold voltage distribution diagram 1000a to threshold voltage distribution diagram 1000d.

[0092] Next, in step S909, the ECC module executes the retry reading of voltage V. RRi The read user data is ECC decoded, and the reading voltage V is determined in step S910. RRi Check if the read data was successfully decoded using ECC. If ECC decoding was successful, output the user data to the host (step S906). If ECC decoding failed, similar to step S907, read the failed module (e.g., ...) in step S911. Figure 1 The read failure module 135 calculates the retry read voltage V. RRi The absolute difference in the number of corresponding 0 / 1 bit values ​​(|(1#)-(0#)|), such as Figure 10 The |(1#)-(0#)|V shown RR1 Next, in step S912, the processor determines the absolute difference between the previous two values ​​(e.g., ...). Figure 10 |(1#)-(0#)|V RR1 With |(1#)-(0#)|V Read The comparison determines the next retry reading voltage V. RRi This is used for the next retry read. The following will be... Figure 10 Explain how to apply the absolute difference (|(1#)-(0#)|V) to the four cases in the threshold voltage distribution diagrams 1000a to 1000d. RR1 With |(1#)-(0#)|V Read The comparison determines the next retry reading voltage V. RRi .

[0093] In the case of threshold voltage distribution diagram 1000a (voltage difference) Corresponding to the first direction (X-axis to the right is positive), since VRead The absolute difference in the number of corresponding 0 / 1 bit values ​​|(1#)-(0#)|V Read Less than V RR1 The absolute difference in the number of corresponding 0 / 1 bit values ​​|(1#)-(0#)|V RR1 , representing V RR1 The corresponding EBC is greater than V Read The corresponding EBC. That is, the direction of the lower EBC corresponding to the trough position in the graph is opposite to the direction of the read voltage V. Read Apply voltage difference Obtain retry read voltage V RR1 In the first direction of the X-axis, that is, the lower EBC is located at the read voltage V Read The left side (which can be referenced as the second direction (X-axis to the left)). Therefore, in order to find the retry read voltage V corresponding to the lower EBC. RRi The next retry reads the voltage V. RRi By reading the voltage V Read Subtract the predefined voltage difference (in the second direction opposite to the first direction) from the X-axis. (Positive number) is used to obtain it. Because in the case of threshold voltage distribution diagram 1000a, the voltage difference... Since it is a positive number, the reading voltage V Read Reduce the predefined voltage difference along the X-axis (in a second direction opposite to the previous first direction). In essence, it refers to reading the voltage V. Read Reduce the voltage so that the voltage V will be read again on the next retry. RRi Located at the reading voltage V Read The left side (not shown in the picture).

[0094] In the case of threshold voltage distribution diagram 1000c (voltage difference) Corresponding to the first direction (X-axis to the right is positive), since V Read The absolute difference in the number of corresponding 0 / 1 bit values ​​|(1#)-(0#)|V Read Greater than V RR1 The absolute difference in the number of corresponding 0 / 1 bit values ​​|(1#)-(0#)|V RR1 , representing V RR1 The corresponding EBC is less than V Read The corresponding EBC. That is, the direction of the lower EBC corresponding to the trough position in the graph is the same as the direction of the read voltage V. Read Apply voltage difference Obtain retry read voltage V RR1 In the first direction of the X-axis, that is, the lower EBC is located at the retry read voltage V. RR1To the right of. Therefore, in order to find the retry read voltage V corresponding to the lower EBC. RRi The next retry reads the voltage V. RRi The voltage V can be read from the previous retry. RR1 Increase the voltage difference along the X-axis (equivalent to the first direction of the previous operation). To obtain. Because in the case of threshold voltage distribution diagram 1000c, the voltage difference... Since it is a positive number, the previous retry voltage V... RR1 Increase the voltage difference along the X-axis (equivalent to the first direction of the previous operation). In essence, it refers to reading the voltage V. RR1 Increase the voltage so that the voltage V will be read again on the next retry. RRi Located at the previous retry read voltage V RR1 The right side (not shown in the picture).

[0095] In the case of threshold voltage distribution diagram 1000b (voltage difference) Corresponding to the first direction (the X-axis to the right is negative), since V Read The absolute difference in the number of corresponding 0 / 1 bit values ​​|(1#)-(0#)|V Read Greater than V RR1 The absolute difference in the number of corresponding 0 / 1 bit values ​​|(1#)-(0#)|V RR1 , representing V RR1 The corresponding EBC is less than V Read The corresponding EBC. That is, the direction of the lower EBC corresponding to the trough position in the graph is the same as the direction of the read voltage V. Read Apply voltage difference (Negative number) to obtain the retry read voltage V RR1 In the first direction, that is, the lower EBC is located at the read voltage V RR1 To the left. Therefore, in order to find the retry read voltage V corresponding to the lower EBC. RRi The next retry reads the voltage V. RRi The voltage V can be read from the previous retry. RR1 Increase the voltage difference along the X-axis (equivalent to the first direction of the previous operation). (Negative numbers) are used to obtain this. Because in the case of threshold voltage distribution diagram 1000b, the voltage difference... Since it is a negative number, the previous retry voltage V... RR1 Increase the voltage difference along the X-axis (equivalent to the first direction of the previous operation). (Negative number), essentially refers to the reading voltage V. RR1 Reduce the voltage so that the voltage V will be read again on the next retry. RRi Located at the previous retry read voltage V RR1 The left side (not shown in the picture).

[0096] In the case of the threshold voltage distribution graph 1000d (voltage difference (positive number) corresponding to the first direction (X-axis rightward) is negative), since V Read The absolute difference value of the number of 0 / 1 bit values corresponding to (1#) - (0#) |V Read is less than V RR1 The absolute difference value of the number of 0 / 1 bit values corresponding to (1#) - (0#) |V RR1 , represents that V RR1 The EBC corresponding to is greater than V Read The EBC corresponding to. That is, the direction of the lower EBC corresponding to the position of the graph valley is opposite to the original read voltage V Read The voltage difference (negative number) is applied to obtain the retry read voltage V RR1 , that is, the lower EBC is located on the right side of the read voltage V Read (corresponding to the voltage difference (negative number) can be referred to as the second direction (X-axis leftward)). Therefore, in order to find the retry read voltage V RRi corresponding to the lower EBC, the next retry read voltage V RRi can be obtained by subtracting (in the second direction opposite to the first direction of the previous time) the predefined voltage difference (negative number) from the read voltage V Read on the X-axis. In the case of the threshold voltage distribution graph 1000d, the voltage difference is negative, so subtracting (in the second direction opposite to the first direction of the previous time) the voltage difference (negative number) from the read voltage V Read on the X-axis, that is, subtracting the voltage difference (negative number) is actually increasing the voltage of the read voltage V Read , so that the next retry read voltage V RRi is located on the right side of the read voltage V Read (not shown in the figure).

[0097] Therefore, from the above multiple examples of the threshold voltage distribution graph 1000a to the threshold voltage distribution graph 1000d, it can be known that the technology provided by the present application can determine the next retry read voltage V RRi according to the comparison of the absolute difference value of the previous two read voltages, and determine whether the read user data passes the ECC decoding in step S913. These steps can be repeatedly executed (steps S911 to S913) until the retry read voltage that can pass the ECC decoding is found, and the read data is output to the host (step S906).

[0098] According to various embodiments of the present invention, V is determined RRi Setting direction and adjusting voltage difference The technology will be referenced below Figure 11A , Figure 11B to Figure 13 Further explanation.

[0099] Figure 11A and Figure 11B A flowchart illustrating a retry read voltage setting procedure 1100 for ECC with read failure error handling according to one or more embodiments of the present invention is shown. Figure 11A Steps S1102 to S1107 are similar to several examples of threshold voltage distribution maps 1000a to 1000d described above, at the beginning of determining V RRi After the value (step S1101), compare V. RRi Is the absolute difference in the number of corresponding 0 / 1 bit values ​​lower than the previous V? Read or V RRi The absolute difference (step S1102), which is the comparison as described above: |(1#)-(0#)|V Read (or the previous V) RRi ) and |(1#)-(0#)|V RRi To determine the setting of V RRi Is the direction correct (consistent with the direction of the lower EBC)? If V RRi The corresponding absolute difference is greater than the V value of the previous failed read. Read (or V) RRi If so, in step S1103, the next V is set in the opposite direction. RRi (similar to) Figure 10 Examples of threshold voltage distribution plots 1000a and 1000d). Figure 10 The example differs in that, due to V RRi It may have been executed several times. Therefore, in step S1104, it is determined whether i is greater than or equal to 2, that is, whether the retry read has been executed more than 2 times (e.g., V). RR2 This step is to ensure that V is set when changing direction. RRi At that time, it will not be directly equal to the V set twice before. RRi (For example Figure 13 V RR4 If directly from V RR3 Reverse setting V RR4 It will be equivalent to V RR2 Therefore, if i is less than 2, it represents the first change of direction (similar to...). Figure 10 Examples of threshold voltage distribution diagrams 1000a and 1000d), then according to the determined direction... Change settings V RRi (Step S1106). If i is greater than or equal to 2, then decrease according to the determined direction. Change settings V RRi (Step S1105) to avoid returning to the V value set two times earlier. RRi In step S1107, record the next V. RRi The direction, the recorded direction (e.g., via) Figure 1 The read failure module 135 (recorded) can be used when subsequent V RRi The corresponding absolute difference is again higher than V of the previous read failure. RRi At that time, change direction again (for example, at) Figure 13 (Example of threshold voltage distribution in Figure 1302).

[0100] Besides deciding V RRi The set direction, at Figure 11B In the middle section, steps S1108 to S1111 further explain how to adjust the voltage difference. When there is no need to change V RRi When setting the direction (determined in step S1102), V is calculated and compared multiple times in step S1108. RRi Multiple slopes between the absolute differences in the number of 0 / 1 bit values. As the slope of these absolute differences increases, it indicates a faster rate of EBC descent; therefore, an increase in the slope will... Reduce and set the next V RRi (Step S1109) to reduce V RRi The set spacing (e.g., at) Figure 12 (Example of threshold voltage distribution in Figure 1202), to avoid setting V RRi The position exceeding the trough of the chart (lowest EBC). When the slope of these absolute differences decreases, it means the rate of EBC decline is slower, therefore the corresponding decrease in slope will... Increase and set the next V RRi (Step S1111) to increase V RRi The set spacing, the accelerated V RRi The position is near the trough of the graph (lowest EBC). If the slope of the absolute difference remains unchanged, it remains the same. And set the next V RRi (Step S1110). These steps are followed in conjunction with the following... Figure 12 and Figure 13 Example illustration.

[0101] Figure 12 and Figure 13 Implementation of the drawing Figure 11A and Figure 11BThe retry voltage setting procedure 1100 is illustrated in the threshold voltage distribution of user data (threshold voltage distribution diagrams 1202 and 1302). Figure 12 As shown in data table 1201 and threshold voltage distribution diagram 1202, when V is executed... RR2 This allows us to obtain the slope change of the absolute difference in the number of bit values ​​between the two sets, i.e., V. Read With V RR1 The slope variation (1000-800) and V RR1 With V RR2 The slope changes between (800-200). At this time, due to V RR1 With V RR2 The slope change (600) is greater than V Read With V RR1 The slope changes between (200), therefore, if the same is used directly... And set the next V RR3 This will directly exceed the position of the graphical trough, as shown in the threshold voltage distribution diagram 1202. Therefore, through the above... Figure 11B Steps S1108 to S1111 can replace V RR3 Changes and adjustments (In this example, it is adjusted to) V RRi Set to V RR3 This facilitates finding the V position near the trough of the chart (lowest EBC). RRi Successfully decoded via ECC (V in this example). RR4 ).

[0102] At Figure 13 As shown in data table 1301 and threshold voltage distribution diagram 1302, when V is executed... RR3 V RR3 The absolute difference (500) in the number of corresponding 0 / 1 bit values ​​is greater than V. RR2 The absolute difference (400) in the number of corresponding 0 / 1 bit values. Therefore, through the above... Figure 11A Steps S1103 to S1107 can change V RRi Set the direction and lower accordingly. (In this example, it is adjusted to) V RRi Set to V RR4 To avoid V RR4 When set in reverse, it is directly equivalent to V. RR2 The voltage is used to locate the V value near the trough of the graph (lowest EBC). RRi Successfully decoded via ECC (V in this example). RR4 ).

[0103] Based on the above examples and embodiments of hard decoding, this invention further provides a software decoding technique to reduce the number (or order) of retries and increase the probability of passing ECC decoding. The following will be used in conjunction with... Figure 14 and Figure 15 illustrate.

[0104] Then refer to Figure 14 and Figure 15 , Figure 14 A flowchart illustrating a software decoding program 1400 for ECC according to one or more embodiments of the present invention, and Figure 15 Implementation of the drawing Figure 14 A schematic diagram of the threshold voltage distribution of user data in the software decoding program 1400. Figure 14 The software decoding program 1400 and Figure 7 The difference between the software decoding program 700 and the program is that steps S1401 to S1409 are performed similarly. Figure 9 to Figure 13 The described hard decoding techniques (e.g., in) Figure 15 The threshold voltage distribution is shown in Figure 1500a and Data Table 1500b. (V in Threshold Voltage Distribution Figure 1500a is shown in...) Read This corresponds to HD0 in the predefined retry read data table 1501, while the retry read parameter (voltage) V in data table 1500b... RR1 V RR2 V RR3 These can correspond sequentially to HD1, HD2, HD3, etc., in the predefined retry read data table 1501. Therefore, after repeatedly executing the hard decoding steps S1401 to S1409, when it is determined that the hard decoding sequence has ended (determined in step S1411) (for example, the sequence n-1 in the predefined retry read data table 1501 has been executed), and the obtained data has not been decoded by ECC (for example, the sequence n-1 in the predefined retry read data table 1501 has been executed), the soft decoding steps S1412 to S1414 begin. Then, in step S1412, the smallest HD is selected. i The result is as HD x That is, based on what was recorded during the previous hard decoding (e.g., via...). Figure 1 The retry read parameter (voltage) with the smallest absolute difference (lowest EBC) among the results of the read failure module 135 (e.g., data table 1500b) is selected as the HD used for soft decoding. x (In this example, V is in data table 1500b) RR4 Instead of directly using predefined voltage values ​​(e.g.) Figure 8 Predefined retry read of HD from data table 801 n). Then, in step S1413, the HD x and 2 soft-decoding read voltage operations Figure 15 of the pre-defined retry read data table 1501 of the (HD x + SD11 n + SD12 n ) to the NAND flash. Then, soft-decoding is performed (step S1414) in the same manner as described above with reference to Figure 7 and Figure 8 Since the selected HD x has the lowest EBC, and the absolute difference of the number of 1 / 0 bit values calculated when the hard-decoding was performed previously is the lowest, the soft-decoding is performed with reference to this HD x , the probability of passing the ECC decoding of the soft-decoding can be increased.

[0105] According to the above embodiments and examples, the technology provided by the present application can dynamically adjust the retry read voltage of the next time and the voltage difference between the retry read voltages according to the absolute difference of the number of the first bit value / second bit value (1 / 0 bit value) corresponding to the retry read voltage. Further, after the hard-decoding in the pre-set order, the soft-decoding can be performed using the hard-decoding retry read voltage corresponding to the absolute difference of the number of the lowest 1 / 0 bit value recorded, which can reduce the number (or order) of the retry read and the probability of the data with the error bit passing the ECC decoding, and improve the efficiency of the read operation of the memory device.

[0106] The present application and other examples can be implemented as one or more computer program products, e.g., one or more modules of computer program instructions encoded on a computer readable medium to be executed by, or to control the operation of, data processing apparatus. The computer readable medium can be a machine-readable storage

[0107] A computer program (also known as a program, software, software application, instructions for operation, or program code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of programs). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and that are interconnected by a communication network.

[0108] The processes and logic flows described herein can be performed by one or more programmable processors executing one or more computer programs to perform functions described herein. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

[0109] Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read-only memory or a random access memory or both. The essential elements of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical, or optical disks. However, a computer need not have such devices. Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto-optical disks; and CD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0110] Although a number of details of the application have been set forth in the foregoing description, these details are merely for the purposes of explanation and are not to be construed as limiting the scope of the present application as it is set forth in the appended claims. Certain features of the application, which are, for clarity, described above and in the claims in conjunction with only one of the exemplary embodiments, can also be found in the other exemplary embodiments. Conversely, various features of the

[0111] Only a few examples and implementations are described herein. Modifications and variations of such examples and implementations can be made based on the teachings of the present invention as set forth herein.

[0112] In closing, the present application has been described with reference to specific exemplary embodiments and implementations. It will, of course, be understood that various modifications and changes can be made to the embodiments described without departing from the broader scope of the present application as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. An operating method for retrying reading data from a memory device, the operating method comprising: A first read voltage is applied to the memory device, and a first absolute difference between the number of a first bit value and the number of a second bit value obtained corresponding to the first read voltage is calculated. A second read voltage is applied to the memory device, the second read voltage having a first voltage difference with the first read voltage in a first direction, and a second absolute difference between the number of the first bit value obtained corresponding to the second read voltage and the number of the second bit value is calculated; as well as Compare the second absolute difference with the first absolute difference; Specifically, when the second absolute difference is less than the first absolute difference, at least one retry read voltage is obtained by sequentially increasing the first voltage difference in the first direction on the second read voltage, and the memory device is read by applying the at least one retry read voltage until the data read by one of the at least one retry read voltages is decoded by the error correction code (ECC). When the second absolute difference is greater than the first absolute difference, the first voltage difference is sequentially reduced in a second direction opposite to the first direction to obtain at least one retry read voltage, and the memory device is read by applying the at least one retry read voltage until the data read by one of the at least one retry read voltages is decoded by the error correction code.

2. The method of claim 1, wherein during the process of obtaining the at least one retry read voltage by sequentially increasing the first voltage difference on the second read voltage in the first direction, at least two absolute differences between the number of the first bit values ​​and the number of the second bit values ​​obtained between these retry read voltages are calculated. When the at least two absolute differences increase, a second voltage difference is sequentially reduced in the second direction for a previously retry read voltage until the data read by one of the at least one retry read voltages is decoded by the error correction code. The second voltage difference is smaller than the first voltage difference.

3. The method of claim 1, wherein during the process of obtaining the at least one retry read voltage by sequentially reducing the first voltage difference of the first read voltage in the second direction, at least two absolute differences between the number of the first bit values ​​and the number of the second bit values ​​obtained between these retry read voltages are calculated. When the at least two absolute differences increase, a second voltage difference is sequentially increased in the first direction for a previous retry read voltage until the data read by one of the corresponding at least one retry read voltages is decoded by the error correction code. The second voltage difference is smaller than the first voltage difference.

4. The operating method according to claim 2 or claim 3, wherein the second voltage difference is one-half or one-quarter of the first voltage difference.

5. The method of claim 1, wherein during the process of obtaining the at least one retry read voltage by sequentially increasing the first voltage difference on the second read voltage in the first direction, a plurality of absolute difference slopes corresponding to a plurality of absolute differences between the number of the first bit values ​​and the number of the second bit values ​​obtained between these retry read voltages are calculated. When the slope of these absolute differences decreases, a third voltage difference is sequentially increased in the first direction to read the memory device from a previous retry read voltage. As the slope of these absolute differences increases, a fourth voltage difference is sequentially added to the previous retry read voltage in the first direction to read the memory device. The third voltage difference is greater than the first voltage difference, and the fourth voltage difference is less than the first voltage difference.

6. The method of claim 1, wherein during the process of obtaining the at least one retry read voltage by sequentially reducing the first voltage difference of the first read voltage in the second direction, a plurality of absolute difference slopes corresponding to a plurality of absolute differences between the number of the first bit values ​​and the number of the second bit values ​​obtained between these retry read voltages are calculated. When the slope of these absolute differences decreases, a third voltage difference is sequentially reduced in the second direction to read the memory device from a previous retry read voltage. As the slope of these absolute differences increases, a fourth voltage difference is sequentially reduced in the second direction to read the memory device from a previous retry read voltage. The third voltage difference is greater than the first voltage difference, and the fourth voltage is less than the third voltage.

7. The operating method according to claim 5 or claim 6, wherein an absolute voltage difference between the first voltage difference and the third voltage difference or the fourth voltage difference corresponds to a change in the slope of these absolute differences.

8. An operating method for retrying reading data from a memory device, the operating method comprising: A read operation is performed on the memory device, the read operation comprising the following steps: A first hard-decode read voltage is applied to the memory device, and a first absolute difference between the number of a first bit value and the number of a second bit value obtained corresponding to the first hard-decode read voltage is calculated. A second hard-decode read voltage is applied to the memory device, the second hard-decode read voltage having a first voltage difference with the first hard-decode read voltage in a first direction, and a second absolute difference between the number of the first bit value and the number of the second bit value obtained corresponding to the second hard-decode read voltage is calculated. as well as Compare the second absolute difference with the first absolute difference; Specifically, when the second absolute difference is less than the first absolute difference, the first voltage difference is sequentially increased in a preset order along the first direction to obtain at least one hard-decoding read voltage, and the at least one hard-decoding read voltage is applied to read the memory device. Specifically, when the second absolute difference is greater than the first absolute difference, the first voltage difference is sequentially reduced in a preset order in a second direction opposite to the first direction to obtain at least one hard-decoding read voltage, and the at least one hard-decoding read voltage is applied to read the memory device. Specifically, when the preset order of the read operation is reached, if the read data still cannot be decoded by the error correction code, a soft decoding operation is performed on the memory device. The soft decoding operation includes the following steps: A first soft decoding voltage is a hard decoding voltage used to measure the absolute difference between the number of the smallest first bit value and the number of the second bit value in the at least one hard decoding read voltage. A second soft decoding read voltage and a third soft decoding read voltage are generated based on the first soft decoding read voltage; The log-likelihood ratio (LLR) is calculated using the first, second, and third soft-decoding read voltages, and soft decoding is performed; and Repeat the software decoding operation until the read data is decoded using the error correction code.

9. The method of claim 8, wherein during the process of obtaining the at least one hard-decode read voltage by sequentially increasing the first voltage difference in the first direction according to the preset order to the second hard-decode read voltage, at least two absolute differences between the number of the first bit value and the number of the second bit value obtained between the at least one hard-decode read voltage are calculated. When the at least two absolute differences increase, the memory device is read sequentially in the second direction by decreasing the previous hard-decoding read voltage by a second voltage difference. The second voltage difference is smaller than the first voltage difference.

10. The method of claim 8, wherein during the process of obtaining the at least one hard-decode read voltage by sequentially reducing the first voltage difference in the preset order of the first hard-decode read voltage in the second direction, at least two absolute differences between the number of the first bit value and the number of the second bit value obtained between the at least one hard-decode read voltage are calculated. When the at least two absolute differences increase, a second voltage difference is sequentially added to the previous hard-decoding read voltage in the first direction to read the memory device. The second voltage difference is smaller than the first voltage difference.

11. The operating method according to claim 9 or claim 10, wherein the second voltage difference is one-half or one-quarter of the first voltage difference.

12. The method of claim 8, wherein during the process of obtaining the at least one hard-decode read voltage by sequentially increasing the first voltage difference in the first direction in the preset order to the second hard-decode read voltage, a plurality of absolute difference slopes corresponding to a plurality of absolute differences between the number of the first bit values ​​and the number of the second bit values ​​obtained between these hard-decode read voltages are calculated. When the slope of these absolute differences decreases, a third voltage difference is sequentially increased in the first direction to read the memory device from a previous hard-decoding read voltage. As the slope of these absolute differences increases, a fourth voltage difference is sequentially added to the previous hard-decoding read voltage in the first direction to read the memory device. The third voltage difference is greater than the first voltage difference, and the fourth voltage is less than the third voltage.

13. The method of claim 8, wherein during the process of obtaining the at least one hard-decode read voltage by sequentially reducing the first voltage difference in the second direction in the preset order to obtain the first hard-decode read voltage, a plurality of absolute difference slopes corresponding to a plurality of absolute differences between the number of the first bit values ​​and the number of the second bit values ​​obtained between these hard-decode read voltages are calculated. When the slope of these absolute differences decreases, a third voltage difference is sequentially reduced in the second direction to read the memory device from the previous hard-decoded read voltage. As the slope of these absolute differences increases, a fourth voltage difference is sequentially reduced in the second direction to read the memory device from a previous hard-decoding read voltage. The third voltage difference is greater than the first voltage difference, and the fourth voltage is less than the third voltage.

14. The method of operation according to claim 12 or claim 13, wherein an absolute voltage difference between the first voltage difference and the third voltage difference or the fourth voltage difference corresponds to a change in the slope of these absolute differences.

15. A memory device, comprising: A memory array; as well as A controller, coupled to the memory array, includes: One processor; An error correction code (ECC) module is coupled to the processor; and A read failure module is coupled to the processor and the error correction code module. Specifically, the controller performs read operations on the memory array by executing the following program: The controller applies a first hard-decode read voltage to the memory array to read data. When the read data cannot be decoded by the error correction code of the error correction code module, the read failure module calculates and records a first absolute difference between the number of a first bit value and the number of a second bit value obtained corresponding to the first hard-decode read voltage. The controller applies a second hard-decoding read voltage to the memory array to read data. This second hard-decoding read voltage has a first voltage difference with the first hard-decoding read voltage in a first direction. When the read data cannot be decoded by the error correction code module, the read failure module calculates and records a second absolute difference between the number of the first bit value and the number of the second bit value obtained corresponding to the second hard-decoding read voltage. The processor compares the second absolute difference with the first absolute difference; Specifically, when the second absolute difference is less than the first absolute difference, the controller sequentially increases the first voltage difference in a preset order in the first direction to generate at least one hard-decoding read voltage for the read operation to read the memory array until the read data is decoded by the error correction code module. When the second absolute difference is greater than the first absolute difference, the controller sequentially reduces the first voltage difference in a preset order in a second direction opposite to the first direction to generate at least one hard-decoding read voltage in the read operation to read the memory array until the read data is decoded by the error correction code of the error correction code module.

16. The memory device according to claim 15, wherein, When the preset order of the read operation is reached, and the read data still cannot be decoded by the error correction code module, the controller performs a soft decode operation on the read from the memory array, executing the following procedure: The processor uses a hard-decode read voltage, which is the absolute difference between the number of the smallest first bit value and the number of the second bit value recorded by the read failure module, as a first soft-decode voltage. The processor generates a second software decoding read voltage and a third software decoding read voltage based on the first software decoding read voltage; The ECC module uses the first soft-decoding read voltage, the second soft-decoding read voltage, and the third soft-decoding read voltage to calculate the log-likelihood ratio (LLR) and perform soft decoding; and The controller repeats the soft decoding operation until the read data is decoded by the error correction code of the error correction code module.

17. The memory device of claim 15, wherein during the process of the controller sequentially increasing the first voltage difference in the preset order by the second hard-decoding read voltage in the first direction to read the memory array, the read failure module calculates at least two absolute differences between the number of the first bit value and the number of the second bit value obtained between the at least one hard-decoding read voltage. When the at least two absolute differences increase, the controller sequentially reduces the previous hard-decoded read voltage by a second voltage difference in the second direction to read the memory array. The second voltage difference is smaller than the first voltage difference.

18. The memory device of claim 15, wherein during the period when the controller reads the memory array by sequentially reducing the first voltage difference in the preset order according to the first hard-decode read voltage in the second direction, the read failure module calculates at least two absolute differences between the number of the first bit value and the number of the second bit value obtained between the at least one hard-decode read voltage. When the at least two absolute differences increase, the controller sequentially increases a second voltage difference in the first direction on a previous hard-decoded read voltage to read the memory array. The second voltage difference is smaller than the first voltage difference.

19. The memory device of claim 15, wherein during the process of the controller sequentially increasing the first voltage difference in the preset order by the second hard-decoding read voltage in the first direction to read the memory array, the read failure module calculates a plurality of absolute difference slopes between a plurality of absolute differences between the number of the first bit values ​​and the number of the second bit values ​​obtained between these hard-decoding read voltages. When the slope of these absolute differences decreases, the controller sequentially increases a third voltage difference in the first direction on a previous hard-decoding read voltage to read the memory array. As the slope of these absolute differences increases, the controller sequentially increases the previous hard-decoding read voltage in the first direction by a fourth voltage difference to read the memory array. Wherein the third voltage difference is greater than the first voltage difference, the fourth voltage difference is less than the first voltage difference, and an absolute voltage difference between the first voltage difference and the third voltage difference or the fourth voltage difference corresponds to the change in the slope of these absolute differences.

20. The memory device of claim 15, wherein during the period when the controller reads the memory array by sequentially reducing the first voltage difference in the second direction according to the preset order of the first hard-decoded read voltage, the read failure module calculates a plurality of absolute difference slopes between a plurality of absolute differences between the number of the first bit values ​​and the number of the second bit values ​​obtained between these hard-decoded read voltages. When the slope of these absolute differences decreases, the controller sequentially reduces a third voltage difference in the second direction from the previous hard-decoded read voltage to read the memory device. When the slope of these absolute differences increases, the controller sequentially reduces the previous hard-decoding read voltage by a fourth voltage difference in the second direction to read the memory array. Wherein the third voltage difference is greater than the first voltage difference, the fourth voltage difference is less than the first voltage difference, and an absolute voltage difference between the first voltage difference and the third voltage difference or the fourth voltage difference corresponds to the change in the slope of these absolute differences.

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