Mask structure and etching method

Abstract

The invention relates to the technical field of semiconductors, in particular to a mask structure and an etching method. The etching method comprises the steps that an etching stop layer, a mask structure and a patterned photoresist layer are provided, the mask structure comprises a first mask layer and a second mask layer which are sequentially stacked on the etching stop layer, and the photoresist layer shields part of the second mask layer; performing first etching treatment on the mask structure until the unshielded second mask layer region is removed and at least part of the unshielded first mask layer region is left; performing second etching processing on the mask structure and the photoresist layer until the photoresist layer, the shielded second mask layer area and the remaining unshielded first mask layer area are removed so as to expose the unshielded etching stop layer; the total etching duration of the photoresist layer and the shielded second mask layer region is less than or equal to the etching duration of the remaining unshielded first mask layer region. According to the invention, the problem that the photoresist is difficult to clean and remove after being adhered and wrapped by the by-product can be avoided.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a mask structure and etching method. Background Technology

[0002] In the fabrication of semiconductor devices, pattern transfer is achieved through photoresist exposure and mask etching to form device components with specified patterns. However, some etching processes have excessively high Taper Rate (TR), which generates a large number of etching byproducts and leads to over-etching of the etch stop layer. Byproducts and over-etched materials continuously adhere to and encapsulate the photoresist, hindering its removal during the resist stripping process. Residual photoresist can affect subsequent top-layer etching and corresponding dielectric layer deposition, thus impacting device performance. Furthermore, the presence of a large amount of polymer inside the cavity complicates equipment maintenance. Summary of the Invention

[0003] To address the aforementioned technical problems, this application discloses an etching method, comprising: An etch stop layer, a mask structure, and a patterned photoresist layer are provided. The mask structure includes a first mask layer and a second mask layer sequentially stacked on the etch stop layer, and the photoresist layer partially masks the second mask layer. The mask structure is subjected to a first etching process until the unmasked second mask layer area is removed and at least part of the unmasked first mask layer area remains. A second etching process is performed on the mask structure and the photoresist layer to remove the photoresist layer, the masked second mask layer area, and the remaining unmasked first mask layer area, so as to expose the unmasked etch stop layer; the total etching time of the photoresist layer and the masked second mask layer area is less than or equal to the etching time of the remaining unmasked first mask layer area.

[0004] In one example implementation, the preset thickness of the unmasked first mask layer region remaining after the first etching process is determined based on the etching ratio between the combined etching rate of the photoresist layer and the second mask layer and the etching rate of the first mask layer during the second etching process.

[0005] In one example implementation, the etching ratio is 1:1 to 1.5:1, and after the first etching process, the total thickness of the photoresist layer and the masked second mask layer region is less than or equal to the preset thickness.

[0006] In one example implementation, the total etching time of the photoresist layer and the masked second mask layer region is equal to the etching time of the remaining unmasked first mask layer region; The second etching process on the mask structure and the photoresist layer, to remove the photoresist layer, the masked second mask layer area, and the remaining unmasked first mask layer area, to expose the unmasked etch stop layer, includes: The photoresist layer, the masked second mask layer area, and the remaining unmasked first mask layer area are etched together until the etching time reaches a preset time, so as to expose the unmasked etch stop layer, and the remaining masked first mask layer area forms a photolithographic pattern.

[0007] In one example implementation, the total etching time of the photoresist layer and the masked second mask layer region is less than the etching time of the remaining unmasked first mask layer region; The second etching process on the mask structure and the photoresist layer, to remove the photoresist layer, the masked second mask layer area, and the remaining unmasked first mask layer area, to expose the unmasked etch stop layer, includes: The photoresist layer, the masked second mask layer region, and the remaining unmasked first mask layer region are etched together until the photoresist layer and the masked second mask layer region are removed. The remaining unmasked first mask layer area is etched using a low-power etching method until the unmasked etch stop layer is exposed, and the remaining masked first mask layer area forms a photolithographic pattern.

[0008] In one example implementation, during the etching process of the low-power etching method, the upper electrode power is 200-500W and the lower electrode power is 100-300W.

[0009] In one example implementation, the etch stop layer comprises a titanium-containing compound.

[0010] In one example implementation, the material of the first mask layer includes SiON.

[0011] In one example implementation, the second mask layer is a dielectric anti-reflective coating.

[0012] In one example implementation, the material of the second mask layer includes at least one of silicon oxynitride, silicon carbide nitride, titanium oxide, and carbon oxynitride.

[0013] In another aspect, this application also discloses a mask structure comprising a first mask layer and a second mask layer sequentially stacked on an etch stop layer, wherein the photoresist layer partially masks the second mask layer; the mask structure is applied to the etching method described above.

[0014] In another aspect, this application also discloses a semiconductor structure, which includes the mask structure described above.

[0015] Based on the above technical solution, this application has the following beneficial effects: The mask structure of this application includes a first mask layer and a second mask layer sequentially stacked on an etch stop layer. A photoresist layer partially masks the second mask layer. After the first etching process, a portion of the first mask layer remains unmasked to protect the etch stop layer. This ensures that during subsequent etching removal of the photoresist and mask structure, the removal of the unmasked first mask layer area does not occur earlier than the removal of the photoresist layer and the masked second mask layer area. This avoids over-etching of the etch stop layer, reduces the total amount of etching byproducts, and prevents the photoresist from becoming difficult to clean after being adhered and encapsulated by byproducts, thus reducing equipment maintenance costs. Furthermore, removing the photoresist layer in advance during mask etching eliminates the need to change equipment for photoresist stripping, simplifying the etching process. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram illustrating the process principle of an existing etching method. Figure 2 A schematic flowchart of an etching method provided in an embodiment of this application; Figure 3 A schematic diagram illustrating the process principle of an etching method provided in an embodiment of this application; Figure 4 A schematic diagram illustrating the process principle of another etching method provided in this application embodiment; The following is supplementary explanation of the attached figures: 10 - Etching stop layer, 20 - Mask structure, 201 - First mask layer, 202 - Second mask layer, 30 - Photoresist layer, 40 - Dielectric layer, 50 - Polymer. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0019] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of this application. In the description of this application, it should be understood that the terms "upper," "lower," "top," "bottom," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein.

[0020] When a numerical range is disclosed herein, the range is considered continuous and includes the minimum and maximum values ​​of the range, as well as every value between the minimum and maximum values. Furthermore, when the range refers to an integer, it includes every integer between the minimum and maximum values ​​of the range. Additionally, when multiple ranges are provided to describe a feature or characteristic, the ranges may be combined. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all subranges to which they are included. For example, a specified range from “1 to 10” should be considered to include any and all subranges between the minimum value 1 and the maximum value 10. Exemplary subranges of the range 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc.

[0021] As used in this application, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entire lower or upper structure, or it may extend within a localized area of ​​the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along irregularly shaped surfaces. A single layer may comprise multiple layers. For example, dielectric layer 40230 may comprise multiple sublayers, etc., and may have the same or different materials.

[0022] It should be understood that the terms "consistent" and "perpendicular" used in this application refer to basic consistency or basic perpendicularity that meet the requirements of process tolerance, and do not refer to absolute consistency or absolute perpendicularity in a physical sense.

[0023] It should be understood that the term "plane" as used in this application, such as "first plane", "second plane", etc., refers to the XY plane of the substrate 100 or substrate structure, corresponding to the XY plane of the mask structure 20. "In-plane direction" refers to the direction parallel to the XY plane. "Thickness direction", "trench depth direction" or "longitudinal direction" refers to the Z direction relative to the XY plane.

[0024] The following combination Figure 1-4 This application introduces an etching method provided in its embodiments. Figure 2 This is a flowchart illustrating the etching method. This specification provides method operation steps as shown in the embodiments or flowcharts, but based on conventional or non-inventive methods, more or fewer operation steps may be included. The order of steps listed in the embodiments is merely one possible execution order among many and does not represent the only possible execution order. In actual etching method execution, the method can be executed in the order shown in the embodiments or drawings, or in parallel. Reference Figure 2 The etching method may include S11-S13: S11: Provides an etch stop layer 10, a mask structure 20, and a patterned photoresist layer 30.

[0025] Specifically, the mask structure 20 includes a first mask layer 201 and a second mask layer 202 sequentially stacked on the etch stop layer 10, with the photoresist layer 30 partially obscuring the second mask layer 202. The photoresist layer 30 is a film formed by patterning exposure after coating photoresist onto the mask structure 20. The material of the photoresist layer 30 can be one or more of the following, including but not limited to phenolic resin, diazonaphthoquinone, polytelluric acid, poly(p-hydroxystyrene), organic molecular glass, polymethyl methacrylate, and PHS derivatives. Understandably, when the etching area is large, a thicker photoresist layer 30 is used; for example, the thickness of the photoresist layer 30 can be greater than or equal to 2.2 μm.

[0026] Specifically, the etch stop layer 10 provides selective stop points during the etching process of the mask structure 20, thereby protecting the underlying material of the etch stop layer 10. In some embodiments, the etch stop layer 10 comprises a titanium-containing compound; exemplaryly, the etch stop layer 10 comprises titanium nitride (TIN), thereby precisely controlling the etching depth based on the highly etch-selective titanium-containing compound, preventing over-etching damage to the substrate material, and ensuring the accuracy of pattern transfer.

[0027] Specifically, refer to Figure 3The first mask layer 201 is stacked on the etch stop layer 10 and can be used as a spacer layer to protect the etch stop layer 10. Simultaneously, the final critical dimension (CD) can be precisely controlled by adjusting the thickness of the first mask layer 201. In one embodiment, the material of the first mask layer 201 includes, but is not limited to, SiON. In some embodiments, in scenarios such as electrode etching, the first mask layer 201 can be used as a barrier layer for subsequent via etching.

[0028] Specifically, the second mask layer 202 is stacked on top of the first mask layer 201, serving as a core pattern transfer layer. In one embodiment, the second mask layer 202 is a dielectric anti-reflective coating (DARC), which can reduce reflection and standing wave effects during photolithography, improving the accuracy of the photoresist pattern. Specifically, the second mask layer 202 is also used to adjust the etching selectivity ratio between itself and the first mask layer 201.

[0029] Optionally, the material of the second mask layer 202 includes at least one of silicon oxynitride, silicon carbide nitride, titanium oxide, and carbon nitride, or it can be any other material that can be used to allow the photoresist layer 30 and the second mask layer 202 to be etched away before the first mask layer 201 in the second etching process by adjusting the etching rate and thickness.

[0030] Understandably, titanium-containing compounds, when used as the etch stop layer 10, offer high etching precision but also exhibit strong adhesion. Consequently, Ti byproducts ejected during etching continuously adhere to the surface of the photoresist material, encapsulating it and making it difficult to remove during subsequent photoresist stripping. (Reference) Figure 1 , Figure 1The etching process of a 90nm RRAM (Resistive Random Access Memory) using a TEHM (Top Electrode Hard Mask) is illustrated. The etching stop layer 10TIN, mask structure 20, and photoresist layer 30 are stacked sequentially. Due to the large etching area, the photoresist layer 30 and mask structure 20 are relatively thick. For example, using a photoresist layer 30 with a thickness of approximately 2.5μm results in a TR (transfer rate) close to 98% after exposure. A SiON / APF (advanced patterning film) / SiON layer with a total thickness of approximately 3.5μm is used as the mask structure 20. After bombarding the mask structure 20 with high etching power to achieve pattern transfer, a large amount of etching byproducts are generated. Titanium-containing compounds at the bottom are lost, and these byproducts combine with the surface photoresist to form a difficult-to-remove titanium-containing polymer 50 (such as titanium nitride polymer). Simultaneously, an even larger amount of polymer 50 adheres to the cavity interior. Next, the etched semiconductor structure needs to be replaced with a different machine to remove the resist, and then the etching machine is switched to etch the remaining mask structure 20. Due to the high adhesion of the polymer 50, it remains on the surface of the etch stop layer 10 after the etching process of the mask structure 20, which not only reduces the etching accuracy, but also affects the subsequent deposition of the dielectric layer 40.

[0031] S12: Perform a first etching process on the mask structure 20 until the unmasked second mask layer area is removed and at least part of the unmasked first mask layer area remains.

[0032] Specifically, the unmasked first mask layer region and the unmasked second mask layer region are the mask structure regions exposed by the photoresist layer 30.

[0033] Specifically, after the first etching process, the unmasked area of ​​the second mask layer is removed. The photoresist layer 30 may have etching loss, but it still masks the pattern area of ​​the second mask layer 202. The unmasked area of ​​the first mask layer may not be etched during the first etching process, and its own thickness may be the preset thickness, or it may be partially etched to reduce it to the preset thickness.

[0034] Compared to the photoresist layer 30, the first etching process has a higher selectivity for the mask structure 20, and is used to perform preliminary etching of the mask structure 20 to etch the desired cross-sectional morphology, leaving the area of ​​the first mask layer used in the second etching process to protect the etch stop layer 10. Optionally, the first etching process can be wet etching or dry etching, preferably a dry etching process.

[0035] In some embodiments, the preset thickness of the unmasked first mask layer region remaining after the first etching process is determined based on the etching ratio between the combined etching rate of the photoresist layer 30 and the second mask layer 202 and the etching rate of the first mask layer 201 during the second etching process. Understandably, the etching rate is adjusted by regulating the etching ratio and thickness. By adjusting an appropriate etching ratio and combining it with the combined etching rate, the required etching time for the photoresist layer 30 and the second mask layer 202 is determined. Then, based on the etching rate of the first mask layer 201, the required preset thickness is determined, ensuring that the unmasked first mask layer region does not expose the etch stop layer 10 during the second etching process, avoiding over-etching of the etch stop layer 10, reducing the loss of the etch stop layer 10, and effectively removing byproduct polymers.

[0036] In some embodiments, the etching ratio is 1:1 to 1.5:1, preferably 1:1. After the first etching process, the total thickness of the photoresist layer 30 and the masked second mask layer area is less than or equal to a preset thickness. Thus, by adjusting the etching ratio to the above value, the preset thickness can be optimized to match the total thickness, which is beneficial for adjusting the etching time and controlling the remaining thickness, and simplifies process control.

[0037] S13: Perform a second etching process on the mask structure 20 and the photoresist layer 30 to remove the photoresist layer 30, the masked second mask layer area and the remaining unmasked first mask layer area, so as to expose the unmasked etch stop layer 10.

[0038] Specifically, the first mask layer region and the second mask layer region that are masked are the mask structure regions that are masked by the photoresist layer 30.

[0039] Specifically, the photoresist layer 30, the second mask layer 202, and the first mask layer 201 can all be etched during the second etching process. This process removes the photoresist layer 30, the second mask layer 202, and the unmasked first mask layer 201, leaving the masked first mask layer 201 to form an etching pattern and expose the unmasked etch stop layer 10. Optionally, the second etching process can be wet etching or dry etching, preferably a dry etching process.

[0040] Specifically, the total etching time of the photoresist layer 30 and the masked second mask layer region is less than or equal to the etching time of the remaining unmasked first mask layer region. Understandably, based on the aforementioned etching ratio and preset thickness settings, the total etching time can be adjusted to be less than or equal to the etching time of the remaining unmasked first mask layer region. This ensures that the etch stop layer 10 is exposed only after the photoresist layer 30 and the unmasked first mask layer region are completely removed. This prevents etching byproducts from the etch stop layer 10 from combining with the photoresist layer 30 to form a difficult-to-remove polymer 50, and also prevents the loss of the etch stop layer 10 during the etching process of the first mask layer region. This further reduces the weight of byproducts and polymers, and reduces the wet etching load effect of subsequent cleaning processes.

[0041] Understandably, during the first etching process, the photoresist layer 30 may suffer etching loss. Accordingly, the total etching time refers to the total time required to etch away the remaining photoresist layer 30 and the masked first mask layer area.

[0042] In one embodiment, the first mask layer 201 is a SiON layer, and the second mask layer 202 is a DARC layer. The DARC layer can adaptively adjust the etching ratio between the combined etching rate of the photoresist layer 30 and the second mask layer 202 and the etching rate of the first mask layer 201, while ensuring the required thickness of the existing photoresist layer 30 and the mask layer. This ensures that the removal of the remaining area of ​​the first mask layer does not occur earlier than the removal of the photoresist layer 30 and the second mask layer 202, thereby achieving one-step removal of the photoresist during the second etching process and avoiding over-etching of the etch stop layer 10.

[0043] Compared to the SiON / APF film layer used in existing technologies, the DARC film layer in this embodiment has better etching ratio adjustment performance and will not cause process risks such as mask collapse due to excessive mask structure 20 thickness. Specifically, the etching ratio can be achieved by adjusting etching process parameters or etching materials.

[0044] In some embodiments, the total etching time for the photoresist layer 30 and the masked second mask layer region is equal to the etching time for the remaining unmasked first mask layer region. Accordingly, refer to Figure 3S13 may include S131: co-etching the photoresist layer 30, the masked second mask layer region, and the remaining unmasked first mask layer region until the etching time reaches a preset time, thereby exposing the unmasked etch stop layer 10, and forming a photolithographic pattern in the remaining masked first mask layer region. Thus, by adjusting the etching ratio and the preset thickness, the photoresist layer 30, the masked second mask layer region, and the remaining unmasked first mask layer region can be removed simultaneously, simplifying the etching process and avoiding over-etching of the etch stop layer 10 and the formation of difficult-to-remove polymers. Understandably, when the etching ratio is 1:1, the total thickness of the photoresist layer 30 and the masked second mask layer region is consistent with the preset thickness.

[0045] In other embodiments, the total etching time of the photoresist layer 30 and the masked second mask layer region is less than the etching time of the remaining unmasked first mask layer region; correspondingly, referring to Figure 4 S13 includes S132-S133: S132: Co-etch the photoresist layer 30, the masked second mask layer region, and the remaining unmasked first mask layer region, until the photoresist layer 30 and the masked second mask layer region are removed. S133: The remaining unmasked first mask layer area is etched using a low-power etching method until the unmasked etch stop layer 10 is exposed, and the remaining masked first mask layer area forms a photolithographic pattern.

[0046] Specifically, after the photoresist layer 30 and the masked second mask layer region are etched away, a residual film layer still exists in the unmasked first mask layer region. Specifically, the etching duration in step S132 can be controlled to avoid exposing the etch stop layer 10. Then, a low-power etching method is used to etch the remaining unmasked first mask layer region at a low speed, thereby further reducing the amount of etch stop layer 10 ejected, preventing the etch stop layer 10 material from forming polymers with the photoresist, and reducing the wet etching load effect.

[0047] Understandably, when the etching ratio is 1:1, the total thickness of the photoresist layer 30 and the masked second mask layer region is less than the preset thickness.

[0048] Understandably, the electrode power of the etching method in step S132 is higher than that of the low-power etching method in step S133, thereby balancing etching efficiency and etching effect.

[0049] In some embodiments, during the etching process of the low-power etching method, the upper electrode power is 200-500W and the lower electrode power is 100-300W. By setting the etching power to the above range, the removal effect of the first mask layer 201 can be ensured while effectively reducing the loss of the etch stop layer 10 and mitigating the adhesion effect of the subsequent etch stop layer 10 material on other device structures.

[0050] In one embodiment, taking the TEHM etching of RRAM as an example, the etch stop layer 10 is a TIN layer, the first mask layer 201 of the mask structure 20 is a SION layer, and the second mask layer 202 is a DARC layer. The remaining thickness of the unmasked SION layer is controlled to be greater than or equal to a preset thickness by controlling the etching time of the first etching process. Then, the etching power of the existing process is reduced, and the etching selectivity ratio of the photoresist layer 30 / DARC layer to the SION layer is adjusted to 1:1. The remaining photoresist layer 30 / DARC layer and the remaining unmasked SION layer at the bottom are etched through the second etching process. This ensures that after the photoresist layer 30 / DARC layer is completely removed, the unmasked SION layer is just removed or still has some residue, so that the exposure of the TIN layer does not occur earlier than the removal time of the photoresist layer 30 / DARC layer. During this process, because the photoresist is removed in advance, the TI ejected later will not adhere to the photoresist, allowing for one-step removal of the photoresist in the etching chamber.

[0051] Preferably, in this embodiment, the gas pressure in the etching reaction chamber of the first etching process is 50mT-400mT, and the gas flow rate is a mixture of CHF3 and CF4 at 20-300sccm.

[0052] Preferably, in this embodiment, in the second etching process, the etching ratio of the photoresist layer 30 / DARC layer to the SION layer is 1:1, the gas pressure in the etching reaction chamber is 50-100mT, the gas flow rate is a mixture of 20-30sccm C4F8 and 20-30sccm O2, the low-frequency power (HF power) of the upper electrode is 800-1000W, and the low-frequency power (LF power) of the lower electrode is 900-1600W.

[0053] Preferably, in this embodiment, in the second etching process, the remaining unmasked SION layer is etched using a low-power etching method, and the gas flow rate in the etching reaction chamber is a mixed gas of 20-200 sccm CF4 and 20-200 sccm O2, with a reaction HF power of 100-300W and an LF power of 200-500W.

[0054] In summary, this embodiment removes photoresist in one step within the etching chamber, eliminating the need to change equipment for stripping and cleaning the photoresist layer 30. This saves on preparation costs and reduces the amount of TiN bombarded, thereby reducing the amount of polymer generated and mitigating the load effect of wet etching.

[0055] This application embodiment also provides a mask structure 20, which includes a first mask layer 201 and a second mask layer 202 sequentially stacked on the etch stop layer 10, and a photoresist layer 30 partially shielding the second mask layer 202; the mask structure 20 is applied to the etching method described above.

[0056] In a possible implementation, the etch stop layer 10 comprises a titanium-containing compound.

[0057] In a possible implementation, the material of the first mask layer 201 includes SiON.

[0058] In a possible implementation, the second mask layer 202 is a dielectric anti-reflective coating.

[0059] In a possible implementation, the material of the second mask layer 202 includes at least one of silicon oxynitride, silicon carbide nitride, and titanium oxide.

[0060] In a possible implementation, after the first etching process, the preset thickness of the remaining unmasked first mask layer area is determined based on the etching ratio between the combined etching rate of the photoresist layer 30 and the second mask layer 202 and the etching rate of the first mask layer 201 during the second etching process.

[0061] In a possible implementation, the etching ratio is 1:1, and after the first etching process, the total thickness of the photoresist layer 30 and the masked second mask layer region is less than or equal to a preset thickness.

[0062] In a possible implementation, the total etching time of the photoresist layer 30 and the masked second mask layer region is equal to the etching time of the remaining unmasked first mask layer region.

[0063] In a possible implementation, the total etching time of the photoresist layer 30 and the masked second mask layer region is less than the etching time of the remaining unmasked first mask layer region.

[0064] This application also provides a semiconductor structure, which includes the mask structure 20 described above.

[0065] This application also provides an electronic device, which is fabricated using the etching method and mask structure 20 described above.

[0066] The electronic device in this application embodiment can be selected from any electronic product or device such as mobile phone, PDA, tablet computer, laptop computer, game console, television, video compact disc (VCD), digital video disc (DVD), navigator, camera, camcorder, voice recorder, MP3, MP4, PlayStation Portable (PSP), etc., or it can be any intermediate product including the electronic device made of the above-described mask structure 20.

[0067] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, specific embodiments have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0068] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0069] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0070] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An etching method, characterized in that, include: An etch stop layer, a mask structure, and a patterned photoresist layer are provided. The mask structure includes a first mask layer and a second mask layer sequentially stacked on the etch stop layer, and the photoresist layer partially masks the second mask layer. The mask structure is subjected to a first etching process until the unmasked second mask layer area is removed and at least part of the unmasked first mask layer area remains. A second etching process is performed on the mask structure and the photoresist layer to remove the photoresist layer, the masked second mask layer area, and the remaining unmasked first mask layer area, so as to expose the unmasked etch stop layer. The total etching time of the photoresist layer and the masked second mask layer region is less than or equal to the etching time of the remaining unmasked first mask layer region.

2. The etching method according to claim 1, characterized in that, The preset thickness of the unmasked first mask layer area remaining after the first etching process is determined based on the etching ratio between the combined etching rate of the photoresist layer and the second mask layer and the etching rate of the first mask layer during the second etching process.

3. The etching method according to claim 2, characterized in that, The etching ratio is 1:1-1.5:1, and after the first etching process, the total thickness of the photoresist layer and the masked second mask layer area is less than or equal to the preset thickness.

4. The etching method according to claim 1, characterized in that, The total etching time of the photoresist layer and the masked second mask layer area is equal to the etching time of the remaining unmasked first mask layer area; The second etching process on the mask structure and the photoresist layer, to remove the photoresist layer, the masked second mask layer area, and the remaining unmasked first mask layer area, to expose the unmasked etch stop layer, includes: The photoresist layer, the masked second mask layer area, and the remaining unmasked first mask layer area are etched together until the etching time reaches a preset time, so as to expose the unmasked etch stop layer, and the remaining masked first mask layer area forms a photolithographic pattern.

5. The etching method according to claim 1, characterized in that, The total etching time of the photoresist layer and the masked second mask layer area is less than the etching time of the remaining unmasked first mask layer area; The second etching process on the mask structure and the photoresist layer, to remove the photoresist layer, the masked second mask layer area, and the remaining unmasked first mask layer area, to expose the unmasked etch stop layer, includes: The photoresist layer, the masked second mask layer region, and the remaining unmasked first mask layer region are etched together until the photoresist layer and the masked second mask layer region are removed. The remaining unmasked first mask layer area is etched using a low-power etching method until the unmasked etch stop layer is exposed, and the remaining masked first mask layer area forms a photolithographic pattern.

6. The etching method according to claim 5, characterized in that, During the etching process of the low-power etching method, the upper electrode power is 200-500W and the lower electrode power is 100-300W.

7. The etching method according to any one of claims 1-6, characterized in that, The etch stop layer comprises a titanium-containing compound.

8. The etching method according to any one of claims 1-6, characterized in that, The etching method satisfies at least one of the following characteristics: The material of the first mask layer includes SiON; The second mask layer is a dielectric anti-reflective coating.

9. The etching method according to any one of claims 1-6, characterized in that, The material of the second mask layer includes at least one of silicon oxynitride, silicon carbide nitride, titanium oxide, and carbon oxynitride.

10. A mask structure, characterized in that, The mask structure includes a first mask layer and a second mask layer sequentially stacked on an etch stop layer, wherein the photoresist layer partially masks the second mask layer; the mask structure is applied to the etching method as described in any one of claims 1-9.

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