High-precision wafer manufacturing method with photoetching morphology adjusting function

Abstract

The invention provides a high-precision wafer manufacturing method with a photoetching morphology adjusting function. The high-precision wafer manufacturing method comprises the following steps: depositing a first dielectric film layer on one surface, with a bonding pad, of a chip through a PECVD (Plasma Enhanced Chemical Vapor Deposition) process; applying photoresist to the first dielectric film layer and enabling the photoresist to form a first etching pattern; adjusting a first etching formula to enable the first dielectric film layer to have a non-through first design pattern and a first etching pattern of the photoresist to remain unchanged; only completely etching the photoresist and not further etching the first dielectric film layer by adjusting a second etching formula; controlling the etching speed of the first dielectric film layer by adjusting a third etching formula so as to enable the chip to form a through double-layer pattern along the depth direction; and forming a barrier layer / seed layer on the double-layer pattern through a PVD deposition method, and electroplating a metal copper layer to obtain a first interlayer interconnection structure. According to the invention, the tedious process steps are greatly reduced, the production efficiency is improved, and the cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor manufacturing, and particularly relates to a high-precision wafer manufacturing method with photoetching topography adjustment function. BACKGROUND

[0002] At present, in the process of integrated circuit, the pattern on the circuit is defined by photoetching process. In the process of chip manufacturing, the super-high-density multi-layer copper interconnection process is involved to complete the metal wiring structure of the interconnection between transistors and the outside of the chip. However, each time a pattern of copper interconnection is formed, the same process steps need to be repeated, resulting in complicated and lengthy overall process flow. SUMMARY

[0003] Therefore, the present application provides a high-precision wafer manufacturing method with photoetching topography adjustment function, characterized in that it comprises the following steps: step S1, depositing a first dielectric film layer on one side of the chip with a pad by PECVD process; step S2, applying photoresist to the first dielectric film layer and making the photoresist form a first etching pattern; step S3, performing first plasma dry etching by adjusting the first etching formula, so that the first dielectric film layer has a first design pattern that is not penetrated and the first etching pattern of the photoresist remains unchanged; step S4, performing second plasma dry etching by adjusting the second etching formula, which can only completely etch the photoresist and not further etch the first dielectric film layer; step S5, performing third plasma dry etching by adjusting the third etching formula, which can control the etching speed of the first dielectric film layer to form a double-layer pattern penetrating in the depth direction of the chip; step S6, forming a barrier layer / seed layer on the double-layer pattern by PVD deposition method, and electroplating a copper layer on the barrier layer / seed layer until the double-layer pattern is filled, to obtain a first interconnection structure.

[0004] In addition, preferably, the high-precision wafer manufacturing method according to the present application further comprises: step S7, depositing a second dielectric film layer on one side of the first interconnection structure with a conductive pattern by PECVD process, and repeating the above steps S2 to S5 for the second dielectric film layer to obtain a second interconnection structure including the first interconnection structure.

[0005] In addition, preferably, the high-precision wafer manufacturing method according to the present application, the photoresist has a high etching selectivity and a non-vertical topography in the etching depth direction after exposure and development.

[0006] In addition, preferably, in the high-precision wafer manufacturing method according to the present application, step S5 further comprises: step S51, after forming the double-layer pattern, removing the photoresist and etching by-products by plasma ashing.

[0007] In addition, preferably, in the high-precision wafer manufacturing method according to the present application, step S6 further comprises: step S61, after filling the double-layer pattern, removing the excess metal copper by a face copper chemical mechanical polishing process to form a planar surface.

[0008] In addition, preferably, in the high-precision wafer manufacturing method according to the present application, in step S2, the processing time of the plasma etching is controlled to only consume the photoresist at positions with a critical dimension less than a set standard, while retaining the photoresist at positions with a critical dimension greater than the set standard.

[0009] In addition, preferably, in the high-precision wafer manufacturing method according to the present application, in step S2, the processing time of the plasma etching is controlled to enable the pattern of the photoresist to be transferred to the dielectric film layer, thereby forming a second pattern with a larger critical dimension, and in the etching process of the pattern with the larger critical dimension, the pattern with the smaller critical dimension continues to be etched downward under the action of the plasma until the double-layer pattern contacts the underlying metal layer, to achieve subsequent electrical leads.

[0010] Through the present application, the process flow is greatly optimized, the number of steps in the overall process flow is reduced, the production efficiency is improved, and the manufacturing cost is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 FIG. 1 is a schematic diagram illustrating a multilayer copper interconnection process flow.

[0012] Figure 2 FIG. 2 is a schematic diagram illustrating an improved multilayer copper interconnection process flow.

[0013] Figure 3 FIG. 3 is a schematic diagram illustrating a multilayer copper interconnection process flow according to the present application.

[0014] Figure 4 FIG. 4 is a schematic diagram illustrating a 3-step plasma dry etching process flow according to the present application.

[0015] Figure 5 FIG. 5 is a schematic diagram illustrating a mixed bonding via / pad structure according to the present application.

[0016] Figure 6 FIG. 6 is a schematic diagram illustrating a photoresist anamorphic topography according to the present application.

[0017] Figure 7 is a schematic diagram illustrating the profile of the inventive anisotropic photoresist pattern, showing the effective and ineffective areas.

[0018] Figure 8 is a schematic diagram illustrating the requirement criteria for etch selectivity. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Other embodiments or variants obtained by those of ordinary skill in the art without creative effort based on the embodiments in the present application are within the scope of protection of the present application.

[0020] At present, in the process of integrated circuits, the pattern on the circuit is defined by a photoetch process. In the process of chip manufacturing, a super-high-density multi-layer copper interconnection process is involved to complete the metal wiring structure of the interconnection between transistors and the outside of the chip. A common multi-layer copper interconnection process flow diagram is shown in Figure 1 .

[0021] The process flow is described as follows:

[0022] After the preceding process steps are completed, a continuous metal layer is mainly formed on the wafer surface. Next, through subsequent metal re-wiring process, the electrical performance of the metal pad is effectively led out to realize the interconnection and functional expansion of the subsequent circuit.

[0023] A dielectric film layer is deposited on the surface by using a PECVD process. The film layer here plays a role in the later.

[0024] The photoetch process is used, that is, the coating, exposure, and development process of photoresist is performed to form the corresponding pattern on the surface.

[0025] The plasma dry etching technology is used to etch the dielectric layer to form the required pattern structure with the photoresist pattern as a mask, and the etching stops at the front layer metal.

[0026] The photoresist ashing process and cleaning process are used, and the purpose is to remove the residual photoresist and by-products generated by etching.

[0027] The PVD process of the barrier layer and the seed layer is performed. The role of the barrier layer is to prevent copper from diffusing into the dielectric layer (for example, the dielectric layer of Low K material) to avoid the performance degradation and reliability problems caused by copper diffusion. The role of the seed layer is to provide a continuous, conductive, and well-adhered base layer for the subsequent electroplating process to ensure the integrity and good coverage of the subsequent electroplated copper.

[0028] Through the electrochemical plating process, copper metal is deposited inside the pre-etched pattern to realize the filling of metal. The plated copper layer is in good contact with the bottom metal layer, thereby realizing the effective lead-out of the bottom electrical signal.

[0029] Through the chemical mechanical polishing process, the excess copper metal on the surface is removed until only the copper metal in the pattern area is left, thereby completing the required metal pattern structure and internal metal filling.

[0030] By repeating the above steps, copper metal of various patterns can be realized in sequence, and the construction of the electrical interconnection and wiring structure of multiple layers of copper metal is formed, thereby meeting the functional requirements of complex integrated circuits.

[0031] As can be seen from the above process flow, the same process steps need to be repeated for each copper interconnection pattern formed, resulting in a cumbersome and lengthy overall process flow. In view of this problem, the above process flow is optimized to reduce the number of steps in the overall process flow, thereby improving production efficiency and reducing costs.

[0032] The number of process steps required to fabricate two-layer copper metal interconnection using the above two schemes is as follows:

[0033] First: twice PECVD, twice photolithography, twice etching, twice B&S PVD, twice ECP, and twice Cu CMP.

[0034] Second: once PECVD, twice photolithography, three times etching, once Barc coating, once B&S PVD, once ECP, and once Cu CMP.

[0035] As can be seen, the improved scheme can effectively reduce the process steps, but there is still room for optimization. Through further improvement of the present application, the process flow can be further simplified on the basis of the existing process, thereby significantly improving production efficiency and reducing manufacturing costs. Therefore, the first purpose of the present application, i.e., the primary technical problem, is to reduce the process steps through optimization, thereby improving production efficiency and reducing manufacturing costs.

[0036] The second purpose of the present application is to address the problem that in the current integrated circuit manufacturing process, if a specific pattern needs to be fabricated on a chip, a special photomask must be made. If the size (CD) of the pattern needs to be changed, the corresponding size of the photomask must be redesigned and manufactured. That is, even if the pattern itself does not change, only the size is different, the photomask needs to be replaced accordingly. This not only increases the manufacturing cost, but also reduces the production efficiency. Therefore, the present application aims to solve this problem, so that even if the CD changes, the same photomask can be used for manufacturing when the pattern is the same, thereby improving the flexibility and efficiency of production.

[0037] Currently, the commonly used manufacturing process can generally fine-tune the critical dimension (CD) of the photoresist pattern by adjusting the photoetching (photoetching) process parameters, that is, the CD of the photoresist pattern is slightly larger or smaller. Subsequently, in the plasma dry etching process, the photoresist pattern can be used as a mask to further manufacture the circuit pattern. Because the change of the pattern formed by the previous photoetching can be directly transmitted to the final etching pattern, different CD circuit structures can be realized. In addition, by adjusting the etching process parameters (also known as "etching formula"), even under the same photoetching pattern conditions, the final etching CD will change, thereby forming different pattern CDs. Therefore, by using the same mask and combining flexible adjustment of the photoetching and etching conditions, the CD of the final pattern can be finely adjusted to meet different manufacturing requirements.

[0038] However, the existing method of adjusting the photoetching (photoetching) or etching (etching) process conditions to achieve CD change still has a limited adjustment range, which is difficult to meet the demand of a larger range of CD adjustment, and it is still not possible to effectively achieve the adjustment target in a wider CD range using the same mask. In contrast, the present application provides an innovative solution that can achieve a larger range of CD adjustment under the same mask, thereby significantly improving the flexibility of the manufacturing process and the adaptability of the process. Therefore, the second purpose of the present application, that is, the second technical problem that the present application expects to solve, is how to achieve a larger range of CD adjustment under the same mask.

[0039] The deficiencies of the foregoing prior art solutions are as follows: when the multilayer copper interconnection structure is manufactured, the process steps are relatively more, although certain improvements have been made (such as Figure 2 ), there is still room for optimization. Therefore, through the present application, process innovation will continue to be carried out to reduce the overall required process steps, thereby improving production efficiency and reducing manufacturing costs.

[0040] Currently, using the same mask can usually only achieve a single CD pattern, although the CD of the final pattern can be fine-tuned by adjusting the photoetching and etching process parameters, but the adjustment range is relatively limited. Therefore, the present application proposes a new technical solution that can achieve a larger range of CD adjustment under the same mask conditions, thereby significantly improving the flexibility and adaptability of the process.

[0041] The multilayer copper interconnection process flow of the present application is shown in Figure 3 . The details are as follows:

[0042] Similar to the above process flow, the pre-process is completed.

[0043] PECVD process is used to deposit a dielectric film layer,

[0044] A photoetching process, i.e. coating, developing and exposing photoresist, is performed to finally make the photoresist into a pattern as shown in Fig. Figure 3

[0045] A first step of plasma dry etching is performed, at this time, the etching formula is selected to etch the dielectric film layer only and almost not etch the photoresist.

[0046] A second step of plasma dry etching is performed, at this time, the etching formula is selected to etch the photoresist only and the etching rate of the dielectric film layer is low.

[0047] After the photoresist is etched, a third step of plasma dry etching is performed to make a second pattern, meanwhile, the first pattern formed in the first step is etched downward. After the third step is completed, the second pattern is formed and the first pattern contacts the bottom metal.

[0048] A plasma ashing process and a cleaning process are performed to remove the photoresist and etching by-products.

[0049] A barrier layer and a seed layer PVD deposition process is performed.

[0050] A Cu ECP plating process is performed to fill the metal copper in the formed pattern.

[0051] A surface copper chemical mechanical polishing Cu CMP process is performed to remove the excess metal copper on the surface. Thus, the two-layer metal copper interconnection is completed.

[0052] The above steps are repeated to make a multi-layer metal copper interconnection structure.

[0053] In addition, the details of the present application are further described as follows.

[0054] 1. The present application is directed to the preparation of two-layer metal copper interconnection structure, and the preparation process of two-layer metal copper interconnection structure in the first and second process mode described above, the number of specific process steps required is as follows:

[0055] First: twice PECVD, twice photoetching, twice etching, twice B&S PVD, twice ECP, twice Cu CMP.

[0056] Second: once PECVD, twice photoetching, three times etching, once Barc coating, once B&S PVD, once ECP, once Cu CMP.

[0057] The present application: once PECVD, once photoetching, three times etching, once B&S PVD, once ECP, once Cu CMP.

[0058] ​We can see that the number of process steps is reduced, thus improving production efficiency and reducing manufacturing cost.

[0059] 2、The photoetching process in the application, the photoresist pattern formed at last is not the conventional vertical pattern, but the special pattern shown in the figure Figure 3-3 , which is characterized by different CD at different positions, thus making it possible to produce patterns with different CD in the etching process.

[0060] 3、In the step of plasma dry etching 1, a high selectivity of photoresist etching is needed, thus the photoresist with small CD acts as an effective mask layer, forming a pattern with small CD.

[0061] 4、In the step of plasma dry etching 2, a formula for etching photoresist is needed, thus the photoresist is consumed. At this time, the photoresist in the position vertically contacted with plasma is consumed, but the position with the smallest CD is the "sharp corner" pattern, thus it is consumed first. At this time, the photoresist at other positions, such as the top of the photoresist, is also consumed, but it is a plane, thus the consumption rate is slow. Therefore, the time of plasma etching is controlled, only the photoresist with small CD is consumed, and when the photoresist with large CD is consumed to the position needed, the step of plasma dry etching 2 is stopped.

[0062] 5、The process of plasma dry etching 3 is similar to that of plasma etching 1, with high selectivity of photoresist etching, thus the photoresist pattern can be successfully transferred to the dielectric film, thus forming a second pattern with large CD. In the process of etching the pattern with large CD, the pattern with small CD also continuously receives the action of plasma, and continues to etch downward. Therefore, after the pattern 2 is produced, the pattern 1 contacts the underlying metal pattern, thus the patterns 1 and 2 are produced, and the subsequent electrical property can be led out.

[0063] 6、The core of the scheme is to adjust the pattern of photoresist by the process of plasma dry etching 2, thus adjusting the CD of the photoetching mask layer of the second pattern, thus controlling the CD of the second photoetching pattern, thus forming two patterns with different CD. The principle diagram is shown in the figure Figure 4 .

[0064] 7、The present application can prepare double-layer patterns with the same geometric shape but different critical dimensions (CD), and thus can be applied to advanced packaging technology with differentiated requirements on CD, such as via / pad structure design in hybrid bonding. In this structure, the two metal layers can be prepared into the same geometric shape (such as square or circle) to meet the design and manufacturing needs. However, there are significant differences in the functions and process requirements of the two.

[0065] For a via, its main function is to lead out the electrical properties of the lower metal. Since the CD of the lower metal is smaller, in order to ensure the accuracy of the electrical connection, the size of the via must be correspondingly reduced and higher process precision must be maintained in order to accurately complete the electrical lead-out. In addition, if the size of the via is too large, it may also cause connection with metal lines in the same layer that do not need to be connected, forming a short circuit or electrical property interference, which must be avoided. Therefore, the miniaturization of the via size not only helps to accurately lead out the electrical properties, but also effectively avoids the risk of accidental shorting or misconnection with metal in the same layer that does not need to be connected.

[0066] For a pad, the size needs to be relatively enlarged, which is mainly based on two considerations:

[0067] First, there is a certain alignment error in the subsequent bonding process. In order to ensure reliable electrical connection between the pads after wafer stacking, sufficient overlapping area needs to be reserved. Therefore, if the size of the pad is too small, it will cause the process window to be too narrow during the bonding process, and it is easy to cause the pad to fail to contact due to excessive alignment deviation, ultimately causing electrical property failure.

[0068] In addition, after the pad is completed, copper chemical mechanical polishing (Cu CMP) needs to be performed to form a bowl and dish topography. If the size of the pad is too small, it is difficult to accurately control its surface topography during the CMP process, resulting in difficulty in achieving the bowl and dish topography, thereby affecting the subsequent bonding effect. Therefore, by using the same geometric pattern design for the two metal layers, but optimizing the CD of the via and the pad according to the process requirements, the electrical lead-out and the process window of the subsequent process can be considered, thereby meeting the requirements of hybrid bonding in advanced packaging. The present application is applied to a hybrid bonding via / pad structure diagram as shown in Figure 5 .

[0069] 8、After lithography is completed, the final topography of the photoresist can be formed into various irregular profiles through process design to meet the process needs of the present application. Some irregular topography of the photoresist after lithography is shown in Figure 6The photoresist pattern after the lithography is shown in FIG. 2. The photoresist pattern is formed by the same mask, and the CD of the photoresist pattern is controlled by adjusting the exposure dose, focus offset, and numerical aperture (NA). The photoresist pattern is then developed to form a pattern with different CDs, as shown in FIG. 3. Figure 6 The range of different CDs that can be achieved by this method is shown in FIG. 4. Figure 6 The green arrows in FIG. 4 show the flexibility and feasibility of this method in adjusting the CD of the pattern.

[0070] 9. This method can also be extended to more layers of patterns with different CDs, such as 3 layers, 4 layers, etc. However, it is important to note that the CD of the metal pattern in the later layers should not be smaller than the CD of the metal pattern in the previous layers.

[0071] 10. This method can also be used to form a special photoresist pattern after lithography, and then perform different etching adjustments on the photoresist using the plasma dry etching method 2, to finally obtain patterns with different CDs. The range of CD changes is consistent with that shown in FIG. 4. Figure 6

[0072] The special photoresist pattern formed after lithography in this method, where "special" refers to different CDs at different depths. The effective area is the smallest CD, and the photoresist with a larger CD above the smallest CD is the effective area. The area below the smallest CD area does not determine the final CD of the pattern, which is the ineffective area. Therefore, the special photoresist in this method needs to have a certain thickness of effective area. The schematic diagram is shown in FIG. 5. Figure 7

[0073] In the optimization method for manufacturing two CD patterns in this method, the plasma etching is performed in three steps. The first step is to etch the dielectric film, and the photoresist has a high selectivity ratio to form the first pattern. The second step is to etch the photoresist, and the etching rate of the photoresist is very fast, which is to define the CD of the second pattern. The third step is to etch the dielectric layer again, and the photoresist has a high selectivity ratio to form the second pattern, while the first pattern continues to etch and stops on the lower metal layer.

[0074] This method can also be used to manufacture patterns with different critical dimensions (CD) using the same mask. Specifically, after the lithography step is completed, a photoresist pattern with a special structure is formed. Then, different plasma dry etching methods 2 are used to convert the photoresist into a mask layer with different CDs, which serves as a mask for subsequent pattern transfer. Subsequently, plasma dry etching 3 is used to perform pattern transfer etching on the substrate. Through the above method, patterns with different CD ranges can be manufactured using the same mask.​​

[0075] In addition, it should be noted that the etching selectivity of the photoresist in the present application is described as follows:

[0076] If the first step is to finally obtain the size of CD1, the target etching depth is T2, and the maximum loss of the thickness of the photoresist is T1, then the selectivity of the material / photoresist to be etched should be greater than or equal to T2 / T1.

[0077] If the second step is to finally obtain the size of CD2, the target etching depth is T4, and the maximum loss of the thickness of the photoresist is T3, then the selectivity of the material / photoresist to be etched should be greater than or equal to T4 / T3.

[0078] It should be noted that the relational terms herein such as first and second and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any such actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises... a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.

[0079] Each of the embodiments in the specification is described in a relevant manner, and the same and similar parts between the embodiments can be referred to each other, and each embodiment focuses on the difference from other embodiments.

[0080] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

[0081] The above embodiments of the present application are only examples for clearly illustrating the present application, and are not limitations on the embodiments of the present application. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, it is not necessary or possible to exhaust all the embodiments. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application should be included in the protection scope of the claims of the present application.

Claims

1. A high-precision wafer manufacturing method with photolithography topography adjustment function, characterized in that, include: Step S1: Deposit a first dielectric film layer on the side of the chip with pads using a PECVD process; Step S2: Apply photoresist to the first dielectric film layer and make the photoresist form a first etched pattern; Step S3: Perform first plasma dry etching by adjusting to the first etching formula, so that the first dielectric film layer has a non-penetrating first design pattern and the first etching pattern of the photoresist remains unchanged. Step S4: Perform a second plasma dry etching by adjusting the second etching formula, wherein the second etching formula can completely etch the photoresist without further etching the first dielectric film layer. Step S5: Perform third plasma dry etching by adjusting the third etching formula. The third etching formula can control the etching rate of the first dielectric film layer so that the chip forms a through double-layer pattern along the depth direction. Step S6: A barrier layer / seed layer is formed on the double-layer pattern by PVD deposition, and a copper layer is electroplated on the barrier layer / seed layer until the interior of the double-layer pattern is filled to obtain the first interlayer interconnect structure.

2. The high-precision wafer manufacturing method according to claim 1, characterized in that, Also includes: Step S7: Deposit a second dielectric film layer on the conductive patterned side of the first interlayer interconnect structure using a PECVD process. Repeat steps S2 to S5 for the second dielectric film layer to obtain a second interlayer interconnect structure including the first interlayer interconnect structure.

3. The high-precision wafer manufacturing method according to claim 1, characterized in that, The photoresist has a high etch selectivity and, after exposure and development, exhibits a non-perpendicular morphology in the etch depth direction.

4. The high-precision wafer manufacturing method according to claim 1, characterized in that, Step S5 also includes: Step S51, after forming the double-layer pattern, removing the photoresist and etching byproducts by plasma ashing.

5. The high-precision wafer manufacturing method according to claim 1, characterized in that, Step S6 also includes: Step S61, after filling the interior of the double-layer pattern, performing a surface copper chemical mechanical polishing process on the electroplated copper layer to remove excess copper and form a flattened surface.

6. The high-precision wafer manufacturing method according to claim 1, characterized in that, In step S2, the processing time of plasma etching is controlled so that only the photoresist in the position where the critical size is smaller than the set standard is consumed, while the photoresist in the position where the critical size is larger than the set standard is retained.

7. The high-precision wafer manufacturing method according to claim 1, characterized in that, In step S2, the plasma etching time is controlled so that the pattern of the photoresist can be transferred to the dielectric film layer, thereby forming a second pattern with a larger critical size. During the etching process of the pattern with a larger critical size, the pattern with a smaller critical size continues to be etched downwards under the action of plasma until the double-layer pattern contacts the metal layer below to achieve subsequent electrical lead-out.

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