Semiconductor structure comprising substrate with silicon-coated insulating layer and manufacturing method thereof

Abstract

The invention discloses a semiconductor structure comprising a silicon-coated insulating layer substrate and a manufacturing method thereof, the semiconductor structure comprising the silicon-coated insulating layer substrate comprises a material layer, a middle area and two edge areas are defined on the material layer, the middle area is located between the two edge areas, and the middle area is located between the two edge areas. An oxide layer and a silicon layer are stacked on the material layer from bottom to top, wherein the thickness of the silicon layer in the middle region is greater than the thickness of the silicon layer in the two edge regions. The semiconductor structure has the advantages that the interface capacitance is reduced, the matrix impedance is reduced, the influence of drain electrode leakage current caused by the grid electrode is reduced, the closing capacitance is high, the static power consumption is reduced, and the element quality is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, and in particular, to a semiconductor structure with a special-shaped silicon-on-insulator substrate and a manufacturing method thereof, which has the advantages of reducing interface capacitance, reducing substrate impedance, reducing the influence of gate-induced drain leakage current, having high off-capacitance, reducing static power consumption, and improving device quality. BACKGROUND

[0002] Silicon on insulator (SOI) technology is widely used in the field of semiconductor. The key feature of this technology is to place an insulating layer (usually silicon oxide) between the silicon substrate and the active layer of the chip, thereby improving the electrical performance and performance of the chip.

[0003] SOI technology brings many advantages in manufacturing process. First, traditional semiconductor elements are built on a single-crystal silicon substrate, while SOI technology allows elements to be built on an insulating layer, which effectively eliminates the negative impact of impurities on the substrate on element performance. This makes the element operate faster, consume less power, and also increases the ability to resist radiation and noise, which is very important for some applications with strict reliability requirements.

[0004] Second, SOI technology also provides better element insulation. Since the active layer is covered by an insulating layer, the crosstalk effect between elements is significantly reduced, thereby improving the integration and performance of integrated circuits. At the same time, SOI technology also reduces the capacitive coupling between elements, further improving the operating speed and power efficiency of the elements.

[0005] However, SOI technology also faces some challenges and shortcomings. First, the cost of manufacturing SOI wafers is usually high because an additional insulating layer processing step is required in the manufacturing process. Second, the insulating layer in SOI technology may impose some restrictions on element design, such as in some high-power applications, the insulating layer may affect heat dissipation, limiting the power density of the element.

[0006] In summary, SOI technology, as an important semiconductor manufacturing technology, has significant advantages, including excellent electrical performance and performance. However, the cost of manufacturing process and the limitations of element design are still challenges that need to be overcome. SUMMARY

[0007] The present application provides a semiconductor structure comprising a silicon-on-insulator substrate, comprising a material layer, which defines an intermediate region and two edge regions, wherein the intermediate region is located between the two edge regions, an oxide layer and a silicon layer are stacked from bottom to top on the material layer, wherein the thickness of the silicon layer in the intermediate region is greater than the thickness of the silicon layer in the two edge regions.

[0008] The present application also provides a method for manufacturing a semiconductor structure comprising a silicon-on-insulator substrate, comprising providing a material layer, which is defined with a middle region and two edge regions, wherein the middle region is between the two edge regions, forming an oxide layer and a silicon layer stacked on the material layer from bottom to top, forming a mask layer on the silicon layer, and the mask layer is in the middle region, and performing an oxygen ion doping step to pass oxygen ions through the silicon layer.

[0009] The present application also provides a method for manufacturing a semiconductor structure comprising a silicon-on-insulator substrate, comprising providing a material layer and a silicon layer, which are defined with a middle region and two edge regions respectively, wherein the middle region is between the two edge regions, forming an oxide layer on the material layer, forming a first mask layer on the middle region of the silicon layer, performing a first etching step on the oxide layer to form a recessed portion in the middle region of the oxide layer, performing a second etching step on the silicon layer to form a protruding portion in the middle region of the silicon layer, and turning over the silicon layer so that the recessed portion on the oxide layer and the protruding portion on the silicon layer are combined with each other.

[0010] The present application provides a semiconductor structure comprising a silicon-on-insulator substrate, which comprises a silicon-on-insulator substrate with a special shape, the oxide layer in the middle region has a recessed portion, so that the thickness of the silicon layer in the middle portion is larger, and the thickness of the silicon layer in the edge region remains unchanged. In this way, the thickness of the silicon layer under the gate is larger, which can provide more space for storing charges, but the thickness of the silicon layer at the source / drain position remains unchanged. Therefore, the present application has the following advantages: 1. reducing the interface capacitance; 2. reducing the substrate impedance; 3. reducing the influence of gate-induced drain leakage (GIDL); 4. compatible with existing technology and no additional photomask is needed; 5. high off-capacitance and low static power consumption; 6. improving device quality. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to make the following text easier to understand, reference can be made to the accompanying drawings and detailed written description when reading the present application. The specific embodiments of the present application are illustrated in detail in the text herein and reference is made to the corresponding drawings, in order to explain the principles of the specific embodiments of the present application and to describe the effects of the specific embodiments of the present application. In addition, in order to make the drawings clear, the features in the drawings can not be drawn according to the actual proportions, so the sizes of some features in the drawings can be intentionally enlarged or reduced.

[0012] Figure 1 A cross-sectional view of a semiconductor structure comprising a silicon-on-insulator (SOI) substrate according to an embodiment of the present application;

[0013] Figure 2FIG. 1 is a cross-sectional view of a semiconductor structure including a silicon-on-insulator (SOI) substrate according to an embodiment of the present application;

[0014] Figures 3 to 5 FIG. 2 is a cross-sectional view of a semiconductor structure including a silicon-on-insulator (SOI) substrate according to another embodiment of the present application;

[0015] Figures 6 to 11 FIG. 3 is a cross-sectional view of a semiconductor structure including a silicon-on-insulator (SOI) substrate according to another embodiment of the present application.

[0016] Symbol Description

[0017] 10: substrate

[0018] 10A: silicon layer

[0019] 10B: silicon oxide layer

[0020] 10C: material layer

[0021] 11: substrate

[0022] 11A: silicon layer

[0023] 11B: oxide layer

[0024] 11C: material layer

[0025] 12: well region

[0026] 14: dielectric layer

[0027] 16: dielectric layer

[0028] 18: dielectric layer

[0029] 20: spacer

[0030] 21: recess

[0031] 22: mask layer

[0032] 24: oxygen-rich region

[0033] 26: silicon oxide layer

[0034] 30: material layer

[0035] 32: silicon layer

[0036] 34: oxide layer

[0037] 36: mask layer

[0038] 38: mask layer

[0039] 40: protrusion

[0040] 42: recess

[0041] 44: oxide layer

[0042] C: intermediate region

[0043] C1: intermediate region

[0044] C2: intermediate region

[0045] CT: contact structure

[0046] D: drain region

[0047] D1: thickness

[0048] D2: height

[0049] D3: height

[0050] E: edge region

[0051] E1: edge region

[0052] E2: edge region

[0053] G: gate

[0054] LDD: lightly doped drain

[0055] M1: metal layer

[0056] M2: metal layer

[0057] P1: doping step

[0058] P2: annealing step

[0059] P3: etching step

[0060] P4: etching step

[0061] S: source region

[0062] STI: shallow trench isolation

[0063] T: transistor

[0064] V1: contact pillar DETAILED DESCRIPTION

[0065] In order to enable those skilled in the art to better understand the present application, the preferred embodiments of the present application are listed below, and the effects and contents of the present application are described in detail with reference to the accompanying drawings.

[0066] For ease of explanation, the drawings for the present application are only schematic and are non-to-scale with respect to dimensions of the components they depict. The relative dimensions of the various elements in the drawings are intended to explain the concepts of the present application more clearly and are not necessarily drawn to scale. In the description of the drawings, relative positions of the various elements in the drawings are intended to represent relative positions of the objects, and thus can be reversed to present the same components, which should all be within the scope of the present disclosure.

[0067] Although the present application uses first, second, third, etc. words to describe elements, components, regions, layers, and / or sections, it should be understood that these words are used only to distinguish one element, component, region, layer, and / or section from another element, component, region, layer, and / or section. These words are not intended to imply or represent any previous ordinal number or any order of arrangement or manufacture. Thus, the first element, component, region, layer, or section discussed below can also be the second element, component, region, layer, or section.

[0068] The terms "about" or "substantially" as used herein generally mean within 20% of a given value or range, such as within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, i.e., the meaning of "about" or "substantially" is implied where not specifically stated.

[0069] The terms "coupled", "coupling", "electrically connected" as used herein include any direct and indirect electrical connection means. For example, if a first component is described as being coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

[0070] Although the following describes the present application by way of specific embodiments, the inventive principles of the present application can also be applied to other embodiments. In addition, specific details are omitted in order not to obscure the spirit of the present application, which is within the knowledge of one of ordinary skill in the art.

[0071] Figure 1 A cross-sectional view of a semiconductor structure including a silicon-on-insulator (SOI) substrate according to an embodiment of the present application is shown. As shown in FIG. 1, the semiconductor structure 100 includes a substrate 110, a buried oxide layer 120, a semiconductor layer 130, a gate dielectric layer 140, a gate electrode 150, a spacer 160, a source region 170, a drain region 180, and a gate electrode 150. Figure 1As shown, a substrate 10 is provided, which is a silicon on insulator (SOI) substrate including a silicon layer 10A on an insulating layer, where the silicon layer 10A is of silicon and the insulating layer is of, for example, silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the silicon layer 10A is on a silicon oxide layer 10B and a material layer 10C, where the material layer 10C can be a silicon layer or a silicon oxynitride layer, but the present application is not limited thereto. Then, a transistor T is formed above the silicon layer 10A, where the transistor T includes a gate G, a source region S and a drain region D. In more detail, a well region 12, the source region S, the drain region D and a lightly doped drain LDD are formed in the silicon layer 10A by doping, and a shallow trench isolation STI is formed outside the source region S and the drain region D. In addition, in this embodiment, if the transistor is an N-type transistor, the source region S, the drain region D and the lightly doped drain LDD are doped with N-type ions, and the well region 12 is doped with P-type ions. However, the present application is not limited thereto. The material of the shallow trench isolation STI is, for example, silicon oxide, which is the same as the material of the silicon oxide layer 10B. Figure 1

[0072] The above-mentioned structures can further include a plurality of layers of dielectric layers, and the dielectric layers can further include a plurality of elements, such as a gate of a transistor, a contact structure or a conductive structure. In more detail, a dielectric layer 14, a dielectric layer 16 and a dielectric layer 18 are formed on the silicon layer 10A, where the dielectric layers 14, 16 and 18 are of, for example, silicon oxide, silicon nitride, silicon oxynitride, an ultra low k (ULK) material, a low-k material, a fluorosilicate glass (FSG) or the like, but the present application is not limited thereto. The gate G is flanked by a spacer 20, and the gate G and the spacer 20 are in the dielectric layer 14, where the gate G can be of polysilicon or a metal, and the gate G can further include a gate dielectric layer (not shown) below the gate G, and the spacer 20 is of, for example, silicon oxide, silicon nitride or silicon oxynitride. In addition, the dielectric layer 14 further includes a contact structure CT electrically connecting the source region S and the drain region D, and the contact structure CT further connects a metal layer M1, a contact pillar V1 and a metal layer M2 in the dielectric layers 16 and 18 above, where the metal layers and the contact pillar are used to connect the transistor T to other elements, such as various active or passive elements to be formed later, or to other chips in a hybrid bond.

[0073] It is worth noting that other dielectric layers or metal layers can be further formed above the metal layer M2. Figure 1 ​The transistor structure and other components described herein are mostly prior art of this invention. Therefore, the parts not described in detail herein can be referred to existing transistor structures or related components and will not be repeated here.

[0074] According to the applicant's experiments, the structure and size of the silicon-coated insulating substrate will affect the performance of semiconductor devices (such as transistors), especially the thickness D1 of the silicon layer 10A, which is a significant influencing factor. Specifically, in some embodiments, the thickness of the silicon layer 10A is, for example, around 750 angstroms, which is relatively large. Because the gate G of the transistor T is located above the silicon layer 10A and the silicon layer 10A is relatively thick, there is sufficient silicon layer space below the gate G to store charge, avoiding gate-induced drain leakage (GIDL) and affecting the electrical performance of the device. However, the large thickness of the silicon layer 10A also has corresponding disadvantages. For example, from a cross-sectional view, the interface area between the silicon layer 10A and the source region S, drain region D, or lightly doped drain LDD is large (due to the large thickness of the silicon layer 10A). Therefore, charge easily flows out from the interface between the source region S, drain region D, or lightly doped drain LDD, resulting in a low turn-off capacitance (Coff) and high power consumption of the semiconductor device.

[0075] However, reducing the thickness of the 10A silicon layer also introduces other drawbacks. For example... Figure 1 For example, if the thickness of the silicon layer 10A is reduced to about 500 angstroms, although the turn-off capacitance (Coff) of the semiconductor device can be increased and the power consumption reduced, there are disadvantages such as the smaller charge storage space under the gate G (because the thickness of the silicon layer 10A is smaller), which can easily cause gate-induced drain leakage (GIDL), less space for charge storage, stronger short-channel effect (SCE), increased turn-off current (Ioff), and lower breakdown voltage.

[0076] In other words, regardless of whether the thickness of the silicon layer 10A is large (approximately 750 angstroms) or small (approximately 500 angstroms), there will be corresponding disadvantages. This invention proposes an improved silicon-coated insulating layer substrate structure that combines the advantages of the aforementioned embodiments with thicker and thinner silicon layers, while minimizing the disadvantages of both embodiments, as detailed in the following paragraphs.

[0077] In the following paragraphs, since the structure of the silicon-on-insulator substrate is emphasized, only some of the elements, such as the silicon layer 10A, the silicon oxide layer 10B, the material layer 10C, the source region S, the drain region D, the lightly doped drain LDD, the shallow trench isolation STI, the spacer 20, and the transistor T, are drawn in the corresponding figures. The rest of the elements, such as the dielectric layer, the contact structure, the metal layer, and the like, are omitted and not drawn in the figures, which are described herein.

[0078] In the following, different embodiments of the silicon-on-insulator structure and the method of fabricating the same will be described. For simplicity of the description, the following description mainly focuses on the differences between the embodiments, and the same parts are not described repeatedly. In addition, the same elements in the embodiments of the present application are denoted by the same reference numerals for the purpose of mutual comparison between the embodiments.

[0079] Figure 2 A cross-sectional view of a semiconductor structure including a silicon-on-insulator (SOI) substrate according to another embodiment of the present application is shown. As shown, in this embodiment, a substrate 11 is provided, which is a silicon-on-insulator substrate and includes, from bottom to top, a material layer 11C, an oxide layer 11B, and a silicon layer 11A. The silicon layer 11A, the oxide layer 11B, and the material layer 11C described herein have similar or the same features as the silicon layer 10A, the oxide layer 10B, and the material layer 10C described in the first embodiment, respectively, and the features are not described repeatedly. However, the shapes of some of the elements are slightly different from the cross-sectional view, which will be described in the following paragraphs. Figure 2

[0080] The substrate 11 defines a middle region C and two edge regions E, the middle region C is located between the two edge regions E, and a gate G is located in the middle region C. The width of the middle region C is approximately equal to the width of the gate G, but the present application is not limited thereto, and the width of the middle region C can be adjusted according to actual needs.

[0081] In this embodiment, the silicon oxide layer 11B in the middle region C has a recess 21, which is located directly below and corresponds to the position of the gate G. More specifically, from the top view or the cross-sectional view, the defined range of the gate G and the range of the recess 21 have more than 90% overlap. The silicon layer 11A is located on the silicon oxide layer 11B and fills the recess 21. Therefore, for the silicon layer 11A, the thickness of the silicon layer 11A in the middle region C is larger, and the thickness of the silicon layer 11A in the edge regions E remains unchanged. For example, in the middle region C, the thickness of the silicon layer 11A is equal to the distance between the bottom surface of the gate G and the bottom surface of the recess 21 in the vertical direction, i.e. Figure 2 Figure 2 ​​The indicated height D2, in this embodiment, is approximately 750 angstroms, but is not limited to this. On the other hand, the thickness of the silicon layer 11A within the edge region E remains constant; that is, the thickness of the silicon layer 11A within the edge region E is less than the thickness of the silicon layer 11A within the middle region C. Figure 2 For example, within the edge region E, the thickness of the silicon layer 11A is equal to the vertical distance from the bottom surface of the gate G to the top surface of the silicon oxide layer 11B, i.e. Figure 2 The indicated height D3 is approximately 500 angstroms in this embodiment, but is not limited to this.

[0082] In this embodiment, the semiconductor structure includes a silicon-coated insulating layer substrate with a special shape, wherein the thickness of the silicon layer 11A is larger in the middle region C and smaller in the edge region E. Therefore, there is sufficient space below the gate G to store charge, which has the advantage of being less prone to gate-induced drain leakage (GIDL). At the same time, the interface area between the silicon layer and the source region S, drain region D, and lightly doped drain LDD in the edge region E is small (related to the thickness of the silicon layer), thus also having advantages such as high turn-off capacitance (Coff) and low power consumption. In other words, the semiconductor structure of this embodiment combines... Figure 1 The advantages of the two embodiments shown.

[0083] Figures 3 to 5 A cross-sectional schematic diagram illustrating the process of fabricating a semiconductor structure including a silicon-coated insulating layer substrate according to an embodiment of the present invention is shown. Figure 3 As shown, a substrate 11 is provided, comprising a stacked structure of a material layer 11C, an oxide layer 11B, and a silicon layer 11A. The material characteristics of the material layer 11C, the oxide layer 11B, and the silicon layer 11A described herein can be referred to the above. Figure 2 The materials mentioned above will not be repeated here.

[0084] like Figure 4 As shown, a mask layer 22 is formed on the silicon layer 11A of the substrate 11, wherein the mask layer 22 is located in the central region C. Next, a doping step P1 is performed, in which oxygen ions (O+) are doped into the silicon layer 11A. It is worth noting that the doping depth of the ions can be controlled by adjusting the parameters of the doping step P1. Specifically, oxygen ions can be doped into the edge region E near the oxide layer 11B, and an oxygen-rich region 24 is formed in this region. The center of the oxygen-rich region 24 contains a high concentration of oxygen ions, while the oxygen ion concentration decreases gradually further away from the center of the oxygen-rich region 24.

[0085] like Figure 5As shown, an annealing step P2 is then performed, in which the annealing step P2 heats the temperature to about 1300 degrees Celsius, so that the oxygen ions in the oxygen-rich region 24 react with the silicon layer 11A to form a silicon oxide layer 26, which is adjacent to the underlying oxide layer 11B, so that the two can be combined with each other to form an integral silicon oxide layer. After the annealing step P2 is performed, the thickness of the oxide layer 11B in the central region C of the substrate 11 remains unchanged, but the thickness of the oxide layer 11B in the edge region E is increased due to the combination with the silicon oxide layer 26. Subsequent steps, such as the formation of the gate G, source S, drain D, lightly doped drain LDD, etc. of a transistor, can be continued to form a structure as shown in Figure 2 . These steps are well known to those skilled in the art and are not repeated here. Thus, by the method described in this embodiment, a silicon-on-insulator substrate 11 with a special shape as shown in Figure 2 can be formed.

[0086] The above Figures 3 to 5 is formed by doping oxygen ions into a silicon layer and performing an annealing step to form a silicon-on-insulator substrate 11 as shown in Figure 2 . Then, please refer to Figures 6 to 11 , Figures 6 to 11 draws a cross-sectional structure diagram of a process for manufacturing a semiconductor structure including a silicon-on-insulator substrate according to another embodiment of the present application. First, as shown in Figure 6 , a material layer 30 and a silicon layer 32 are provided, where the material layer 30 is made of, for example, a silicon layer or a silicon oxynitride layer, but is not limited thereto. The silicon layer 32 can include a single crystal silicon layer or a polycrystalline silicon layer, and the present application is not limited thereto. In addition, the material layer 30 and the silicon layer 32 also define a central region and an edge region, and for clarity, the central region C1 and the edge region E1 are defined on the material layer 30, where the central region C1 is located between the edge region E1. In addition, the central region C2 and the edge region E2 are also defined on the silicon layer 32, where the central region C2 is located between the edge region E2. Here, the definitions of the central region C1 and the central region C2 are the same as the above-mentioned central region C, and the definitions of the edge region E1 and the edge region E2 are the same as the above-mentioned edge region E.

[0087] Then, as shown in Figure 7 , an oxide layer 34 is formed on the material layer 30, and a mask layer 36 is formed in the central region C2 of the silicon layer 32. The material of the oxide layer 34 is, for example, silicon oxide, and the material of the mask layer 36 is, for example, silicon oxide, silicon nitride, or silicon oxynitride, but the present application is not limited thereto.

[0088] As shown in Figure 8 , the oxide layer 34 is removed by etching, and the mask layer 36 is also removed by etching.As shown, a mask layer 38 is then formed in the edge region E1 of the oxide layer 34. The material of the mask layer is, for example, silicon oxide, silicon nitride, or silicon oxynitride, but the present invention is not limited thereto. It is worth noting that in this embodiment, the mask layer 38 exposes the oxide layer 34 in the middle region E1, that is, the mask layer 38 is not formed in the middle region E1.

[0089] Please continue to refer to this. Figure 8 An etching step P3 is performed on the silicon layer 32. Etching step P3 includes, but is not limited to, dry etching or wet etching. Using mask layer 36 as a mask, a portion of the silicon layer 32 located in the edge region E2 is removed. Since the silicon layer 32 in the middle region C2 is covered by mask layer 36, the silicon layer 32 in the middle region C2 is not removed and retains its original height. After etching step P3, a protrusion 40 appears on the top surface of the silicon layer 32.

[0090] Then as Figure 9 As shown, an etching step P4 is performed on the oxide layer 34. Etching step P4 includes, but is not limited to, dry etching or wet etching. Using the mask layer 38 as a mask, a portion of the oxide layer 34 located in the middle region E1 is removed. Since the oxide layer 34 in the edge region E2 is covered by the mask layer 38, the oxide layer 34 in the edge region E1 is not removed and retains its original height. After etching step P4, a recessed portion 42 appears on the top surface of the oxide layer 34.

[0091] On the other hand, please continue to refer to Figure 9 The mask layer 36 is removed, and then an oxide layer 44 is formed on the top surface of the silicon layer 32 and the protrusion 40. The thickness of the oxide layer 44 is approximately less than 100 angstroms, but is not limited thereto. The oxide layer 44 can be formed by growing the oxide layer directly on the surface of the silicon layer 32 and the protrusion 40 using an oxidation step, or by depositing the oxide layer onto the surface of the silicon layer 32 and the protrusion 40 using a deposition step, both of which are within the scope of this invention.

[0092] It is worth noting that, in Figure 9 The recessed portion 42 formed within the oxide layer 34 will correspond to the Figure 8 The protrusion 40 is formed on the surface of the silicon layer 32, meaning that in the following steps, the recessed portion 42 will be bonded to the protrusion 40. The purpose of forming the oxide layer 44 is to form the oxide layer 44 on the surface of the protrusion 40 beforehand. Therefore, in the subsequent bonding step between the recessed portion 42 and the protrusion 40, the interface material for both is silicon oxide, which allows the recessed portion 42 and the protrusion 40 to bond better.

[0093] In addition, forming the oxide layer 44 here serves another purpose: to adjust the width of the protrusion 40 and the oxide layer 44 to correspond to the width of the recessed portion 42. Since the protrusion 40 and the recessed portion 42 will be bonded together in subsequent steps to form a silicon-coated insulating layer substrate, the etching parameters in etching steps P3 and P4 can be adjusted to ensure that the dimensions of the protrusion 40 and the recessed portion 42 correspond as closely as possible to avoid gaps at the joint. However, various errors may occur in the actual manufacturing process, resulting in the etched protrusion 40 and the recessed portion 42 not perfectly corresponding in size. In this case, forming the oxide layer 44 can cover the protrusion 40 and increase its size. Therefore, if the size of the protrusion 40 is smaller than the size of the recessed portion 42, the size can still be fine-tuned by forming the oxide layer 44, making it less likely for gaps to form at the bonding surface.

[0094] However, in other embodiments of the present invention, the step of forming an oxide layer 44 on the surface of the protruding portion 40 may be omitted. That is, the protruding portion 40 may be directly bonded to the recessed portion 42 without forming an oxide layer 44 on its surface. The above variations are also within the scope of the present invention.

[0095] like Figure 10 and Figure 11 As shown, after flipping the silicon layer 32 vertically, the protruding portion 40 is aligned with the recessed portion 42 on the oxide layer 34 for bonding. At this point, the central region C and the edge region E can be redefined on the substrate. A subsequent polishing step, such as chemical mechanical polishing, can reduce the thickness of part of the silicon layer 32, thus forming a structure as shown. Figure 11 The structure shown. Wherein Figure 11 The structure shown is similar to that described in the above embodiment. Figure 2 The silicon-coated insulating substrate 11 shown has material layer 30 corresponding to material layer 11C, oxide layers 34 and 44 corresponding to oxide layer 11B, and silicon layer 32 corresponding to silicon layer 11A. However, the fabrication process in this embodiment differs from the previous embodiment. Similarly, in subsequent steps, other steps can be performed, such as forming transistor gate G, source region S, drain region D, lightly doped drain LDD, etc., to construct a structure as shown above. Figure 2 The structure shown is described. These steps are well known to those skilled in the art and will not be repeated here. Therefore, the method described in this embodiment can form a structure as shown. Figure 2 The silicon-coated insulating substrate 11 shown has a special shape.

[0096] Based on the above description and accompanying drawings, the present invention provides a semiconductor structure including a silicon-coated insulating substrate 11 (see reference). Figure 2), comprising a material layer 11C, which is defined with a middle region C and two edge regions E, wherein the middle region C is located between the two edge regions E, an oxide layer 11B and a silicon layer 11A are stacked on the material layer from bottom to top, wherein a height D2 of the silicon layer 11A in the middle region E is greater than a height D3 of the silicon layer in the two edge regions.

[0097] In some embodiments of the present application, wherein a top surface of the oxide layer 11B in the two edge regions E is flush with each other (as shown in Figure 2 ).

[0098] In some embodiments of the present application, wherein a bottom surface of the silicon layer 11A in the middle region (i.e. a top surface of the oxide layer 11B) is lower than a bottom surface of the silicon layer 11A in the two edge regions E (i.e. a bottom surface of the recess 21).

[0099] In some embodiments of the present application, wherein a gate structure G is further included, which is located on the silicon layer 11A and in the middle region C.

[0100] In some embodiments of the present application, wherein a source region S and a drain region D are further included, which are located in the silicon layer 11A and in the two edge regions E respectively.

[0101] In some embodiments of the present application, wherein a shallow trench isolation STI is further included, which is located on the oxide layer 11B and on both sides of the silicon layer 11A.

[0102] In some embodiments of the present application, wherein a top surface of the silicon layer 11A is flush with a top surface of the shallow trench isolation STI.

[0103] The present application further provides a method for manufacturing a semiconductor structure comprising a silicon-on-insulator substrate (refer to Figures 3 to 5 ), comprising providing a material layer 11C, which is defined with a middle region C and two edge regions E, wherein the middle region C is located between the two edge regions E, forming an oxide layer 11B and a silicon layer 11A stacked on the material layer from bottom to top, forming a mask layer 22 on the silicon layer 11A, and the mask layer 22 is located in the middle region C, and performing an oxygen ion doping step P1 to pass oxygen ions through the silicon layer 11A.

[0104] In some embodiments of the present application, wherein a thickness of the oxide layer 11B in the middle region C is less than a thickness of the oxide layer 11B in the two edge regions E (refer to Figure 2 or is Figure 5 ).

[0105] In some embodiments of the present application, wherein after the oxygen ion doping step, an annealing step P2 is further included to increase the thickness of the oxide layer 11B in the middle region C (the overall oxide layer thickness is increased due to the combination of the oxide layer 11B and the silicon oxide layer 26).

[0106] In some embodiments of the present application, wherein the bottom surface of the silicon layer 11A in the middle region C is lower than the bottom surface of the silicon layer 11A in the edge regions E.

[0107] In some embodiments of the present application, wherein a gate structure G is further included, which is formed on the silicon layer 11A and in the middle region C.

[0108] In some embodiments of the present application, wherein a source region S and a drain region D are further included, which are formed in the silicon layer 11A and in the edge regions E, respectively.

[0109] The present application further provides a method for manufacturing a semiconductor structure including a silicon-on-insulator substrate (as shown in the embodiment of Figures 6 to 11 The method includes providing a material layer 30 and a silicon layer 32, the material layer 30 and the silicon layer 32 are defined with a middle region (C1 / C2) and two edge regions (E1 / E2), respectively, wherein the middle region (C1 or C2) is located between the edge regions (E1 or E2), forming an oxide layer 34 on the material layer 30, forming a first mask layer (mask layer 36) on the middle region C2 of the silicon layer 32, performing a first etching step P4 on the oxide layer 34 to form a recessed portion 42 in the middle region C1 of the oxide layer 34, performing a second etching step P3 on the silicon layer 32 to form a protruding portion 40 in the middle region C2 of the silicon layer 32, and turning over the silicon layer 32 so that the recessed portion 42 on the oxide layer 34 and the protruding portion 40 on the silicon layer 32 are combined with each other.

[0110] In some embodiments of the present application, wherein after the protruding portion 40 is formed in the middle region C2 of the silicon layer 32, an oxidation step (such as the step of forming the oxide layer 44) is further included to form a second oxide layer 44 on the surface of the protruding portion 40. Figure 9

[0111] In some embodiments of the present application, wherein the step of forming the recessed portion 42 in the middle region C1 of the oxide layer 34 further includes: forming two second mask layers 38 on the oxide layer 34 and in the edge regions E1, performing the second etching step P4 to remove part of the oxide layer 34 in the middle region C1 and form the recessed portion 42.

[0112] ​In some embodiments of the present application, the width of the protrusion 40 and the second oxide layer 44 is equal to the width of the recessed portion 42.

[0113] In some embodiments of the present application, the first mask layer 36 is removed before the oxidation step.

[0114] In some embodiments of the present application, a grinding step is performed to reduce the thickness of the silicon layer 32. Figure 11

[0115] In some embodiments of the present application, the ratio of the height of the protrusion 40 to the thickness of the silicon layer 32 is between 0.3 and 0.7 (e.g. as shown in Figure 11 , for example, the thickness of the silicon layer is about 500 angstroms and the thickness of the protrusion 40 is about 250 angstroms).

[0116] In summary, the present application provides a semiconductor structure comprising a silicon-on-insulator substrate, which comprises a specially shaped silicon-on-insulator substrate. The oxide layer in the middle region has a recessed portion, so that the thickness of the silicon layer in the middle portion is larger, while the thickness of the silicon layer in the edge region remains unchanged. In this way, the thickness of the silicon layer under the gate is larger, so that there is more space to accommodate the storage charge, but the thickness of the silicon layer at the source / drain location remains unchanged. Therefore, the present application has the following advantages: 1. reduces the interface capacitance; 2. reduces the substrate impedance; 3. reduces the impact of gate-induced drain leakage (GIDL); 4. is compatible with existing technology and does not require additional photomasks; 5. has high off-capacitance and reduces static power consumption; 6. improves device quality.

[0117] The above description is only the preferred embodiments of the present application, and any equivalent changes and modifications made in accordance with the claims of the present application should be within the scope of the present application.​

Claims

1. A semiconductor structure comprising a silicon-coated insulating layer substrate, comprising: A material layer having a central region and two edge regions defined thereon, wherein the central region is located between the two edge regions; An oxide layer and a silicon layer are stacked on the material layer from bottom to top, wherein the thickness of the silicon layer in the middle region is greater than the thickness of the silicon layer in the two edge regions.

2. The semiconductor structure comprising a silicon-coated insulating substrate as claimed in claim 1, wherein the top surfaces of the oxide layer are aligned with each other in the two edge regions.

3. The semiconductor structure comprising a silicon-coated insulating layer substrate as claimed in claim 1, wherein the bottom surface of the silicon layer in the intermediate region is lower than the bottom surface of the silicon layer in the two edge regions.

4. The semiconductor structure comprising a silicon-coated insulating layer substrate as claimed in claim 1, further comprising a gate structure located on the silicon layer and in the intermediate region.

5. The semiconductor structure comprising a silicon-coated insulating layer substrate as claimed in claim 1, further comprising a source region and a drain region located within the silicon layer and respectively located within the two edge regions.

6. The semiconductor structure comprising a silicon-coated insulating substrate as claimed in claim 1, further comprising shallow trench isolation located on the oxide layer and on both sides of the silicon layer.

7. The semiconductor structure comprising a silicon-coated insulating substrate as claimed in claim 6, wherein the top surface of the silicon layer is flush with the top surface of the shallow trench isolation.

8. A method for fabricating a semiconductor structure comprising a silicon-coated insulating layer substrate, comprising: A material layer is provided, on which a central region and two edge regions are defined, wherein the central region is located between the two edge regions; An oxide layer and a silicon layer are stacked on the material layer from bottom to top; A mask layer is formed on the silicon layer, and the mask layer is located in the intermediate region; as well as An oxygen ion doping step is performed to allow oxygen ions to pass through the silicon layer.

9. The method for fabricating a semiconductor structure comprising a silicon-coated insulating layer substrate as described in claim 8, wherein the thickness of the oxide layer in the intermediate region is less than the thickness of the oxide layer in the two edge regions.

10. The method for fabricating a semiconductor structure comprising a silicon-coated insulating layer substrate as claimed in claim 8, wherein after the oxygen ion doping step, an annealing step is further performed to increase the thickness of the oxide layer in the two edge regions.

11. The method of fabricating a semiconductor structure comprising a silicon-coated insulating layer substrate as claimed in claim 8, wherein the bottom surface of the silicon layer in the intermediate region is lower than the bottom surface of the silicon layer in the two edge regions.

12. The method of fabricating a semiconductor structure comprising a silicon-coated insulating layer substrate as claimed in claim 8, further comprising forming a gate structure located on the silicon layer and in the intermediate region.

13. The method for fabricating a semiconductor structure comprising a silicon-coated insulating layer substrate as described in claim 8, further comprising forming a source region and a drain region located within the silicon layer and respectively located within the two edge regions.

14. A method for fabricating a semiconductor structure comprising a silicon-coated insulating layer substrate, comprising: A material layer and a silicon layer are provided, wherein a middle region and two edge regions are defined on the material layer and the silicon layer, respectively, and the middle region is located between the two edge regions; An oxide layer is formed on the material layer, and a first mask layer is formed in the intermediate region on the silicon layer; A first etching step is performed on the oxide layer to form a recessed portion in the middle region of the oxide layer; A second etching step is performed on the silicon layer to form a protrusion in the middle region of the silicon layer; as well as The silicon layer is flipped so that the recessed portion on the oxide layer is bonded to the protruding portion on the silicon layer.

15. The method of fabricating a semiconductor structure comprising a silicon-coated insulating layer substrate as claimed in claim 14, wherein after forming the protrusion in the intermediate region of the silicon layer, the method further comprises performing an oxidation step to form a second oxide layer on the surface of the protrusion.

16. The method of fabricating a semiconductor structure comprising a silicon-coated insulating layer substrate as claimed in claim 14, wherein the step of forming the recessed portion in the intermediate region of the oxide layer further comprises: Two second mask layers are formed on the oxide layer and located within the edge region; The second etching step is performed to remove part of the oxide layer in the intermediate region and form the recessed portion.

17. The method of fabricating a semiconductor structure comprising a silicon-coated insulating layer substrate as claimed in claim 15, wherein after the second oxide layer covers the protruding portion, the sum of the widths of the protruding portion and the second oxide layer is equal to the width of the recessed portion.

18. The method for fabricating a semiconductor structure comprising a silicon-coated insulating substrate as described in claim 15, further comprising removing the first mask layer before performing the oxidation step.

19. The method for fabricating a semiconductor structure comprising a silicon-coated insulating layer substrate as described in claim 14, further comprising a polishing step to reduce the thickness of the silicon layer.

20. The method for fabricating a semiconductor structure comprising a silicon-coated insulating substrate as claimed in claim 19, wherein after the polishing step, the ratio of the height of the protrusion to the thickness of the silicon layer is between 0.3 and 0.7.

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